MM54HC283 [NSC]
4-Bit Binary Adder with Fast Carry; 4位二进制加法器与快速进
| 型号： | MM54HC283 |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Bit Binary Adder with Fast Carry |
| 文件： | 总6页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC283/MM74HC283
4-Bit Binary Adder with Fast Carry
General Description
Features
Y
Full-carry look-ahead across the four bits
This full adder performs the addition of two 4-bit binary num-
bers utilizing advanced silicon-gate CMOS technology. The
sum (R) outputs are provided for each bit and the resultant
carry (C4) is obtained from the fourth bit. These adders fea-
ture full internal look ahead across all four bits. This pro-
vides the system designer with partial look-ahead perform-
ance at the economy and reduced package count of a rip-
ple-carry implementation.
Y
Systems achieve partial look-ahead performance
with the economy of ripple carry
Y
Y
Y
Wide supply range: 2V to 6V
Low quiescent power consumption: 8 mA at 25 C
§
Low input current: 1 mA maximum
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accom-
plished without the need for logic or level inversion. All in-
puts are protected from damage due to static discharge by
internal diode clamps to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
TL/F/5332–1
Top View
Order Number MM54HC283 or MM74HC283
C
1995 National Semiconductor Corporation
TL/F/5332
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
2
0
6
V
CC
DC Input or Output Voltage
(V , V
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
1.5V
IN
CC
CC
Operating Temp. Range (T )
A
DC Output Voltage (V
)
0.5 to V
b
b
a
85
a
125
OUT
MM74HC
MM54HC
40
55
C
§
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
C
IK OK
DC Output Current, per pin (I
)
OUT
Input Rise or Fall Times
DC V or GND Current, per pin (I
CC
)
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
ns
ns
ns
CC
CC
CC
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
400
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
8.0
80
160
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e
e
t 6 ns
f
AC Electrical Characteristics V
5V, T
25 C, C
§
15 pF, t
CC
A
L
r
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t
t
t
t
t
t
, t
PHL PLH
Maximum Propagation
18
27
27
30
26
32
32
ns
Delay From C0 to R1 or R2
, t
PHL PLH
Maximum Propagation
18
20
17
22
22
ns
ns
ns
ns
ns
Delay From C0 to R3
, t
PHL PLH
Maximum Propagation
Delay From C0 to R4
, t
PHL PLH
Maximum Propagation
Delay From A1 or B1 to R1
, t
PHL PLH
Maximum Propagation
Delay From C0 to C4
, t
PHL PLH
Maximum Propagation
Delay From A1 or B1 to C4
e
e
t
f
e
AC Electrical Characteristics C
50 pF, t
6 ns (unless otherwise specified)
L
r
74HC
54HC
e
T
25 C
§
A
eb
eb
T
A
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
t
t
t
t
t
t
t
, t
PHL PLH
Maximum Propagation
2.0V
4.5V
6.0V
60
21
18
150
30
188
37
225
45
ns
ns
ns
Delay From C0 to R1 or R2
26
32
39
, t
PHL PLH
Maximum Propagation
2.0V
4.5V
6.0V
60
21
18
150
30
188
37
225
45
ns
ns
ns
Delay From C0 to R3
26
32
39
, t
PHL PLH
Maximum Propagation
2.0V
4.5V
6.0V
65
24
19
162
34
202
43
243
51
ns
ns
ns
Delay From C0 to R4
28
35
42
, t
PHL PLH
Maximum Propagation
2.0V
4.5V
6.0V
60
22
18
150
33
188
41
225
50
ns
ns
ns
Delay From A1 or B1 to R1
27
34
41
, t
PHL PLH
Maximum Propagation
Delay From C0 to C4
2.0V
4.5V
6.0V
70
26
21
175
39
219
49
263
59
ns
ns
ns
32
40
46
, t
PHL PLH
Maximum Propagation
2.0V
4.5V
6.0V
70
26
21
175
39
219
49
263
59
ns
ns
ns
Delay From A1 or B1 to C4
32
40
46
, t
THL TLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
28
8
75
15
13
95
19
16
110
22
ns
ns
ns
7
19
C
C
Maximum Input
Capacitance
6
10
10
10
pF
IN
Power Dissipation
150
pF
PD
Capacitance (Note 5)
2
e
a
I
CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
V
, and the no load dynamic current consumption,
D
e
a
I
CC
I
S
C
V
PD CC
f
.
3
Truth Table
Output
When
When
e
e
Input
C0
L
C0
H
When
e
When
e
C2
L
C2
H
A1 A3 B1 B3 A2 A4 B2 B4 R1 R3 R2 R4 C2 C4 R1 R3 R2 R4 C2 C4
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
H
L
L
H
H
L
L
L
H
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
L
L
H
L
H
H
L
e
e
low level
H
high level, L
Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the
internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs R3, R4, and C4
4
Logic Diagram
’HC283
TL/F/5332–2
5
Physical Dimensions inches (millimeters)
Order Number MM54HC283J or MM74HC283J
NS Package J16A
Order Number MM74HC283N
NS Package N16E
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