MM54HC75 [NSC]
4-Bit Bistable Latch with Q and Q Output; 4位双稳态锁存器与Q和Q输出
| 型号： | MM54HC75 |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Bit Bistable Latch with Q and Q Output |
| 文件： | 总4页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC75/MM74HC75
4-Bit Bistable Latch with Q and Q Output
General Description
This 4-bit latch utilizes advanced silicon-gate CMOS tech-
nology to achieve the high noise immunity and low power
consumption normally associated with standard CMOS inte-
grated circuits. These devices can drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
and ground.
CC
This latch is ideally suited for use as temporary storage for
binary information processing, input/output, and indicator
units. Information present at the data (D) input is transferred
to the Q output when the enable (G) is high. The Q output
will follow the data input as long as the enable remains high.
When the enable goes low, the information that was present
at the data input at the time the transition occurred is re-
tained at the Q output until the enable is permitted to go
high again.
Features
Y
Typical operating frequency: 50 MHz
Y
Y
Y
Y
Typical propagation delay: 12 ns
Wide operating supply voltage range: 2–6V
Low input current: 1 mA maximum
Low quiescent supply current: 80 mA maximum
(74HC Series)
Y
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
Inputs
Outputs
D
G
Q
Q
L
H
X
H
H
L
L
H
L
H
Q
Q
0
0
e
e
e
e
High Level: L Low Level
H
X
Don’t Care
Q
0
The level of Q before the transition of G
TL/F/5303–1
Order Number MM54HC75 or MM74HC75
(1 of 4 latches)
TL/F/5303–2
C
1995 National Semiconductor Corporation
TL/F/5303
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
IN
CC
CC
b
b
a
40
55
85
C
C
§
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
r
f
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
T
A
40 to 85 C
T
55 to 125 C
§
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
I
V
s
or V
4.0 mA
5.2 mA
IN
IH IL
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
s
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
I
IN
s
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
I
V
s
or V
4.0 mA
5.2 mA
IN
IH IL
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
s
e
g
g
g
I
I
Maximum Input
Current
V
V
or GND
6.0V
0.1
1.0
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
V
IN
V
CC
or GND
6.0V
4.0
40
80
mA
CC
e
I
0 mA
OUT
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t
t
t
t
, t
PHL PLH
Maximum Propagation
Delay, Data to Q
14
23
20
27
23
ns
, t
PHL PLH
Maximum Propagation
Delay, Data to Q
10
16
11
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay, Enable to Q
, t
Maximum Propagation
Delay, Enable to Q
PHL PLH
t
t
t
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
20
0
ns
ns
ns
s
b
2
H
W
16
e
e
e
AC Electrical Characteristics C 50 pF, t
t
f
6 ns (unless otherwise specified)
L
r
74HC
54HC
e
T
25 C
§
A
eb
eb
T
A
40 to 85 C
T
A
55 to 125 C
§
§
Symbol
Parameter
Conditions
V
Units
CC
Typ
Guaranteed Limits
t
t
t
t
t
t
t
t
, t
Maximum Propagation
Delay, Data to Q
2.0V
4.5V
6.0V
37
15
14
125
25
24
156
32
27
188
38
32
ns
ns
ns
PHL PLH
, t
PHL PLH
Maximum Propagation
Delay, Data to Q
2.0V
4.5V
6.0V
29
12
11
110
22
19
138
28
24
165
33
29
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay, Enable to Q
2.0V
4.5V
6.0V
40
18
16
145
29
25
181
36
31
218
44
38
ns
ns
ns
, t
Maximum Propagation
Delay, Enable to Q
2.0V
4.5V
6.0V
36
15
14
125
25
22
156
31
28
188
38
33
ns
ns
ns
PHL PLH
Minimum Set Up Time
Data to Enable
2.0V
4.5V
6.0V
40
10
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
s
b
Minimum Hold Time
Enable to Data
2.0V
4.5V
6.0V
10
0
0
0
0
0
0
0
0
0
ns
ns
ns
H
W
b
b
2
2
Minimum Enable Pulse Width
2.0V
4.5V
6.0V
40
11
9
80
16
14
100
20
18
120
24
21
ns
ns
ns
, t
TLH THL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
C
C
Power Dissipation
Capacitance (Note 5)
(per commonly
clocked latched
pair)
40
pF
PD
Maximum Input
Capacitance
5
10
10
10
pF
IN
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches (millimeters)
Order Number MM54HC75J or MM74HC75J
NS Package J16A
Order Number MM54HC75N
NS Package N16E
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with instructions for use provided in the labeling, can
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to the user.
2. A critical component is any component of a life
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