MM54HCT151J [NSC]
8-Channel Digital Multiplexer; 8通道数字多路复用器
| 型号： | MM54HCT151J |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Channel Digital Multiplexer |
| 文件： | 总4页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1995
MM54HCT151/MM74HCT151
8-Channel Digital Multiplexer
General Description
This high speed Digital multiplexer utilizes advanced silicon-
gate CMOS technology. Along with the high noise immunity
and low power dissipation of standard CMOS integrated cir-
cuits, it possesses the ability to drive 10 LS-TTL loads. The
MM54HCT151/MM74HCT151 selects one of the 8 data
sources, depending on the address presented on the A, B,
and C inputs. It features both true (Y) and complement (W)
outputs. The STROBE input must be at a low logic level to
enable this multiplexer. A high logic level at the STROBE
forces the W output high and the Y output low.
devices. These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
Features
Y
Typical propagation delay: 20 ns
Y
Low quiescent supply current: 40 mA maximum
(74HCT Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
Y
TTL input compatible
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
Inputs
Select
Outputs
Strobe
S
Y
W
C
B
A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
H
e
e
e
Low Level, X Don’t Care
H
High Level, L
TL/F/9399–1
e
D0, D1...D7
the level of the respective D input
Top View
Order Number MM54HCT151 or MM74HCT151
TL/F/9399–2
C
1995 National Semiconductor Corporation
TL/F/9399
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.5
Units
V
Supply Voltage (V
)
CC
4.5
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5V to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HCT
MM54HCT
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5V to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
(t , t )
DC Output Current, per Pin (I
)
OUT
500
ns
r
f
DC V or GND Current, per Pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HCT
e b
54HCT
55 C to 125 C
§
e
T
25 C
§
A
a
e b
A
a
T
A
40 C to 85 C T
§
§
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
IH
2.0
0.8
2.0
0.8
2.0
0.8
V
V
Maximum Low Level
Input Voltage
IL
e
Minimum High Level V
Output Voltage
V or V
IH IL
20 mA
OH
IN
s
I
4.5V
4.4
4.4
4.4
V
l
OUT
l
e
V
I
I
V
s
or V
4.0 mA
4.8 mA
IN
IH
IL
4.5V 4.2 3.98
5.5V 5.2 4.98
3.84
4.84
3.7
4.7
V
V
l
l
OUT
OUT
l
l
s
e
V
OL
Maximum Low Level V
V or V
IH IL
IN
e
e
e
Output Voltage
I
I
I
20 mA
4.0 mA
4.8 mA
0
0.1
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
4.5V 0.2 0.26
5.5V 0.2 0.26
e
I
I
Maximum Input
Current
V
V
or GND
6.0V
IN
IN
CC
g
g
g
1.0
0.1
8.0
0.25 0.4
1.0
80
0.55
mA
e
Maximum Quiescent V
Supply Current
V
CC
or GND
CC
IN
160
mA
e
I
0 mA
OUT
e
V
IN
2.4V or 0.5V (Note 4)
0.65
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HCT at 4.5V. Thus the 4.5V values should be used when
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current
IH
e
designing with this supply. Worst case V and V occur at V
IH IL
CC
(I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC OZ
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
ns
t
t
t
t
t
t
, t
PHL PLH
Maximum Propagation Delay
A, B or C to Y
26
26
22
22
17
17
35
35
29
29
23
23
, t
PHL PLH
Maximum Propagation Delay
A, B or C to W
ns
, t
PHL PLH
Maximum Propagation Delay
Any D to Y
ns
, t
PHL PLH
Maximum Propagation Delay
any D to W
ns
, t
PHL PLH
Maximum Propagation Delay
Strobe to Y
ns
, t
PHL PLH
Maximum Propagation Delay
Strobe to W
ns
e
e
e
t
f
e
g
5.0V 10%, C
AC Electrical Characteristics V
50 pF, t
6 ns (unless otherwise specified)
CC
L
r
74HCT
40 C to 85 C
§
54HCT
eb a
55 C to 125 C
§ §
e
T
25 C
§
A
eb
a
T
T
§
Symbol
Parameter
Conditions
Units
A
A
Typ
Guaranteed Limits
t
t
t
t
t
t
t
, t
Maximum Propagation Delay
A, B or C to Y
PHL PLH
33
46
46
39
39
28
28
15
58
69
69
59
59
42
42
23
ns
ns
ns
ns
ns
ns
ns
pF
pF
, t
PHL PLH
Maximum Propagation Delay
A, B or C to W
33
27
27
21
21
8
58
49
49
35
35
19
, t
PHL PLH
Maximum Propagation Delay
any D to Y
, t
PHL PLH
Maximum Propagation Delay
any D to W
, t
PHL PLH
Maximum Propagation Delay
Strobe to Y
, t
PHL PLH
Maximum Propagation Delay
Strobe to W
, t
TLH THL
Maximum Output Rise
and Fall Time
C
Power Dissipation
Capacitance (Note 5)
(per package)
PD
IN
110
5
C
Maximum Input
Capacitance
10
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches, (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HCT151J or MM74HCT151J
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM74HCT151N
NS Package Number N16E
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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