MM58274C [NSC]
Microprocessor Compatible Real Time Clock; 微处理器兼容实时时钟
| 型号： | MM58274C |
| 厂家： | 
National Semiconductor |
| 描述： | Microprocessor Compatible Real Time Clock |
| 文件： | 总16页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1991
MM58274C
Microprocessor Compatible Real Time Clock
General Description
Features
Y
Same pin-out as MM58174A, MM58274B, and
MM58274
The MM58274C is fabricated using low threshold metal gate
CMOS technology and is designed to operate in bus orient-
ed microprocessor systems where a real time clock and cal-
endar function are required. The on-chip 32.768 kHz crystal
controlled oscillator will maintain timekeeping down to 2.2V
to allow low power standby battery operation. This device is
pin compatible with the MM58174A but continues timekeep-
ing up to tens of years. The MM58274C is a direct replace-
ment for the MM58274 offering improved Bus access cycle
times.
Y
Timekeeping from tenths of seconds to tens of years in
independently accessible registers
Leap year register
Y
Y
Hours counter programmable for 12 or 24-hour
operation
Y
Y
Buffered crystal frequency output in test mode for easy
oscillator setting
Data-changed flag allows simple testing for time
rollover
Applications
Y
Y
Y
Y
Y
Independent interrupting time with open drain output
Fully TTL compatible
Point of sale terminals
Y
Teller terminals
Low power standby operation (10 mA at 2.2V)
Low cost 16-pin DIP and 20-pin PCC
Y
Word processors
Y
Data logging
Y
Industrial process control
Block Diagram
TL/F/11219–1
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
MicrobusTM is a trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/11219
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.5
Units
Operating Supply Voltage
4.5
2.2
0
V
V
V
Standby Mode Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
5.5
b
a
DC Input or Output Voltage
0.3V to V
DD
0.3V
V
DD
85
b
40
C
g
§
DC Input or Output Diode Current
5.0 mA
b
a
Storage Temperature, T
STG
65 C to 150 C
§
§
6.5V
Supply Voltage, V
DD
Power Dissipation, P
500 mW
D
Lead Temperature
(Soldering, 10 seconds)
260
§
e
e b
a
40 C to 85 C unless otherwise stated.
g
5V 10%, T
Electrical Characteristics V
§
§
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High Level Input
Voltage (except
XTAL IN)
2.0
V
V
IL
Low Level Input
Voltage (except
XTAL IN)
0.8
V
e b
e b
b
3.7
V
V
High Level Output
I
I
20 mA
V
V
0.1
0.1
V
V
OH
OH
DD
Voltage (DB0–DB3)
1.6 mA
OH
OH
e b
b
High Level Output
Voltage (INT)
I
20 mA
V
OH
DD
(In Test Mode)
e
e
V
OL
Low Level Output
Voltage (DB0–DB3,
INT)
I
20 mA
0.1
0.4
V
V
OL
i
1.6 mA
OL
e
e
e
b
b
b
b
80
I
I
I
Low Level Input Current
(AD0–AD3, DB0–DB3)
V
V
V
V
V
V
(Note 2)
(Note 2)
(Note 2)
5
5
5
mA
mA
mA
mA
IL
IL
IL
IN
IN
IN
SS
SS
SS
b
Low Level Input Current
(WR, RD)
190
550
b
Low Level Input Current
(CS)
V
e
I
Ouput High Level
V
DD
2.0
OZH
OUT
Leakage Current (INT)
e
I
Average Supply Current
All V
IN
V
CC
or Open Circuit
DD
e
e
V
DD
V
DD
2.2V (Standby Mode)
5.0V (Active Mode)
4
10
1
mA
mA
C
Input Capacitance
Output Capacitance
5
10
pF
pF
IN
C
OUT
(Outputs Disabled)
10
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless otherwise noted.
Note 2: The DB0–DB3 and AD0–AD3 lines all have active P-channel pull-up transistors which will source current. The CS, RD, and WR lines have internal pull-up
resistors to V
DD
.
2
AC Switching Characteristics
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR V
e
e
100 pF
g
5V 0.5V, C
DD
L
Commercial
Specification
Symbol
Parameter
Units
e b
a
40 C to 85 C
T
§
§
A
Min
Typ
390
140
140
Max
650
300
300
DC
t
t
t
t
t
Address Bus Valid to Data Valid
Chip Select On to Data Valid
ns
ns
ns
AD
CSD
RD
Read Strobe On to Data Valid
Read Strobe Width (Note 3, Note 7)
RW
RA
Address Bus Hold Time from Trailing Edge
of Read Strobe
0
0
ns
ns
ns
ns
t
t
t
Chip Select Hold Time from Trailing Edge
of Read Strobe
CSH
RH
Data Hold Time from Trailing Edge
of Read Strobe
70
160
Time from Trailing Edge of Read Strobe
250
HZ
Until O/P Drivers are TRI-STATE
É
e
g
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL V
DD
5V 0.5V
Commercial
Specification
Symbol
Parameter
Units
e b
a
40 C to 85 C
T
A
§
§
Min
Typ
125
Max
t
Address Bus Valid to Write Strobe O
(Note 4, Note 6)
400
ns
AW
t
Chip Select On to Write Strobe O
Data Bus Valid to Write Strobe O
Write Strobe Width (Note 6)
250
400
250
0
100
220
95
ns
ns
ns
ns
CSW
t
DW
t
t
WW
Chip Select Hold Time Following
WCS
Write Strobe O
t
t
t
Address Bus Hold Time Following
0
ns
ns
ns
WA
Write Strobe O
Data Bus Hold Time Following
100
70
35
20
WD
Write Strobe O
Address Bus Valid Before
Start of Write Strobe
AWS
Note 3: Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt
Programming.
Note 4: All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR).
Note 5: Input test waveform peak voltages are 2.4V and 0.4V. Output signals are measured to their 2.4V and 0.4V levels.
e
a
WR. Hence write
Note 6: Write strobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS,
CS
strobe commences when both signals are low, and terminates when the first signal returns high.
e
a
RD.
Note 7: Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie., RS
CS
e
e
25 C.
Note 8: Typical numbers are at V
CC
5.0V and T
§
A
3
Switching Time Waveforms
Read Cycle Timing (Notes 5 and 7)
TL/F/11219–2
Write Cycle Timing (Notes 5 and 6)
TL/F/11219–3
Connection Diagrams
PCC Package
Dual-In-Line Package
TL/F/11219–4
Top View
TL/F/11219–5
Top View
FIGURE 2
Order Number MM58274CJ, MM58274CN or MM58274CV
See NS Package J16A, N16A, or V20A
4
Functional Description
The MM58274C is a bus oriented microprocessor real time
clock. It has the same pin-out as the MM58174A while offer-
ing extended timekeeping up to units and tens of years. To
enhance the device further, a number of other features have
been added including: 12 or 24 hours counting, a testable
data-changed flag giving easy error-free time reading and
simplified interrupt control.
CIRCUIT DESCRIPTION
The block diagram in Figure 1 shows the internal structure
of the chip. The 16-pin package outline is shown inFigure 2.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on-chip
bias resistor. Externally a 20 pF capacitor, a 6 pF–36 pF
trimmer capacitor and a crystal are suggested to complete
the 32.768 kHz timekeeping oscillator circuit.
A buffered oscillator signal appears on the interrupt output
when the device is in test mode. This allows for easy oscilla-
tor setting when the device is initially powered up in a sys-
tem.
The 6 pF–36 pF trimmer fine tunes the crystal load imped-
ance, optimizing the oscillator stability. When properly ad-
justed (i.e., to the crystal frequency of 32.768 kHz), the cir-
cuit will display a frequency variation with voltage of less
than 3 ppm/V. When an external oscillator is used, connect
to oscillator input and float (no connection) the oscillator
output.
The counters are arranged as 4-bit words and can be ran-
domly accessed for time reading and setting. The counters
output in BCD (binary coded decimal) 4-bit numbers. Any
register which has less than 4 bits (e.g., days of week uses
only 3 bits) will return a logic 0 on any unused bits. When
written to, the unused inputs will be ignored.
When the chip is enabled into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscilla-
tor output that can be used to set the crystal frequency
when the device is installed in a system. For further informa-
tion see the section on Test Mode.
Writing a logic 1 to the clock start/stop control bit resets the
internal oscillator divider chain and the tenths of seconds
counter. Writing a logic 0 will start the clock timing from the
nearest second. The time then updates every 100 ms with
all counters changing synchronously. Time changing during
a read is detected by testing the data-changed bit of the
control register after completing a string of clock register
reads.
Divider Chain
The crystal oscillator is divided down in three stages to pro-
duce a 10 Hz frequency setting pulse. The first stage is a
non-integer divider which reduces the 32.768 kHz input to
30.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
Johnson counter divides this by six, generating a 10 Hz out-
put. The 10 Hz clock is gated with the 32.768 kHz crystal
frequency to provide clock setting pulses of 15.26 ms dura-
tion. The setting pulse drives all the time registers on the
Interrupt delay times of 0.1s, 0.5s, 1s, 5s, 10s, 30s or 60s
can be selected with single or repeated interrupt outputs.
The open drain output is pulled low whenever the interrupt
timer times out and is cleared by reading the control regis-
ter.
TL/F/11219–6
FIGURE 3. Typical System Connection Diagram
5
Functional Description (Continued)
device which are synchronously clocked by this signal. All
time data and data-changed flag change on the falling edge
of the clock setting pulse.
Both counters may be accessed for read or write operations
as desired.
In 12-hour mode, the tens of hours register has only one
active bit and the top three bits are set to logic 0. Data bit 1
of the clock setting register is the AM/PM indicator; logic 0
indicating AM, logic 1 for PM.
Data-Changed Flag
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the clock
was last read. This flag occupies bit 3 of the control register
where it can be tested by the processor to sense data-
changed. It will be reset by a read of the control register.
See the section, ‘‘Methods of Device Operation’’, for sug-
gested clock reading techniques using this flag.
When 24-hour mode is programmed, the tens of hours reg-
ister reads out two bits of data and the two most significant
bits are set to logic 0. There is no AM/PM indication and bit
1 of the clock setting register will read out a logic 0.
In both 12/24-hour modes, the units of hours will read out
four active data bits. 12 or 24-hour mode is selected by bit 0
of the clock setting register, logic 0 for 12-hour mode, logic
1 for the 24-hour mode.
Seconds Counters
There are three counters for seconds:
a) tenths of seconds
Days Counters
b) units of seconds
There are two days counters:
a) units of days
c) tens of seconds.
The registers are accessed at the addresses shown in Ta-
ble I. The tenths of seconds register is reset to 0 when the
clock start/stop bit (bit 2 of the control register) is set to
logic 1. The units and tens of seconds are set up by the
processor, giving time setting to the nearest second. All
three registers can be read by the processor for time output.
b) tens of days.
The days counters will count up to 28, 29, 30 or 31 depend-
ing on the state of the months counters and the leap year
counter. The microprocessor has full read/write access to
these registers.
Months Counters
Minutes Counters
There are two months counters:
a) units of months
There are two minutes counters:
a) units of minutes
b) tens of months.
b) tens of minutes.
Both these counters have full read/write access.
Both registers may be read to or written from as required.
Years Counters
Hours Counters
There are two years counters:
a) units of years
There are two hours counters:
a) units of hours
b) tens of years.
b) tens of hours.
Both these counters have full read/write access. The years
will count up to 99 and roll over to 00.
TABLE I. Address Decoding of Real-Time Clock Internal Registers
Address (Binary)
Register Selected
(Hex)
Access
AD3
AD2
AD1
AD0
0
Control Register
Tenths of Seconds
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Unit Hours
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Split Read and Write
Read Only
R/W
1
2
3
4
5
6
7
8
9
R/W
R/W
R/W
R/W
Tens Hours
R/W
Units Days
R/W
Tens Days
R/W
10 Units Months
11 Tens Months
12 Units Years
13 Tens Years
14 Day of Week
15 Clock Setting/
Interrupt Registers
R/W
R/W
R/W
R/W
R/W
R/W
6
Functional Description (Continued)
Day of Week Counter
The day of week counter increments as the time rolls from
23:59 to 00:00 (11:59 PM to 12:00 AM in 12-hour mode). It
counts from 1 to 7 and rolls back to 1. Any day of the week
may be specified as day 1.
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from 11:59
to 12:00 in 12-hour mode. In 24-hour mode this bit is set to
logic 0.
The 12/24-hour mode set determines whether the hours
counter counts from 1 to 12 or from 0 to 23. It also controls
the AM/PM indicator, enabling it for 12-hour mode and forc-
ing it to logic 0 for the 24-hour mode. The 12/24-hour mode
bit is set to logic 0 for 12-hour mode and it is set to logic 1
for 24-hour mode.
Clock Setting Register/Interrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the processor
at address 15. Normal clock and interrupt timing operations
will always continue regardless of which register is selected
onto the bus. The layout of these registers is shown in
Table II.
IMPORTANT NOTE: Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on Ini-
tialization (Methods of Device Operation) for a suggested
setting routine.
The clock setting register is comprised of three separate
functions:
a) leap year counter: bits 2 and 3
b) AM/PM indicator: bit 1
All bits in the clock setting register may be read by the proc-
essor.
c) 12-hour mode set: bit 0 (see Table IIA).
The interrupt register controls the operation of the timer for
interrupt output. The processor programs this register for
single or repeated interrupts at the selected time intervals.
The leap year counter is a 2-stage binary counter which
is clocked by the months counter. It changes state as the
time rolls over from 11:59 on December 31 to 00:00 on
January 1.
The lower three bits of this register set the time delay period
that will occur between interrupts. The time delays that can
be programmed and the data words that select these are
outlined in Table IIB.
The counter should be loaded with the ‘number of years
since last leap year’ e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap year,
then the leap year counter should be set to 0. The contents
of the leap year counter can be read by the mP.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode, logic 1 sets
for repeated mode.
Using the interrupt is described in the Device Operation sec-
tion.
TABLE IIA. Clock Setting Register Layout
Data Bits Used
Function
Comments
Access
DB3
DB2
DB1
DB0
Leap Year Counter
X
X
0 Indicates a Leap Year
e
PM
R/W
R/W
e
0 in 24-Hour Mode
AM/PM Indicator (12-Hour Mode)
X
0
AM
1
e
e
12/24-Hour Select Bit
X
0
1
12-Hour Mode
24-Hour Mode
R/W
TABLE IIB. Interrupt Control Register
Comments
DB3
Control Word
Function
DB2
DB1
DB0
No Interrupt
Interrupt output cleared,
start/stop bit set to 1.
X
0
0
0
0.1 Second
0.5 Second
1 Second
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
e
e
DB3
DB3
0 for single interrupt
5 Seconds
10 Seconds
30 Seconds
60 Seconds
1 for repeated interrupt
g
Timing Accuracy: single interrupt mode (all time delays): 1 ms
Repeated Mode: 1 ms on initial timeout, thereafter synchronous
g
with first interrupt (i.e., timing errors do not accumulate).
7
Functional Description (Continued)
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the
interrupt register.
Control Register
There are three registers which control different operations
of the clock:
The interrupt start/stop bit controls the running of the inter-
rupt timer. It is programmed in the same way as the clock
start/stop bit; logic 1 to halt the interrupt and reset the tim-
er, logic 0 to start interrupt timing.
a) the clock setting register
b) the interrupt register
c) the control register.
The clock setting and interrupt registers both reside at ad-
dress 15, access to one or the other being controlled by the
interrupt select bit; data bit 1 of the control register.
When no interrupt is programmed (interrupt control register
set to 0), the interrupt start/stop bit is automatically set to a
logic 1. When any new interrupt is subsequently pro-
grammed, timing will not commence until the start/stop bit
is loaded with 0.
The clock setting register programs the timekeeping of the
clock. The 12/24-hour mode select and the AM/PM indica-
tor for 12-hour mode occupy bits 0 and 1, respectively. Data
bits 2 and 3 set the leap year counter.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing log-
ic 0 into the start/stop bit.
The interrupt register controls the operation of the interrupt
timer, selecting the required delay period and either single
or repeated interrupt.
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary.
The control register is responsible for controlling the opera-
tions of the clock and supplying status information to the
processor. It appears as two different registers; one with
write only access and one with read only access.
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start/stop bit. The timer is reset and
can be restarted in the normal way, giving a full time delay
period before the next interrupt.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
In general, the control register is set up such that writing 0’s
into it will start anything that is stopped, pull the clock out of
test mode and select the clock setting register onto the bus.
In other words, writing 0 will maintain normal clock operation
and restart interrupt timing, etc.
The read only register contains two output data latches
which will supply status information for the processor. Table
III shows the mapping of the various control latches and
status flags in the control register. The control register is
located at address 0.
The read only portion of the control register has two status
outputs:
The write only portion of the control register contains four
latches:
Since the MM58274C keeps real time, the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock.
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency as well
as rapid testing of the device registers, if required. A more
complete description is given in the Test Mode section. For
normal operation the test bit is loaded with logic 0.
Some method of warning the processor when the time data
has changed must thus be included. This is provided for by
the data-changed flag located in bit 3 of the control register.
This flag is set by the clock setting pulse which also clocks
the time registers. Testing this bit can tell the processor
whether or not the time has changed. The flag is cleared by
a read of the control register but not by any write operations.
No other register read has any effect on the state of the
data-changed flag.
The clock start/stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing. Tim-
ing is restarted when the start/stop bit is written with a logic
0.
Data bit 0 is the interrupt flag. This flag is set whenever the
interrupt timer times out, pulling the interrupt output low. In a
polled interrupt routine the processor can test this flag to
determine if the MM58274C was the interrupting device.
This interrupt flag and the interrupt output are both cleared
by a read of the control register.
The interrupt select bit determines which of the two regis-
ters mapped onto address 15 will be accessed when this
address is selected.
TABLE III. The Control Register Layout
DB2
Access (addr0)
Read From:
Write To:
DB3
Data-Changed Flag
Test
DB1
DB0
0
0
Interrupt Flag
Clock Start/Stop
Interrupt Select
Interrupt Start/Stop
e
e
e
e
e
e
0
Normal
0
1
Clock Run
Clock Stop
0
Clock Setting Register
e
Interrupt Register
0
1
Interrupt Run
Interrupt Stop
e
1
Test Mode
1
8
Functional Description (Continued)
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe. The flag information is held
latched during a control register read, guaranteeing that sta-
ble status information will always be read out by the proces-
sor.
1) Disable interrupt on the processor to allow oscillator set-
ting. Write 15 into the control register:The clock and inter-
10
rupt start/stop bits are set to 1, ensuring that the clock and
interrupt timers are both halted. Test mode and the interrupt
register are selected.
Interrupt timeout is detected and stored internally if it occurs
during a read of the control register, the interrupt output will
then go low only after the read has been completed.
2) Write 0 to the interrupt register: Ensure that there are no
interrupts programmed and that the oscillator will be gated
onto the interrupt output.
A clock setting pulse occurring during a control register read
will not affect the data-changed flag since time data read
out before or after the control read will not be affected by
the time change.
3) Set oscillator frequency: All timing has been halted and
the oscillator is buffered out onto the interrupt line.
4) Write 5 to the control register:The clock is now out of test
mode but is still halted. The clock setting register is now
selected by the interrupt select bit.
METHODS OF DEVICE OPERATION
Test Mode
5) Write 0001 to all registers. This ensures starting with a
valid BCD value in each register.
National Semiconductor uses test mode for functionally
testing the MM58274C after fabrication and again after
packaging. Test mode can also be used to set up the oscil-
lator frequency when the part is first commissioned.
6) Set 12/24 Hours Mode: Write to the clock setting register
to select the hours counting mode required.
7) Load Real-Time Registers: All time registers (including
Leap Years and AM/PM bit) may now be loaded in any
order. Note that when writing to the clock setting register to
set up Leap Years and AM/PM, the Hours Mode bit must
not be altered from the value programmed in step 5.
Figure 4 shows the internal clock connections when the de-
vice is written into test mode. The 32.768 kHz oscillator is
gated onto the interrupt output to provide a buffered output
for initial frequency setting. This signal is driven from a
TRI-STATE output buffer, enabling easy oscillator setting in
systems where interrupt is not normally used and there is no
external resistor on the pin.
8) Write 0 to the control register: This operation finishes the
clock initialization by starting the time. The final control reg-
ister write should be synchronized with an external time
source.
If an interrupt is programmed, the 32.768 kHz output is
switched off to allow high speed testing of the interrupt tim-
er. The interrupt output will then function as normal.
In general, timekeeping should be halted before the time
data is altered in the clock. The data can, however, be al-
tered at any time if so desired. Such may be the case if the
user wishes to keep the clock corrected without having to
stop and restart it; i.e., winter/summer time changing can be
accomplished without halting the clock. This can be done in
software by sensing the state of the data-changed flag and
only altering time data just after the time has rolled over
(data-changed flag set).
The clock start/stop bit can be used to control the fast
clocking of the time registers as shown in Figure 4.
Initialization
When it is first installed and power is applied, the device will
need to be properly initialized. The following operation steps
are recommended when the device is set up (all numbers
are decimal):
TL/F/11219–7
FIGURE 4. Test Mode Organization
9
Functional Description (Continued)
Reading the Time Registers
Using the data-changed flag technique supports microproc-
essors with block move facilities, as all the necessary time
data may be read sequentially and then tested for validity as
shown below.
Single Interrupt Mode:
When appropriate, write 0 or 2 to the control register to
restart the interrupt timer.
Repeated Interrupt Mode:
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
Timing continues, synchronized with the control register
write which originally started interrupt timing. No further in-
tervention is necessary from the processor to maintain tim-
ing.
2) Read time registers: All desired time registers are read
out in a block.
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt start/stop set to 1). Timing
for the full delay period recommences when the interrupt
start/stop bit is again loaded with 0 as normal.
3) Read the control register and test DCF: If DCF is cleared
(logic 0), then no clock setting pulses have after occurred
since step 1. All time data is guaranteed good and time
reading is complete.
IMPORTANT NOTE: Using the interrupt timer places a con-
straint on the maximum Read Strobe width which may be
applied to the clock. Normally all registers may be read from
If DCF is set (logic 1), then a time change has occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1 ac-
tion.
with a t
RW
down to DC (i.e., CS and RD held continuously
low). When the interrupt timer is active however, the maxi-
mum read strobe width that can be applied to the control
register (Addr 0) is 30 ms.
Interrupt Programming
This restriction is to allow the interrupt timer to properly re-
set when it times out. Note that it only affects reading of the
control registerÐall other addresses in the clock may be
accessed with DC read strobes, regardless of the state of
the interrupt timer. Writes to any address are unaffected.
The interrupt timer generates interrupts at time intervals
which are programmed into the interrupt register. A single
interrupt after delay or repeated interrupts may be pro-
grammed. Table IIB lists the different time delays and the
data words that select them in the interrupt register.
Once the interrupt register has been used to set up the
delay time and to select for single or repeat, it takes no
further part in the workings of the interrupt system. All activi-
ty by the processor then takes place in the control register.
NOTES ON AC TIMING REQUIREMENTS
Although the Switching Time Waveforms show Microbus
control signals used for clock access, this does not pre-
clude the use of the MM58274C in other non-Microbus sys-
tems. Figure 5 is a simplified logic diagram showing how the
control signals are gated internally to control access to the
clock registers. From this diagram it is clear that CS could
be used to generate the internal data transfer strobes, with
RD and WR inputs set up first. This situation is illustrated in
Figure 6.
Initializing:
1) Write 3 to the control register (AD0): Clock timing contin-
ues, interrupt register selected and interrupt timing stopped.
2) Write interrupt control word to address 15: The interrupt
register is loaded with the correct word (chosen from Table
IIB) for the time delay required and for single or repeated
interrupts.
The internal data busses of the MM58274C are fully CMOS,
contributing to the flexibility of the control inputs. When de-
termining the suitability of any given control signal pattern
for the MM58274C the timing specifications in AC Switching
Characteristics should be examined. As long as these tim-
ings are met (or exceeded) the MM58274C will function cor-
rectly.
3) Write 0 or 2 to the control register: Interrupt timing com-
mences. Writing 0 selects the clock setting register onto the
data bus; writing 2 leaves the interrupt register selected.
Normal timekeeping remains unaffected.
On Interrupt:
Read the control register and test for Interrupt Flag (bit 0).
When the MM58274C is connected to the system via a pe-
ripheral port, the freedom from timing constraints allows for
very simple control signal generation, as in Figure 7. For
reading (Figure 7a), Address, CS and RD may be activated
simultaneously and the data will be available at the port
If the flag is cleared (logic 0), then the device is not the
source of the interrupt.
If the flag is set (logic 1), then the clock did generate an
interrupt. The flag is reset and the interrupt output is cleared
by the control register read that was used to test for inter-
rupt.
after t -max (650 ns). For writing (Figure 7b), the address
AD
and data may be applied simultaneously; 70 ns later CS and
WR may be strobed together.
10
Functional Description (Continued)
TL/F/11219–8
FIGURE 5. MM58274C Microprocessor Interface Diagram
TL/F/11219–9
FIGURE 6. Valid MM58274C Control Signals Using Chip Select Generated Access Strobes
11
Functional Description (Continued)
TL/F/11219–10
a. Port Generated Read AccessÐ2 Addresses Read Out
TL/F/11219–11
b. Port Generated Write AccessÐ2 Addresses Written To
FIGURE 7. Simple Port Generated Control Signals
12
Functional Description (Continued)
APPLICATION HINTS
2) Read control register AD0: This is a dummy read to reset
the data-changed flag.
Time Reading Using Interrupt
3) Read control register AD0 until data-changed flag is set.
In systems such as point of sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined in the section
on methods of operation is ideal for this type of system.
Some systems, however, need to sense a change in real
time; e.g., industrial timers/process controllers, TV/VCR
clocks, any system where real time is displayed.
4) Write 0 or 2 to control register. Interrupt timing com-
mences.
Time Reading with Very Slow Read Cycles
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS proces-
sors are used) or where high level interpreted language rou-
tines are used, then the data-changed flag will always be set
when tested and is of no value. In this case, the time regis-
ters themselves must be tested to ensure data accuracy.
The interrupt timer on the MM58274C can generate inter-
rupts synchronously with the time registers changing, using
software to provide the initial synchronization.
The technique below will detect both time changing be-
tween read strobes (i.e., between reading tens of minutes
and units of hours) and also time changing during read,
which can produce invalid data.
In single interrupt mode the processor is responsible for ini-
tiating each timing cycle and the timed period is accurate to
g
1 ms.
In repeated interrupt mode the period from the initial proces-
g
1) Read and store the value of thelowest order time register
required.
sor start to the first timeout is also only accurate to 1 ms.
The following interrupts maintain accurate delay periods rel-
ative to the first timeout. Thus, to utilize interrupt to control
time reading, we will use repeated interrupt mode.
2) Read out all the time registers required. The registers
may be read out in any order, simplifying software require-
ments.
In repeated mode the time period between interrupts is ex-
act, which means that timeouts will always occur at the
same point relative to the internal clock setting pulses. The
case for 0.1s interrupts is shown in Figure A-1. The same is
true for other delay periods, only there will be more clock
setting pulses between each interrupt timeout. If we set up
the interrupt timer so that interrupt always times out just
after the clock setting pulse occurs (Figure A-2), then there
is no need to test the data-changed flag as we know that
the time data has just changed and will not alter again for
another 100 ms.
3) Read the lowest order register and compare it with the
value stored previously in step 1. If it is still the same, then
all time data is good. If it has changed, then store the new
value and go back to step 2.
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time reg-
ister to change, all the lower order registers must also
change. If the lowest order register does not change, then
no higher order register has changed either.
This can be achieved as outlined below:
1) Follow steps 1 and 2 of the section on interrupt program-
ming. In step 2 set up for repeated interrupt.
TL/F/11219–12
FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt is Constant
TL/F/11219–13
FIGURE A-2. Interrupt Timer Synchronized with Clock Setting Pulses
13
14
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number MM58274CJ
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM58274CN
NS Package Number N16A
15
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number MM58274CV
NS Package Number V20A
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