MM58341 [NSC]
High Voltage Display Driver; 高电压显示驱动
| 型号： | MM58341 |
| 厂家： | 
National Semiconductor |
| 描述： | High Voltage Display Driver |
| 文件： | 总6页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1991
MM58341 High Voltage Display Driver
General Description
Features
Y
Direct interface to high voltage display
The MM58341 is a monolithic MOS integrated circuit utiliz-
ing CMOS metal gate low threshold P and N-channel devic-
es. It is available both in 40-pin molded dual-in-line pack-
ages or as dice. The MM58341 is particularly suited for driv-
ing high voltage (35V max) vacuum fluorescent (VF) dis-
plays, (e.g., a 32-digit alphanumeric or dot matrix display).
Y
Serial data input
Y
No external resistors required
Y
Wide display power supply operation
Y
LSTTL compatible inputs
Y
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Y
Y
Y
Applications
COPSTM or microprocessor-driven displays
Y
Simple to cascade
Y
Instrumentation readouts
Y
Industrial control indicator
Y
Digital clock, thermostat, counter, voltmeter
Y
Word processor text displays
Y
Automotive dashboards
Block Diagram
TL/F/5603–1
FIGURE 1
COPSTM is a trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/5603
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
e
)
DD
V
0V
4.5
5.5
V
V
SS
b
b
a
Display Voltage (V
)
30
40
10
85
a
b
0.3V
DIS
Voltage at Any Input Pin
Voltage at Any Display Pin
V
DD
0.3V to V
SS
b
Temperature Range
C
§
b
V
to V
DD
36.5V
36.5V
DD
a
V
V
DIS
DD
l
Storage Temperature
l
b
a
65 C to 150 C
§
§
Power Dissipation at 25 C
§
Molded DIP Package, Board Mount
2.28W*
Molded DIP Package, Socket Mount
*Molded DIP Package, Board Mount,
2.05W**
46 C/W
§
e
e
i
i
JA
JA
Derate 21.7 mW C Above 25 C
§
§
**Molded DIP Package, Socket Mount,
51 C/W
§
Derate 19.6 mW/ C Above 25 C
§
§
Junction Temperature
130 C
§
Lead Temperature (Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics
e b
a
40 C to 85 C, V
e
e
5V 0.5V, V 0V unless otherwise specified
SS
g
T
A
§
§
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
0V,
I
Power Supply Currents
V
V
or V , V
DD SS
DD
IN
SS
Disconnected
150
mA
V
DIS
e
e b
e
0V,
I
V
V
5.5V, V
SS
DIS
DD
10
mA
V
30V, All Outputs Low
DIS
V
V
V
V
V
Input Logic Levels DATA IN,
IL
0.8
CLOCK ENABLE, BLANK Logic ‘0’
Input Logic Levels DATA IN,
(Note 1)
IH
2.4
V
CLOCK ENABLE, BLANK Logic ‘1’
e
400 mA
Data Output Logic Levels
Logic ‘0’
I
I
I
OH
OH
OH
OUT
OUT
OUT
0.4
V
e b
e b
Data Output Logic Levels
Logic ‘1’
10 mA
b
V
0.5
V
DD
Data Output Logic Levels
Logic ‘1’
500 mA
2.8
V
e
I
Input Currents DATA IN,
CLOCK ENABLE, BLANK
V
IN
0V or V
DD
IN
b
10
10
15
mA
pF
C
Input Capacitance DATA IN,
CLOCK ENABLE, BLANK
IN
e
e
0V
R
OFF
Display Output Impedances
Output Off(Figure 3a)
V
V
V
V
5.5V, V
DD
SS
e b
e b
e b
10V
20V
30V
55
60
65
250
300
400
kX
kX
kX
DIS
DIS
DIS
R
ON
Display Output Impedances
Output On(Figure 3b)
e b
e b
e b
V
DIS
V
DIS
V
DIS
10V
20V
30V
700
600
500
800
750
680
X
X
X
e
e
Open Circuit,
V
Display Output Low Voltage
V
5.5V, I
DOL
DD
OUT
a
V
DIS
V
DIS
2
V
s
s
b
b
30V
V
10V
DIS
OUT
@
@
I
e
e
b
e
400 mA, TTL V
OH
e b
400 mA.
Note 1: 74LSTTL V
2.7V
I
2.4V
OH
OUT
2
e b
a
e
DD
g
5V 0.5V
AC Electrical Characteristics T
Symbol
40 C to
§
85 C, V
§
A
Parameter
Conditions
Min
Typ
Max
Units
kHz
ns
f
t
t
t
t
t
t
t
Clock Input Frequency
Clock Input High Time
Clock Input Low Time
Data Input Setup Time
Data Input Hold Time
Enable Input Setup Time
Enable Input Hold Time
(Notes 3, 4)
800
C
300
300
100
100
100
100
H
ns
L
ns
DS
DH
ES
EH
CDO
ns
ns
ns
e
50 pF
Data Output Clock Low to
Data Out Time
C
L
500
ns
Note 2: Note that, for timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
s
s
20 ns, f
e
g
800 kHz, 50% 10% duty cycle.
Note 3: AC input waveform specification for test purpose: t
20 ns, t
r
f
Note 4: Clock input rise and fall times must not exceed 5 ms.
Connection Diagrams
Dual-In-Line Package
Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58341 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic ‘1’
will turn off all sections of the display. A block diagram of
the MM58341 is shown in Figure 1.
Figure 2 shows the pinout of the MM58341 device, where
output 1 (pin 18) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic ‘1’ at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58341, because external pull-
down resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3a
and 3b show that this output impedance will remain con-
stant for a fixed value of display voltage.
TL/F/5603–2
Top View
Order Number MM58341N
See NS Package Number N40A
Plastic Chip Carrier
Figure 4 demonstrates the critical timing requirements be-
tween CLOCK and DATA IN for the MM58341.
To clear (reset) the display driver at power on or any time,
the following flushing routine may be used. With the enable
signal high, clock in 32 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic ‘1’ does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., ‘0’–‘1’
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58341, being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure 6 shows a schematic diagram of a microprocessor-
based system where the MM58341 is used to provide the
grid drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent
(VF) display. The anode drive in this example is provided by
another member of the high voltage display driver family,
namely the MM58348, which does not require an externally
generated load signal.
TL/F/5603–8
Top View
Order Number MM58341V
See NS Package Number V44A
3
Functional Decription (Continued)
TL/F/5603–3
FIGURE 3a. Output Impedance Off
TL/F/5603–4
FIGURE 3b. Output Impedance On
Timing Diagrams
TL/F/5603–5
e
e
0.8V.
For the purposes of AC measurements, V
2.4V, V
IH
IL
FIGURE 4. Clock and Data Timings
TL/F/5603–6
FIGURE 5. MM58341 Timings (Data Format)
4
Typical Application
TL/F/5603–7
FIGURE 6. Microprocessor-Controlled Word Processor
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number MM58341N
NS Package Number N40A
5
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier
Order Number MM58341V
NS Package Number V44A
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