MM74HC245AWM/A+ [NSC]
IC,BUS TRANSCEIVER,SINGLE,8-BIT,HC-CMOS,SOP,20PIN,PLASTIC;型号: | MM74HC245AWM/A+ |
厂家: | National Semiconductor |
描述: | IC,BUS TRANSCEIVER,SINGLE,8-BIT,HC-CMOS,SOP,20PIN,PLASTIC |
文件: | 总6页 (文件大小:130K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
January 1988
MM54HC245A/MM74HC245A
Octal TRI-STATE Transceiver
É
General Description
This TRI-STATE bidirectional buffer utilizes advanced sili-
con-gate CMOS technology, and is intended for two-way
asynchronous communication between data buses. It has
high drive current outputs which enable high speed opera-
tion even when driving large bus capacitances. This circuit
possesses the low power consumption and high noise im-
This device can drive up to 15 LS-TTL Loads, and does not
have Schmitt trigger inputs. All inputs are protected from
damage due to static discharge by diodes to V
ground.
and
CC
Features
munity usually associated with CMOS circuitry, yet has
speeds comparable to low power Schottky TTL circuits.
Y
Typical propagation delay: 13 ns
Wide power supply range: 2–6V
Low quiescent current: 80 mA maximum (74 HC)
Y
This device has an active low enable input G and a direction
control input, DIR. When DIR is high, data flows from the A
Y
Y
TRI-STATE outputs for connection to bus oriented
systems
inputs to the B outputs. When DIR is low, data flows from
B inputs to the A outputs. The MM54HC245A/
the
MM74HC245A transfers true data from one bus to the oth-
er.
Y
Y
High output drive: 6 mA (minimum)
Same as the ’645
Connection Diagram
Dual-In-Line Package
TL/F/5165–1
Top View
Order Number MM54HC245A or MM74HC245A
Truth Table
Control
Inputs
Operation
G
DIR
L
L
L
H
X
B data to A bus
A data to B bus
Isolation
H
e
e
e
low level, X irrelevant
H
high level, L
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/5165
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
CC
2
6
V
DC Input or Output Voltage
(V , V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
0
V
V
IN OUT
CC
b
b
a
a
DC Input Voltage DIR and G pins (V
)
1.5 to V
1.5V
0.5V
IN
CC
CC
Operating Temp. Range (T )
A
DC Input/Output Voltage (V , V
)
0.5 to V
IN OUT
b
b
a
85
a
125
MM74HC
MM54HC
40
55
C
§
§
g
g
g
Clamp Diode Current (I
)
20 mA
35 mA
70 mA
CD
C
DC Output Current, per pin (I
)
OUT
Input Rise/Fall Times
DC V or GND Current, per pin (I
CC
)
CC
e
V
CC
(t , t )
r f
2.0V
4.5V
6.0V
1000
500
ns
ns
ns
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
e
e
STG
V
CC
V
CC
Power Dissipation (P )
D
(Note 3)
400
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
25 C
§
A
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
V
V
V
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level Input
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Voltage**
e
V or V
IH IL
Minimum High Level Output
Voltage
V
I
OH
IN
s
20 mA
2.0V 2.0
4.5V 4.5
6.0V 6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 4.2 3.98
6.0V 5.7 5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level Output
Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 0.2 0.26
6.0V 0.2 0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
V to GND
CC
g
g
g
1.0
I
I
I
Input Leakage
V
6.0V
0.1
1.0
mA
mA
mA
IN
IN
Current (G and DIR)
e
V or GND 6.0V
CC
g
g
g
10
Maximum TRI-STATE Output
Leakage Current
V
0.5
5.0
OZ
CC
OUT
e
Enable G
V
IH
or GND
CC
e
Maximum Quiescent Supply
Current
V
IN
V
6.0V
8.0
80
160
e
I
0 mA
OUT
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
e
**V limits are currently tested at 20% of V . The above V specification (30%) of V ) will be implemented no later than Q1, CY’89. O
IL CC IL CC
V .
IL
2
e
e
e e
25 C, t t 6 ns
§
r f
AC Electrical Characteristics V
5V, T
CC
A
Guaranteed
Limit
Symbol
, t
Parameter
Conditions Typ
Units
e
t
t
Maximum Propagation Delay
Maximum Output Enable Time
C
45 pF
12
24
17
35
ns
ns
PHL PLH
L
e
e
, t
PZH PZL
R
1 kX
L
C
45 pF
L
e
e
t , t
PHZ PLZ
Maximum Output Disable Time
R
1 kX
18
25
ns
L
C
L
5 pF
e
e
e
t
f
e
AC Electrical Characteristics V
2.0V to 6.0V, C
50 pF, t
6 ns (unless otherwise specified)
54HC
CC
L
r
74HC
eb
e
T
25 C
§
A
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
e
e
t
t
,
Maximum Propagation Delay
C
C
50 pF
2.0V
31
41
90
96
113
116
135
128
ns
ns
PHL
L
150 pF 2.0V
PLH
L
e
e
C
C
50 pF
4.5V
13
17
18
22
23
28
27
33
ns
ns
L
150 pF 4.5V
L
e
e
C
C
50 pF
6.0V
11
14
15
19
19
23
23
28
ns
ns
L
150 pF 6.0V
L
e
t
t
,
Maximum Output Enable
Time
R
1 kX
PZH
L
PZL
e
e
C
C
50 pF
2.0V
71
81
190
240
240
300
285
360
ns
ns
L
150 pF 2.0V
L
e
e
C
C
50 pF
4.5V
26
31
38
48
48
60
57
72
ns
ns
L
150 pF 4.5V
L
e
e
C
C
50 pF
6.0V
21
25
32
41
41
51
48
61
ns
ns
L
150 pF 6.0V
L
e
e
t
t
,
Maximum Output Disable
Time
R
1 kX
2.0V
4.5V
6.0V
39
20
18
135
27
169
34
203
41
ns
ns
ns
PHZ
L
C
L
50 pF
PLZ
23
29
34
e
t , t
TLH THL
Output Rise and Fall Time
C
L
50 pF
2.0V
4.5V
6.0V
20
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
5
e
e
C
PD
Power Dissipation
G
G
V
V
50
5
pF
pF
IL
Capacitance (Note 5)
IH
C
C
Maximum Input Capacitance
5
10
20
10
20
10
20
pF
pF
IN
Maximum Input/Output
Capacitance, A or B
15
IN/OUT
2
e
a
e
a
V f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I V
CC CC
, and the no load dynamic current consumption, I
C
.
D
S
3
Logic Diagram
TL/F/5165–2
4
Physical Dimensions inches (millimeters)
Order Number MM54HC245A or MM74HC245A
NS Package J20A
5
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HC245A
NS Package N20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
(
49) 0-180-530 85 86
@
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a
a
a
a
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English Tel:
Fran3ais Tel:
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(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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