MM74HC280 [NSC]
9-Bit Odd/Even Parity Generator/Checker; 9位奇/偶校验发生器/校验器
| 型号： | MM74HC280 |
| 厂家： | 
National Semiconductor |
| 描述： | 9-Bit Odd/Even Parity Generator/Checker |
| 文件： | 总4页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC280/MM74HC280
9-Bit Odd/Even Parity Generator/Checker
General Description
Features
Y
The MM54HC280/MM74HC280 utilizes advanced silicon-
gate CMOS technology to achieve the high noise immunity
and low power consumption of standard CMOS integrated
circuits. It possesses the ability to drive 10 LS-TTL loads.
Typical propagation delay: 28 ns
Y
Wide power supply range: 2V–6V
Y
Low quiescent current: 80 mA maximum (74HC)
Low input current: 1 mA maximum
Fanout of 10 LS-TTL loads
Y
Y
This parity generator/checker features odd/even outputs to
facilitate operation of either odd or even parity applications.
The word length capability is easily expanded by cascading
devices. The 54HC/74HC logic family is speed, function,
and pinout compatible with the standard 54LS/74LS family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
TL/F/5121–1
Order Number MM54HC280 or MM74HC280
Function Table
Numbers of Inputs A
Outputs
thru 1 that are High
R Even
R Odd
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
L
H
e
e
low level
H
high level,
L
C
1995 National Semiconductor Corporation
TL/F/5121
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
54HC
e
T
A
25 C
§
eb
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
8.0
80
160
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I ,
IH IN
e
designing with this supply. Worst case V and V occur at V
IH IL
CC
I
, and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
CC
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e
t
f
e
6 ns
AC Electrical Characteristics V
5V, T
25 C, C
§
15 pF, t
CC
A
L
r
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t , t
PHL PLH
Maximum Propagation
Delay, Data to R Even
28
35
ns
t , t
PHL PLH
Maximum Propagation
Delay, Data to R Odd
28
35
ns
e
e
e
e
AC Electrical Characteristics V
2.0V to 6.0V, C
50 pF, t
t
f
6 ns (unless otherwise specified)
54HC
CC
L
r
74HC
eb
e
T
25 C
§
A
eb
T
40 to 85 C
T
A
55 to 125 C
§
Guaranteed Limits
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
t
t
t
, t
PHL PLH
Maximum Propagation
Delay, Data to R Even
2.0V 103 205
258
52
44
305
61
52
ns
ns
ns
4.5V
6.0V
21
17
41
35
, t
PHL PLH
Maximum Propagation
Delay, Data to R Odd
2.0V 103 205
258
52
44
305
61
52
ns
ns
ns
4.5V
6.0V
21
17
41
35
, t
TLH THL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
C
C
Power Dissipation
Capacitance (Note 5)
83
pF
PD
Maximum Input Capacitance
5
10
10
10
pF
IN
2
e
a
e
a
V f I
PD CC CC
Note 5:
C
determines the no load dynamic power consumption, P
C V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
.
PD
D
S
Logic Diagram
e
V
pin 14
CC
e
GND pin 7
’HC280
TL/F/5121–2
3
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM54HC280J or MM74HC280J
NS Package J14A
Dual-In-Line Package
Order Number MM74HC280J,N
NS Package N14A
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SEMICONDUCTOR CORPORATION. As used herein:
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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