MM74HC623N [NSC]
IC HC/UH SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20, Bus Driver/Transceiver;
| 型号： | MM74HC623N |
| 厂家： | 
National Semiconductor |
| 描述： | IC HC/UH SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20, Bus Driver/Transceiver |
| 文件： | 总4页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
MM54HC620/MM74HC620 Inverting
Octal TRI-STATE Transceiver
É
MM54HC623/MM74HC623 True
Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional buffers utilize advanced sili-
con-gate CMOS technology and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption and high noise
immunity usually associated with CMOS circuitry, yet have
speeds comparable to low power Schottky TTL circuits.
These devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus depending on the
logic levels at the enable inputs. Both buses can be isolated
from each other with proper logic levels at the enable in-
puts. When GAB is taken high and GBA is taken low, these
devices store the states presently appearing at the data in-
puts. The 8-bit codes appearing on the two sets of buses
will be indentical for the 623 option or complimentary for the
620 option.
These devices can drive up to 15 LS-TTL loads. All inputs
are protected from damage due to static discharge by di-
odes to V
CC
and ground.
Features
Y
Typical propagation delays: 13 ns
Y
Wide power supply range: 2V–6V
Y
Low quiescent supply current: 80 mA
maximum (74HC series)
Y
TRI-STATE outputs for connection to system buses
Y
High output drive: 6 mA (minimum)
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/9393–2
TL/F/9393–1
Top View
Top View
Order Number MM54HC620 or MM74HC620
Order Number MM54HC623 or MM74HC623
Truth Table
Enable Inputs
Operation
GBA
L
GAB
L
H
L
B data to A bus
B data to A bus
A data to B bus
Isolation
H
A data to B bus
Isolation
H
B data to A bus,
A data to B bus
B data to A bus,
A data to B bus
L
L
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9393
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
CC
2
6
V
DC Input or Output Voltage
(V , V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
)
0
V
CC
V
IN OUT
b
a
a
DC Input Voltage DIR and G pins (V
)
IN
1.5V to V
1.5V
0.5V
CC
CC
Operating Temp. Range (T )
A
b
0.5 to V
DC Output Voltage (V , V
)
b
b
a
85
a
125
IN OUT
MM74HC
MM54HC
40
55
C
§
§
g
Clamp Diode Current (I
)
CD
20 mA
35 mA
70 mA
C
g
DC Output Current, per pin (I
)
OUT
Input Rise/Fall Times
g
DC V or GND Current, per pin (I
CC
)
CC
e
e
e
(t , t )
r f
V
CC
V
CC
V
CC
2.0V
4.5V
6.0V
1000
500
ns
ns
ns
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
400
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HC
a
40 C to 85 C
54HC
a
55 C to 125 C Units
e
T
A
25 C
§
e b
e b
T
A
Symbol
Parameter
Conditions
V
T
A
§
§
§
§
CC
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V 2.0
4.5V 4.5
6.0V 6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 4.2 3.98
6.0V 5.7 5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 0.2 0.26
6.0V 0.2 0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
I
I
Input Leakage
V
V
or GND
IN
IN
CC
g
g
g
g
g
1.0
6.0V
6.0V
0.1
0.5
1.0
5.0
mA
mA
Current (G and DIR)
e
Enable G
Maximum TRI-STATE
Output Leakage
Current
V
V
or GND
OZ
OUT
CC
e
g
10
V
IH
e
I
Maximum Quiescent
Supply Current
V
V
or GND
CC
IN
CC
6.0V
8.0
80
160
mA
e
I
0 mA
OUT
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power dissipation temperature deratingÐplastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e
t
f
AC Electrical Characteristics V
5V, T
25 C, t
§
6 ns
Typ
CC
A
r
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
Units
ns
e
t
t
Maximum Propagation Delay
C
45 pF
15
31
PHL PLH
L
e
e
, t
PZH PZL
Maximum Output Enable Time
R
1 kX
L
ns
C
45 pF
L
e
e
t , t
PHZ PLZ
Maximum Output Disable Time
R
1 kX
ns
L
18
C
L
5 pF
e
e
e
e
t 6 ns unless otherwise specified
f
AC Electrical Characteristics V
2.0V to 6.0V, C
50 pF, t
CC
L
r
74HC
54HC
a
55 C to 125 C Units
e
T
25 C
§
A
e b
a
e b
40 C to 85 C T
§
A
Symbol
Parameter
Conditions
V
T
A
§
§
§
CC
Typ
Guaranteed Limits
e
e
t
t
,
Maximum Propagation
Delay
C
C
50 pF
2.0V
2.0V
85
105
130
130
160
ns
ns
PHL
L
150 pF
105
PLH
L
e
e
C
C
50 pF
4.5V
4.5V
17
21
21
26
26
32
ns
ns
L
150 pF
L
e
e
C
C
50 pF
6.0V
6.0V
14
18
18
22
22
27
ns
ns
L
150 pF
L
e
t
t
,
Maximum Output
Enable
R
1 kX
PZH
L
PZL
e
e
C
C
50 pF
2.0V
2.0V
170
195
215
245
255
295
ns
ns
L
150 pF
L
e
e
C
C
50 pF
4.5V
4.5V
34
39
43
49
51
59
ns
ns
L
150 pF
L
e
e
C
C
50 pF
6.0V
6.0V
29
33
37
42
43
50
ns
ns
L
150 pF
L
e
e
t
t
,
Maximum Output
Disable Time
R
1 kX
2.0V
4.5V
6.0V
130
26
165
33
195
39
ns
ns
ns
PHZ
L
C
L
50 pF
PLZ
22
28
33
e
t
t
,
Output Rise and
Fall Time
C
L
50 pF
2.0V
4.5V
6.0V
60
12
10
75
15
13
90
18
15
ns
ns
ns
THL
TLH
e
, GAB
C
C
C
Power Dissipation
GBA, GAB
e
V
120
12
pF
pF
PD
IL
e
V
IL
Capacitance (Note 5) GBA
V
IH
Maximum Input
Capacitance
5
10
20
10
20
10
20
pF
IN
Maximum Input/Output
Capacitance, A or B
IN/OUT
15
pF
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC620, MM54HC623, MM74HC620 or MM74HC623
NS Package Number J20A
Molded Dual-In-Line Package (N)
Order Number MM54HC620, MM54HC623, MM74HC620 or MM74HC623
NS Package Number N20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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