MM74HC73N/A+ [NSC]
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,PLASTIC;
| 型号： | MM74HC73N/A+ |
| 厂家： | 
National Semiconductor |
| 描述： | IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,PLASTIC 振荡器 |
| 文件： | 总6页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC73/MM74HC73
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology. They possess the high noise immunity and low
power dissipation of standard CMOS integrated circuits.
These devices can drive 10 LS-TTL loads.
All inputs are protected from damage due to static dis-
and ground.
charge by internal diode clamps to V
CC
Features
Y
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent, J, K, CLOCK, and
CLEAR inputs and Q and Q outputs. CLEAR is independent
of the clock and accomplished by a low level on the input.
Typical propagation delay: 16 ns
Y
Wide operating voltage range: 2–6V
Y
Y
Y
Low input current: 1 mA maximum
Low quiescent current: 40 mA (74HC Series)
High output drive: 10 LS-TTL loads
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
Inputs
Outputs
CLR
CLK
J
K
Q
Q
L
X
X
L
X
L
L
Q0
H
H
Q0
L
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE
Q0 Q0
Top View
TL/F/5072–1
Order Number MM54HC73 or MM74HC73
TL/F/5072–2
TL/F/5072–3
(1 of 2)
C
1995 National Semiconductor Corporation
TL/F/5072
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
2
0
6
V
CC
DC Input or Output Voltage
(V , V
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
IN
CC
CC
Operating Temp. Range (T )
A
DC Output Voltage (V
)
0.5 to V
OUT
b
b
a
85
a
125
MM74HC
MM54HC
40
55
C
§
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
C
DC Output Current, per pin (I
)
OUT
Input Rise or Fall Times
DC V or GND Current, per pin (I
CC
)
CC
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
ns
ns
ns
CC
CC
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
400
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
4.0
40
80
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
t
r f
AC Electrical Characteristics V
Symbol
5V, T
25 C, C
15 pF, t
6 ns
Guaranteed Limit
§
Conditions
CC
A
L
Parameter
Typ
Units
f
t
t
t
t
t
t
Maximum Operating
Frequency
50
30
21
26
20
20
0
MHz
MAX
, t
PHL PLH
Maximum Propagation
Delay Clock to Q or Q
16
21
10
14
ns
ns
ns
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay Clear to Q or Q
Minimum Removal Time,
Clear to Clock
REM
S
Minimum Setup Time,
J or K to Clock
b
Minimum Hold Time
J or K to Clock
3
H
Minimum Pulse Width,
Clock or Clear
10
16
W
e
e
t
f
e
AC Electrical Characteristics C 50 pF, t
6 ns (unless otherwise specified)
L
r
74HC
40 to 85 C
54HC
55 to 125 C
e
T
25 C
§
A
eb
eb
T
T
Symbol
Parameter
Conditions
V
§
Guaranteed Limits
§
Units
A
A
CC
Typ
f
t
t
t
t
t
t
t
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
32
4
21
25
3
18
21
MHz
MHz
MHz
MAX
, t
PHL PLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
70
18
15
126
25
21
160
32
27
185
37
32
ns
ns
ns
, t
PHL PLH
Maximum Propagation
Delay Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
194
39
32
250
47
40
ns
ns
ns
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
55
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
REM
S
Minimum Setup Time
J or K to Clock
2.0V 77
4.5V 15.4
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
13
b
b
b
Minimum Hold Time
J or K from Clock
2.0V
4.5V
6.0V
3
3
3
0
0
0
0
0
0
0
0
0
ns
ns
ns
H
Minimum Pulse Width
Clock or Clear
2.0V
4.5V
6.0V
55
11
9
80
16
14
100
20
18
120
24
21
ns
ns
ns
W
, t
TLH THL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
t , t
r f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
C
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
80
5
pF
PD
Maximum Input
Capacitance
10
10
10
pF
IN
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Typical Applications
N Bit Binary Ripple Counter with Enable and Reset
TL/F/5072–4
N Bit Shift Register with Clear
TL/F/5072–5
4
5
Physical Dimensions inches (millimeters)
Dual-In Line Package (J)
Order Number MM54HC73J or MM74HC73J
NS Package J14A
Dual-In Line Package (N)
Order Number MM74HC73N
NS Package N14A
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to the user.
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support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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