MM74HCT643 [NSC]
Inverting Octal TRI-STATE Transceiver; 反相八路三态收发器
| 型号： | MM74HCT643 |
| 厂家： | 
National Semiconductor |
| 描述： | Inverting Octal TRI-STATE Transceiver |
| 文件： | 总4页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
MM54HCT640/MM74HCT640
Inverting Octal TRI-STATE Transceiver
É
MM54HCT643/MM74HCT643
True-Inverting Octal TRI-STATE Transceiver
General Description
TheseTRI-STATEbi-directionaltransceiversutilizeadvanced
silicon-gate CMOS technology and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption of CMOS cir-
cuitry, yet have speeds comparable to low power Schottky
TTL circuits.
MM74HCT640 transfers inverted data from one bus to the
other. The MM54HCT643/MM74HCT643 transfers inverted
data from the A bus to the B bus and non-inverted data from
the B bus to the A bus.
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
All devices are TTL input compatible and can drive up to 15
LS-TTL loads, and all inputs are protected from damage due
Features
Y
to static discharge by diodes to V
and ground.
CC
TTL input compatible
Both the MM54HCT640/MM74HCT640 and the
MM54HCT643/ MM74HCT643 have one active low enable
input (G), and a direction control (DIR). When the DIR input
is high, data flows from the A inputs to the B outputs. When
DIR is low, data flows from B to A. The MM54HCT640/
Y
Octal TRI-STATE outputs for mP bus applications:
6 mA, typical
Y
High speed: 16 ns typical propagation delay
Y
Low power: 80 mA maximum (74HCT)
Connection Diagram
Dual-In-Line Packages
TL/F/5370–1
TL/F/5370–2
Top View
Order Number MM54HCT643 or MM74HCT643
Top View
Order Number MM54HCT640 or MM74HCT640
Truth Table
Control
Inputs
Operation
G
L
DIR
L
640
643
B data to A bus B data to A bus
A data to B bus A data to B bus
L
H
H
X
Isolation
Isolation
e
e e
high level, L low level, X irrelevant
H
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/5370
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.5
Units
V
Supply Voltage (V
)
CC
4.5
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HCT
MM54HCT
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
35 mA
70 mA
IK OK
Input Rise or Fall Times
(t , t )
DC Output Current, per pin (I
)
OUT
500
ns
r
f
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
e
g
5V 10% (unless otherwise specified)
DC Electrical Characteristics V
CC
74HCT
54HCT
e
T
25 C
§
A
eb
eb
A
T
40 to 85 C
T
55 to 125 C
§
§
Guaranteed Limits
Symbol
Parameter
Conditions
Units
A
Typ
V
V
V
Minimum High Level
Input Voltage
2.0
0.8
2.0
2.0
0.8
V
V
IH
Maximum Low Level
Input Voltage
0.8
IL
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
e
e
e
20 mA
V
V
-0.1
CC
3.98
V
-0.1
CC
V
-0.1
CC
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
CC
4.5V 4.2
5.5V 5.2
e
e
I
I
6.0mA, V
7.2mA, V
3.84
4.84
3.7
4.7
CC
4.98
CC
e
V or V
IH IL
V
OL
Maximum Low Level
Voltage
V
IN
e
e
e
I
20 mA
0
4.5V 0.2
5.5V 0.2
0.1
0.1
0.1
0.4
0.4
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
e
e
I
I
6.0mA, V
7.2mA, V
0.26
0.26
0.33
0.33
CC
CC
e
V or GND,
CC
g
g
g
1.0
I
I
Maximum Input
Current
V
0.1
1.0
mA
IN
IN
IH
V
or V
IL
e
Enable G
g
g
g
10
Maximum TRI-STATE
Output Leakage
Current
V
V or GND
CC
0.5
5.0
mA
OZ
CC
OUT
e
V
IH
e
I
Maximum Quiescent
Supply Current
V
IN
V
or GND
8
80
160
1.5
mA
CC
0mA
e
I
OUT
e
(Note 4)
V
IN
2.4V or 0.5V
0.6
1.0
1.3
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
§
§
Note 4: Measured per input. All other inputs held at V
CC
or ground.
AC Electrical Characteristics MM54HCT640/MM74HCT640
e
e
e
e
6 ns, T 25 C (unless otherwise specified)
A
V
5.0V, t
t
§
CC
r
f
Guaranteed
Limits
Symbol
Parameter
Conditions
Typ
Units
e
t
t
t
, t
PHL PLH
Maximum Output
Propagation Delay
C
45 pF
16
20
40
25
ns
L
e
e
, t
PZL PZH
Maximum Output
Enable Time
C
L
45 pF
29
20
ns
ns
R
1 kX
L
e
e
, t
PLZ PHZ
Maximum Output
Disable Time
C
L
5 pF
R
1 kX
L
2
AC Electrical Characteristics MM54HCT640/MM74HCT640
e
e e
t 6 ns (unless otherwise specified)
f
g
V
5.0V
10%, t
CC
r
74HCT
eb
54HCT
55 to 125 C
e
T
25 C
§
A
eb
T
40 to 85 C
T
Symbol
Parameter
Conditions
Units
§
Guaranteed Limits
§
A
A
Typ
17
e
e
e
t
, t
PHL PLH
Maximum Output
Propagation Delay
C
C
50 pF
150 pF
1kX
23
30
30
29
38
38
34
45
45
ns
ns
ns
L
24
L
e
L
t
t
t
, t
PZH PZL
Maximum Output
Enable Time
R
C
50 pF
23
L
e
e
, t
PHZ PLZ
Maximum Output
Disable Time
R
1kX
50 pF
21
8
30
12
15
25
38
15
15
25
45
18
15
25
ns
ns
pF
pF
L
L
C
C
e
, t
THL TLH
Maximum Output
Rise and Fall Time
50 pF
L
C
C
C
Maximum Input
Capacitance
10
20
IN
Maximum Output/
Input Capacitance
OUT
PD
e
e
Power Dissipation
Capacitance (Note 5)
(per output)
G
G
V
CC
GND
7
100
pF
pF
AC Electrical Characteristics MM54HCT643/MM74HCT643
e
e
e
e
6 ns, T 25 C (unless otherwise specified)
A
V
5.0V, t
t
f
§
CC
r
Guaranteed
Limits
Symbol
, t
Parameter
Conditions
Typ
Units
e
t
t
t
Maximum Output
Propagation Delay
C
L
45 pF
16
20
40
25
ns
ns
ns
PHL PLH
e
e
, t
PZL PZH
Maximum Output
Enable Time
C
R
45 pF
1 kX
29
20
L
L
e
e
, t
PLZ PHZ
Maximum Output
Disable Time
C
R
5 pF
1 kX
L
L
AC Electrical Characteristics MM54HCT643/MM74HCT643
e
e e
t 6 ns (unless otherwise specified)
f
g
5.0V 10%, t
V
CC
r
74HCT
54HCT
55 to 125 C
e
T
25 C
§
A
eb
eb
T
40 to 85 C
T
Symbol
Parameter
Conditions
Units
§
Guaranteed Limits
§
A
A
Typ
17
e
e
e
t
, t
PHL PLH
Maximum Output
Propagation Delay
C
C
50 pF
150 pF
1 kX
23
30
30
29
38
38
34
45
45
ns
ns
ns
L
24
L
e
L
t
t
t
, t
PZH PZL
Maximum Output
Enable Time
R
C
50 pF
23
L
e
e
, t
PHZ PLZ
Maximum Output
Disable Time
R
1 kX
50 pF
21
8
30
12
15
25
38
15
15
25
45
18
15
25
ns
ns
L
L
C
C
e
, t
THL TLH
Maximum Output
Rise and Fall Time
50 pF
ns
pF
pF
L
C
C
C
Maximum Input
Capacitance
10
20
IN
Maximum Output/
Input Capacitance
OUT
e
Power Dissipation
Capacitance (Note 5)
(per output)
G
G
V
CC
GND
7
100
pF
pF
PD
e
2
e
a
e
a
V I
PD CC CC
Note 5:
C
determines the no load power consumption. P
C
V
PD CC
f
I
V
CC CC
. The no load dynamic current consumption, I
C
.
PD
D
S
3
Physical Dimensions inches (millimeters)
Cavity Dual-In line Package (J)
Order Number MM54HCT640J, MM54HCT643J, MM74HCT640J, or MM74HCT643J
See NS Package J20A
Moulded Dual-In line Package (N)
Order Number MM74HCT640N or MM74HCT643N
See NS Package N20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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