MM82PC12JI [NSC]
IC,I/O PORT,8-BIT,CMOS,DIP,24PIN,CERAMIC;
| 型号： | MM82PC12JI |
| 厂家： | 
National Semiconductor |
| 描述： | IC,I/O PORT,8-BIT,CMOS,DIP,24PIN,CERAMIC |
| 文件： | 总8页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1987
MM82PC12 8-Bit Input/Output Port
General Description
Features
Y
Y
Y
Y
Y
Y
Y
Y
Drive capabilityÐ150 pF load
The MM82PC12 is a microCMOS 8-bit input/output port
contained in a standard 24-pin dual-in-line package. The
MM82PC12 can be used to implement latches, gated buff-
ers, or multiplexers. Thus, all of the major peripheral and
input/output functions of a microcomputer system can be
implemented with this device.
High noise immunity
Low power dissipation
Full interface to CMOS logic levels
microCMOS technology
e
TTL drive capability when V
8-bit data latch and buffer
5V
CC
The MM82PC12 includes an 8-bit latch with TRI-STATE
É
output buffers, and device selection and control logic. Also
included is a service request flip-flop for the generation and
control of interrupts to the microprocessor.
Service request flip-flop for generation and control of
interrupts
Y
Y
1 mA input load current
The MM82PC12 is pinout and function compatible with stan-
dard INS8212 and DP8212 devices.
Reduces system package count by replacing buffers,
latches, and multiplexers in microcomputer systems
For military applications, the MM82PC12 is available with
class B screening in accordance with method 5004 of MIL-
STD-883.
System Configuration
TL/C/5596–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/C/5596
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed. Con-
tinuous operation at these limits is not intended; operation
should be limited to those conditions specified under DC
Electrical Characteristics.
b
a
65 C to 150 C
Storage Temperature Range
§
§
Voltage at Any Pin With
Respect to Ground
b
a
0.3V
0.3V to V
CC
e
g
5V 10%
Operating Range V
Ambient Temperature
Military
CC
Lead Temperature
(Soldering, 10 seconds)
300 C
§
500 mW
b
a
55 C to 125 C
§
§
§
Power Dissipation
b
a
40 C to 85 C
§
Industrial
Maximum V
7V
CC
a
0 C to 70 C
Commercial
§
§
DC Electrical Characteristics
e
e
g
5V 10%, GND
V
CC
0V, unless otherwise specified
Symbol
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
Output High Current
Output Low Current
Power Supply Current
Test Conditions
Min
Typ
Max
Units
V
V
V
V
V
0.7 V
0
V
CC
IH
CC
0.2 V
V
IL
CC
e
e
e
e
e
e
e
e
e
e
e
e
e b
2 mA
OH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
4.5V, V
5.5V, V
5.5V, V
5.5V, V
4.5V, V
5.5V, V
5.5V, V
5.5V, V
4.5V, I
2.4
V
OH
OL
IH
e
e
2 mA
0V, V
5.5V
0V
5.5V, I
0.4
10
V
IL
IH
OL
I
I
I
I
I
I
mA
mA
mA
mA
mA
mA
IH
IN
IN
b
10
IL
e
e
e
e
b
2.4V, V
0.4V, V
4.5V
0V
2.0
OH
OL
CC
OZL
OUT
OUT
IH
2.0
IL
e
e
5.5V, V
IL
0V
400
IH
e
b
10
TRI-STATE Low Leakage
Current
0V
OUT
e
e
I
TRI-STATE High Leakage
Current
V
CC
4.5V, V
4.5V
10
mA
OZH
OUT
AC Electrical Characteristics
e
e b
a
55 C to 125 C, V
e
0V, unless otherwise specified
g
5V 10%, GND
T
A
§
§
CC
Symbol
Parameter
Test Conditions
Min
Typ
25
Max
40
Units
ns
t
Pulse Width (STB, DS1 DS2, CLR)
#
PW
t
t
t
t
t
t
t
t
Data In to Data Out
Write Enable to Data Out
Data Setup Time
45
60
ns
PD
WE
SET
H
55
75
ns
15
20
ns
Data Hold Time
ns
Reset to Data Out
Select to Interrupt
50
50
45
50
65
65
60
65
ns
R
ns
S
Clear to Data Out
ns
C
Output Enable/Disable Time
ns
ED
2
Timing Waveforms
Read Timing
TL/C/5596–2
Write Timing
TL/C/5596–3
Data Setup, Hold Delay Timing
TL/C/5596–4
Interrupt Timing
TL/C/5596–5
Clear Timing
TL/C/5596–6
3
Propagation Delays
Figure 1 illustrates the calculations of a more useful propa-
Pin Descriptions
The following describes the function of all the MM82PC12
input/output pins. Some of these descriptions reference in-
ternal circuits.
gation delay. The figure uses a 5V supply with a tolerance of
a
g
tance of 100 pF. The AC Characteristics table depicts t
10%, ambient temperature of 25 C, and a load capaci-
§
,
PD
at 5V, 25 C, equalling 25 ns. Use the graph inFigure 1 to get
INPUT SIGNALS
§
Device Select (DS , DS : When DS is low and DS is high,
1
1
2
2
the degradation multiple for 150 pF. The number shown is
c
the device is selected. The output buffers are enabled and
the service request flip-flop is asynchronously reset
(cleared) when the device is selected.
1.09. The adjusted propagation delay is, therefore 25
1.09 or 27 ns.
Mode (MD): When MD is high (output mode), the output
buffers are enabled and the source of the data latch clock
input is the device selection logic (DS
DS ). When MD is
2
#
1
low (input mode), the state of the output buffers is deter-
mined by the device selection logic (DS DS ) and the
source of the data latch clock input is the strobe (STB) in-
put.
#
TL/C/5596–7
*Including jig and probe capacitance.
Output Test Circuit
1
2
for Propagation Delays
Strobe (STB): STB is used as the data latch clock input
when the mode (MD) input is low (input mode). STB is also
used to synchronously set the service request flip-flop,
which is negative edge triggered.
Data In (DI –DI ): Data In is the 8-bit data input to the data
8
1
latch, which consists of eight D-type flip-flops incorporating
a level sensitive clock. While the data latch clock input is
high, the Q output of each flip-flop follows the data input.
When the clock input returns low, the data latch stores the
data input. Clear (CLR) is only effective when the clock is
low (latch in the latched state).
TL/C/5596–8
Clear (CLR): When CLR is low, the data latch is reset
(cleared) if the clock is also low. The clock input high over-
rides the clear (CLR) input data latch reset. CLR being low
also resets the service request flip-flop. The service request
flip-flop is in the non-interrupting state when reset.
OUTPUT SIGNALS
Interrupt (INT): The interrupt pin goes low (interrupting
state) when either the service request flip-flop is synchro-
nously set by the strobe (STB) input or the device is select-
ed.
Data Out (DO –DO ): Data Out is the 8-bit data output of
8
1
data buffers, which are TRI-STATE, non-inverting stages.
These buffers have a common control line that either en-
ables the buffers to transmit the data from the data latch
outputs or disables the buffers by placing them in the high-
impedance state.
TL/C/5596–9
FIGURE 1. Normalized Typical Propagation Delay vs.
Load Capacitance
Reliability Information
Gate Count 108
Transistor Count 248
4
Connection Diagrams
Logic Diagram
Dual-In-Line Package
TL/C/5596–10
Top View
Order Number MM82PC12J or N
See NS Package Number J24A or
N24A
Plastic Chip Carrier
TL/C/5596–11
TL/C/5596–12
Top View
Order Number MM82PC12V
See NS Package Number V28A
Logic Table A
Logic Table B
Data Out
Equals
CLR
DS DS
#
STB
Q*
INT
1
2
STB
MD
DS DS
#
1
2
0 RESET
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
TRI-STATE
TRI-STATE
Data Latch
Data Latch
Data Latch
1
1
1
1
K
0
1 RESET
0
0
*Internal Service Request flip-flop.
Data In
Data In
Data In
Note: CLR K resets data latch to the output low state. The data latch
clock is level sensitive, a low level clock latches the data.
5
Applications in Microcomputer Systems
TL/C/5596–13
Gated Buffer
(TRI-STATE)
TL/C/5596–14
Bidirectional Bus Driver
TL/C/5596–15
Interrupting Input Port
TL/C/5596–16
Interrupt Instruction Port
TL/C/5596–17
Output Port (with Handshaking)
6
Ordering Information
TL/C/5596–18
Note 1: Do not specify a temperature option; all parts are screened to military temperature.
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM82PC12J
NS Package J24A
Molded Dual-In-Line Package (N)
Order Number MM82PC12N
NS Package N24A
7
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier Package (V)
Order Number MM82PC12V
NS Package V28A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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