NM93C06L [NSC]
256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface); 256 / 1024 / 2048- / 4096位串行EEPROM ，支持扩展电压（ 2.7V至5.5V ） （ MICROWIRE总线接口）
| 型号： | NM93C06L |
| 厂家： | 
National Semiconductor |
| 描述： | 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface) |
| 文件： | 总12页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1996
NM93C06L/C46L/C56L/C66L
256-/1024-/2048-/4096-Bit Serial EEPROM
with Extended Voltage (2.7V to 5.5V)
(MICROWIRETM Bus Interface)
General Description
The
Features
Y
2.7V to 5.5V operation in all modes
NM93C06L/C46L/C56L/C66L
devices
are
Y
256/1024/2048/4096 bits, respectively, of non-volatile
electrically erasable memory divided into 16/64/128/256 x
16-bit registers (addresses). The NM93CxxL Family func-
tions in an extended voltage operating range, requires only
a single power supply and is fabricated using National Semi-
conductor’s floating gate CMOS technology for high reliabili-
ty, high endurance and low power consumption. These de-
vices are available in both SO and TSSOP packages for
small space considerations.
Typical active current of 100 mA; Typical standby
current of 1 mA
Y
Y
Y
Y
Y
Y
Y
Y
No erase required before write
Reliable CMOS floating gate technology
MICROWIRE compatible serial I/O
Self-timed programming cycle
Device status during programming mode
40 years data retention
6
Endurance: 10 data changes
The EEPROM Interfacing is MICROWIRE compatible for
simple interface to standard microcontrollers and micro-
processors. There are 7 instructions that control these de-
vices: Read, Erase/Write Enable, Erase, Erase All, Write,
Write All, and Erase/Write Disable. The ready/busy status
is available on the DO pin during programming.
Packages available: 8-pin SO, 8-pin DIP, and 8-pin
TSSOP
Block Diagram
TL/D/10045–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/D/10045
RRD-B30M126/Printed in U. S. A.
http://www.national.com
Connection Diagrams
Dual-In-Line Package (N)
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
Pin Names
Chip Select
CS
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
GND
TL/D/10045–2
V
CC
Power Supply
Top View
NS Package Number N08E, M08A or MTC08
Ordering Information
a
Commercial Temp. Range (0 C to 70 C)
§
§
Order Number
NM93C06LN/NM93C46LN
NM93C56LN/NM93C66LN
NM93C06LM8/NM93C46LM8
NM93C56LM8/NM93C66LM8
NM93C06LMT8/NM93C46LMT8
NM93C56LMT8/NM93C66LMT8
b
a
Extended Temp. Range ( 40 C to 85 C)
§
§
Order Number
NM93C06LEN/NM93C46LEN
NM93C56LEN/NM93C66LEN
NM93C06LEM8/NM93C46LEM8
NM93C56LEM8/NM93C66LEM8
NM93C06LEMT8/NM93C46LEMT8
NM93C56LEMT8/NM93C66LEMT8
b
a
Automotive Temp. Range ( 40 C to 125 C)
§
§
Order Number
NM93C06LVN/NM93C46LVN
NM93C56LVN/NM93C66TLVN
NM93C06LVM8/NM93C46LVM8
NM93C56LVM8/NM93C66LVM8
NM93C06LVMT8/NM93C46LVMT8
NM93C56LVMT8/NM93C66LVMT8
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Ambient Operating Temperature
NM93C06L–NM93C66L
NM93C06LE–NM93C66LE
NM93C06LV–NM93C66LV
a
0 C to 70 C
§
§
b
b
a
40 C to 85 C
§
§
40 C to 125 C
a
§
§
2.7V to 5.5V
b
a
65 C to 150 C
Ambient Storage Temperature
§
§
Power Supply (V ) Range
CC
a
b
6.5V to 0.3V
All Input or Output Voltages
with Respect to Ground
a
Lead Temp. (Soldering, 10 sec.)
ESD Rating
300 C
§
2000V
k
k
4.5V
DC and AC Electrical Characteristics: 2.7 V
V
CC
Symbol
Parameter
Operating Current
Standby Current
Part Number
Conditions
Min
Max
1
Units
mA
e
e
e
e
I
I
CS
CS
V
V
, SK
250 kHz
CCA
CCS
IH
10
mA
IL
I
I
Input Leakage
V
IN
0V to V
IL
CC
g
1
mA
Output Leakage
OL
b
0.8 V
V
V
Input Low Voltage
Input High Voltage
0.1
0.15 V
IL
CC
1
V
V
a
V
CC
IH
CC
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
10 mA
0.1 V
OL
OL
CC
10 mA
0.9 V
OH
OH
CC
f
t
t
t
SK Clock Frequency
SK High Time
0
1
1
250
kHz
ms
SK
SKH
SKL
SKS
SK Low Time
ms
SK Setup Time
SK Must Be at V for
IL
0.2
1
ms
ms
t
before CS goes high
SKS
t
CS
Minimum CS
Low Time
(Note 2)
t
t
t
t
t
t
t
t
t
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
0.2
70
0.4
0
ms
ns
ms
ms
ms
ms
ms
ms
CSS
DH
DIS
CSH
DIH
PD1
PD0
SV
DI Hold Time
0.4
Output Delay to ‘‘1’’
Output Delay to ‘‘0’’
CS to Status Valid
CS to DO in
2
2
1
e
CS
V
IL
DF
0.4
15
ms
TRI-STATE
É
t
Write Cycle Time
ms
WP
3
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k
k
5.5V
DC and AC Electrical Characteristics: 4.5V
V
CC
Symbol
Parameter
Operating Current
Standby Current
Part Number
Conditions
Min
Max
1
Units
mA
e
e
e
e
I
I
CS
CS
V
V
, SK
1 MHz
CCA
CCS
IH
50
mA
IL
I
I
Input Leakage
V
IN
0V to V
CC
IL
g
1
mA
V
Output Leakage
(Note 4)
OL
b
V
V
Input Low Voltage
Input High Voltage
0.1
0.8
IL
a
2
V
1
IH
CC
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
2.1 mA
0.4
0.2
1
OL1
OL
V
400 mA
2.4
OH1
OH
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
10 mA
OL2
OL
V
MHz
ns
b
10mA
V
0.2
OH2
OL
CC
f
t
SK Clock Frequency
SK High Time
(Note 5)
0
SK
NM93C06L-NM93C66L
250
300
SKH
NM93C06LE-NM93C66LE
t
t
SK Low Time
250
50
ns
SKL
SK Setup TIme
SK Must Be at V for
IL
SKS
ns
t
before CS goes high
SKS
t
CS
Minimum CS
Low Time
(Note 2)
250
ns
t
t
t
CS Setup Time
DO Hold Time
DI Setup Time
50
70
ns
ns
CSS
DH
NM93C06L-NM93C66L
100
200
DIS
ns
NM93C06LE-NM93C66LE
t
t
t
t
t
t
CS Hold Time
0
ns
ns
ns
ns
ns
CSH
DIH
PD1
PD0
SV
DI Hold Time
20
Output Delay to ‘‘1’’
Output Delay to ‘‘0’’
CS to Status Valid
500
500
500
CS to DO in
TRI-STATE
DF
100
10
ns
e
CS
V
IL
t
Write Cycle Time
ms
WP
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4
Capacitance (Note 3)
e
e
T
A
25 C, f
§
1 MHz
Symbol
Test
Typ
Max
5
Units
pF
C
C
Output Capacitance
Input Capacitance
OUT
5
pF
IN
Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2: CS (Chip Select) must be brought low (to V ) for an interval of t in order to reset all internal device registers (device reset) prior to beginning another
IL CS
opcode cycle (this is shown in the opcode diagrams in the following pages).
Note 3: This parameter is periodically sampled and not 100% tested.
Note 4: Typical leakage values are in the 20 nA range.
e
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
Note 5: The shortest allowable SK clock period
1/f (as shown under the f parameter). Maximum SK clock speed (minimum SK period) is determined by the
SK SK
and t
limits must be observed. Therefore, it is not allowable to set
SKH
SKL
e
a
t
SKL (minimum)
1/t
SK
t
for shorter SK cycle time operation.
SKH (minimum)
AC Test Conditions
V
/V
IL IH
V
/V
IL IH
V
/V
OL OH
V
Range
I
/I
OL OH
CC
Input Levels
Timing Levels
Timing Levels
s
k
g
10 mA
2.7V
V
CC
4.5V
0.3V/1.8V
1.0V
0.8V/1.5V
(Extended Voltage Levels)
s
s
5.5V
b
2.1 mA/0.4 mA
4.5V
V
CC
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
(TTL Levels)
e
Output Load: 1 TTL Gate (C
100 pF)
L
Functional Description
The NM93C06L/C46L/C56L/C66L device have 7 instruc-
tions as described below. Note that the MSB of any instruc-
tion is a ‘‘1’’ and is viewed as a start bit in the interface
sequence. For the C06 and C46 the next 8 bits carry the op
code and the 6-bit address for register selection. For the
C56 and C66 the next 10-bits carry the op code and the 8-
bit address for register selection.
instruction. Once an Erase/Write Enable instruction is exe-
cuted, programming remains enabled until an Erase/Write
Disable (WDS) instruction is executed or V
removed from the part.
is completely
CC
Erase (ERASE):
The ERASE instruction will program all bits in the selected
register to the logical ‘‘1’’ state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
Read (READ):
The READ instruction outputs serial data on the DO pin.
After a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register.
A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
The DO pin indicates the READY/BUSY status of the chip if
e
indicates that programming is still in progress. DO
CS is brought high after the t interval. DO
CS
logical ‘‘0’’
e
logical
‘‘1’’ indicates that the register, at the address specified in
the instruction, has been erased, and the part is ready for
another instruction.
Erase/Write Enable (WEN):
When V is applied to the part, it powers up in the Erase/
CC
Write Disable (WDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable WEN
5
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Functional Description (Continued)
Write (WRITE):
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
The WRITE instruction is followed by 16 bits of data to be
written into the specificed address. After the last bit of data
is put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of CS
initiates the self-timed programming cycle. The DO pin indi-
cates the READY/BUSY status of the chip if CS is brought
CS is brought high after the t interval.
CS
Write All (WRALL):
The WRALL instruction will simultaneously program all reg-
isters with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
e
logical 0 indicates that
high after the t
interval. DO
programming is still in progress. DO
CS
e
logical 1 indicates
status of the chip if CS is brought high after the t interval.
CS
that the register at the address specified in the instruction
has been written with the data pattern specified in the in-
struction and the part is ready for another instruction.
Write Disable (WDS):
To protect against accidental data distrub, the WDS instruc-
tion disables all programming modes and should follow all
programming operations. Execution of a READ instruction is
independent of both the WEN and WDS instructions.
Erase All (ERAL):
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical ‘‘1’’
Note: NSC CMOS EEPROMs do not require an ‘‘ERASE’’ or ‘‘ERASE ALL’’ operation prior to the ‘‘WRITE’’ and ‘‘WRITE ALL’’ instructions. The ‘‘ERASE’’ and
‘‘ERASE ALL’’ instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the NM93C06L and NM93C46L
Instruction
READ
SB
1
Op Code
Address
A5–A0
Data
Comments
Reads data stored in memory at specified address.
Enable all programming modes.
Erase selected register.
10
00
11
01
00
00
00
WEN
1
11XXXX
A5–A0
ERASE
WRITE
ERAL
1
1
A5–A0
D15–D0
D15–D0
Writes selected register.
1
10XXXX
01XXXX
00XXXX
Erases all registers.
WRALL
WDS
1
Writes all registers.
1
Disables all programming modes.
Note: Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93C06L.
Instruction Set for the NM93C56L and NM93C66L
Instruction
READ
SB
1
Op Code
Address
A7–A0
Data
Comments
Reads data stored in memory at specified address.
Enable all programming modes.
Erase selected register.
10
00
11
01
00
00
00
WEN
1
11XXXXXX
A7–A0
ERASE
WRITE
ERAL
1
1
A7–A0
D15–D0
D15–D0
Writes selected register.
1
10XXXXXX
01XXXXXX
00XXXXXX
Erases all registers.
WRALL
WDS
1
Writes all registers.
1
Disables all programming modes.
Note: Address bit A7 is ‘‘Don’t Care’’ for the NM93C56L.
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6
Timing Diagrams
Synchronous Data Timing
TL/D/10045–13
READ
TL/D/10045–5
WEN
TL/D/10045–6
7
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Timing Diagrams (Continued)
WDS
TL/D/10045–7
WRITE
TL/D/10045–8
WRALL
TL/D/10045–9
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8
Timing Diagrams (Continued)
ERASE
TL/D/10045–10
ERAL
TL/D/10045–11
9
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Physical Dimensions inches (millimeters) unless otherwise noted
Molded Small Out-Line Package (M8)
NS Package Number M08A
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Pin Molded TSSOP, JEDEC (MT8)
NS Package Number MTC08
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N08E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
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Japan Ltd.
a
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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