NM93C13 [NSC]
256-/1024-Bit Serial EEPROM; 256 / 1024位串行EEPROM
| 型号： | NM93C13 |
| 厂家： | 
National Semiconductor |
| 描述： | 256-/1024-Bit Serial EEPROM |
| 文件： | 总8页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1994
NM93C13/C14
256-/1024-Bit Serial EEPROM
General Description
Features
Y
Typical active current 400 mA; Typical standby current
25 mA
The NM93C13/C14 is 256/1024, respectively, bits of
CMOS electrically erasable memory divided into 16/64 16-
bit registers. They are fabricated using National Semicon-
ductor’s floating-gate CMOS process for high speed, high
reliability and low power. The NM93C13/C14 is available in
an 8-pin SO package to save board space.
Y
Y
Y
Y
Y
Y
Y
Y
Reliable CMOS floating gate technology
4.5V to 5.5V operation in all modes
MICROWIRE compatible serial I/O
Self-timed programming cycle
The serial interface of the NM93C13/C14 is MICROWIRETM
compatible for simple interface to standard microcontrollers
and microprocessors. There are
Erase/Write Enable, Erase, Erase All, Write, Write All, and
Erase/Write Disable.
Device status indication during programming mode
15 years data retention
7 instructions: Read,
Endurance: 100,000 read/write cycles minimum
Packages available: 8-pin DIP, 8-pin SO
All programming cycles are completely self-timed for simpli-
fied operation. The ready/busy status is available on the DO
pin to indicate the completion of a programming cycle.
Block Diagram
TL/D/11291–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/D/11291
RRD-B30M65/Printed in U. S. A.
Connection Diagrams
Dual-In-Line Package (N)
and 8-Pin SO (M8)
Alternate SO Pinout (TM8)
NM93C14 Only
TL/D/11291–2
TL/D/11291–3
Top View
See NS Package M08A
See NS Package Number
N08E and M08A
Ordering Information
a
Commercial Temp. Range (0 C to 70 C)
Pin Names
§
§
Order Number*
CS
SK
Chip Select
NM93C13N/NM93C14N
NM93C13M8/NM93C14M8
NM93C14TM8
Serial Data Clock
DI
Serial Data Input
Serial Data Output
Ground
DO
GND
V
CC
Power Supply
2
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Operating Temperature
NM93C13–NM93C14
b
a
65 C to 150 C
Ambient Storage Temperature
§
§
a
0 C to 70 C
§ §
4.5V to 5.5V
a
b
6.5V to 0.3V
All Input or Output Voltages
with Respect to Ground
Power Supply
a
Lead Temp. (Soldering, 10 sec.)
ESD Rating
300 C
§
2000V
e
g
5.0V 10% (unless otherwise specified) (Note 2)
DC and AC Electrical Characteristics V
CC
Symbol
Parameter
Operating Current
Standby Current
Input Leakage
Conditions
Min
Max
4
Units
mA
mA
e
e
e
e
e
I
I
I
I
CS
CS
V
, SK
IH
1 MHz
CC1
CC3
IL
0V
200
10
b
b
V
IN
V
IN
0V to V
10
10
mA
CC
CC
Output Leakage
0V to V
10
mA
OL
b
V
V
Input Low Voltage
Input High Voltage
0.1
0.8
IL
V
a
2
V
1
IH
CC
e
V
OL1
V
OH1
Output Low Voltage
Output High Voltage
I
I
2.1 mA
0.4
V
V
OL
e b
400 mA
2.4
OH
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
10 mA
0.2
1
OL2
OL
V
b
10 mA
V
CC
0.2
OH2
OH
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SK Clock Frequency
SK High Time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SK
(Note 3)
(Note 3)
300
250
50
SKH
SKL
SKS
CS
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
250
50
CSS
DH
D0 Hold Time
70
DI Setup Time
100
0
DIS
CSH
DIH
PD1
PD0
SV
CS Hold Time
DI Hold Time
20
Output Delay to ‘‘1’’
Output Delay to ‘‘0’’
CS to Status Valid
CS to DO in TRI-STATE
Write Cycle Time
500
500
500
100
10
e
CS
V
IL
É
DF
WP
Capacitance (Note 4)
AC Test Conditions
Output Load
e
e
T
A
25 C f
§
1 MHz
e
1 TTL Gate and C
100 pF
L
Input Pulse Levels
0.4V to 2.4V
Symbol
Test
Typ
Max
5
Units
pF
Timing Measurement Reference Level
Input
Output
C
C
Output Capacitance
Input Capacitance
OUT
1V and 2V
0.8V and 2V
5
pF
IN
Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: 100% functional test; AC/DC parameters sample tested to 0.4% AQL.
a
Note 3: The SK frequency specification specifies a minimum SK clock period of 1 ms, therefore in an SK clock cycle t
t
must be greater than or equal to
SKH
e
500 ns in order to meet the SK frequency specification.
SKL
e
1 ms. For example, if the t
SKL
500 ns then the minimum t
SKH
Note 4: This parameter is periodically sampled and not 100% tested.
3
Functional Description
The NM93C13/C14 have 7 instructions as described below.
Note that the MSB of any instruction is a ‘‘1’’ and is viewed
as a start bit in the interface sequence. For the C13 and C14
the next 8 bits carry the op code and the 6-bit address for
register selection.
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of CS
initiates the self-timed programming cycle. The DO pin indi-
cates the READY/BUSY status of the chip if CS is brought
Read (READ):
The READ instruction outputs serial data on the DO pin.
After a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register.
A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
e
high after a minimum of 500 ns (t ). DO
CS
cates that programming is still in progress. DO
logical 0 indi-
e
logical 1
indicates that the register at the address specified in the
instruction has been written with the data pattern specified
in the instruction and the part is ready for another instruc-
tion.
Erase All (ERAL):
Erase/Write Enable (EWEN):
When V is applied to the part, it powers up in the Erase/
CC
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical ‘1’
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
Write Disable (EWDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruc-
tion is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or V
is removed from the part.
CS is brought high after a minimum of 500 ns (t ). The
CS
ERASE ALL instruction is not required, see note below.
CC
Erase (ERASE):
Write All (WRAL):
The ERASE instruction will program all bits in the specified
register to the logical ‘1’ state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The WRAL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
500 ns (t ).
CS
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after
a
minimum of 500 ns (t ).
CS
logical ‘0’ indicates that programming is still in prog-
Erase/Write Disable (EWDS):
e
DO
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
e
ress. DO
logical ‘1’ indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Note: The NM93C13/C14 devices do not require an ‘ERASE’ or ‘ERASE ALL’ prior to the ‘WRITE’ and ‘WRITE ALL’ instructions. The ‘ERASE’ and ‘ERASE ALL’
instructions are included to maintain compatibility with the NMOS NMC9346.
Instruction Set for the NM93C13 and NM93C14
Instruction
SB
Op Code
Address
Data
Comments
Reads data stored in memory at specified address.
Write enable must precede all programming modes.
Erase selected register.
READ
1
10
00
11
01
00
00
00
A5–A0
EWEN
ERASE
WRITE
ERAL
1
11XXXX
A5–A0
1
1
A5–A0
D15–D0
D15–D0
Writes selected register.
1
10XXXX
01XXXX
00XXXX
Erases all registers.
WRAL
1
Writes all registers.
EWDS
1
Disables all programming instructions.
4
Timing Diagrams
Synchronous Data Timing
TL/D/11291–4
READ:
*Address bits A5 and A4 become ‘‘don’t care’’ for NM93C13.
TL/D/11291–5
EWEN:
*The NM93C13 and NM93C14 require a minimum of 9 clock cycles.
TL/D/11291–6
5
Timing Diagrams (Continued)
EWDS:
*The NM93C13 and NM93C14 require a minimum of 9 clock cycles.
TL/D/11291–7
WRITE:
*Address bit A5 and A4 become ‘‘don’t care’’ for NM93C13.
TL/D/11291–8
WRAL:
*The NM93C13 and NM93C14 require a minimum of 9 clock cycles.
TL/D/11291–9
6
Timing Diagrams (Continued)
ERASE:
*Address bits A5 and A4 are ‘‘don’t care’’ for NM93C13.
TL/D/11291–10
ERAL:
TL/D/11291–11
Physical Dimensions inches (millimeters)
Molded Small Out-Line Package (M8)
Order Number NM93C13M8 or NM93C14M8
NS Package Number M08A
7
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number NM93C13N or NM93C14N
NS Package Number N08E
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