NM93CS06M8 [NSC]
(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential Read; （ MICROWIRETM总线接口）， 256 / 1024 / 2048- / 4096位串行EEPROM与数据保护和连续读
| 型号： | NM93CS06M8 |
| 厂家： | 
National Semiconductor |
| 描述： | (MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential Read |
| 文件： | 总14页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1994
NM93CS06/CS46/CS56/CS66
(MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit
Serial EEPROM with Data Protect and Sequential Read
General Description
The NM93CS06/CS46/CS56/CS66 devices are 256/
1024/2048/4096 bits, respectively, of CMOS non-volatile
electrically erasable memory divided into 16/64/128/
256 16-bit registers. Selected registers can be protected
against data modification by programming the Protect Reg-
ister with the address of the first register to be protected
against data modification (all registers greater than, or equal
to, the selected address are then protected from further
change). Additionally, this address can be ‘‘locked’’ into the
device, making all future attempts to change data impossi-
ble. These devices are fabricated using National Semicon-
ductor floating-gate CMOS process for high reliability, high
endurance and low power consumption. The NM93CSXX
Family is offered in an SO package for small space consid-
erations.
READ, WRITE, WRITE ALL, WRITE ENABLE, and WRITE
DISABLE. The Protect register instructions are PRREAD,
PRWRITE, PRENABLE, PRCLEAR, and PRDISABLE.
Features
Y
Write protection in a user defined section of memory
Y
Sequential register read
Y
Typical active current of 400 mA and standby current of
25 mA
Y
No erase required before write
Y
Reliable CMOS floating gate technology
Y
MICROWIRE compatible serial I/O
Y
Self timed write cycle
Y
Device status during programming mode
Y
The EEPROM interfacing is MICROWIRE compatible pro-
viding simple interfacing to standard microcontrollers and
microprocessors. There are a total of 10 instructions, 5
which operate on the EEPROM memory, and 5 which oper-
ate on the Protect Register. The memory instructions are
40 year data retention
6
Endurance: 10 data changes
Y
Y
Y
4.5V to 5.5V operation in all modes of operation
Packages available: 8-pin SO, 8-pin DIP
Block Diagram
TL/D/10750–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/D/10750
RRD-B30M75/Printed in U. S. A.
Connection Diagram
Dual-In-Line Package (N)
and 8-Pin SO (M8)
Pin Names
CS
SK
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
GND
PE
TL/D/10750–2
Program Enable
Protect Register Enable
Power Supply
Top View
PRE
NS Package Number
N08E and M08A
V
CC
Ordering Information
a
Commercial Temp. Range (0 C to 70 C)
§
§
Order Number*
NM93CS06N/NM93CS46N/NM93CS56N/NM93CS66N
NM93CS06M8/NM93CS46M8/NM93CS56M8/NM93CS66M8
b
a
Extended Temp. Range ( 40 C to 85 C)
§
§
Order Number*
NM93CS06EN/NM93CS46EN/NM93CS56EN/NM93CS66EN
NM93CS06EM8/NM93CS46EM8/NM93CS56EM8/NM93CS66EM8
b
a
Military Temp. Range ( 55 C to 125 C)
§
§
Order Number*
NM93CS06MN/NM93CS46MN/NM93CS56MN/NM93CS66MN
NM93CS06MM8/NM93CS46MM8/NM93CS56MM8/NM93CS66MM8
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Ambient Operating Temperature
NM93CSxx
NM93CSxxE
NM93CSxxM
a
0 C to 70 C
§
§
b
b
a
40 C to 85 C
§
§
55 C to 125 C
a
§
§
4.5V to 5.5V
b
a
65 C to 150 C
Ambient Storage Temperature
§
§
Power Supply (V
)
CC
a
b
6.5V to 0.3V
All Input or Output Voltages
with Respect to Ground
a
Lead Temperature (Soldering, 10 sec.)
ESD rating
300 C
§
2000V
e
a
DC and AC Electrical Characteristics V
§
4.5V to 5.5V unless otherwise specified
CC
Throughout this table, ‘‘M’’ refers to temperature range ( 55 C to 125 C), not package.
b
§
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
e
e
e
e
1.0 MHz
0.5 MHz
I
Operating Current
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
CS
SK
SK
V
, SK
1.0 MHz
1
1
1
CCA
CCS
IH
mA
e
I
Standby Current
NM93CS06–NM93CS66
NM93CS06E–NM93CS06E
NM93CS06M–NM93CS06M
CS
V
IL
50
50
100
mA
e
(Note 4)
I
I
Input Leakage
Output Leakage
V
0V to V
CC
IL
IN
b
g
1
mA
V
OL
b
0.1
2
V
V
Input Low Voltage
Input High Voltage
0.8
IL
a
V
1
IH
CC
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
2.1 mA
400 mA
0.4
0.2
OL1
OH1
OL
V
2.4
OH
e
e b
V
OL2
V
OH2
Output Low Voltage
Output High Voltage
I
I
10 mA
10 mA
OL
V
b
V
0.2
OH
CC
f
SK
SK Clock Frequency
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
(Note 5)
0
0
0
1
1
0.5
MHz
t
SK High Time
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
250
300
500
SKH
ns
ns
ns
t
t
SK Low Time
250
SKL
SK Setup Time
SK Must Be at V
IL
for t before CS
SKS
goes high
50
50
100
SKS
t
CS
Minimum CS
Low Time
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
(Note 2)
250
250
500
ns
ns
ns
ns
ns
t
t
CS Setup Time
PRE Setup Time
100
CSS
NM93CS06-NM93CS66
NM93CS06E-NM93CS66E
NM93CS06M–NM93CS66M
50
50
100
PRES
t
t
DO Hold Time
PE Setup Time
70
DH
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
50
50
100
PES
t
DI Setup Time
CS Hold Time
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
100
100
200
DIS
ns
ns
t
0
CSH
3
e
DC and AC Electrical Characteristics V
4.5V to 5.5V unless otherwise specified (Continued)
CC
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
t
PE Hold Time
NM93CS06–NM93CS66
250
250
500
PEH
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
ns
t
t
t
PRE Hold Time
DI Hold Time
50
20
ns
ns
PREH
DIH
Output Delay to ‘‘1’’
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
500
500
PD1
ns
ns
ns
1000
t
t
t
t
Output Delay to ‘‘0’’
CS to Status Valid
CS to DO in
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
500
500
PD0
SV
1000
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
500
500
1000
e
NM93CS06–NM93CS66
NM93CS06E–NM93CS66E
NM93CS06M–NM93CS66M
CS
V
IL
100
100
200
DF
TRI-STATE
ns
É
Write Cycle Time
10
ms
WP
Capacitance (Note 3)
e
e
T
A
25 C, f
§
1 MHz
Symbol
Test
Typ
Max
5
Units
pF
C
C
Output Capacitance
Input Capacitance
OUT
5
pF
IN
Note 1: Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: CS (Chip Select) must be brought low (to V ) for an interval of t in order to reset all internal device registers (device reset) prior to beginning another
IL CS
opcode cycle (this is shown in the opcode diagrams in the following pages).
Note 3: This parameter is periodically sampled and not 100% tested.
Note 4: Typical leakage values are in the 20 nA range.
e
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
Note 5: The shortest allowable SK clock period
1/f (as shown under the f parameter). Maximum SK clock speed (minimum SK period) is determined by the
SK SK
and t
limits must be observed. Therefore, it is not allowable to set
SKH
SKL
e
a
t
SKL (minimum)
1/f
SK
t
for shorter SK cycle time operation.
SKH (minimum)
AC Test Conditions
V
/V
IL IH
V
/V
IL IH
V
/V
OL OH
V
CC
Range
I
/I
OL OH
Input Levels
Timing Level
Timing Level
s
4.5V
s
V
CC
5.5V
b
2.1 mA/
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
0.4 mA
(TTL Levels)
e
Output Load: 1 TTL Gate (C
100 pF)
L
4
Functional Description
The NM93CSxx EEPROM Family has 10 instructions as de-
scribed below. All Data-In signals are clocked into the de-
vice on the low-to-high SK transition.
Note: For all Protect Register Operations: If the PRE pin is
not held at all instructions will be applied to the
EEPROM array, rather than the Protect Register.
V
IH
,
Read and Sequential Register Read (READ):
Protect Register Read (PRREAD):
The READ instruction outputs serial data on the D0 pin.
After a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register.
A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock. In the sequential register read
mode of operation, the memory automatically cycles to the
next register after each 16 data bits are clocked out. The
dummy-bit is suppressed in this mode and a continuous
string of data is obtained.
The PRREAD instruction outputs the address stored in the
Protect Register on the DO pin. The PRE pin MUST be held
high while loading the instruction sequence. Following the
PRREAD instruction the 6- or 8-bit address stored in the
memory protect register is transferred to the serial out shift
register. As in the READ mode, a dummy bit (logical 0) pre-
cedes the 6- or 8-bit address string.
Protect Register Enable (PREN):
The PREN instruction is used to enable the PRCLEAR,
PRWRITE, and PRDS modes. Before the PREN mode can
be entered, the part must be in the Write Enable (WEN)
mode. Both the PRE and PE pins MUST be held high while
loading the instruction sequence.
Write Enable (WEN):
When V is applied to the part, it ‘‘powers up’’ in the Write
CC
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
Note that a PREN instruction must immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
executed or V
is completely removed from the part.
The PRCLEAR instruction clears the address stored in the
Protect Register and, therefore, enables all registers for the
WRITE and WRALL instruction. The PRE and PE pins must
be held high while loading the instruction sequence, howev-
er, after loading the PRCLEAR instruction the PRE and PE
pins become ‘‘don’t care’’. Note that a PREN instruction
must immediately precede a PRCLEAR instruction.
CC
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. The PE pin
MUST be held high while loading the WRITE instruction,
however, after loading the WRITE instruction the PE pin be-
comes a ‘‘don’t care’’. The D0 pin indicates the READY/
Please note that the PRCLEAR instruction and the
PRWRITE instruction will both program the Protect Register
with all 1s. However, the PRCLEAR instruction will allow the
LAST register to be programmed, whereas the PRWRITE
BUSY status of the chip if CS is brought high after the t
e
CS
logical 0 indicates that programming is still in
e
instruction
all 1s will PREVENT the last register from
interval. D0
progress. D0
being programmed. In addition, the PRCLEAR instruction
will allow the use of the WRALL command, where the
e
logical 1 indicates that the register at the
address specified in the instruction has been written with
the data pattern specified in the instruction and the part is
ready for another instruction.
e
PRWRITE
code.
all 1s will lock out the Bulk programming op-
Protect Register Write (PRWRITE):
Write All (WRALL):
The PRWRITE instruction is used to write into the Protect
Register the address of the first register to be protected.
After the PRWRITE instruction is executed, all memory reg-
isters whose addresses are greater than or equal to the
address specified in the Protect Register are protected from
The WRALL instruction is valid only when the Protect Regis-
ter has been cleared by executing a PRCLEAR instruction.
The WRALL instruction will simultaneously program all reg-
isters with the data pattern specified in the instruction. Like
the WRITE instruction, the PE pin MUST be held high while
loading the WRALL instruction, however, after loading the
instruction the PE pin becomes a ‘‘don’t care’’. As in the
WRITE mode, the DO pin indicates the READY/BUSY
the WRITE operation. Note that before executing
a
PRWRITE instruction the Protect Register must first be
cleared by executing a PRCLEAR operation and that the
PRE and PE pins must be held high while loading the in-
struction, however, after loading the PRWRITE instruction
the PRE and PE pins become ‘don’t care’. Note that a
PREN instruction must immediately precede a PRWRITE
instruction.
status of the chip if CS is brought high after the t interval.
CS
This function is DISABLED if the Protect Register is in use
to lock out a section of memory.
Write Disable (WDS):
To protect against accidental data disturb, the Write Disable
(WDS) instruction disables all programming modes and
should follow all programming operations. Execution of a
READ instruction is independent of both the WEN and WDS
instructions.
Protect Register Disable (PRDS):
The PRDS instruction is a ONE TIME ONLY instruction
which renders the Protect Register unalterable in the future.
Therefore, the specified registers become PERMANENTLY
protected against data changes. As in the PRWRITE in-
struction the PRE and PE pins must be held high while
loading the instruction, and after loading the PRDS instruc-
tion the PRE and PE pins become ‘‘don’t care’’.
Note that a PREN instruction must immediately precede a
PRDS instruction.
5
Instruction Set for the NM93CS06 and NM93CS46
Instruction SB Op Code Address
Data
PRE PE
Comments
READ
WEN
1
1
1
1
10
00
01
00
A5–A0
11XXXX
A5–A0
0
0
0
0
X
1
1
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
WRITE
WRALL
D15–D0
D15–D0
Writes address if unprotected.
01XXXX
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
1
1
00
10
00
00XXXX
XXXXXX
11XXXX
0
1
1
X
X
1
Disables all programming modes.
PRREAD
PREN
Reads address stored in Protect Register.
Must immediately precede PRCLEAR, PRWRITE, and
PRDS instructions.
PRCLEAR
PRWRITE
1
1
11
01
111111
A5–A0
1
1
1
1
Clears the Protect Register so that no registers are
protected from WRITE.
Programs address into Protect Register. Thereafter,
t
memory addresses the address in Protect Register are
protected from WRITE.
PRDS
1
00
000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93CS06.
Instruction Set for the NM93CS56 and NM93CS66
Instruction SB Op Code
Address
A7–A0
Data
PRE PE
Comments
READ
WEN
1
1
1
1
10
00
01
00
0
0
0
0
X
1
1
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
11XXXXXX
A7–A0
WRITE
WRALL
D15–D0
Writes address if unprotected.
01XXXXXX D15–D0
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
1
1
00
10
00
00XXXXXX
XXXXXXXX
11XXXXXX
0
1
1
X
X
1
Disables all programming modes.
PRREAD
PREN
Reads address stored in Protect Register.
Must immediately precede PRCLEAR, PRWRITE, and
PRDS instructions.
PRCLEAR
PRWRITE
1
1
11
01
11111111
A7–A0
1
1
1
1
Clears the ‘‘protect register’’ so that no registers are
protected from WRITE.
Programs address into Protect Register. Thereafter,
t
memory addresses the address in Protect Register are
protected from WRITE.
PRDS
1
00
00000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bit A7 becomes ‘‘Don’t Care’’ for the NM93CS56.
6
Timing Diagrams
Synchronous Data Timing
TL/D/10750–15
READ:
e
e
X
PRE
0, PE
²
TL/D/10750–4
The memory automatically cycles to the next register with continued clocking of SK.
7
Timing Diagrams (Continued)
WEN:
e
e
TRI-STATE
PRE
0, D0
TL/D/10750–5
WDS:
e
X, DO TRI-STATE
e
e
PRE
0, PE
TL/D/10750–6
WRITE:
e
PRE
0
TL/D/10750–7
8
Timing Diagrams (Continued)
WRALL:
e
(PROTECT REGISTER MUST BE CLEARED)
PRE
0
TL/D/10750–8
PRREAD:
e
PE
X
TL/D/10750–9
9
Timing Diagrams (Continued)
PREN:
TRI-STATE
e
D0
(A WEN CYCLE MUST PRECEDE A PREN CYCLE)
TL/D/10750–10
PRCLEAR:
(A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRCLEAR CYCLE)
TL/D/10750–11
10
Timing Diagrams (Continued)
PRWRITE:
(PREN CYCLES MUST IMMEDIATELY PRECEDE A PRWRITE CYCLE.)
TL/D/10750–12
PRDS:
(*ONE TIME ONLY INSTRUCTION. A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRDS CYCLE.)
TL/D/10750–13
11
12
Physical Dimensions inches (millimeters)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Order Number NM93CS06M8, NM93CS46M8 or NM93CS56M8
NS Package Number M08A
13
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number NM93CS06N, NM93CS46N,
NM93CS56 or NM93CS66N
NS Package Number N08E
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