NM93CS56LVN [NSC]
256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE-TM Bus Interface); 256 / 1024 / 2048- / 4096位串行EEPROM ，支持扩展电压（ 2.7V至5.5V ）和数据保护（ MICROWIRE -TM总线接口）
| 型号： | NM93CS56LVN |
| 厂家： | 
National Semiconductor |
| 描述： | 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE-TM Bus Interface) |
| 文件： | 总14页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
NM93CS06L/CS46L/CS56L/CS66L
256-/1024-/2048-/4096-Bit Serial EEPROM
with Extended Voltage (2.7V to 5.5V) and Data Protect
(MICROWIRETM Bus Interface)
memory and 5 which operate on the Protect Register. The
General Description
The NM93CS06L/CS46L/CS56L/CS66L devices are
256/1024/2048/4096 bits, respectively, of non-volatile
ter instructions are PRREAD, PRWRITE, PRCLEAR,
memory instructions are READ, WRITE, WRITE ALL,
WRITE ENABLE, and WRITE DISABLE. The Protect regis-
electrically erasable memory divided into 16/64/128/256 x
16-bit registers (addresses). The NM93CSxxL Family func-
PRDISABLE and PRENABLE.
tions in an extended voltage operating range, and is fabri-
cated using National Semiconductor’s floating gate CMOS
Features
Y
Sequential register read
technology for high reliability, high endurance and low pow-
s
Y
Write protection in a user defined section of memory
s
s
s
er consumption. N registers (N 16, N 64, N 128, N
Y
Y
2.7V to 5.5V operating range in all modes
Typical active current of 200 mA; typical standby
current of 1 mA
256) can be protected against data modification by pro-
gramming the Protect Register with the address of the first
register to be protected against data modification. (All regis-
ters greater than, or equal to, the selected address are then
protected from further change.) Additionally, this address
can be ‘‘locked’’ into the device, making all future attempts
to change data impossible.
Y
Y
Y
Y
Y
Y
Y
Y
No erase required before write
Reliable CMOS floating gate technology
MICROWIRE compatible serial I/O
Self timed write cycle
These devices are available in both SO and TSSOP pack-
ages for small space considerations.
Device status during programming mode
40 year data retention
6
Endurance: 10 data changes
The serial interface that controls these EEPROMs is
MICROWIRE compatible, providing simple interfacing to
standard microcontrollers and microprocessors. There
are a total of 10 instructions, 5 which operate on the EEPROM
Packages Available: 8-pin SO, 8-pin DIP, and 8-pin
TSSOP
Block Diagram
TL/D/10044–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/D/10044
RRD-B30M126/Printed in U. S. A.
http://www.national.com
Connection Diagrams
Dual-In-Line Package (N)
8-Pin SO Package (M8) and 8-Pin TSSOP Package (MT8)
Pin Names
Chip Select
CS
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
GND
PE
TL/D/10044–2
Program Enable
Protect Register Enable
Power Supply
Top View
PRE
See NS Package Number N08E (N)
See NS Package Number M08A (M8)
See NS Package Number MTC08 (MT8)
V
CC
Ordering Information
a
Commercial Temp. Range (0 C to 70 C)
§
§
Order Number
NM93CS06LN/NM93CS46LN/NM93CS56LN/NM93CS66LN
NM93CS06LM8/NM93CS46LM8/NM93CS56LM8/NM93CS66LM8
NM93CS46LMT8/NM93CS56LMT8/NM93CS66LMT8
b
a
Extended Temp. Range ( 40 C to 85 C)
§
§
Order Number
NM93CS06LEN/NM93CS46LEN/NM93CS56LEN/NM93CS66LEN
NM93CS06LEM8/NM93CS46LEM8/NM93CS56LEM8/NM93CS66LEM8
NM93CS46LEMT8/NM93CS56LEMT8/NM93CS66LEMT8
b
a
Automotive Temp. Range ( 40 C to 125 C)
§
§
Order Number
NM93CS06LVN/NM93CS46LVN/NM93CS56LVN/NM93CS66LVN
NM93CS06LVM8/NM93CS46LVM8/NM93CS56LVM8/NM93CS66LVM8
NM93CS46LVMT8/NM93CS56LVMT8/NM93CS66LVMT8
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Ambient Operating Temperature
NM93CSxxL
NM93CSxxLE
a
0 C to 70 C
§
§
§
b
a
40 C to 85 C
§
b
a
65 C to 150 C
Ambient Storage Temperature
Power Supply (V ) Range
CC
Read Mode
§
§
2.0V to 5.5V
3.0V to 5.5V
2.5V to 5.5V
a
b
6.5V to 0.3V
All Input or Output Voltages
with Respect to Ground
WRALL Bulk Programming
All Other Modes
a
Lead Temperature (Soldering, 10 sec.)
ESD rating
300 C
§
2000V
k
k
4.5V
DC and AC Electrical Characteristics: 2V
V
CC
Symbol
Parameter
Operating Current
Standby Current
Conditions
Min
Max
1
Units
mA
e
e
e
e
I
I
CS
CS
V
V
, SK
250 kHz
CCA
IH
50
mA
CCS
IL
I
I
Input Leakage
V
IN
0V to V
CC
IL
g
1
mA
V
Output Leakage
(Note 4)
OL
b
0.8 V
V
V
Input Low Voltage
Input High Voltage
0.1
0.15 V
CC
IL
a
V
1
IH
CC
CC
e
V
V
Output Low Voltage
Output High Voltage
I
I
10 mA
e b
0.1 V
OL
OL
CC
V
10 mA
0.9 V
OH
OH
CC
f
t
t
t
SK Clock Frequency
SK High Time
(Note 5)
0
1
1
250
kHz
ms
SK
SKH
SKL
SKS
SK Low Time
ms
SK Setup Time
SK must be at V for
IL
0.2
1
ms
ms
t
before CS goes high
SKS
t
CS
Minimum CS
Low Time
(Note 2)
t
t
t
t
t
t
t
t
t
t
t
t
t
CS Setup Time
PRE Setup Time
PE Setup Time
DI Setup Time
DO Hold Time
CS Hold Time
0.2
0.2
0.2
0.4
70
ms
ms
ms
ms
ns
ms
ms
ms
ms
ms
ms
ms
CSS
PRES
PES
DIS
DH
0
CSH
PEH
PREH
DIH
PE Hold Time
0.4
0.4
0.4
PRE Hold Time
DI Hold Time
Output Delay to ‘‘1’’
Output Delay to ‘‘0’’
CS to Status Valid
CS to DO in
2
2
1
PD1
PD0
SV
e
CS
V
IL
DF
0.4
15
ms
TRI-STATE
É
t
Write Cycle Time
ms
WP
3
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k
k
5.5V
DC and AC Electrical Characteristics: 4.5V
V
CC
Symbol
Parameter
Part Number
Conditions
Min
Max
1
Units
mA
e
e
I
Operating Current
CMOS Input Levels
CS
CS
V
V
, SK
1.0 MHz
CCA
IH
e
e
I
Standby Current
50
mA
CCS
IL
I
I
Input Leakage
V
IN
0V to V
CC
IL
g
1
mA
Output Leakage
(Note 4)
OL
b
V
V
Input Low Voltage
Input High Voltage
0.1
0.8
IL
V
V
a
2
V
1
IH
CC
e
e
V
V
Output Low Voltage
Output High Voltage
I
I
2.1 mA
0.4
0.2
1
OL1
OL
400 mA
2.4V
OH1
OL
e
e b
V
V
Output Low Voltage
Output High Voltage
I
I
10 mA
OL2
OL
V
MHz
ns
b
10 mA
V
0.2
OH2
OL
CC
f
t
SK Clock Frequency
SK High Time
(Note 5)
0
SK
NM93CS06L-NM93CS66L
250
300
SKH
NM93CS06LE-NM93CS66LE
t
t
SK Low Time
250
50
ns
SKL
SK Setup Time
SK must be at V for
IL
SKS
ns
t
before CS goes High
SKS
t
CS
Minimum CS
Low Time
(Note 2)
250
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
CS Setup Time
PRE Setup Time
DO Hold Time
50
50
70
50
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSS
PRES
DH
PE Setup Time
DI Setup Time
PES
DIS
CS Hold Time
CSH
PEH
PREH
DIH
PE Hold Time
250
50
20
PRE Hold Time
DI Hold Time
Output Delay to ‘‘1’’
Output Delay to ‘‘0’’
CS to Status Valid
500
500
500
PD1
PD0
SV
e
V
IL
CS to DO in
TRI-STATE
CS
DF
100
10
ns
t
Write Cycle Time
ms
WP
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4
Capacitance (Note 3)
e
e
1 MHz
T
A
25 C f
§
Symbol
Test
Max
5
Units
pF
C
C
Output Capacitance
Input Capacitance
OUT
5
pF
IN
Note 1: Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: CS (Chip Select) must be brought low (to V ) for an interval of t in order to reset all internal device registers (device reset) prior to beginning another
IL CS
opcode cycle (This is shown in the opcode diagrams in the following pages).
Note 3: This parameter is periodically sampled and not 100% tested.
Note 4: Typical leakage values are in the 20 nA range.
e
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
Note 5: The shortest allowable SK clock period
1/f (as shown under the f parameter). Maximum SK clock speed (minimum SK period) is determined by the
SK SK
and t
limits must be observed. Therefore, it is not allowable to set
SKH
SKL
e
a
t
SKL (minimum)
1/f
SK
t
for shorter SK cycle time operation,
SKH (minimum)
AC Test Conditions
V
/V
IL IH
V
/V
IL IH
V
/V
OL OH
V
CC
Range
I
/I
OL OH
Input Levels
Timing Level
Timing Level
s
k
g
10 mA
2.0V
V
CC
4.5V
0.3V/1.8V
1.0V
0.8V/1.5V
(Extended Voltage Levels)
s
s
5.5V
b
2.1 mA/0.4 mA
4.5V
V
CC
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
(TTL Levels)
e
Output Load: 1 TTL Gate (C
100 pF)
L
5
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Functional Description
The extended voltage EEPROMs of the NM93CSxxL Family
have 10 instructions as described below. Note that MSB of
any instruction is a ‘‘1’’ and is viewed as a start bit in the
interface sequence. For the CS06 and CS46 the next 8 bits
carry the opcode and the 6-bit address for register selec-
tion. For the CS56 and CS66, the next 10 bits carry the
opcode and the 8-bit address for register selection. All Data
In signals are clocked into the device on the low-to-high SK
transition.
Protect Register Read (PRREAD):
The PRREAD instruction outputs the address stored in the
Protect Register on the DO pin. The PRE pin MUST be held
high while loading the instruction sequence. Following the
PRREAD instruction the 6- or 8-bit address stored in the
memory protect register is transferred to the serial out shift
register. As in the READ mode, a dummy bit (logical 0) pre-
cedes the 6- or 8-bit address string.
Protect Register Enable (PREN):
Read and Sequential Register Read (READ):
The PREN instruction is used to enable the PRCLEAR,
PRWRITE, and PRDS modes. Before the PREN mode can
be entered, the part must be in the Write Enable (WEN)
mode. Both the PRE and PE pins MUST be held high while
loading the instruction sequence.
The READ instruction outputs serial data on the D0 pin.
After a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register.
A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock. In the Sequential Read mode of
operation, the memory automatically cycles to the next reg-
ister after each 16 data bits are clocked out. The dummy-bit
is suppressed in this mode and a continuous string of data is
obtained.
Note that a PREN instruction must immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
The PRCLEAR instruction clears the address stored in the
Protect Register and therefore enables all registers for the
WRITE and WRALL instruction. The PRE and PE pins must
be held high while loading the instruction sequence; howev-
er, after loading the PRCLEAR instruction, the PRE and PE
pins become ‘‘don’t care’’. Note that a PREN instruction
must immediately precede a PRCLEAR instruction.
Write Enable (WEN):
When V is applied to the part, it ‘‘powers up’’ in the Write
CC
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
Please note that the PRCLEAR instruction and the
PRWRITE instruction will both program the Protect Register
with all 1s. However, the PRCLEAR instruction will allow the
LAST register to be programmed, whereas the PRWRITE
e
executed or V
is removed from the part.
CC
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
allocated to the data-in (DI) pin, CS must be brought low
before the next rising edge of the SK clock. This falling edge
of the CS initiates the self-timed programming cycle. The PE
pin MUST be held high while loading the WRITE instruction;
however, after loading the WRITE instruction, the PE pin
becomes a ‘‘don’t care’’. The D0 pin indicates the READY/
instruction
all 1s will PREVENT the last register from
being programmed. In addition, the PRCLEAR instruction
will allow the use of the WRALL command, where the
e
PRWRITE
code.
all 1s will lock out the Bulk programming op-
Protect Register Write (PRWRITE):
The PRWRITE instruction is used to write into the Protect
Register the address of the first register to be protected.
After the PRWRITE instruction is executed, all memory reg-
isters whose addresses are greater than or equal to the
address specified in the Protect Register are protected from
BUSY status of the chip if CS is brought high after the t
e
CS
logical 0 indicates that programming is still in
internal. D0
progress. D0
e
logical 1 indicates that the register at the
address specified in the instruction has been written with
the data pattern specified in the instruction and that the part
is ready for another instruction.
the WRITE operation. Note that before executing
a
PRWRITE instruction, the Protect Register must first be
cleared by executing a PRCLEAR operation and the PRE
and PE pins must be held high while loading the instruction;
however, after loading the PRWRITE instruction, the PRE
and PE pins become ‘‘don’t care’’. Note that a PREN in-
struction must immediately precede a PRWRITE instruc-
tion.
Write All (WRALL):
The WRALL instruction is valid only when the Protect Regis-
ter has been cleared by executing a PRCLEAR instruction.
The WRALL instruction will simultaneously program all reg-
isters with the data pattern specified in the instruction. Like
the WRITE instruction, the PE pin MUST be held high while
loading the WRALL instruction; however, after loading the
WRITE instruction, the PE pin becomes a ‘‘don’t care’’. As
in the WRITE mode, the DO pin indicates the READY/
Protect Register Disable (PRDS):
The PRDS instruction is a ONE TIME ONLY instruction
which renders the Protect Register unalterable in the future.
Therefore, the specified registers become PERMANENTLY
protected against data changes. As in the PRWRITE in-
struction the PRE and PE pins must be held high while
loading the instruction, and after loading the PRDS instruc-
tion the PRE and PE pins become ‘‘don’t care’’.
BUSY status of the chip if CS is brought high after the t
CS
interval. This function is DISABLED if the protect register is
in use to lock out a section memory.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruc-
tion disables all programming modes and should follow all
programming operations. Execution of a READ instruction is
independent of both the WEN and WDS instructions.
Note that a PREN instruction must immediately precede a
PRDS instruction.
Note: For all protect register operations: If the PRE pin is
not held at V , all instructions will be applied to the
IH
EEPROM array, rather than the Protect Register.
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6
Instruction Set for the NM93CS06L and NM93CS46L
Instruction SB Op Code Address
Data
PRE PE
Comments
READ
WEN
1
1
1
1
10
00
01
00
A5–A0
11XXXX
A5–A0
0
0
0
0
X
1
1
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
WRITE
WRALL
D15–D0
D15–D0
Writes address if unprotected.
01XXXX
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
1
1
00
10
00
00XXXX
XXXXXX
11XXXX
0
1
1
X
X
1
Disables all programming modes.
PRREAD
PREN
Reads address stored in Protect Register.
Must immediately precede PRCLEAR, PRWRITE, and
PRDS instructions.
PRCLEAR
PRWRITE
1
1
11
01
111111
A5–A0
1
1
1
1
Clears the Protect Register so that no registers are
protected from WRITE.
Programs address into Protect Register. Thereafter,
t
memory addresses the address in Protect Register are
protected from WRITE.
PRDS
1
00
000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93CS06L.
Instruction Set for the NM93CS56L and NM93CS66L
Instruction SB Op Code
Address
A7–A0
Data
PRE PE
Comments
READ
WEN
1
1
1
1
10
00
01
00
0
0
0
0
X
1
1
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
11XXXXXX
A7–A0
WRITE
WRALL
D15–D0
Writes address if unprotected.
01XXXXXX D15–D0
Writes all registers. Valid only when Protect Register is
cleared.
WDS
1
1
1
00
10
00
00XXXXXX
XXXXXXXX
11XXXXXX
0
1
1
X
X
1
Disables all programming modes.
PRREAD
PREN
Reads address stored in Protect Register.
Must immediately precede PRCLEAR, PRWRITE, and
PRDS instructions.
PRCLEAR
PRWRITE
1
1
11
01
11111111
A7–A0
1
1
1
1
Clears the ‘‘protect register’’ so that no registers are
protected from WRITE.
Programs address into Protect Register. Thereafter,
t
memory addresses the address in Protect Register are
protected from WRITE.
PRDS
1
00
00000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bit A7 becomes ‘‘Don’t Care’’ for the NM93CS56L.
7
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Timing Diagrams
Synchronous Data Timing
TL/D/10044–15
READ:
e
e
X
PRE
0, PE
TL/D/10044–5
²
The memory automatically cycles to the next register.
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8
Timing Diagrams (Continued)
WEN:
e
e
TRI-STATE
PRE
0, D0
TL/D/10044–6
WDS:
e
X, DO TRI-STATE
e
e
PRE
0, PE
TL/D/10044–7
WRITE:
e
PRE
0
TL/D/10044–8
9
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Timing Diagrams (Continued)
WRALL:
e
(PROTECT REGISTER MUST BE CLEARED)
PRE
0
TL/D/10044–9
PRREAD:
e
PE
X
TL/D/10044–10
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10
Timing Diagrams (Continued)
PREN:
TRI-STATE
e
D0
(A WEN CYCLE MUST PRECEDE A PREN CYCLE)
TL/D/10044–11
PRCLEAR:
(A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRCLEAR CYCLE)
TL/D/10044–12
11
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Timing Diagrams (Continued)
PRWRITE:
(A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRWRITE CYCLE.
TL/D/10044–13
PRDS:
(ONE TIME ONLY INSTRUCTION. A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRDS CYCLE.)
TL/D/10044–14
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Small Out-Line Package (M8)
NS Package Number M08A
8-Pin Molded TSSOP, JEDEC (MT8)
NS Package Number MTC08
13
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N08E
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a
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