NS32AM162V-20 [NSC]
IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor;
| 型号： | NS32AM162V-20 |
| 厂家： | 
National Semiconductor |
| 描述： | IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor 时钟 外围集成电路 装置 |
| 文件： | 总80页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
December 1992
NS32AM162-20/NS32AM163-20
Voice Processor with Serial CODEC Interface
Y
On-chip DSP Module (DSPM) for high speed DSP
operations
General Description
The NS32AM162 and the NS32AM163 are integrated 32 bit
Y
Three modes of operation configured via strap pins:
Ð Internal ROM mode
members of the Series 32000 /EP family of National’s Em-
É
bedded System ProcessorsTM, tuned for the Digital (tape-
less) Answering Machine (DAM) market. These processors
integrate the functions of a traditional Digital Signal Pro-
cessing (DSP) chip and of a system controller. The devices
contain system support functions such as DRAM Controller,
Interrupt Control Unit, Pulse Width Modulator, CODEC Inter-
face, WATCHDOGTM timer, and a Clock Generator. The
NS32AM162 and the NS32AM163 can execute instructions
from either an on-chip ROM or from an external ROM.
X
25 Kbyte Internal ROM (32 Kbyte in the
NS32AM163)
X
X
X
8-bit external data bus
16-bit programmable I/O lines
8 output lines
Ð External ROM mode
X
X
X
16-bit external data bus
8-bit programmable I/O lines
The NS32AM162 and NS32AM163 have all the features of
National’s NS32AM160 and NS32AM161 respectively. The
main difference between the formers and the latters is in the
CODEC interface. The NS32AM160 and NS32AM161 sup-
port a parallel CODEC. The NS32AM162 and NS32AM163
support one or two serial CODECs.
16-bit address bus with support for external
128 Kbyte ROM
X
Support for external I/O devices
Ð Development mode
X
X
16-bit external data bus
Throughout this data sheet, unless otherwise mentioned,
every reference to the NS32AM162 is applicable to the
NS32AM163 as well.
18-bit address bus with support for external
512 Kbyte ROM
X
X
Support for external I/O devices
Support for device test via status pins
Features
Y
Y
Y
On-chip Interrupt Control Unit (ICU) provides 4 levels of
interrupts
NS32AM162 is software and pin compatible with
NS32AM160 (NS32AM163Ðwith NS32AM161)
On-chip DRAM Controller for 4 Mbit and 16 Mbit
devices
Y
Software compatible with the Series 32000/EP
processors
Y
Y
Y
Y
Y
On-chip CODEC clock generation and interface
On-chip 2 ms Real Time Counter
On-chip 8-bit Pulse Width Modulator (PWM) module
On-chip WATCHDOG Timer
Y
Designed around the CPU core of the NS32CG16
Y
32-bit architecture and implementation
Y
20.48 MHz operation
Y
2.1 Kbyte on-chip RAM
Power down mode
Block Diagram
TL/EE/11732–1
Series 32000É is a registered trademark of National Semiconductor Corporation.
EPTM, Embedded System ProcessorsTM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/EE11732
RRD-B30M115/Printed in U. S. A.
Table of Contents
1.0 PRODUCT INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ7
1.1 NS32AM162 Special Features ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
2.0 ARCHITECTURAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
2.1 Register SetÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
2.1.1 General Purpose Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
2.1.2 Address RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
2.1.3 Processor Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
2.1.4 Confirmation RegisterÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
2.1.5 DSP Module Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
2.1.6 Interrupt Control Unit (ICU) Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
2.1.7 CODEC Interface RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
2.1.8 Pulse Width Modulator (PWM) RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
2.1.9 Clock Generator RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
2.1.10 WATCHDOG (WD) Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
2.2 Memory OrganizationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
2.2.1 Address MappingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16
2.3 Instruction SetÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
2.3.1 General Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
2.3.2 Addressing ModesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
2.3.3 Instruction Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
2.4 Graphics Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23
2.4.1 Frame Buffer Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ23
2.4.2 BITBLT Fundamentals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24
2.4.2.1 Frame Buffer Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24
2.4.2.2 Bit Alignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24
2.4.2.3 Block Boundaries and Destination MasksÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24
2.4.2.4 BITBLT DirectionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ26
2.4.3 Graphics Support InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ26
2.4.3.1 BITBLT (BIT-aligned Block Transfer)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ26
2.4.3.2 Pattern Fill ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
2.4.3.3 Data Compression, Expansion and Magnify ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
2.4.3.3.1 Magnifying Compressed DataÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28
3.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1 Instruction Execution ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1.1 Operating States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1.2 Instruction Endings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1.2.1 Completed Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1.2.2 Suspended Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
3.1.2.3 Terminated Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30
3.1.2.4 Partially Completed Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30
3.2 Exception Processing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30
3.2.1 Exception Acknowledge Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30
3.2.2 Returning from an Exception Service Procedure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
3.2.3 Maskable InterruptsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
3.2.3.1 Non-Vectored Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
3.2.4 Non-Maskable Interrupt ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
3.2.5 Traps ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
3.2.6 Priority among Exceptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ32
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Table of Contents (Continued)
3.2.7 Exception Acknowledge Sequences: Detailed Flow ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.2.7.1 Maskable/Non-Maskable Interrupt Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.2.7.2 ILL/SVC/DVZ/FLG/BPT/UND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.2.7.3 Trace Trap Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.3 Debugging Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.3.1 Instruction TracingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
3.4 On-Chip PeripheralsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35
3.4.1 Interrupt Controller Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35
3.4.1.1 Interrupt SourcesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36
3.4.2 BIU and DRAM Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36
3.4.2.1 DRAM Access ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36
3.4.2.2 CODEC InterfaceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ36
3.4.2.3 Accesses to Off-Chip Memory Devices ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37
3.4.3 I/O Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.4.4 Pulse Width Modulator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.4.5 Clock GeneratorÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.4.6 WATCHDOG CounterÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.4.7 Internal ROM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.4.8 Internal RAM Arrays ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.5 DSP Module ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.5.1 Programming Model ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
3.5.2 RAM Organization and Data Types ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.1 Integer Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.2 Aligned Integer Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.3 Real Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.4 Aligned-Real Values ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.5 Extended-Precision Real ValuesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ39
3.5.2.6 Complex ValuesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
3.5.3 Command List Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
3.5.4 CPU Core Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
3.5.4.1 Synchronization of Parallel Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ40
3.5.4.2 DSPM RAM OrganizationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41
3.5.5 DSPM Instruction Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41
3.5.5.1 Conventions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ41
3.5.5.2 Type Casting ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ42
3.5.5.3 General Notes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ42
3.5.5.4 Load Register InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ42
3.5.5.5 Store Register Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ43
3.5.5.6 Adjust Register InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ44
3.5.5.7 Flow Control Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45
3.5.5.8 Internal Memory Move Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46
3.5.5.9 External Memory Move Instuctions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46
3.5.5.10 Arithmetic/Logical InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47
3.5.5.11 Multiply-and-Accumulate Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ47
3.5.5.12 Multiply-and-Add Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ48
3.5.5.13 Clipping and Min/Max InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ49
3.5.5.14 Special Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ50
3.6. System Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
3.6.1 Power and Grounding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
3.6.2 Clocking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
3
Table of Contents (Continued)
3.6.2.1 High Speed Clock OscillatorÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
3.6.2.2 Low Frequency Clock Oscillator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
3.6.3 Power Down ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54
3.6.4 Resetting ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54
4.0 DEVICE SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55
4.1 NS32AM162 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55
4.1.2 Input SignalsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55
4.1.3 Output Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55
4.1.4 Input/Output SignalsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ55
4.2 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ57
4.3 Electrical CharacteristicsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ57
4.4 Switching Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
4.4.1 DefinitionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
4.4.2 Synchronous Timing Tables ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59
4.4.2.1 Output Signals: Internal Propagation Delays, NS32AM162–20 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ59
4.4.2.2 Input SignalsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ60
4.4.3 Timing Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61
APPENDIX A: INSTRUCTION FORMATSÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ68
APPENDIX B: INSTRUCTION EXECUTION TIMES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71
B.1 Basic Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71
B.1.1 Equations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ71
B.1.2 Notes on Table Use ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72
B.1.3 Calculation of the Execution Time TEX for Basic Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ72
B.2 Special Graphics InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
B.2.1 Execution Time Calculation for Special Graphics InstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
B.3 Command List OperationsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ79
4
List of Figures
FIGURE 1-1. NS32AM162ÐInternal ROM Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ7
FIGURE 1-2. NS32AM162ÐExternal ROM ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
FIGURE 1-3. NS32AM162ÐDevelopment Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
FIGURE 2-1. NS32AM162 Internal Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
FIGURE 2-2. Processor Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ11
FIGURE 2-3. Configuration Register (CFG) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
FIGURE 2-4. DSP Module Registers Address MapÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
FIGURE 2-5. Accumulator Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
FIGURE 2-6. X, Y, Z Registers Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12
FIGURE 2-7. EABR Register FormatÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
FIGURE 2-8. OVF Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
FIGURE 2-9. PARAM Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
FIGURE 2-10. REPEAT Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
FIGURE 2-11. EXT Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13
FIGURE 2-12. CLSTAT Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-13. DSPINT and DSPMASK Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-14. NMISTAT Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-15. IVCT Register FormatÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-16. IMASK Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-17. IPEND Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-18. IECLR Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
FIGURE 2-19. CLKCTL Register Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15
FIGURE 2-20a. NS32AM162 Address Mapping ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16
FIGURE 2-20b. NS32AM162 Modules Address Mapping ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16
FIGURE 2-21. Index Byte FormatÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
FIGURE 2-22. General Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
FIGURE 2-23. Displacement Encodings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18
FIGURE 2-24. Correspondence between Linear and Cartesian Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ24
FIGURE 2-25. 32-Pixel by 32-Scan Line Frame BufferÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ25
FIGURE 2-26. Overlapping BITBLT Blocks ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ25
FIGURE 2-27. BB Instructions Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
FIGURE 2-28. BITWT Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
FIGURE 2-29. MOVMPi Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
FIGURE 2-30. TBITS Instruction FormatÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28
FIGURE 2-31. SBITS Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28
FIGURE 2-32. SBITPS Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ28
FIGURE 3-1. Operating States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ29
FIGURE 3-2. Interrupt Dispatch and Cascade Tables ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31
FIGURE 3-3. Exception Acknowledge Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ31
FIGURE 3-4. Exception Processing Flowchart ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ33
FIGURE 3-5. Service SequenceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ34
FIGURE 3-6. CODEC ProtocolÐShort Frame ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37
FIGURE 3-7. CODEC ProtocolÐLong Frame ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ37
FIGURE 3-8. DSP Module Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ51
FIGURE 3-9. High Frequency Crystal ConnectionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ52
FIGURE 3-10. Low Frequency Resonator ConnectionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53
FIGURE 3-11. Recommended Reset ConnectionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53
FIGURE 3-12. Power-On Reset Requirements ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54
FIGURE 3-13. General Reset TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ54
FIGURE 4.1 Connection Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ56
FIGURE 4.2 Synchronous Output Signals Specification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
FIGURE 4.3 Synchronous Input Signals Specification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
5
List of Figures (Continued)
FIGURE 4.4 Asynchronous Signals Specification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
FIGURE 4.4a PWM Output Signal Specification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
FIGURE 4.4b Hysteresis Inputs Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ58
FIGURE 4.5a DRAM Read Cycle Timing (Internal ROM Mode Only)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61
FIGURE 4.5b DRAM Read Cycle Timing (External ROM Mode or Development Modes) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ61
FIGURE 4-5c. DRAM Write Cycle Timing (Internal ROM Mode Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ62
FIGURE 4-5d. DRAM Write Cycle Timing (External ROM or Development Modes) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ62
FIGURE 4-6. DRAM Refresh Cycle Timing (In Normal Operation Mode) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ62
FIGURE 4-7. DRAM Power Down RefreshÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ63
FIGURE 4-8. CODEC Long Frame Timing, 8 KHz Sampling Rate ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ63
FIGURE 4-9. CODEC Short Frame Timing, 8 KHz Sampling Rate ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ63
FIGURE 4-10. CDOUT Hold TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64
FIGURE 4-11a. External Memory Read Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ64
FIGURE 4-11b. I/O Read Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ65
FIGURE 4-12a. External Memory WriteÐCycle Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ65
FIGURE 4-12b. I/O Write Cycle TimingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66
FIGURE 4-13a. Port A, Port B and Port C Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66
FIGURE 4-13b. PWM Output Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66
FIGURE 4-14. Port A and Port B Input Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ66
FIGURE 4-15. CTTL, OSCIN1 and OSCIN2 Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ67
FIGURE 4-16. Non Power On Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ67
FIGURE 4-17. Power On Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ67
List of Tables
TABLE 2-1. NS32AM162 Addressing ModesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
TABLE 2-2. NS32AM162 Instruction Set Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
TABLE 2-3. ‘op’ and ‘i’ Field Encodings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ27
TABLE 3-1. Summary of Exception ProcessingÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ35
TABLE 3-2. High Frequency Oscillator Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53
TABLE 3-3. Low Frequency Oscillator Circuit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ53
TABLE B-1. Basic Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ73
TABLE B-2. Average Instruction Execution Times with No Wait-States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ77
TABLE B-3. Average Instruction Execution Times with Wait-States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ78
PHYSICAL DIMENSIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ80
6
1.0 Product Introduction
The NS32AM162 processor performs the main tasks of a
Digital Answering Machine: system control, voice compres-
sion/decompression, and other voice services.
provides 25 Kbytes of on-chip program ROM (32 Kbytes in
the NS32AM163), and three on-chip general purpose I/O
ports. Figure 1-1 shows a DAM based on the NS32AM162
in its Internal ROM mode.
System control includes user interface via keyboard and dis-
play handling. This task also controls the phone line, and
monitors the activity on the line. The system control also
keeps track of the time and detects power failures.
External ROM Mode. This mode allows program flexibility
in the DAM application. In this mode, an external ROM can
be attached to the NS32AM162 to provide an easy way of
changing the DAM’s program. One on-chip general purpose
I/O port is provided, and two other I/O ports can be added
with minimal logic. Figure 1-2 shows a DAM based on the
NS32AM162 in its External ROM mode.
The voice compression/decompression consists of per-
forming transformations between voice samples and com-
pressed digital data. The on-chip DSPM allows the imple-
mentation of different voice handling algorithms, such as
GSM, Sub-Band Coding (SBC), and Linear Predictive Code
(LPC).
Development Mode. Development mode is useful for eval-
uation and testing. In this mode, external ROM, RAM, and
I/O devices can be connected to the NS32AM162. Some
pins are used to reflect the internal status of the
NS32AM162. No on-chip I/O ports are provided in this
mode. Figure 1-3 shows an Evaluation Board based on the
NS32AM162 in its Development mode.
Other voice services include DTMF detection and genera-
tion, tone generation, voice synthesis, voice recognition,
VOX detection, etc.
Three different system configurations are supported:
Internal ROM Mode. This mode provides the lowest chip
count for a full DAM solution. In this mode the NS32AM162
TL/EE/11732–2
FIGURE 1-1. NS32AM162ÐInternal ROM Mode
7
1.0 Product Introduction (Continued)
TL/EE/11732–3
FIGURE 1-2. NS32AM162ÐExternal ROM Mode
TL/EE/11732–4
FIGURE 1-3. NS32AM162ÐDevelopment Mode
8
1.0 Product Introduction (Continued)
The NS32AM162 is software-compatible with all other CPUs
in the family.
To summarize, the architectural features cited above pro-
vide two primary performance advantages and characteris-
tics:
The device incorporates all of the Series 32000 advanced
architectural features, with the exception of the virtual mem-
ory capability.
High-Level Language Support
#
Application Flexibility
#
Brief descriptions of the NS32AM162 features that are
shared with other members of the family are provided be-
low:
1.1 NS32AM162 SPECIAL FEATURES
In addition to the above Series 32000 features, the
NS32AM162 provides features that make the device ex-
tremely attractive for a wide range of applications where
graphics support, low chip count, and low power consump-
tion are required.
Powerful Addressing Modes. Eight addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
The most relevant of these features are the enhanced Digi-
tal Signal Processing performance which makes the chip
very attractive for voice applications.
Symmetric Instruction Set. While avoiding special case
instructions that compilers can’t use, the Series 32000 fami-
ly incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Graphics support is provided by seventeen instructions that
allow operations such as BITBLT, data compression/expan-
sion, fills, and line drawing, to be performed very efficiently.
The NS32AM162 allows systems to be built with either no or
a relatively small amount of random logic. The bus is highly
optimized to allow simple interfacing to a large variety of
DRAMs and peripheral devices. All the relevant bus access
signals and clock signals are generated on-chip. The cycle
extension logic is also incorporated on-chip.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each op-
erand can be referenced by any one of the addressing
modes provided.
This powerful memory-to-memory architecture permits
memory locations to be treated as registers for all useful
operations. This is important for temporary operands as well
as for context switching.
The device is fabricated in a low-power, high speed CMOS
technology. It also includes a power down mode to minimize
the power consumption.
The power save feature, the DSP Module and the Bus Char-
acteristics are described in the ‘‘Functional Description’’
section. A general overview of BITBLT operations and a
description of the graphics support instructions is provided
in Section 2.5. Details on all the NS32AM162 graphics in-
structions can be found in the NS32CG16 Printer/Display
Processor Programmer’s Reference Supplement.
Large, Uniform Addressing. The NS32AM162 has 32-bit
address pointers that can address up to 4 gigabytes without
any segmentation; this addressing scheme provides flexible
memory management without add-on expense.
Modular Software Support. Any software package for the
Series 32000 architecture can be developed independent of
all other packages, without regard to individual addressing.
In addition, ROM code is totally relocatable and easy to
access, which allows a significant reduction in hardware and
software cost.
9
2.0 Architectural Description
2.1 REGISTER SET
instructions or through the register addressing mode. The
other 29 belong to the DSP Module and to the on-chip pe-
ripherals. Figure 2-1 shows the NS32AM162 internal regis-
ters.
The NS32AM162 has 45 internal registers and a 2.1 Kbyte
RAM array. 16 of these registers belong to the CPU portion
of the device and are addressed either implicitly by specific
CPU Registers
DSP Module
General Purpose
32 Bits
Peripherals Registers
w
x
Interrupt Control Unit
R0–R7
A
X
IVCT
IMASK
IPEND
IECLR
Address
PC
Y
Z
SP0, SP1
FP
EABR
PARAM
REPEAT
Clock Generator
CLKCTL
SB
INTBASE
CLPTR
OVF
WATCHDOG
WDCTL
Processor Status
CLSTAT
ABORT
DSPINT
DSPMASK
EXT
PSR
PWM
PWMCTL
Configuration
CODEC Interface
MCFG
CFG
NMISTAT
CDATA0
CDATA1
CCTL1
CCTL2
I/O Ports
DIRA
DIRB
FIGURE 2-1. NS32AM162 Internal Registers
10
2.0 Architectural Description (Continued)
2.1.1 General Purpose Registers
15
8
7
0
There are eight registers (R0–R7) used for satisfying the
high speed general storage requirements, such as holding
temporary variables and addresses. The general purpose
registers are free for any use by the programmer. They are
32 bits in length. If a general purpose register is specified for
an operand that is 8 or 16 bits long, only the low part of the
register is used; the high part is not referenced or modified.
I
P
S
U
N
Z
F
J
K
L
T
C
FIGURE 2-2. Processor Status Register (PSR)
C
The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used with
the ADDC and SUBC instructions to perform multiple-
precision integer arithmetic calculations. It may have a
setting of 0 (no carry or borrow) or 1 (carry or borrow).
2.1.2 Address Registers
The seven address registers are used by the processor to
implement specific address functions. Except for the MOD
register that is 16 bits wide, all the others are 32 bits. A
description of the address registers follows.
T
L
The T bit causes program tracing. If this bit is set to 1, a
TRC trap is executed after every instruction (Section
3.3.1).
The L bit is altered by comparison instructions. In a com-
parison instruction the L bit is set to ‘‘1’’ if the second
operand is less than the first operand, when both oper-
ands are interpreted as unsigned integers. Otherwise, it
is set to ‘‘0’’. In Floating-Point comparisons, this bit is
always cleared.
PCÐProgram Counter. The PC register is a pointer to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section.
SP0, SP1ÐStack Pointers. The SP0 register points to the
lowest address of the last item stored on the INTERRUPT
STACK. This stack is normally used only by the operating
system. It is used primarily for storing temporary data, and
holding return information for operating system subroutines
and interrupt and trap service routines. The SP1 register
points to the lowest address of the last item stored on the
USER STACK. This stack is used by normal user programs
to hold temporary data and subroutine return information.
K
J
Reserved for use by the CPU.
Reserved for use by the CPU.
F
The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
Z
The Z bit is altered by comparison instructions. In a com-
parison instruction the Z bit is set to ‘‘1’’ if the second
operand is equal to the first operand; otherwise it is set
to ‘‘0’’.
When a reference is made to the selected Stack Pointer
(see PSR S-bit), the terms ‘‘SP Register’’ or ‘‘SP’’ are used.
SP refers to either SP0 or SP1, depending on the setting of
the S bit in the PSR register. If the S bit in the PSR is 0, SP
refers to SP0. If the S bit in the PSR is 1 then SP refers to
SP1.
N
The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to ‘‘1’’ if the sec-
ond operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to ‘‘0’’.
Stacks in the Series 32000 architecture grow downward in
memory. A Push operation pre-decrements the Stack Point-
er by the operand length. A Pop operation post-increments
the Stack Pointer by the operand length.
U
If the U bit is ‘‘1’’ no privileged instructions may be exe-
cuted. If the U bit is ‘‘0’’ then all instructions may be
FPÐFrame Pointer. The FP register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
e
executed. When U 0 the processor is said to be in Su-
pervisor Mode; when U 1 the processor is said to be in
e
User Mode. A User Mode program is restricted from exe-
cuting certain instructions and accessing certain regis-
ters which could interfere with the operating system. For
example,
a User Mode program is prevented from
The frame pointer holds the address in memory occupied by
the old contents of the frame pointer.
changing the setting of the flag used to indicate its own
privilege mode. A Supervisor Mode program is assumed
to be a trusted part of the operating system, hence it has
no such restrictions.
SBÐStatic Base. The SB register points to the global vari-
ables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module.
S
The S bit specifies whether the SP0 register or SP1 reg-
ister is used as the Stack Pointer. The bit is automatical-
ly cleared on interrupts and traps. It may have a setting
of 0 (use the SP0 register) or 1 (use the SP1 register).
INTBASEÐInterrupt Base. The INTBASE register holds
the address of the dispatch table for interrupts and traps
(Section 3.2.1).
P
I
The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3.3.1). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
2.1.3 Processor Status Register
The Processor Status Register (PSR) holds status informa-
tion for the microprocessor.
e
e
If I 1, then all interrupts will be accepted. If I 0, only
the NMI interrupt is accepted. Trap enables are not af-
fected by this bit.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all pro-
grams, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
11
2.0 Architectural Description (Continued)
2.1.4 Configuration Register
AÐAccumulator
The Configuration Register (CFG) is 32 bits wide, of which 5
bits are implemented.
The format of the accumulator is shown in Figure 2-5.
33
0
33
0
CFG is programmed by the SETCFG instruction. Whenever
the program writes into CFG, a 0 must be written into bits 1,
2, 3.
Imaginary
Real
FIGURE 2-5. Accumulator Format
[
]
The user must set bit 8 to 1 using the SETCFG DE instruc-
tion during the initialization of the chip. The format of CFG is
shown in Figure 2-3. The various control bits are described
below.
The A register is a complex accumulator. It has two 34-bit
fields: a real part, and an imaginary part. Bits 15 through 30
of the real and the imaginary parts of the accumulator can
be read or written by the core in one double-word access.
Bits 15 through 30 of the real part are mapped to the oper-
and’s bits 0 through 15, and bits 15 through 30 of the imagi-
nary part are mapped to the operand’s bits 16 through 31.
The accumulator can also be read and written by the com-
mand-list execution unit using the SA, SEA, LA and LEA
instructions (See Section 3.5 for more information).
31
8
7
0
Reserved
1
Res
0
0
0
I
FIGURE 2-3. Configuration Register (CFG)
I
Interrupt vectoring. This bit controls whether maskable
Note that when a value is stored in the accumulator by the
core, the value of PARAM.RND bit is copied into bit position
14 of both real and imaginary parts of the accumulator. This
technique allows rounding of the accumulator’s value in the
following DSPM instructions (See Section 3.5.5.3 for more
information on rounding).
e
interrupts are handled in nonvectored (I 0) or vec-
tored (I 1) mode. Refer to Section 3.2.3 for more in-
e
formation.
2.1.5 DSP Module Registers
The DSP Module (DSPM) contains 15 memory-mapped reg-
isters. All the registers, except OVF, CLSTAT, ABORT,
DSPINT and NMISTAT, are readable and writable. OVF,
CLSTAT, DSPINT and NMISTAT are read-only. ABORT is
write-only.
When the Accumulator is loaded either by the core or by the
LA or LEA instructions, bits 31–33 of the real and the imagi-
nary accumulators are loaded with the values of bit 30 of the
real and the imaginary parts respectively.
The DSPM registers are divided into two groups, according
to their function PARAM, OVF, X, Y, Z, A, REPEAT, CLPTR
and EABR are called DSPM dedicated registers. CLSTAT,
ABORT, DSPINT, DSPMASK, EXT and NMISTAT are called
CPU core interface registers.
When the Accumulator is loaded either by the core or by the
LA instruction, bits 0–13 of the real and the imaginary accu-
mulators are loaded with zeros.
X, Y, Z - Vector Pointers
The format of X, Y, and Z registers is shown in Figure 2-6.
Accesses to these registers must be aligned; word and dou-
ble-word accesses must occur on word and double-word
address boundaries respectively. Failing to do will cause un-
predictable results. Figure 2-4 shows the address map of
the DSP Module registers.
31
16 15
8 7
4 3
0
ADDRESS Reserved WRAP-AROUND INCREMENT
FIGURE 2-6. X, Y, Z Registers Format
The X, Y, and Z registers are used for addressing up to
three vector operands. They are 32-bit registers, with three
fields: ADDRESS, INCREMENT, and WRAP-AROUND. The
value in the ADDRESS field specifies the address of a word
in the on-chip memory. This field has 16 bits, and can ad-
dress up to 64 Kwords of internal memory. The ADDRESS
fields are initialized with the vector operands’ start-address-
es by commands in the command list. At the beginning of
each vector operation, the contents of the ADDRESS field
are copied to incrementors. Increments can be used by vec-
tor instructions to step through the corresponding vector
operands while executing the appropriate calculations.
There is an address wrap-around for those vector instruc-
tions that require some of their operands to be located in
cyclic buffers. The allowed values for the increment field are
Register
Name
Register
Address
PARAM
OVF
FFFF8000
FFFF8004
FFFF8008
FFFF800C
FFFF8010
FFFF8014
FFFF8018
FFFF8020
FFFF8024
FFFF9000
FFFF9004
FFFF9008
FFFF900C
FFFF9010
FFFF9014
X
Y
Z
A
REPEAT
CLPTR
EABR
CLSTAT
ABORT
DSPINT
DSPMASK
EXT
INCREMENT
0 through 15. The actual increment will be 2
words. The allowed values for the WRAP-AROUND field are
0
2
through 15. The actual WRAP-AROUND will be
WRAP-AROUND
words. The WRAP-AROUND must be
greater or equal to the INCREMENT.
The X, Y, and Z registers can be read and written by the
core. These registers can be read and written by the com-
mand-list execution unit, as well as by the core, when using
SX, SXL, SXH, SY, SZ, LX, LY and LZ instructions.
NMISTAT
FIGURE 2-4. DSP Module Registers Address Map
12
2.0 Architectural Description (Continued)
EABRÐExternal Address Base Register
PARAMÐVector Parameter Register
The format of the external address base register is shown in
Figure 2-7.
The format of the PARAM register is shown in Figure 2-9.
31
Reserved RND OP SUB CLR COJ
FIGURE 2-9. PARAM Register Format
26 25 24 19 18 17 16 15
0
31
17 16
0
Length
ADDRESS
0
FIGURE 2-7. EABR Register Format
The PARAM register is used to specify the number of itera-
tions and special options for the various instructions. The
options are: RND, OP, SUB, CLR, and COJ. The effect of
each of the bits of the PARAM register is specified in Sec-
tion 3.5.
The EABR register is used together with a 16-bit address
field to form a 32-bit external address. External addresses
are specified as the sum of the value in EABR and two times
the value of the 16-bit address pointed by registers X, Y or
Z. The only value allowed to be written into bits 0 through 16
of EABR is ‘‘0’’. The EABR register can be read and written
by the core. It can also be written by the command-list exe-
cution unit by using the LEABR instruction.
The PARAM register can be read and written by the core. It
can also be written by the command-list execution unit, by
using the LPARAM instruction. The value written into
PARAM.LENGTH must be greater then 0.
EABR can hold any value except for 0xFFFE0000. Access-
ing external memory with an 0xFFFE0000 in the EABR will
cause unpredictable results.
The value of PARAM.LENGTH is not changed during com-
mand-list execution, unless it is written into using the LPAR-
AM instruction.
CLPTRÐCommand List Pointer
REPEATÐCommand-List Repeat Register
The CLPTR is a 16-bit register that holds the address of the
current command in the internal RAM. Writing into the
CLPTR causes the DSPM command-list execution unit to
begin executing commands, starting from the address in
CLPTR. The CLPTR can be read and written by the core
while the command-list execution is idle.
The format of the repeat register is shown in Figure 2-10.
31
16 15
0
COUNT
TARGET
FIGURE 2-10. REPEAT Register Format
The REPEAT register is used, together with appropriate
commands, to implement loops and branches in the com-
mand list (see Section 3.5.5.7). The count is used to specify
the number of times a loop in the command list is to be
repeated. The target is used to specify a jump address with-
in the command list.
Whenever the DSPM command-list execution unit reads a
command from the DSPM RAM, the value of CLPTR is up-
dated to contain the address of the next command to be
executed. This implies, for example, that if the last com-
mand in a list is in address N, the CLPTR will hold a value of
a
N
1 following the end of command list execution.
The REPEAT register can be read and written by the core. It
can also be read and written by the command-list execution
unit by using SREPEAT and LREPEAT instructions respec-
tively.
OVFÐOverflow Register
The format of the overflow register is shown in Figure 2-8.
15
2
1
0
The value of REPEAT.COUNT changes during the execu-
tion of the DJNZ command.
Reserved
OVF SAT
FIGURE 2-8. OVF Register Format
ABORTÐAbort Register
The OVF register holds the current status of the DSPM
arithmetic unit. It has two fields: OVF and SAT. The OVF bit
is set to ‘‘1’’ whenever an overflow is detected in the DSPM
34-bit ALU (e.g., bits 32 and 33 of the ALU are not equal).
No overflow detection is provided for integers. The SAT bit
is set to ‘‘1’’ whenever a value read from the accumulator
cannot be represented within the limits of its data type (e.g.,
16 bits for real and integer, and 31 bits for extended real). In
this case the value read from the accumulator will either be
the maximum allowed value or the minimal allowed value for
this data type depending on the sign of the accumulator
value. Note that in some cases when the OVF is set, the
SAT will not be set. The reason is that if an OVF occurred,
the value in the accumulator can no longer be used for
proper SAT detection. Upon reset, and whenever the
ABORT register is written, the non reserved bits of the OVF
register is cleared to ‘‘0’’.
The ABORT register is used to force execution of the com-
mand list to halt. Writing any value into this register stops
execution, and clears the contents of OVF, EXT, DSPINT
and DSPMASK. The ABORT register can only be written
and only by the core.
EXTÐExternal Memory Reference Control Register
The format of the external memory reference control regis-
ter is shown in Figure 2-11.
15
1
0
Reserved
FIGURE 2-11. EXT Register Format
HOLD
The EXT register controls external references. The com-
mand-list execution unit checks the value of EXT. HOLD
before each external memory reference. When EXT.HOLD
is ‘‘0’’, external memory references are allowed. When
EXT.HOLD is ‘‘1’’, and external memory references are re-
quested, the execution of the command list will stop until
EXT.HOLD is ‘‘0’’. Upon reset, and whenever the ABORT
register is written, EXT.HOLD is cleared to ‘‘0’’. The EXT
register can be read or written by the core.
The OVF is a read only register. It can be read by the core. It
can also be read by the command-list execution unit using
the SOVF instruction. Reading the OVF by either the core or
the command-list execution unit clears it to ‘‘0’’.
13
2.0 Architectural Description (Continued)
CLSTATÐCommand-List Execution Status Register
while the previous handler has not yet exited) will read and
handle more than one set bit in NMISTAT. Since the read
operation clears the register, the interrupted handler may
find that no bits are set.
The format of the command-list execution status register is
shown in Figure 2-12.
15
1
0
2.1.6 Interrupt Control Unit (ICU) Register
IVCTÐInterrupt Vector Register
Reserved
FIGURE 2-12. CLSTAT Register Format
RUN
Byte wide. Read only. IVCT holds the encoded number of
the highest priority unmasked pending interrupt request. In-
terrupt vector numbers are always positive, in the range
0x11 to 0x14.
The CLSTAT register displays the current status of the exe-
cution of the command list. When the command-list execu-
tion is idle, CLSTAT.RUN is ‘‘0’’, and when it is active,
CLSTAT.RUN is ‘‘1’’. Upon reset, the CLSTAT register is
cleared to ‘‘0’’. It can only be read, and only by the core.
7
6
5
4
3
2
0
DSPINT, DSPMASK, NMISTATÐInterrupt Control
Registers
0
0
0
1
0
VECTOR
FIGURE 2-15. IVCT Register Format
IMASKÐMask Register
The format of DSPINT and DSPMASK is shown in Figure
2-13.
15
1
0
[
]
Byte wide. A value of ‘‘0’’ in bit position i (i in 1..4 ) disables
the corresponding interrupt source. IMASK bits 0 and 5
through 7 are reserved. The non-reserved bits of IMASK
register are cleared to ‘‘0’’ upon reset, and when
CLKCTL.PDM is ‘‘1’’.
Reserved
HALT
FIGURE 2-13. DSPINT and DSPMASK Register Format
The DSPINT register holds the current status of interrupt
requests. Whenever execution of the command list is
stopped, the DSPINT.HALT bit is set to ‘‘1’’. The DSPINT is
a read only register. It is cleared to ‘‘0’’ whenever it is read,
whenever the ABORT register is written, and upon reset.
7
5
4
3
2
1
0
Reserved
M4 M3 M2 M1
Reserved
FIGURE 2-16. IMASK Register Format
The DSPMASK register is used to mask the DSPINT. HALT
flag. An interrupt request is transferred to the interrupt logic
of the IOUT output pin whenever the DSPINT.HALT bit is
set to ‘‘1’’, and the DSPMASK.HALT bit is unmasked (set to
‘‘1’’). See Section 6.1 for the functionality of IOUT.
DSPMASK can be read and written by the core. Upon reset,
and whenever the ABORT register is written, all the bits in
DSPMASK are cleared to ‘‘0’’.
IPENDÐInterrupt Pending Register
Byte wide. Read only. Reading a value of ‘‘1’’ in bit position i
[
]
(i in 1..4 ) indicates that the respective interrupt source is
active. IPEND bits 0 and 5 through 7 are reserved. The non-
reserved bits of IPEND are cleared to ‘‘0’’ upon reset and
when CLKCTL.PDM is ‘‘1’’.
7
5
4
3
2
1
0
The format of the NMISTAT register is shown inFigure 2-14.
Reserved
P4 P3 P2 P1
Reserved
15
4
3
2
1
0
FIGURE 2-17. IPEND Register Format
Reserved
WD ERR UND Res
FIGURE 2-14. NMISTAT Register Format
IECLRÐEdge Interrupt Clear Register
The NMISTAT holds the status of the current pending Non-
Maskable Interrupt (NMI) requests.
Byte wide. Write only. A pending edge triggered interrupt is
cleared by writing ‘‘1’’ to the respective bit position in
IECLR. Writing ‘‘0’’ has no effect. Note that INT2 does not
have a corresponding clear bit in IECLR. INT2 is a level
sensitive interrupt, and it is cleared by writing directly to the
DSPINT register. IECLR bits 0 and 5 through 7 are reserved.
Whenever the core attempts to access the DSPM address
space while the CLSTAT.RUN bit is ‘‘1’’ (except for access-
es to the CLSTAT, EXT, DSPINT, NMISTAT DSPMASK, and
ABORT registers) NMISTAT.ERR is set to ‘‘1’’.
Whenever there is an attempt to execute a DBPT instruc-
tion, a reserved DSPM instruction (Section 3.5), the
NMISTAT.UND bit is set to ‘‘1’’.
7
5
4
3
2
1
0
Reserved
CLR4 CLR3
0
CLR1
Reserved
When the WATCHDOG is not cleared in time (see Section
3.4.6), the NMISTAT.WD bit is set to ‘‘1’’.
FIGURE 2-18. IECLR Register Format
2.1.7 CODEC Interface Registers
When one of the bits in NMISTAT is set to ‘‘1’’, a NMI re-
quest to the core is issued.
The CODEC Interface contains five 8-bit registers that are
used to select the CODEC interface and to communicate
with the CODEC. The CODEC Interface registers should not
be accessed during Power Down.
The NMISTAT register is cleared to 0 upon reset, and each
time its contents are read.
When one of the bits in NMISTAT is set to 1, an NMI occurs.
The NMI handler can read the NMISTAT register to deter-
mine the source of the interrupt. Note that since NMIs may
be nested, it is possible that a second NMI handler (invoked
MCFGÐModules Configuration Register
This register controls the CODEC Interface configuration.
Bits 0–2 of MCFG are desinated CMC (CODEC Mode Con-
trol). Bits 3–7 are reserved.
14
2.0 Architectural Description (Continued)
The different configurations are as follows:
CLKCTLÐClock Generator Control Register
CODEC
CODEC
PWM/CFS1
Output
7
2
1
0
CMC
Configuration
Protocol
Reserved
DHFO
PDM
000 Undefined (Reset)
001 One Serial CODEC
PWM
PWM
FIGURE 2-19. CLKCTL Register Format
Short Frame
Format
PDM Power Down Mode Control
e
e
PDM
PDM
0 : normal operation mode
1 : power down mode
101 One Serial CODEC
Long Frame
Format
PWM
CFS1
CFS1
DHFO Disable High Frequency Oscillator
011 Two Serial CODECs Short Frame
Format
e
e
DHFO
DHFO
0 : High Frequency Oscillator enabled
1 : High Frequency Oscillator disabled
111 Two Serial CODECs Long Frame
Format
2.1.10 WATCHDOG (WD) Registers
The WATCHDOG (WD) contains one 8-bit register (WDCTL)
that controls the operation of the WD.
All other CMC values are reserved.
See Section 3.4.6 for a detailed description of the operation
of the WD.
Upon reset, CMC is set to 000. It must be set to the appro-
priate value prior to any reference to the CODEC, or to the
PWMCNT register, or to the other CODEC Interface regis-
ters. The value of MCFG is retained during power down.
2.1.11 I/O Ports Registers
The I/O Ports block contains two 8-bit write-only registers,
DIRA and DIRB, that control the direction of the bits of Port
A and Port B respectively.
CDATA0ÐCODEC0 Data
Data to be transferred to CODEC0 is written by software to
this register. It is shifted serially to that CODEC following the
next frame sync signal. Data that was shifted in from CO-
DEC0 can be read by software from this register. Bit 7 is
shifted first. The value of CDATA0 is unpredictable during
the shift itself.
A ‘‘1’’ in one of the bits configures the associated I/O pin as
an output. A ‘‘0’’ configures it as an input.
2.2 MEMORY ORGANIZATION
The main memory of the NS32AM162 is a uniform linear
address space. Memory locations are numbered sequential-
32
CDATA1ÐCODEC1 Data
b
ly starting at zero and ending at 2
1. The number speci-
Data to be transferred to CODEC1 is written by software to
this register. It is shifted serially to that CODEC following the
next frame sync signal. Data that was shifted in from CO-
DEC1 can be read by software from this register. Bit 7 is
shifted first. The value of CDATA1 is unpredictable during
the shift itself.
fying a memory location is called an address. The contents
of each memory location is a byte consisting of eight bits.
Unless otherwise noted, diagrams in this document show
data stored in memory with the lowest address on the right
and the highest address on the left. Also, when data is
shown vertically, the lowest address is at the top of a dia-
gram and the highest address at the bottom of the diagram.
When bits are numbered in a diagram, the least significant
bit is given the number zero, and is shown at the right of the
diagram. Bits are numbered in increasing significance and
toward the left.
CCTL1, CCTL2ÐCODEC Clock Control
Control the CODEC frame sync clock and master clock
(CCLK). The NSVOICE software package supports two
sampling ratesÐ8000 Hz and 7273 Hz. The respective
CCTL1 and CCTL2 values are the following:
7
0
Sampling Rate
8000 Hz
CCLK Frequency
2.048 MHz
CCTL1
CCTL2
33 (hex)
23 (hex)
0
0
A
7273 Hz
1.862 MHz
Byte at Address A
Upon reset and upon exit from Power Down mode, CCTL2
is set to 33 (hex), and CCTL1 to 0, selecting a sampling rate
of 8000 Hz.
Two contiguous bytes are called a word. Except where not-
ed, the least significant byte of a word is stored at the lower
address, and the most significant byte of the word is stored
at the next higher address. In memory, the address of a
word is the address of its least significant byte, and a word
may start at any address.
2.1.8 Pulse Width Modulator (PWM) Registers
The Pulse Width Modulator (PWM) contains one 8-bit regis-
ter (PWMCTL) that controls the duty cycle of the 80 KHz
PWM output.
15
8
7
0
See Section 3.4.4 for a detailed description of the operation
of the PWM.
a
A
1
A
2.1.9 Clock Generator Registers
MSB
LSB
Word at Address A
The Clock Generator contains one 8-bit register that con-
trols the high frequency oscillator and the power down
mode.
15
2.0 Architectural Description (Continued)
Two contiguous words are called a double-word. Except
where noted, the least significant word of a double-word is
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher. In
memory, the address of a double-word is the address of its
least significant byte, and a double-word may start at any
address.
Although memory is addressed as bytes, it is actually orga-
nized as words. Therefore, words and double-words that are
aligned to start at even addresses (multiples of two) are
accessed more quickly than words and double-words that
are not so aligned.
2.2.1 Address Mapping
The NS32AM162 supports the use of memory-mapped pe-
ripheral devices and coprocessors. Such memory-mapped
devices can be located at arbitrary locations within the
16-Mbyte address range available externally.
31
24 23
16 15
8
7
0
a
a
a
A 1
A
3
A
2
A
MSB
LSB
Figure 2-20 shows the NS32AM162 address mapping.
Double Word at Address A
First Address
(Hex)
Last Address
(Hex)
(1)
00000000
00000000
00000000
02000000
FFFDFC10
FFFE0000
FFFF8000
FFFF9000
FFFFA000
FFFFFE00
000063FF
Internal ROM Mode Internal ROM (25 Kbytes)
External ROM Mode External Memory
Development Mode External Memory
External DRAM
0001FFFF
0007FFFF
027FFFFF
FFFDFFFF
FFFE045F
FFFF8027
FFFF9013
FFFFA047
FFFFFFFF
System On-Chip RAM (1008 Bytes)
DSPM Internal RAM (1120 Bytes)
DSPM Dedicated Registers
DSPM Control/Status Registers
On-Chip Modules Registers
ICU and NMI Control
All other address ranges are reserved.
FIGURE 2-20a. NS32AM162 Address Mapping
Note 1: 00007FFF in the NS32AM163 (32 Kbytes)
Module
Register
Address
ICU
IVCT
FFFFFE00
FFFFFE04
FFFFFE08
FFFFFE0C
IMASK
IPEND
IECLR
I/O
DIRA
FFFFA101
FFFFA201
FFFFA401
FFFFA501
FFFFA601
DIRB
PORTA
PORTB
PORTC
Clock Generator
WATCHDOG
PWM
CLKCTL
WDCTL
FFFFA010
FFFFA000
FFFFA020
PWMCTL
CODEC Interface
MCFG
FFFFA024
FFFFA028
FFFFA02A
FFFFA02C
FFFFA02E
CDATA0
CDATA1
CCTL1
CCTL2
FIGURE 2-20b. NS32AM162 Modules Address Mapping
16
2.0 Architectural Description (Continued)
2.3 INSTRUCTION SET
Addressing modes in the NS32AM162 are designed to opti-
mally support high-level language accesses to variables. In
nearly all cases, a variable access requires only one ad-
dressing mode, within the instruction that acts upon that
variable. Extraneous data movement is therefore minimized.
2.3.1 General Instruction Format
Figure 2-22 shows the general format of a Series 32000
instruction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Ad-
dressing Mode (‘‘Gen’’) fields. Following the Basic Instruc-
tion field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes se-
lected.
NS32AM162 Addressing Modes fall into eight basic types:
Register: The operand is available in one of the eight Gen-
eral Purpose Registers. In certain Slave Processor instruc-
tions, an auxiliary set of eight registers may be referenced
instead.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before index-
ing.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Memory Space: Identical to Register Relative above, ex-
cept that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas gen-
erally needed by high-level languages.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the select-
ed addressing modes. Each Disp/lmm field may contain
one of two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-23, with the remaining bits inter-
preted as a signed (two’s complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most-signifi-
cant byte first. Note that this is different from the memory
representation of data (Section 2.2).
Memory Relative: A pointer variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pointer to generate the Effec-
tive Address of the operand.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
Some instructions require additional ‘‘implied’’ immediates
and/or displacements, apart from those associated with ad-
dressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Section 2.3.3).
Top of Stack: The currently-selected Stack Pointer (SP0 or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode ex-
cept Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any Gen-
eral Purpose Register by 1, 2, 4 or 8 and adding into the
total, yielding the final Effective Address of the operand.
TL/EE/11732–5
FIGURE 2-21. Index Byte Format
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Series 32000
Instruction Set Reference Manual.
2.3.2 Addressing Modes
The NS32AM162 CPU generally accesses an operand by
calculating its Effective Address based on information avail-
able when the operand is to be accessed. The method to be
used in performing this calculation is specified by the pro-
grammer as an ‘‘addressing mode’’.
In addition to the general modes, Register-Indirect with
auto-increment/decrement and warps or pitch are available
on several of the graphics instructions.
TL/EE/11732–6
FIGURE 2-22. General Instruction Format
17
2.0 Architectural Description (Continued)
b
a
Byte Displacement: Range 64 to 63
TL/EE/11732–7
FIGURE 2-23. Displacement Encodings
18
2.0 Architectural Description (Continued)
TABLE 2-1. NS32AM162 Addressing Modes
ENCODING
Register
00000
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
R0 or F0
R1 or F1
R2 or F2
R3 or F3
R4 or F4
R5 or F5
R6 or F6
R6 or F7
None: Operand is in the specified
register.
00001
00010
00011
00100
00101
00110
00111
Register Relative
01000
a
Register.
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(R0)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp
01001
01010
01011
01100
01101
01110
01111
Memory Relative
10000
a
Pointer; Pointer found at
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (SB))
Disp2
a
Register. ‘‘SP’’
10001
address Disp 1
10010
is either SP0 or SP1, as selected
in PSR.
Reserved
10011
(Reserved for Future Use)
Immediate
Immediate
10100
value
None: Operand is input from
instruction queue.
Absolute
10101
@
Absolute
disp
Disp.
Top Of Stack
10111
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Memory Space
11000
a
Register; ‘‘SP’’ is either
SP0 or SP1, as selected in PSR.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
Disp
11001
11010
a
disp
11011
*
Scaled Index
11100
a
[
]
]
]
]
Index, bytes
mode Rn:B
EA (mode)
EA (mode)
EA (mode)
EA (mode)
Rn.
a
a
a
c
[
11101
Index, words
mode Rn:W
2
Rn.
Rn.
Rn.
c
[
11110
Index, double words
Index, quad words
mode Rn:D
4
c
[
mode Rn:Q
11111
8
‘‘Mode’’ and ‘‘n’’ are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
19
2.0 Architectural Description (Continued)
2.3.3 Instruction Set Summary
e e
Floating Point length suffix: F Standard Floating
f
e
L
Long Floating
Table 2-2 presents a brief description of the NS32AM162
instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the De-
scription column provides a short description of the function
provided by that instruction. Further details of the exact op-
erations performed by each instruction may be found in the
Series 32000 Instruction Set Reference Manual and the
NS32CG16 Printer/Display Processor Programmer’s Refer-
ence.
e
gen General operand. Any addressing mode can be speci-
fied.
e
short A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
e
imm Implied immediate operand. An 8-bit value appended
after any addressing extensions.
e
disp Displacement (addressing constant): 8, 16 or 32 bits.
All three lengths legal.
e
reg Any General Purpose Register: R0–R7.
Notations:
e
areg Any Processor Register: SP, SB, FP, INTBASE, PSR,
US (bottom 8 PSR bits).
e
e
e
e
i
Integer length suffix: B
Byte
Word
Double Word
W
D
e
cond Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
TABLE 2-2. NS32AM162 Instruction Set Summary
MOVES
Format
Operation
Operands
Description
4
2
7
7
7
7
7
4
MOVi
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Move a value.
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
Extend and move a signed 4-bit constant.
Move multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move effective address.
INTEGER ARITHMETIC
Format
Operation
Operands
Description
4
2
4
4
4
6
6
7
7
7
7
7
7
7
ADDi
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2’s complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to extended integer.
Divide extended integer.
MODi
MEIi
DEIi
PACKED DECIMAL (BCD) ARITHMETIC
Format
Operation
Operands
Description
6
6
ADDPi
SUBPi
gen,gen
gen,gen
Add packed.
Subtract packed.
20
2.0 Architectural Description (Continued)
TABLE 2-2. NS32AM162 Instruction Set Summary (Continued)
INTEGER COMPARISON
Format
Operation
Operands
gen,gen
Description
4
2
7
CMPi
Compare.
CMPQi
CMPMi
short,gen
gen,gen,disp
Compare to signed 4-bit constant.
Compare multiple: disp bytes (1 to 16).
LOGICAL AND BOOLEAN
Format
Operation
Operands
Description
4
4
4
4
6
6
2
ANDi
ORi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Logical AND.
Logical OR.
BICi
Clear selected bits.
XORi
COMi
NOTi
Scondi
Logical exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
SHIFTS
Format
Operation
Operands
Description
6
6
6
LSHi
ASHi
ROTi
gen,gen
gen,gen
gen,gen
Logical shift, left or right.
Arithmetic shift, left or right.
Rotate, left or right.
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records used in
Pascal. ‘‘Extract’’ instructions read and align a bit field. ‘‘Insert’’ instructions write a bit field from an aligned source.
Format
Operation
Operands
Description
8
8
7
7
8
EXTi
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm,imm
reg,gen,gen
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to bit field pointer.
INSi
EXTSi
INSSi
CVTP
ARRAYS
Format
Operation
CHECKi
INDEXi
Operands
reg,gen,gen
reg,gen,gen
Description
8
8
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
21
2.0 Architectural Description (Continued)
TABLE 2-2. NS32AM162 Instruction Set Summary (Continued)
Options on all string instructions are:
STRINGS
String instructions assign specific functions to the General
Purpose Registers:
B (Backward):
Decrement string pointers after each
step rather than incrementing.
R4 Ð Comparison Value
R3 Ð Translation Table Pointer
R2 Ð String 2 Pointer
R1 Ð String 1 Pointer
R0 Ð Limit Count
U (Until match):
End instruction if String 1 entry matches
R4.
W (While match): End instruction if String 1 entry does not
match R4.
All string instructions end when R0 decrements to zero.
Format
Operation
Operands
Description
5
MOVSi
MOVST
CMPSi
CMPST
SKPSi
options
options
options
options
options
options
Move string 1 to string 2.
Move string, translating bytes.
Compare string 1 to string 2.
Compare, translating string 1 bytes.
Skip over string 1 entries.
5
5
SKPST
Skip, translating bytes for until/while.
JUMPS AND LINKAGE
Format
Operation
Operands
Description
3
0
0
3
2
3
1
1
1
1
1
1
1
1
1
JUMP
BR
gen
Jump.
disp
Branch (PC Relative).
Bcond
CASEi
ACBi
JSR
disp
Conditional branch.
gen
Multiway branch.
short,gen,disp
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
gen
disp
BSR
Branch to subroutine.
SVC
Supervisor call.
FLAG
BPT
Flag trap.
Breakpoint trap.
[
[
]
]
ENTER
EXIT
RET
reg list , disp
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
reg list
disp
RETT
RETI
disp
Return from trap. (Privileged)
Return from interrupt. (Privileged)
CPU REGISTER MANIPULATION
Format
Operation
Operands
Description
[
[
]
]
1
1
2
2
3
3
3
5
SAVE
reg list
reg list
Save general purpose registers.
RESTORE
LPRi
Restore general purpose registers.
areg,gen
areg,gen
gen
Load dedicated register. (Privileged if PSR or INTBASE)
Store dedicated register. (Privileged if PSR or INTBASE)
Adjust stack pointer.
SPRi
ADJSPi
BISPSRi
BICPSRi
SETCFG
gen
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set configuration register. (Privileged)
gen
[
]
option list
22
2.0 Architectural Description (Continued)
TABLE 2-2. NS32AM162 Instruction Set Summary (Continued)
MISCELLANEOUS
Format
Operation
Operands
Description
1
1
1
NOP
WAIT
DIA
No operation.
Wait for interrupt.
Diagnose. Single-byte ‘‘Branch to Self’’ for hardware
breakpointing. Not for use in programming.
GRAPHICS
Format
Operation
Operands
Description
5
5
5
5
5
5
5
5
5
5
BBOR
options*
options
Bit-aligned block transfer ‘OR’.
Bit-aligned block transfer ‘AND’.
Bit-aligned block transfer fast ‘OR’.
Bit-aligned block transfer ‘XOR’.
Bit-aligned block source to destination.
Bit-aligned word transfer.
Move multiple pattern.
BBAND
BBFOR
BBXOR
BBSTOD
BITWT
MOVMPi
TBITS
options
options
options
Test bit string.
SBITS
Set bit string.
SBITPS
Set bit perpendicular string.
BITS
Format
Operation
Operands
Description
4
6
6
6
8
TBITi
SBITi
CBITi
IBITi
FFSi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Test bit.
Test and set bit.
Test and clear bit.
Test and invert bit.
Find first set bit.
*Note: Options are controlled by fields of the instruction, PSR status bits, or dedicated register values.
2.4 GRAPHICS SUPPORT
the origin in the upper left. A movement to the right increas-
es the x coordinate; a movement downward increases the y
coordinate.
The following sections provide a brief description of the
NS32AM162 graphics support capabilities. Basic discus-
sions on frame buffer addressing and BITBLT operations
are also provided. More detailed information on the
NS32AM162 graphics support instructions can be found in
the NS32CG16 Printer/Display Processor Programmer’s
Reference.
The correspondence between the location of a pixel in the
Cartesian space and the physical (BIT) address in memory
is shown in Figure 2-24. The origin of the Cartesian space
e
e
(x 0, y 0) corresponds to the bit address ‘‘ORG’’. Incre-
menting the x coordinate increments the bit address by one.
Incrementing the y coordinate increments the bit address by
an amount representing the warp (or pitch) of the Cartesian
space. Thus, the linear address of a pixel at location (x, y) in
the Cartesian space can be found by the following expres-
sion.
2.4.1 Frame Buffer Addressing
There are two basic addressing schemes for referencing
pixels within the frame buffer: Linear and Cartesian (or x-y).
Linear addressing associates a single number to each pixel
representing the physical address of the corresponding bit
in memory. Cartesian addressing associates two numbers
to each pixel representing the x and y coordinates of the
pixel relative to a point in the Cartesian space taken as the
origin. The Cartesian space is generally defined as having
e
a
a
y * WARP x
ADDR
ORG
Warp is the distance (in bits) in the physical memory space
between two vertically adjacent bits in the Cartesian space.
23
2.0 Architectural Description (Continued)
Example 1 below shows two NS32AM162 instruction se-
quences to set a single pixel given the x and y coordinates.
Example 2 shows how to create a fat pixel by setting four
adjacent bits in the Cartesian space.
2.4.2 BITBLT Fundamentals
BITBLT, BIT-aligned BLock Transfer, is a general operator
that provides a mechanism to move an arbitrary size rectan-
gle of an image from one part of the frame buffer to another.
During the data transfer process a bitwise logical operation
can be performed between the source and the destination
data. BITBLT is also called RasterOp: operations on rasters.
It defines two rectangular areas, source and destination,
and performs a logical operation (e.g., AND, OR, XOR) be-
tween these two areas and stores the result back to the
destination. It can be expressed in simple notation as:
Example 1: Set pixel at location (x, y)
Setup: R0 x coordinate
R1 y coordinate
Instruction Sequence 1:
Source op Destination
x
Destination
MULD
ADDD
WARP, R1
R0, R1
; Y*WARP
op: AND, OR, XOR, etc.
; 0 X 4 BIT OFFSET
; SET PIXEL
2.4.2.1 Frame Buffer Architecture
SBITD R1, ORG
There are two basic types of frame buffer architectures:
plane-oriented or pixel-oriented. BITBLT takes advantage of
the plane-oriented frame buffer architecture’s attribute of
multiple, adjacent pixels-per-word, facilitating the movement
of large blocks of data. The source and destination starting
addresses are expressed as pixel addresses. The width and
height of the block to be moved are expressed in terms of
pixels and scan lines. The source block may start and end
at any bit position of any word, and the same applies for the
destination block.
Instruction Sequence 2:
INDEXD R1, (WARP-1), R0 ; Y*WARP 0 X
SBITD R1, ORG ; SET PIXEL
Example 2: Create fat pixel by setting bits at locations
a
a
a
(x, y), (x 1, y), (x, y 1) and (x 1, y 1).
a
Setup: R0 x coordinate
R1 y coordinate
2.4.2.2 Bit Alignment
Before a logical operation can be performed between the
source and the destination data, the source data must first
be bit aligned to the destination data. In Figure 2-25, the
source data needs to be shifted three bits to the right in
order to align the first pixel (i.e., the pixel at the top left
corner) in the source data block to the first pixel in the desti-
nation data block.
Instruction Sequence:
INDEXD R1, (WARP-1), R0 ; BIT ADDRESS
SBITD
41, ORG
; SET FIRST PIXEL
ADDQD
SBITD
1, R1
; (X01, Y)
R1, ORG
; SECOND PIXEL
2.4.2.3 Block Boundaries and Destination Masks
ADDD
(WARP-1), R1
R1, ORG
; (X, Y01)
Each BITBLT destination scan line may start and end at any
bit position in any data word. The neighboring bits (bits shar-
ing the same word address with any words in the destination
data block, but not a part of the BITBLT rectangle) of the
BITBLT destination scan line must remain unchanged after
the BITBLT operation.
SBITD
; THIRD PIXEL
ADDQD
SBITD
1, R1
; (X01, Y01)
R1, ORG
; LAST PIXEL
Due to the plane-oriented frame buffer architecture, all
memory operations must be word-aligned. In order to pre-
serve the neighboring bits surrounding the BITBLT destina-
tion block, both a left mask and a right mask are needed for
all the leftmost and all the rightmost data words of the desti-
nation block. The left mask and the right mask both remain
the same during a BITBLT operation.
The following example illustrates the bit alignment require-
ments. In this example, the memory data path is 16 bits
wide. Figure 2-25 shows a 32 pixel by 32 scan line frame
buffer which is organized as a long bit stream which wraps
around every two words (32 bits). The origin (top left corner)
of the frame buffer starts from the lowest word in memory
(word address 00 (hex)).
Each word in the memory contains 16 bits, D0–D15. The
least significant bit of a memory word, D0, is defined as the
first displayed pixel in a word. In this example, BITBLT ad-
dresses are expressed as pixel addresses relative to the
origin of the frame buffer. The source block starting address
is 021 (hex) (the second pixel in the third word). The desti-
nation block starting address is 204 (hex) (the fifth pixel in
the 33rd word). The block width is 13 (hex), and the height is
06 (hex) (corresponding to 6 scan lines). The shift value is 3.
TL/EE/11732–8
FIGURE 2-24. Correspondence between
Linear and Cartesian Addressing
24
2.0 Architectural Description (Continued)
TL/EE/11732–9
FIGURE 2-25. 32-Pixel by 32-Scan Line Frame Buffer
TL/EE/11732–10
TL/EE/11732–11
(a)
(b)
FIGURE 2-26. Overlapping BITBLT Blocks
The left mask and the right mask are 0000,1111,1111,1111 and 1111,1111,0000,0000 respectively.
Note 1: Zeros in either the left mask or the right mask indicate the destination bits which will not be modified.
Note 2: The BB(function) instruction uses different set up parameters, and techniques.
25
2.0 Architectural Description (Continued)
2.4.2.4 BITBLT Directions
line of the source will write to the circled pixel of the destina-
tion. Due to the overlap, this pixel is also part of the upper-
most scan line of the source rectangle. Thus, data needed
later is destroyed. Therefore, this BITBLT must be per-
formed in the DOWN direction. Another example of this oc-
curs any time the screen is moved in a purely vertical direc-
tion, as in scrolling text. It should be noted that, in both of
these cases, the choice of horizontal BITBLT direction may
be made arbitrarily.
A BITBLT operation moves a rectangular block of data in a
frame buffer. The operation itself can be considered as a
subroutine with two nested loops. The loops are preceded
by setup operations. In the outer loop the source and desti-
nation starting addresses are calculated, and the test for
completion is performed. In the inner loop the actual data
movement for a single scan line takes place. The length of
the inner loop is the number of (aligned) words spanned by
each scan line. The length of the outer loop is equal to the
height (number of scan lines) of the block to be moved. A
skeleton of the subroutine representing the BITBLT opera-
tion follows.
Figure 2-26(b) demonstrates a case in which the horizontal
BITBLT direction may not be chosen arbitrarily. This is an
instance of purely horizontal movement of data (panning).
Because the movement from source to destination involves
data within the same scan line, the incorrect direction of
movement will overwrite data which will be needed later. In
this example, the correct direction is from right to left.
BITBLT:
calculate BITBLT setup parameters;
(once per BITBLT operation).
such as
2.4.3 GRAPHICS SUPPORT INSTRUCTIONS
width, height
The NS32AM162 provides eleven instructions for support-
ing graphics oriented applications. These instructions are
divided into three groups according to the operations they
perform. General descriptions for each of them and the re-
lated formats are provided in the following sections.
bit misalignment (shift number)
left, right masks
horizontal, vertical directions
etc
#
2.4.3.1 BITBLT (BIT-aligned BLock Transfer)
#
OUTERLOOP: calculate source, dest addresses;
(once per scanline).
This group includes six instructions. They are used to move
characters and objects into the frame buffer which will be
printed or displayed.
INNERLOOP: move data, (logical operation) and incre-
ment addresses;
(once per word).
BIT-aligned BLock Transfer
Syntax: BB(function) Options
Setup:
R0
R1
R2
R3
R4
R5
R6
R7
base address, source data
base address, destination data
shift value
height (in lines)
first mask
second mask
source warp (adjusted)
destination warp (adjusted)
UNTIL
done horizontally
done vertically
(from BITBLT).
UNTIL
RETURN
Note: In the NS32AM162 only the setup operations must be done by the
programmer. The inner and outer loops are automatically executed
by the BITBLT instructions.
Each loop can be executed in one of two directions: the
inner loop from left to right or right to left, the outer loop
from top to bottom (down) or bottom to top (up).
0(SP) width (in words)
Function: AND, OR, XOR, FOR, STOD
Options: IA Increasing Address (default option).
The ability to move data starting from any corner of the
BITBLT rectangle is necessary to avoid destroying the
BITBLT source data as a result of destination writes when
the source and destination are overlapped (i.e., when they
share pixels). This situation is routinely encountered while
panning or scrolling.
When IA is selected, scan lines are
transferred in the increasing BIT/BYTE
order.
DA
Decreasing Address.
True Source (default option).
Inverted Source.
A determination of the correct execution directions of the
BITBLT must be performed whenever the source and
destination rectangles overlap. Any overlap will result in the
destruction of source data (from a destination write) if the
correct vertical direction is not used. Horizontal BITBLT di-
rection is of concern only in certain cases of overlap, as will
be explained below.
S
b
S
These five instructions perform standard BITBLT operations
between source and destination blocks. The operations
available include the following:
BBAND:
src
src
src
src
src
src
src
src
src
AND
AND
OR
dst
dst
dst
dst
dst
dst
dst
dst
dst
Figures 2-26(a) and(b) illustrate two cases of overlap. Here,
the BITBLT rectangles are three pixels wide by five scan
lines high; they overlap by a single pixel in (a) and a single
column of pixels in (b). For purposes of illustration, the
BITBLT is assumed to be carried out pixel-by-pixel. This
convention does not affect the conclusions.
b
b
b
BBOR:
OR
BBXOR:
XOR
XOR
OR
TO
TO
BBFOR:
BBSTOD:
InFigure 2-26(a), if the BITBLT is performed in the UP direc-
tion (bottom-to-top) one of the transfers of the bottom scan
b
26
2.0 Architectural Description (Continued)
b
Source’ respectively; ‘dst’ stands for ‘Destination’.
‘src’ and
‘
src’ stand for ‘True Source’ and ‘Inverted
2.4.3.2 Pattern Fill
Only one instruction is in this group. It is usually used for
clearing RAM and drawing patterns and lines.
Note 1: For speed reasons, the BB instructions require the masks to be
specified with respect to the source block. In Figure 2-25 masking
was defined relative to the destination block.
Move Multiple Pattern
Syntax: MOVMPi
b
Note 2: The options S and DA are not available for the BBFOR instruc-
tion.
Setup:
R0
R1
R2
R3
base address of the destination
pointer increment (in bytes)
number of pattern moves
source pattern
Note 3: BBFOR performs the same operation as BBOR with IA and S op-
tions.
b
Note 4: IA and DA are mutually exclusive and so are S and S.
Note 5: The width is defined as the number of words of source data to read.
Note: R1 and R3 are not modified by the instruction. R2 will always be
returned as zero. R0 is modified to reflect the last address into which
a pattern was written.
Note 6: An odd number of bytes can be specified for the source warp.
However, word alignment of source scan lines will result in faster
execution.
This instruction stores the pattern in register R3 into the
destination area whose address is in register R0. The pat-
tern count is specified in register R2. After each store oper-
ation the destination address is changed by the contents of
register R1. This allows the pattern to be stored in rows, in
columns, and in any direction, depending on the value and
sign of R1. The MOVMPi instruction format is shown in Fig-
ure 2-29.
The horizontal and vertical directions of the BITBLT opera-
tions performed by the above instructions, with the excep-
tion of BBFOR, are both programmable. The horizontal di-
rection is controlled by the IA and DA options. The vertical
direction is controlled by the sign of the source and destina-
tion warps. Figure 2-27 and Table 2-3 show the format of
the BB instructions and the encodings for the ‘op’ and ‘i’
fields.
23
15
8 7
0
23
16 15
8 7
0
0 0 0 0 0 0
0
0
0
0
0
1 1 1
i
0
0
0
0
1
1
1
0
0 0 0 0 0 0 D X S 0
op
i
0
0
0
0
1
1
1
0
D is set when the DA option is selected
#
#
#
FIGURE 2-29. MOVMPi Instruction Format
2.4.3.3 Data Compression, Expansion and Magnify
b
S is set when the S option is selected
X is set for BBAND, and it is clear for all other BB instructions
The three instructions in this group can be used to com-
press data and restore data from compression. A com-
pressed character set may require from 30% to 50% less
memory space for its storage.
FIGURE 2-27. BB Instructions Format
TABLE 2-3. ‘op’ and ‘i’ Field Encodings
Instruction
BBAND
BBOR
Options
Yes
‘op’ Field
1010
‘i’ Field
11
The compression ratio possible can be 50:1 or higher de-
pending on the data and algorithm used. TBITS can also be
used to find boundaries of an object. As a character is need-
ed, the data is expanded and stored in a RAM buffer. The
expand instructions (SBITS, SBITPS) can also function as
line drawing instructions.
Yes
0110
01
BBXOR
BBFOR
BBSTOD
Yes
1110
01
No
1100
01
Yes
0100
01
Test Bit String
Syntax: TBITS option
BIT-aligned Word Transfer
Syntax: BITWT
Setup:
R0
R1
R2
R3
R4
base address, source (byte address)
starting source bit offset
Setup:
R0
R1
R2
Base address, source word
Base address, destination double word
Shift value
destination run length limited code
maximum value run length limit
maximum source bit offset
The BITWT instruction performs a fast logical OR operation
between a source word and a destination double word,
stores the result into the destination double word and incre-
ments registers R0 and R1 by two. Before performing the
OR operation, the source word is shifted left (i.e., in the
direction of increasing bit numbers) by the value in register
R2.
Option:
1
0
count set bits until a clear bit is found
count clear bits until a set bit is found
Note: R0, R3 and R4 are not modified by the instruction execution. R1
reflects the new bit offset. R2 holds the result.
This instruction starts at the base address, adds a bit offset,
e
1). If clear (or set), the instruction increments to
and tests the bit for clear if ‘‘option’’
e
0 (and for set if
‘‘option’’
This instruction can be used within the inner loop of a block
OR operation. Its use assumes that the source data is
‘‘clean’’ and does not need masking. The BITWT format is
shown in Figure 2-28.
the next higher bit and tests for clear (or set). This testing
for clear proceeds through memory until a set bit is found or
until the maximum source bit offset or maximum run length
value is reached. The total number of clear bits is stored in
the destination as a run length value.
When TBITS finds a set bit and terminates, the bit offset is
adjusted to reflect the current bit address. Offset is then
23
16 15
8
7
0
e
ready for the next TBITS instruction with ‘‘option’’
0. After
0 0
0
0
0
0
0
0
0
0
1
0 0 0 0 1
0
0 0 0
1
1
1
0
FIGURE 2-28. BITWT Instruction Format
27
2.0 Architectural Description (Continued)
the instruction is executed, the F flag is set to the value of
the bit previous to the bit currently being pointed to (i.e., the
value of the bit on which the instruction completed execu-
tion). In the case of a starting bit offset exceeding the maxi-
Set BIT Perpendicular String
Syntax: SBITPS
Setup:
R0
R1
R2
R3
base address, destination (byte address)
starting bit offset
number of bits to set
t
mum bit offset (R1
R4), the F flag is set if the option was
1 and clear if the option was 0. The L flag is set when the
desired bit is found, or if the run length equalled the maxi-
mum run length value and the bit was not found. It is cleared
otherwise. Figure 2-30 shows the TBITS instruction format.
destination warp (signed value, in bits)
Note: When the instruction terminates, the R0 and R3 registers are re-
turned unchanged. R1 becomes the final bit offset. R2 is zero.
The SBITPS can be used to set a string of bits in any direc-
tion. This allows a font to be expanded with a 90 or 270
degree rotation, as may be required in a printer application.
SBITPS sets a string of bits starting at the bit address speci-
fied in registers R0 and R1. The number of bits in the string
is specified in R2. After the first bit is set, the destination
warp is added to the bit address and the next bit is set. The
process is repeated until all the bits have been set. A nega-
tive raster warp offset value leads to a 90 degree rotation. A
positive raster warp value leads to a 270 degree rotation. If
23
15
8 7
0
0 0 0 0 0 0
0
0 S 0
1
0 0 1 1 1 0
0
0
0
1
1
1
0
S is set for ‘‘TBITS 1’’ and clear for ‘‘TBITS 0’’.
#
FIGURE 2-30. TBITS Instruction Format
Set Bit String
Syntax: SBITS
e
a b
the R3 value is
(space warp 1 or 1), then the result is
b
Setup:
R0
R1
R2
R3
base address of the destination
starting bit offset (signed)
number of bits to set (unsigned)
address of string look-up table
a
a 45 degree line. If the R3 value is 1 or 1, a horizontal
line results.
SBITS and SBITPS allow expansion on any 90 degree an-
gle, giving portrait, landscape and mirror images from one
font. Figure 2-32 shows the SBITPS instruction format.
Note: When the instruction terminates, the registers are returned un-
changed.
SBITS sets a number of contiguous bits in memory to 1, and
is typically used for data expansion operations. The instruc-
tion draws the number of ones specified by the value in R2,
starting at the bit address provided by registers R0 and R1.
In order to maximize speed and allow drawing of patterned
lines, an external 1k byte lookup table is used. The lookup
table is specified in the NS32CG16 Printer/Display Proces-
sor Programmer’s Reference Supplement.
23
15
8 7
0
0 0 0 0 0 0
0
0
0
0
1
0 1 1 1 1 0
0
0
0
1
1
1
0
FIGURE 2-32. SBITPS Instruction Format
2.4.3.3.1 Magnifying Compressed Data
Restoring data is just one application of the SBITS and
SBITPS instructions. Multiplying the ‘‘length’’ operand used
by the SBITS and SBITPS instructions causes the resulting
pattern to be wider, or a multiple of ‘‘length’’.
When SBITS begins executing, it compares the value in R2
with 25. If the value in R2 is less than or equal to 25, the F
flag is cleared and the appropriate number of bits are set in
memory. If R2 is greater than 25, the F flag is set and no
other action is performed. This allows the software to use a
faster algorithm to set longer strings of bits. Figure 2-31
shows the SBITS instruction format.
As the pattern of data is expanded, it can be magnified by
2x, 3x, 4x, . . . , 10x and so on. This creates several sizes of
the same style of character, or changes the size of a logo. A
magnify in both dimensions X and Y can be accomplished
by drawing a single line, then using the MOVS (Move String)
or the BB instructions to duplicate the line, maintaining an
equal aspect ratio.
23
15
8 7
0
0 0 0 0 0 0
0
0
0
0
1
1 0 1 1 1 0
0
0
0
1
1
1
0
More information on this subject is provided in the
NS32CG16 Printer/Display Processor Programmer’s Refer-
ence Supplement.
FIGURE 2-31. SBITS Instruction Format
28
3.0 Functional Description
This chapter provides details on the functional characteris-
tics of the NS32AM162 microprocessor.
The chapter is divided into five main sections:
Instruction Execution, Exception Processing, Debugging,
DSP Module and System Interface.
3.1 INSTRUCTION EXECUTION
To execute an instruction, the NS32AM162 performs the
following operations:
Fetch the Instruction
#
Read Source Operands, if Any (1)
#
Calculate Results
#
Write Result Operands, if Any
#
Modify Flags, if Necessary
#
Update the Program Counter
#
Under most circumstances, the CPU can be conceived to
execute instructions by completing the operations above in
strict sequence for one instruction and then beginning the
sequence of operations for the next instruction. However,
due to the internal instruction pipelining, as well as the oc-
currence of exceptions, the sequence of operations per-
formed during the execution of an instruction may be al-
tered. Furthermore, exceptions also break the sequentiality
of the instructions executed by the CPU.
TL/EE/11732–12
Note 1: In this and following sections, memory locations read by the CPU to
calculate effective addresses for Memory-Relative addressing
modes are considered like source operands, even if the effective
address is being calculated for an operand with access class of
write.
FIGURE 3-1. Operating States
Other exceptions, like Divide-By-Zero Trap, are recognized
during execution of an instruction. When an exception is
recognized during execution of an instruction, the instruction
ends in one of four possible ways: completed, suspended,
terminated, or partially completed. Each type of exception
causes a particular ending, as specified in Section 3.2.
3.1.1 Operating States
The CPU has four operating states regarding the execution
of instructions and the processing of exceptions: Reset, Ex-
ecuting Instructions, Processing An Exception and Waiting-
For-An-Interrupt. The various states and transitions be-
tween them are shown in Figure 3-1.
3.1.2.1 Completed Instructions
When an exception is recognized after an instruction is
completed, the CPU has performed all of the operations for
that instruction and for all other instructions executed since
the last exception occurred. Result operands have been
written, flags have been modified, and the PC saved on the
Interrupt Stack contains the address of the next instruction
to execute. The exception service procedure can, at its con-
clusion, execute the RETT instruction (or the RETI instruc-
tion for maskable interrupts), and the CPU will begin execut-
ing the instruction following the completed instruction.
Whenever the RST signal is asserted, the CPU enters the
reset state. The CPU remains in the reset state until the
RST signal is driven inactive, at which time it enters the
Executing-Instructions state. In the Reset state the contents
of certain registers are initialized. Refer to Section 3.5.4 for
details.
In the Executing-Instructions state, the CPU executes in-
structions. It will exit this state when an exception is recog-
nized or a WAIT instruction is encountered. At which time it
enters the Processing-An-Exception state or the Waiting-
For-An-Interrupt state respectively.
3.1.2.2 Suspended Instructions
An instruction is suspended when one of several trap condi-
tions is detected during execution of the instruction. A sus-
pended instruction has not been completed, but all other
instructions executed since the last exception occurred
have been completed. Result operands and flags due to be
affected by the instruction may have been modified, but only
modifications that allow the instruction to be executed again
and completed can occur. For certain exceptions (Trap
While in the Processing-An-Exception state, the CPU saves
the PC and PSR register contents on the stack.
Following the completion of all data references required to
process an exception, the CPU enters the Executing-In-
structions state.
In the Waiting-For-An-Interrupt state, the CPU is idle. A spe-
cial status identifying this state is presented on the system
interface (Section 3.5). When an interrupt is detected, the
CPU enters the Processing-An-Exception State.
3.1.2 Instruction Endings
The NS32AM162 checks for exceptions at various points
while executing instructions. Certain exceptions, like inter-
rupts, are in most cases recognized between instructions.
29
3.0 Functional Description (Continued)
(UND)) the CPU clears the P-flag in the PSR before saving
the copy that is pushed on the Interrupt Stack. The PC
saved on the Interrupt Stack contains the address of the
suspended instruction.
completed instruction. The exception service procedure
can, at its conclusion, simply execute the RETT instruction
(or the RETI instruction for maskable interrupts), and the
CPU will resume executing the partially completed instruc-
tion.
To complete a suspended instruction, the exception service
procedure takes either of two actions:
3.2 EXCEPTION PROCESSING
1. The service procedure can simulate the suspended in-
struction’s execution. After calculating and writing the in-
struction’s results, the flags in the PSR copy saved on the
Interrupt Stack should be modified, and the PC saved on
the Interrupt Stack should be updated to point to the next
instruction to execute. The service procedure can then
execute the RETT instruction, and the CPU begins exe-
cuting the instruction following the suspended instruction.
Exceptions are special events that alter the sequence of
instruction execution. The CPU recognizes two basic types
of exceptions: interrupts and traps.
An interrupt occurs in response to an event signaled by acti-
vating the NMI or INT3 input signals. Interrupts are typically
requested by peripheral devices that require the CPU’s at-
tention.
Traps occur as a result either of exceptional conditions
(e.g., attempted division by zero) or of specific instructions
whose purpose is to cause a trap to occur (e.g., supervisor
call instruction).
2. The suspended instruction can be executed again after
the service procedure has eliminated the trap condition
that caused the instruction to be suspended. The service
procedure should execute the RETT instruction at its con-
clusion; then the CPU begins executing the suspended
instruction again. This is the action taken by a debugger
when it encounters a BPT instruction that was temporarily
placed in another instruction’s location in order to set a
breakpoint.
When an exception is recognized, the CPU saves the PC,
and the PSR register contents on the interrupt stack and
then it transfers control to an exception service procedure.
Details on the operations performed in the various cases by
the CPU to enter and exit the exception service procedure
are given in the following sections.
Note 1: It may be necessary for the exception service procedure to alter the
P-flag in the PSR copy saved on the Interrupt Stack: If the excep-
tion service procedure simulates the suspended instruction and the
P-flag was cleared by the CPU before saving the PSR copy, then
the saved T-flag must be copied to the saved P-flag (like the float-
ing-point instruction simulation described above). Or if the excep-
tion service procedure executes the suspended instruction again
and the P-flag was not cleared by the CPU before saving the PSR
copy, then the saved P-flag must be cleared (like the breakpoint
trap described above). Otherwise, no alteration to the saved P-flag
is necessary.
It is to be noted that the reset operation is not treated here
as an exception. Even though, like any exception, it alters
the instruction execution sequence.
The reason being that the CPU handles reset in a signifi-
cantly different way than it does for exceptions.
Refer to Section 3.6.4 for details on the reset operation.
3.2.1 Exception Acknowledge Sequence
When an exception is recognized, the CPU goes through
three major steps:
3.1.2.3 Terminated Instructions
An instruction being executed is terminated when reset oc-
curs. Any result operands and flags due to be affected by
the instruction are undefined, as is the contents of the PC.
1) Adjustment of Registers.
Depending on the source of the exception, the CPU may
restore and/or adjust the contents of the Program Coun-
ter (PC), the Processor Status Register (PSR) and the
currently-selected Stack Pointer (SP). A copy of the PSR
is made, and the PSR is then set to reflect Supervisor
Mode and selection of the Interrupt Stack.
3.1.2.4 Partially Completed Instructions
When an interrupt condition is recognized during execution
of a string instruction, the instruction is said to be partially
completed. A partially completed instruction has not com-
pleted, but all other instructions executed since the last ex-
ception occurred have been completed. Result operands
and flags due to be affected by the instruction may have
been modified, but the values stored in the string pointers
and other general-purpose registers used during the instruc-
tion’s execution allow the instruction to be executed again
and completed.
2) Vector Acquisition.
A Vector is either obtained from the Data Bus or is sup-
plied by default.
3) Service Call.
The Vector is used as an index into the Interrupt Dis-
patch Table, whose base address is taken from the CPU
Interrupt Base (INTBASE) Register. See Figure 3-2. A
32-bit address of the exception service procedure is read
from the table entry, and is loaded into the PC register.
The CPU clears the P-flag in the PSR before saving the
copy that is pushed on the Interrupt Stack. The PC saved on
the Interrupt Stack contains the address of the partially
30
3.0 Functional Description (Continued)
TL/EE/11732–13
FIGURE 3-2. Interrupt Dispatch and Cascade Tables
This process is illustrated in Figure 3-3, from the viewpoint
of the programmer.
Details on the sequences of events in processing interrupts
and traps are given in the following sections.
TL/EE/11732–14
FIGURE 3-3. Exception Acknowledge Sequence
31
3.0 Functional Description (Continued)
The service procedure returns from the Non-Maskable-In-
terrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
3.2.2 Returning from an Exception Service Procedure
To return control to an interrupted program, one of two in-
structions can be used: RETT (Return from Trap) and RETI
(Return from Interrupt).
3.2.5 Traps
RETT is used to return from any trap or a non-maskable
interrupt service procedure. Since some traps are often
used deliberately as a call mechanism for supervisor mode
procedures, RETT can also adjust the Stack Pointer (SP) to
discard a specified number of bytes from the original stack
as surplus parameter space.
Traps are processing exceptions that are generated as di-
rect results of the execution of an instruction.
The return address saved on the stack by any trap except
Trap (TRC) is the address of the first byte of the instruction
during which the trap occurred.
When a trap is recognized, maskable interrupts are not dis-
abled.
RETI is used to return from a maskable interrupt service
procedure. A difference of RETT, RETI also informs any
external interrupt control units that interrupt service has
completed. Since interrupts are generally asynchronous ex-
ternal events, RETI does not discard parameters from the
stack.
There are 7 trap conditions recognized by the NS32AM162
as described below.
Trap (ILL): Illegal operation. A privileged operation was at-
e
tempted while the CPU was in User Mode (PSR bit U
1).
Trap (SVC): The Supervisor Call (SVC) instruction was exe-
cuted.
Both of the above instructions always restore the PSR and
the PC registers to their previous contents.
Trap (DVZ): An attempt was made to divide an integer by
zero. (The FPU trap is used for Floating-Point division by
zero.)
3.2.3 Maskable Interrupts
Maskable interrupt requests are generated either externally
through the INT3 pin or internally. These requests are en-
abled to generate an interrupt only while the I-bit in the PSR
register is set to 1. The I-bit is automatically cleared during
service of a maskable interrupt or NMI, and is restored to its
original setting upon return from the interrupt service routine
via the RETT or RETI instruction.
Trap (FLG): The FLAG instruction detected a ‘‘1’’ in the
PSR F-bit.
Trap (BPT): The Breakpoint (BPT) instruction was execut-
ed.
Trap (TRC): The instruction just completed is being traced.
Refer to Section 3.3.1 for details.
Maskable interrupts can be configured through the I-bit in
e
Trap (UND): An undefined opcode was encountered by the
CPU.
the CFG register to be either non-vectored (CFG bit I
e
0)
or vectored (CFG bit I
1).
If the non-vectored mode is selected, a default vector value
of zero is always used. For the vectored mode instead, the
on-chip Interrupt Control Unit will provide the CPU with a
vector value. This vector value is then used as an index into
the Dispatch Table in order to find the entry for the proper
interrupt service procedure. The service procedure eventu-
ally returns via the Return from Interrupt (RETI) instruction,
which performs an End of Interrupt bus cycle.
3.2.6 Priority among Exceptions
The CPU checks for specific exceptions at various points
while executing an instruction. It is possible that several ex-
ceptions occur simultaneously. In that event, the CPU re-
sponds to the exception with highest priority.
Figure 3-4 shows an exception processing flowchart.
Before executing an instruction, the CPU checks for pend-
ing interrupts, or Trap (TRC). The CPU responds to any
pending interrupt requests; nonmaskable interrupts are rec-
ognized with higher priority than maskable interrupts. If no
interrupts are pending, then the CPU checks the P-flag in
the PSR to determine whether a Trap (TRC) is pending. If
the P-flag is 1, a Trap (TRC) is processed. If no interrupt or
Trap (TRC) is pending, the CPU begins executing the in-
struction.
3.2.3.1 Non-Vectored Mode
In the Non-Vectored mode, an interrupt request will cause
an Interrupt Acknowledge bus cycle, but the CPU will ignore
any value read from the bus and use instead a default vec-
tor of zero. This mode is useful for small systems in which
hardware interrupt prioritization is unnecessary.
3.2.4 Non-Maskable Interrupt
While executing an instruction, the CPU may recognize up
to two exceptions:
The Non-Maskable Interrupt is triggered whenever one of
the bits in the NMISTAT register is set to ‘‘1’’. The CPU
performs an ‘‘Interrupt Acknowledge’’ bus cycle from Ad-
1. Interrupt, if the instruction is interruptible.
dress FFFFFF00 when processing of this interrupt actual-
16
2. One of 6 mutually exclusive traps: ILL, SVC, DVZ, FLG,
BPT, UND
ly begins. The vector value used for the Non-Maskable In-
terrupt is taken as 1, regardless of the value read from the
bus.
If no exception is detected while the instruction is executing,
then the instruction is completed and the PC is updated to
point to the next instruction.
32
3.0 Functional Description (Continued)
TL/EE/11732–15
FIGURE 3-4. Exception Processing Flowchart
33
3.0 Functional Description (Continued)
3. If Trap (UND)
3.2.7 Exception Acknowledge Sequences: Detailed Flow
a. Clear the Processor Status Register P Bit.
For purposes of the following detailed discussion of excep-
tion acknowledge sequences, a single sequence called
‘‘service’’ is defined in Figure 3-5.
4. Copy the Processor Status Register (PSR) into a tempo-
rary register, then clear PSR bits T, U, S, and P.
5. Set ‘‘Return Address’’ to the address of the first byte of
the trapped instruction.
Upon detecting any interrupt request or trap condition, the
CPU first performs a sequence dependent upon the type of
exception. This sequence will include saving a copy of the
Processor Status Register and establishing a vector and a
return address. The CPU then performs the service se-
quence.
6. Perform Service (Vector, Return Address), Figure 3-5.
3.2.7.3. Trace Trap Sequence
1. In the Processor Status Register (PSR), clear the P bit.
2. Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
3.2.7.1 Maskable/Non-Maskable Interrupt Sequence
This sequence is performed by the CPU when an NMI re-
quest is active, or an interrupt request is active with the
PSR.I bit set. The interrupt sequence begins either at the
next instruction boundary or, in the case of the String in-
structions, or Graphics instructions which have interior
loops (BBOR, BBXOR, BBAND, BBFOR, MOVMP, SBITPS,
TBITS), at the next interruptible point during its execution.
The graphics instructions are interruptible.
3. Set ‘‘Vector’’ to 9.
4. Set ‘‘Return Address’’ to the address of the next instruc-
tion.
5. Perform Service (Vector, Return Address), Figure 3-5.
Service (Vector, Return Address):
1. Push the PSR copy onto the Interrupt Stack
as a 16-bit value.
1. If a String instruction was interrupted and not yet com-
pleted:
2. Read the 32-bit Interrupt Dispatch Table (IDT)
a
a. Clear the Processor Status Register P bit.
entry: address is Vector*4 INTBASE Regis-
ter contents.
b. Set ‘‘Return Address’’ to the address of the first byte
of the interrupted instruction.
3. Place the IDT entry in the Program Counter.
Otherwise, set ‘‘Return Address’’ to the address of the
next instruction.
4. Push the Return Address onto the Interrupt
Stack as a 32-bit quantity.
2. Copy the Processor Status Register (PSR) into a tempo-
rary register, then clear PSR bits S, U, T, P and I.
5. Flush Queue: Non-sequentially fetch first in-
struction of Interrupt Routine.
3. If the interrupt is Non-Maskable:
FIGURE 3-5. Service Sequence
Invoked during All Interrupt/Trap Sequences
a. Read
a
byte from address FFFFFF00
, applying
16
Status Code 0100 (Interrupt Acknowledge). Discard
the byte read.
3.3 DEBUGGING SUPPORT
b. Set ‘‘Vector’’ to 1.
c. Go to Step 6.
The NS32AM162 provides features to assist in program de-
bugging.
4. If the interrupt is Non-Vectored:
Besides the Breakpoint (BPT) instruction that can be used
to generate soft breaks, the CPU also provides the instruc-
tion tracing capability.
a. Read
a byte from address FFFFFE00 , applying
16
Status Code 0100 (Interrupt Acknowledge). Discard
the byte read.
3.3.1 Instruction Tracing
b. Set ‘‘Vector’’ to 0.
c. Go to Step 6.
Instruction tracing is a very useful feature that can be used
during debugging to single-step through selected portions of
a program. Tracing is enabled by setting the T-bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRC) after the execution of each instruction.
5. Here the interrupt is Vectored.
a. Read ‘‘Byte’’ from address FFFFFE00 , applying
16
Status Code 0100 (Interrupt Acknowledge).
At the beginning of each instruction, the T-bit is copied into
the PSR P (Trace ‘‘Pending’’) bit. If the P-bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced in-
struction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap se-
quence handles the P-bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
b. Read vector byte from the IVECT register of the on-
chip Interrupt Control Unit.
6. Perform Service (Vector, Return Address), Figure 3-5.
3.2.7.2 ILL/SVC/DVZ/FLG/BPT/UND
Trap Sequence
1. Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2. Set ‘‘Vector’’ to the value corresponding to the trap type.
The beginning of the execution of a TRAP(UND) is not con-
sidered to be a beginning of an instruction, and hence the
T-bit is not copied into the P-bit.
e
e
e
e
e
e
ILL:
Vector
Vector
Vector
Vector
Vector
Vector
4.
SVC:
DVZ:
FLG:
BPT:
UND:
5.
6.
Due to the fact that some instructions can clear the
T- and P-bits in the PSR, in some cases a Trace Trap may
not occur at the end of the instruction. This happens when
7.
8.
10.
34
3.0 Functional Description (Continued)
TABLE 3-1. Summary of Exception Processing
Instruction
Ending
Cleared before
Saving PSR
Cleared after
Saving PSR
Exception
Interrupt
Before Instruction
None /P*
TUSPI
UND
Suspended
Suspended
P
None
P
TUS
TUSP
TUS
SVC, DVZ, FLG, BPT, ILL
TRC
Before Instruction
one of the privileged instructions BICPSRW or LPRW PSR
is executed.
rupt to the NS32AM162 when required. Priority is resolved
on a fixed scheme. Each interrupt source can be masked by
a mask register. Pending interrupts can be polled using the
interrupt pending register.
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that spe-
cial care is taken before returning from the Trace Trap Serv-
ice Procedure. In case a BICPSRB instruction has been ex-
ecuted, the service procedure should make sure that the
T-bit in the PSR copy saved on the Interrupt Stack is set
before executing the RETT instruction to return to the pro-
gram being traced. If the RETT or RETI instructions have to
be traced, the Trace Trap Service Procedure should set the
P- and T-bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
The ICU handles four sources of interrupts: three of them
are internal, and one external. The external interrupt is trig-
gered by a falling edge on the INT3 input pin. The INT3 has
a Schmitt Trigger input buffer in order to produce jitter-free
interrupt requests out of slowly changing input signals. An
on-chip circuit synchronizes INT3 to the NS32AM162 clock.
For proper interrupt detection, INT3 must be pulled low for
at least 3 clock cycles.
Another interrupt, INT2, is level sensitive. It is triggered by
the DSPM upon completion of a command list execution
and when both DSPINT.HALT and DSPMASK.HALT are
‘‘1’’. INT2 is used to synchronize between command list
execution, and a core program. This can reduce the total
CPU utilization of applications which require asynchronous
operation of the DSPM.
While debugging the NS32AM162 instructions which have
interior loops (BBOR, BBXOR, BBAND, BBFOR, MOVMP,
SBITPS, TBITS), special care must be taken with the single-
step trap. If an interrupt occurs during a single-step of one
of the graphics instructions, the interrupt will be serviced.
Upon return from the interrupt service routine, the new
NS32AM162 instruction will not be re-entered, due to a sin-
gle-step trap. Both the NMI and INT interrupts will cause this
behavior. Another single-step operation (S command in
DBG16/MONCG) will resume from where the instruction
was interrupted. There are no side effects from this early
termination, and the instruction will complete normally.
The other two interrupts are called INT4 and INT1 and are
edge sensitive. They are triggered by the falling edge of the
CODEC and 500 Hz clocks respectively. These clocks are
generated in the Clock Generation Unit.
INT4 is used for timing the accesses to the CODEC. The
same clock that triggers the interrupt is also connected to
the CFS input of the CODEC.
For all other Series 32000 instructions, a single-step opera-
tion will complete the entire instruction before traping back
to the debugger. On the instructions mentioned above, serv-
eral single-step commands may be required to complete the
instruction, ONLY when interrupts are occurring.
All the interrupts are latched by the interrupt pending regis-
ter (IPEND). An edge sensitive pending interrupt is cleared
by writing to the edge interrupt clear register (IECLR). The
INT4 pending bit is also reset when the CODEC is ac-
cessed.
There are some methods to give the appearance of single-
stepping for these NS32AM162 instructions.
There is no hardware limitation on nesting of interrupts. In-
terrupt nesting is controlled by software writing into the
mask register (IMASK). When an interrupt is acknowledged
by the core, the PSR.I bit is cleared to ‘‘0’’, thus disabling
interrupts. While an interrupt is in service, the user may al-
low other interrupts to occur by setting PSR.I bit to ‘‘1’’. The
IMASK register can be used to control which of the other
interrupts is allowed. Clearing bits in the IMASK register
should be done while the PSR.I bit is ‘‘0’’. Setting bits in the
IMASK register may be done regardless of the PSR.I bit
state.
1. MON16/MONCG monitors the return from single-step
trap vector, PC value. If the PC has not changed since
the last single-step command was issued, the single-step
operation is repeated. It is also advisable to ensure that
one of the NS32AM162 instructions is being single-
stepped, by inspecting the first byte of the address point-
ed to by the PC register. If it is 0x0E, then the instruction
is an NS32AM162-specific instruction.
2. A breakpoint following the instruction would also trap af-
ter the instruction had completed.
Clearing an interrupt request before it is serviced may cause
a false interrupt, where the NS32AM162 may detect an in-
terrupt not reflected by IVCT. The user is advised to clear
interrupt requests only when interrupts are disabled.
Note: If instruction tracing is enabled while the WAIT instructioin is execut-
ed, the Trap (TRC) occurs after the next interrupt, when the interrupt
service procedure has returned.
3.4 ON-CHIP PERIPHERALS
3.4.1 Interrupt Controller Unit
e
During power down mode (CLKCTL.PDM
‘‘1’’), the ICU is
disabled. The user must clear the PSR.I bit to ‘‘0’’ before
entering power down mode, and should not attempt to read
or write the ICU registers while in this mode.
The Interrupt Control Unit (ICU) monitors the internal and
external interrupt sources and generates a vectored inter-
35
3.0 Functional Description (Continued)
During reads and writes to the DRAM in Internal ROM
mode, the DRAMC provides the row and column address on
pins A1–A11 and RA12. The row address is bits A11–A22
of the data item’s address. It is provided on pins A1–A11
and RA12. The column address is bits A1–A10 of the data
item’s address. It is provided on pins A1–A10.
3.4.1.1 Interrupt Sources
Name
INT1
INT2
INT3
INT4
Type
2 ms
DSPM
Source
Clock Generator
DSPM
Vector
0x11
0x12
0x13
0x14
Priority
Lowest Priority
External
During reads and writes to the DRAM in External ROM or
Development modes, the DRAMC provides the row and col-
umn address on pins A1–A12. The row address is bits A11–
A22 of the data item’s address. It is provided on pins A1–
A12. The column address is bits A1–A10 of the data item’s
address. It is provided on pins A1–A10.
CODEC Clock Genertor
Highest Priority
3.4.2 BIU and DRAM Controller
The BIU controls all the internal and external accesses. It
provides control signals for the internal cycles to the other
on-chip modules. It also provides control signals to four
types of external devices: DRAM, ROM/RAM, CODEC, and
I/O ports. Different type of accesses are done to each of
the different devices.
DRAM accesses can be divided into two parts: During the
first part (11 cycles), the external data bus is used by the
DRAMC. During the following 2 cycles, the external data
bus can be used to access every device except for the
DRAM (to ensure enough DRAM precharge time).
The BIU provides four types of accesses to the DRAM:
read, write, refresh cycles during normal operation, and spe-
cial refresh cycles during power down mode (CLKCTL.PDM
e
‘‘1’’). No reads and writes to the DRAM are allowed in
power down mode.
e
In normal operation (CLKCTL.PDM
‘‘0’’), DRAM refresh
is done at a rate of 160000 cycles/second. The refresh
clock is generated by the clock generator block. Any bus
transaction except for DRAM accesses can be performed in
parallel with a refresh cycle.
The BIU provides two type of accesses to the ROM/RAM
devices: read and write cycles. These cycles can also be
performed in power down mode.
e
In power down mode (CLKCTL.PDM
‘‘1’’), DRAM refresh
is done at a (/4 of the low speed crystal oscillator frequency
(If Crystal-2 is 455 kHz, the refresh rate is 113750 cycles/
second). The RAS and CAS signals are activated for half a
DRAM refresh cycle.
The BIU provides two type of accesses to the CODEC: read
and write cycles. These cycles are not allowed in power
down mode.
The BIU provides two type of accesses to I/O devices in
External ROM mode and in Development mode: read and
write cycles. These cycles can also be performed in power
mode.
In both modes, the DRAM controller provides control sig-
nals to execute automatic (CAS before RAS) refresh cycles.
3.4.2.2 CODEC Interface
The NS32AM162 provides an on-chip interface to one or
two serial CODECs. The interface supports two CODEC
modes of operationÐlong frame format and short frame for-
mat.
All control signals of external devices are inactive while re-
set.
3.4.2.1 DRAM Accesses
Selecting the CODEC interface is done through the MCFG
register.
The DRAM Controller (DRAMC) supports transactions be-
tween the NS32AM162 and external DRAM and performs
refresh cycles. The DRAMC supports 1M x 4, 1M x 1, 4M x 1
or 4M x 4 DRAM devices. The supported DRAM devices
require minimum 500 ns cycle time and minimum 350 ns
RAS access time, and a short refresh period.
CODEC accesses are done as regular memory accesses to
the addresses of the CODEC Interface registers.
The CODEC interface uses five signalsÐCDIN, CDOUT,
CCLK, CFS0 and CFS1. When one CODEC is used, the
interface uses CDIN, CDOUT, CCLK and CFS0. When two
CODECs are used, they share CDIN, CDOUT and CCLK.
One CODEC receives CFS0 and the other CODEC receives
CFS1.
The external data bus used for all DRAM accesses is 8-bit
wide. There is no hardware support for nibble or byte gath-
ering. The user can handle the nibble gathering with soft-
ware. CPU accesses are only to an aligned word in the
DRAM (byte or double word accesses are not allowed).
The master clock CCLK and the sampling rate are con-
trolled by the CCTL1 and CCTL2 registers. Two values can
be used, depending on the required sampling rate, as
shown below:
During read cycles the DRAMC provides the RAS and CAS
signals. The DRAMC does not use fast page mode access-
es. The user must connect the OE pin of the DRAM to GND.
On write cycles the DRAMC provides the RAS, CAS, and
WE signals to perform early writes according to the DRAM
specifications.
Sampling
Rate
CCLK
CCTL
CTTL1
CCTL2
Frequency
2.048 MHz
1.862 MHz
8000 Hz
7273 Hz
20.48 MHz
20.48 MHz
0
0
33 (hex)
23 (hex)
When the NS32AM162 enters the power down mode, the
DRAMC continues to refresh the DRAM array. The low fre-
quency clock generates RAS and CAS signals. In this mode
no reads and writes to the DRAM are allowed. Note also
that the user must make sure that the instruction that sets
CLKCTL.PDM bit does not directly follow an access to the
DRAM.
Data is transferred to the CODEC through the CDOUT pin.
Data is read from the CODEC through the CDIN pin. The
CPU core accesses the CODECs through the CDATA0 and
CDATA1 registers.
The DRAM address range is 0x02000000 to 0x027FFFFF,
and its size is 8 Mbytes. In a typical system, where only a
single 1M x 4-DRAM device is used, only 2 Mbytes are ac-
cessible, and only one nibble out of four can actually store
data.
36
3.0 Functional Description (Continued)
When a short frame format is selected via the MCFG regis-
CODECs), and then write new data into CDATA0 (and
CDATA1 if there are two CODECs), before the next frame
sync clock. Failure to update a register before the next
frame sync clock will cause a value of FF (hex) to be sent
from that register.
e
ter (CMC
001 or 011), data transfer between the
NS32AM162 and the serial CODEC starts by asserting
(high) the CFS0 frame sync signal. After one CCLK cycle,
CFS0 is de-asserted, data from the NS32AM162 is sent to
the CODEC through CDOUT, and simultaneously data from
the CODEC is sent to the NS32AM162 through CDIN. After
eight bits are shifted out (these are the bits of the CDATA0
register), CFS1 is asserted for one CCLK cycle, and then
the eight bits of CDATA1 are shifted out through CDOUT,
while eight bits from the CODEC are shifted in through
CDIN. See Figure 3-6.
Note: In cases where two serial CODECs are used, but the PWM output is
needed, the user can program the MCFG register to indicate one
serial CODEC, and restore CFS1 using an external circuit. This circuit
can use a 9-bit shift register, whose data input is connected to CFS0,
and whose clock input is connected to CCLK.
3.4.2.3 Accesses to Off-Chip Memory Devices
In the External ROM mode, the NS32AM162 performs read
accesses from external memory for all the addresses be-
tween 0x00000000 and 0x0001FFFF. In the Development
mode, the NS32AM162 performs read or write accesses to
external memory for all the addresses between 0x00000000
and 0x0007FFFF.
When a long frame format is selected via the MCFG register
e
(CMC
101 or 111), data transfer between the
NS32AM162 and the serial CODEC starts by asserting
(high) the CFS0 frame sync signal. When CFS0 is asserted,
data from the NS32AM162 is sent to the CODEC through
CDOUT, and simultaneously data from the CODEC is sent
to the NS32AM162 through CDIN. After eight bits are shift-
ed out (these are the bits of the CDATA0 register), CFS0 is
de-asserted. One CCLK cycle later CFS1 is asserted, and
the eight bits of CDATA1 are shifted out through CDOUT,
while eight bits from the CODEC are shifted in through
CDIN. See Figure 3-7.
On the first cycle (T1) of a read access, the NS32AM162
asserts A1–A16, in the External ROM mode, or A1–A18 in
the Development mode. The address remains active for four
clock cycles (T1 through T4). In the following cycle (T2), the
NS32AM162 activates the MRD signal. MRD remains active
until the fourth cycle (T4). Data is sampled at the end of the
third cycle (T3). See Section 4.4.3 for detailed timing dia-
grams.
Note that the bits of CDATA1 are shifted out as part of the
protocol, regardless of whether one or two CODECs are
used in the system.
On the first cycle (T1) of a write access, the NS32AM162 in
the Development mode asserts A1–A18. The address re-
mains active for four clock cycles (T1 through T4). In the
following cycle (T2), D0–D15 are activated, and MWR0 and
MWR1 are asserted (depending on the byte needed to be
written into). D0–D15 remains active until the next T1.
MWR0 and MWR1 remain active until the fourth cycle (T4).
See Section 4.4.3 for detailed timing diagrams.
The CODEC interrupt is issued after data to both CODECs
is transferred. This is regardless of the actual number of
CODECs in the system. The CODEC interrupt pending bit is
cleared either by writing ‘‘1’’ to the CLR4 bit of the IECLR
register, or by accessing CDATA0 or CDATA1. In order to
ensure proper operation, after a CODEC interrupt, the soft-
ware must first read CDATA0 (and CDATA1 if there are two
TL/EE/11732–16
FIGURE 3-6. CODEC ProtocolÐShort Frame
TL/EE/11732–17
FIGURE 3-7. CODEC ProtocolÐLong Frame
37
3.0 Functional Description (Continued)
The clock generator provides two clocks to the CODEC: a
1.28 MHz clock, and an 8 KHz clock. The 8 KHz clock also
generates INT4.
3.4.3 I/O Ports
Three 8-bit I/O ports are provided in the Internal ROM
mode: PA, PB and PC. Each of the bits in Ports A and B can
be individually programmed as either an input or as an out-
put. Programming the direction of the bits in ports PA and
PB is done by writing to registers DIRA and DIRB respec-
tively. Writing ‘‘1’’ to one of the bits in a DIR register config-
ures the corresponding bit in the port as an output port.
Writing ‘‘0’’ to one of the bits in a DIR register configures the
corresponding bit in the port as an input. Port PC serves as
an output only, and does not have a direction control regis-
ter. On reset, DIRA and DIRB are cleared to ‘‘0’’, and ports
PA and PB are initiated as input ports.
The clock generator provides a 2 ms (0.5 KHz) time base for
the system software. This time base signal generates INT1.
The clock generator provides a refresh request signal at a
rate of 160 KHz during normal operation mode, and a (/4 of
Crystal-2 frequency in power down mode.
The operation of the clock generator is affected by moving
to power down mode. See Section 3.6.3 for a description of
this mode.
3.4.6 WATCHDOG Counter
The WATCHDOG (WD) counter is used to activate a Non-
Maskable Interrupt (NMI) whenever the software is out of
control. The WD module is a 10 Hz timer with a reset mech-
anism. During normal operation mode, the user must clear
the WD at a rate higher than 10 Hz by writing 0x0E into the
WDCTL register. These write accesses ensure that the
WATCHDOG will not issue an NMI for a full 0.1 second.
Failing to clear the WD before 0.1 of a second has passed,
will cause an NMI. If the user does not clear the WATCH-
DOG, an NMI occurs exactly ten times a second. This NMI
can be used to track the time. Upon reset, the WD is dis-
abled until the first write access to the WDCTL register.
The bits in ports PA and PB that are programmed as outputs
can also be read by the CPU by accessing the port. The
values of the output in ports PA, PB, and PC can be set by
writing to the port.
In the External ROM and Development modes the pins of
ports PB and PC are used for different functions. In order to
use these ports, external logic can be added. An external
latch can be connected to the D8–D15, and IOWR signals
to provide the functionality of PC. An external buffer can be
connected to the D8–D15 and IORD signals to provide part
of the functionality of PB. Note that in this mode PB can
serve as an input only.
3.4.7 Internal ROM
In the Development mode, PA pins are also used, and
hence there are no ports available in this mode.
The size of the internal ROM is 25 Kbytes (32 Kbyte in the
NS32AM163). The ROM is organized as a 16-bit wide mem-
ory array with a zero wait-state access time. The ROM’s
starting address is 0x00000000. When the NS32AM162 is in
either External ROM or Development modes, the lower
128 Kbytes or 512 Kbytes respectively are mapped to exter-
nal accesses instead of accesses to the on-chip ROM.
Accesses to the external latch and external buffer are simi-
lar to the accesses to off-chip memory devices, except for
the pins that control the actual reads and writes. On reads,
IORD is asserted, and on writes, IOWR is asserted. The
timings of these signals are exactly the same as the timings
of MRD and MWR1.
3.4.8 Internal RAM Arrays
3.4.4 Pulse Width Modulator
The NS32AM162 provides two zero wait-state on-chip RAM
arrays: a 1008 byte system RAM array and a 1120 byte
DSPM RAM array. The data bus between the CPU and the
system RAM array is 16 bits wide. The data bus between
the DSPM and its RAM is 32 bits wide, to allow high
throughput during DSP operations. While the DSPM is ac-
tive, the CPU is not allowed to access the DSPM RAM.
The Pulse Width Modulator provides one output signal, with
a fixed frequency and a variable duty cycle. The frequency
of the PWM output is 80 KHz. The duty cycle can be pro-
grammed by writing a value from 0 to 0xFF to the PWMCTL
register. The PWM output is active (high) for the number of
20.48 MHz cycles specified in the PWMCTL register. It is
inactive (low) for the rest of the 20.48 MHz cycles in the
80 KHz PWM cycle. During power down mode, and upon
reset, PWMCTL register is cleared to ‘‘0’’, and the PWM
output signal is not active (low). The PWM output pin is
shared with the CFS1 pin of the CODEC interface. Conse-
quently, when the MCM field in the MCFG register is set to
011 or 111, to select a direct interface to two CODECs, the
PWM output signal is not available.
3.5 DSP MODULE
The following sections give full specifications for the
NS32AM162 on-chip DSP Module.
3.5.1 Programming Model
The DSPM programming model consists of the following el-
ements:
3.4.5 Clock Generator
Internal RAM
#
The clock generator provides all the clocks needed for the
various parts of the device. Two crystal oscillators provide
the basic frequencies needed. The high-speed crystal oscil-
lator is designed to operate with a 40.96 MHz crystal. The
low-speed oscillator is designed to operate with a ceramic
resonator at a frequency of 455 KHz. The user can operate
the NS32AM162 in either normal operation or power down
modes. In power down mode, most of the on-chip modules
are running from a very low frequency clock or are totally
disabled. In power down mode, the user can turn off the
high speed crystal oscillator to further reduce the power.
Dedicated registers
#
#
#
#
Command-list execution unit
Interface with CPU core
Vector instruction set
The Internal RAM is used by the DSPM for fetching com-
mands to be executed, and for reading or writing data that is
needed in the course of program execution. DSPM Pro-
grams are encoded as command lists and are interpreted by
the command-list execution unit.
Computations are performed by commands selected from
the set of available ones. These commands employ the
DSP-oriented datapath in a pipelined manner, thus maximiz-
38
3.0 Functional Description (Continued)
15
0
ing the utilization of on-chip hardware resources. A set of
dedicated registers is used to specify operands and options
for subsequent vector commands. These dedicated regis-
ters can be loaded and stored by appropriate commands in
between initiations of vector commands. Additional com-
mands are available for controlling the flow of execution of
the command list, as needed for programming loops and
branches (see Section 4.7.3).
Integer Value
Integer values are typically used for addressing vector oper-
ands and for lookup-table index manipulations.
3.5.2.2 Aligned-Integer Values
Aligned-integer values are represented as pairs of integer
values, and must be aligned on a double-word boundary.
The less significant half represents one integer vector ele-
ment, and must be contained in an even-numbered memory
location. The more significant half represents the next vec-
tor element, and must be contained in the next (odd-num-
bered) memory location.
The CPU core interface specifies the mapping of the DSPM
internal RAM as a contiguous block within the CPU core’s
address space, thus making it possible for normal CPU in-
structions to access and manipulate data and commands in
the DSPM internal RAM (see Section 3.6.2). In addition, the
CPU core interface contains control and status registers
that are needed to synchronize the execution of CPU core
instructions concurrently with execution of the DSPM com-
mand lists (see Section 3.6.1).
15
0
Integer Value (Low)
Integer Value (High)
(Location 2n )
a
(Location 2n
1)
3.5.2 RAM Organization and Data Types
The DSPM internal RAM is organized as a word or double-
word addressable, uniform, linear address space. Memory
locations are numbered sequentially, starting at 0 for the
first location, and incremented by 1 for each successive lo-
cation. The content of each memory location is a 16-bit
word. Double-words must be aligned to an even address.
Valid RAM addresses for access by the command-list exe-
cution unit are 0 through 0x22F. Access to memory loca-
tions out of the DSMP RAM boundary are not allowed.
Aligned-integer values are used for higher throughput in op-
erations where two sequential integer vector elements can
be used in a single iteration. Both elements of an aligned-in-
teger value have the same range and accuracy as specified
for integer values above.
3.5.2.3 Real Values
Real values are represented as 16-bit signed fixed-point
fractional numbers, in 2’s complement format. Bit 15 (MSB)
is the sign bit. Bits 0 (LSB) through 14 represent the frac-
tional part. The binary digit is assumed to lie between bits 14
and 15.
The organization of the DSPM internal RAM is shown be-
low:
15
0
15
0
Location 0
Location 1
. . .
Real Value
Real values are used to represent samples of analog sig-
nals, coefficients of filters, energy levels, and similar contin-
uous quantities that can be represented using 16-bit accura-
Locationn
. . .
b
cy. The range of real values is from 1.0 (represented as
b
15
b
0x8000) through 1.0
2
(represented as 0x7FFF).
The RAM array is not restricted to use by the DSPM, it can
also be accessed by the core with any type of memory ac-
cess (e.g., byte, word, or double-word accesses aligned to
any byte address).
3.5.2.4 Aligned-Real Values
Aligned-real values are represented as pairs of real values,
and they must be aligned on a double-word boundary. The
less significant half represents one real vector element, and
must be contained in an even-numbered memory location.
The more significant half represents the next vector ele-
ment, and must be contained in the next (odd-numbered)
memory location.
The internal RAM stores command lists to be executed, and
data to be manipulated during program execution. Com-
mand lists consist of 16-bit commands, so that each individ-
ual command occupies one memory location.
Each data item is represented as having either a 16-bit or
32-bit value, as follows:
15
0
Integer values (16-bit)
#
#
#
#
Real Value (Low)
Real Value (High)
(Location 2n )
Aligned-integer values (32-bit)
a
(Location 2n
1)
Real values (16-bit)
Aligned-real values are used for higher throughput in opera-
tions where two sequential real vector elements can be
used in a single iteration. Both elements of an aligned-real
value have the same range and accuracy as specified for
real values above.
Aligned-real values (32-bit)
Extended-precision real values (32-bit)
#
Complex values (32-bit)
#
3.5.2.1 Integer Values
Integer values are represented as signed 16-bit binary num-
bers in 2’s complement format. The range of integer values
3.5.2.5 Extended-Precision Real Values
Extended-precision real values are represented as 32-bit
signed fixed-point fractional numbers, in 2’s complement
format. Extended-precision real values must be aligned on a
double-word boundary, so that the less significant half is
15
15
b
b
b
1 (32767). Bit 0 is
is from
2
(
32768) through 2
the Least Significant Bit (LSB), and bit 15 is the Most Signifi-
cant Bit (MSB).
39
3.0 Functional Description (Continued)
contained in an even-numbered memory location, and the
more significant half is contained in the next (odd-num-
bered) memory location. Bit 15 (MSB) of the more signifi-
cant part is the sign bit. Bits from 0 (LSB) of the less signifi-
cant part, through 14 of the more significant part, are used
to represent the fractional part. The binary digit is assumed
to lie between bits 14 and 15 of the more significant part.
When extended-precision values are loaded or stored in the
accumulator, bits 1 through 31 of the extended-precision
argument are loaded or stored in bits 0 through 30 of the
accumulator. Bit 0 of the extended-precision argument is
not used during calculations. This bit is always set to ‘‘0’’
when stored back in the internal memory.
Clipping and Min/Max Instructions
Special Instructions
#
#
See Section 3.4.5 for detailed information on the DSPM in-
struction set.
3.5.4 CPU Core Interface
The interface between the DSPM and the CPU core con-
sists of the following elements:
Parallel Operation and Synchronization
#
#
#
CPU Core Address Space Map
External Memory References
3.5.4.1 Synchronization of Parallel Operation
Since the DSPM is capable of autonomous operation paral-
lel to the CPU core operation, a mechanism is needed to
synchronize the two threads of execution. The parallel syn-
chronization mechanism consists of several control and
status registers, which are used to synchronize the following
activities:
15
0
Less Significant Part
More Significant Part
(Location 2n )
a
(Location 2n
1)
Extended-precision real values are used to represent vari-
ous continuous quantities that require high accuracy. The
Initiation of the command list execution
#
b
range of extended-precision real values is from 1.0 (repre-
(represented
Termination of the command list execution
#
b
30
b
sented as 0x80000000) through 1.0
as 0x7FFFFFFE).
2
Check the DSPM status
#
Access to DSPM internal RAM and registers by CPU
core instructions
#
3.5.2.6 Complex Values
Complex values are represented as pairs of real values, and
must be aligned on a double-word boundary. The less signif-
icant half represents the real part, and must be contained in
an even-numbered memory location. The more significant
half represents the imaginary part, and must be contained in
the next (odd-numbered) memory location.
Access to external memory by DSPM commands
#
The following CPU core interface control and status regis-
ters are available:
Register
CLPTR
Function
Command-List Pointer
Command-List Status Register
Abort Register
15
0
CLSTAT
ABORT
EXT
Real Part
(Location 2n )
a
1)
Imaginary Part
(Location 2n
Disable External Memory References
Interrupt Register
Complex values are used to represent samples of complex
baseband signals, constellation points in the complex plane,
coefficients of complex filters, and rotation angles as points
on the unit circle, etc. Both the real and imaginary parts
have the same range and accuracy as specified for real
values above.
DSPINT
DSPMASK
NMISTAT
Mask Register
NMI Status Register
Execution of the command list begins when the CPU core
writes a value into the CLPTR control register. This causes
the DSPM command-list execution unit to begin executing
commands, starting at the address written to the CLPTR
register. If the written value is outside the range of valid
RAM addresses, the result is unpredictable.
3.5.3 Command List Format
All commands have the same fixed format, consisting of a
5-bit opcode field and a 11-bit arg field, as shown below:
15
11 10
0
opcode
arg
Once started, execution of the command list continues until
one of the following occurs: a HALT or a DBPT command is
executed, the CPU core writes any value into the ABORT
control register, an attempt to execute a reserved com-
mand, an attempt to access the DSPM address space while
the CLSTAT.RUN bit is ‘‘1’’ (except for accesses to the
CLSTAT, EXT, DSPINT, DSPMASK, NMISTAT, and ABORT
registers), or reset occurs. In the last case, the contents of
the DSPM internal RAM, REPEAT, and CLPTR registers are
unpredictable when execution terminates.
The opcode field specifies an operation to be performed.
The arg field interpretation is determined by the class to
which the command belongs. There are several classes of
commands, as follows:
Load Register Instructions
#
#
#
Store Register Instructions
Adjust Register Instructions
Flow Control Instructions
#
#
#
#
The CLSTAT status register can be read by CPU core in-
structions to check whether execution of the DSPM com-
mand list is active or idle. A ‘‘0’’ value read from the
CLSTAT.RUN bit indicates that execution is idle, and a ‘‘1’’
value indicates that it is active.
Internal Memory Move Instructions
External Memory Move Instructions
Arithmetic/Logical Instructions
Multiply-and-Accumulate Instructions
#
Multiply-and-Add Instructions
#
40
3.0 Functional Description (Continued)
15
8
7
0
Whenever the execution of the command list terminates,
CLSTAT.RUN changes its value from ‘‘1’’ to ‘‘0’’, and
DSPINT.HALT is set to ‘‘1’’. The value of the DSPINT.HALT
status bit can be used to generate interrupts. If
DSPMASK.HALT is set, a ‘‘1’’ value on the DSPINT.HALT
will activate interrupt level 2 in the on-chip ICU.
a
a
a
a
base
base
1
3
base
base
0
2
(RAM Location 0)
(RAM Location 1)
. . .
. . .
a
a
a
2n
base
2n
1
base
. . .
(RAM Locationn )
The DSPM internal RAM and the dedicated registers, as
well as the interface control and status registers, are
mapped into certain areas of the CPU core address space
(see Section 2.2.1). Whenever execution of the DSPM com-
mand list is idle, CPU core instructions may access these
memory areas for any purpose, exactly as they would ac-
cess external off-chip memory locations. However, when
the DSPM command list execution unit is active, any at-
tempt to read or write a location within the above memory
areas, except for accessing the CLSTAT, EXT, DSPMASK,
DSPINT, NMISTAT, or ABORT control registers (see be-
low), will be treated as follows: All read data will have unpre-
dictable values, and any attempt to write data will not
change the DSPM memory and registers. Whenever such
an access occurs, NMISTAT.ERR bit is set to ‘‘1’’, an NMI
request to the core is issued, and the command list execu-
tion terminates. In this case, as the command-list execution
terminates asyncronously, the currently executed command
may be aborted. The DSPM RAM and the A, X, Y, Z, and
REPEAT registers may hold temporary values created in
this aborted instruction.
. . .
The RAM array is not restricted to use by the DSPM, but can
also be used by the core as a fast, zero wait-state, on-chip
memory for instructions and data storage. The core can ac-
cess each byte, word, or double-word of the RAM, with no
restrictions on alignment.
3.5.5 DSPM Instruction Set
3.5.5.1 Conventions
The formal description below of DSPM command-list in-
structions is based on the ‘‘C’’ programming language, us-
ing the following conventions:
low
Bits 0 through 15 of a 32 bits entity.
Bits 16 through 31 of a 32 bits entity.
Value of PARAM.LENGTH.
high
LENG
A
Accumulator.
16
[
]
aligned addr An even number in the range 0, 2 , used
for specifying a double word-aligned address
Ð
in internal memory.
Some of the vector instructions executable by the DSPM
can access external off-chip memory to transfer data in or
out of the internal RAM, or to reference large lookup tables.
Normally, external memory references initiated by the
DSPM and CPU core are interleaved by the CPU core bus-
arbitration logic. As a result, it is the user’s responsibility, to
make sure that whenever a write operation is involved, the
DSPM and CPU core should not reference the same exter-
nal memory locations, since the order of these transactions
is unpredictable.
[ ]
mem k
A value in internal memory whose first word
16
s
k
2
address is k, where 0
k
.
[ ]
ext mem k A value in external memory whose first byte
Ð
32
k
2
s
address is k, where 0
k
.
X
Y
Z
Vector in internal memory whose first ad-
dress is pointed to by X.ADDR.
Vector in internal memory whose first ad-
dress is pointed to by Y.ADDR.
Vector in internal memory whose first ad-
dress is pointed to by Z.ADDR.
Each time the DSPM needs to access the external bus, it
issues an internal HOLD request to the CPU core, and waits
for an internal HOLD acknowledge. External HOLD requests
(when the HOLD signal is asserted) have higher priority than
DSPM HOLD requests.
[ ]
X n
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
b
cant bits of X.ADDR. The offset within the
by clearing the (X.WRAP
1) less-signifi-
In order to ensure fast response for time-critical interrupt
requests, the DSPM external referencing mechanism will re-
linquish the core bus for one clock cycle after each memory
transaction. This allows the core to use the bus for one
memory transaction. To further enhance the core speed on
critical interrupt routines, the EXT.HOLD control flag is pro-
vided.
a
buffer is calculated by: (X.ADDR
X.INCR X.WRAP
c
n
2
) modulo 2
.
[ ]
Y n
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
b
cant bits of Y.ADDR. The offset within the
by clearing the (Y.WRAP
1) less-signifi-
Whenever the core sets EXT.HOLD to ‘‘1’’, the DSPM stops
its external memory references. When the DSPM needs to
perform an external memory reference but is disabled, it
enters a HOLD state until a value of ‘‘0’’ is written to the
EXT.HOLD control register.
a
buffer is calculated by: (Y.ADDR
Y.INCR Y.WRAP
c
n
2
) modulo 2
.
[ ]
Z n
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address. The base address is formed
3.5.4.2 DSPM RAM Organization
The mapping of these locations to CPU core address space
is shown below, where base corresponds to the start of the
mapped area (address 0xFFFE0000):
b
cant bits of Z.ADDR. The offset within the
by clearing the (Z.WRAP
1) less-signifi-
a
buffer is calculated by: (Z.ADDR
Z.INCR Z.WRAP
c
n
2
) modulo 2
.
[ ]
&X n
[ ]
The word address of X n .
[ ]
&Y n
[ ]
The word address of Y n .
[ ]
[ ]
&Z n
The word address of Z n .
41
3.0 Functional Description (Continued)
the accumulator, and only then the result of the multiplica-
tion with the imaginary part of the X operand is added.
3.5.5.2 Type Casting
The following data type definitions are used in DSPM in-
struction description:
In general, the X, Y, and Z vectors can overlap. However,
because of the pipelined structure of the DSPM datapath,
the user must verify that a value written into the DSPM inter-
nal memory will not be used in the same vector instruction
as a source operand for the next 8 iterations, in all instruc-
integer
An integer value, as described in Section
3.5.2.1.
aligned integer An aligned integer value, as described in
Ð
Section 3.5.2.2.
[ ]
tions except VCPOLY. In VCPOLY, Y 0 cannot be over-rid-
den at all.
real
A real value, as described in Section
3.5.2.3.
The description below specifies the encoding of each DSPM
instruction. All other values are reserved for future use. Any
attempt to execute any reserved instructions will terminate
execution of the command list, issue an NMI request, and
set NMISTAT.UND to ‘‘1’’. In this case the contents of the
EXT and DSPMASK remain unchanged, but the contents of
the Accumulator and OVF may change.
aligned real
Ð
An aligned real value, as described in Sec-
tion 3.5.2.4.
extended
complex
An extended-precision real value, as de-
scribed in Section 3.5.2.5.
A complex value, as described in Section
3.5.2.6.
3.5.5.4 Load Register Instructions
LXÐLoad X Vector Pointer
vector ptr
Ð
repeat reg
Ð
param reg
Ð
eabr reg
Ð
A valid value for X, Y, and Z registers.
A valid value for REPEAT register.
A valid value for PARAM register.
A valid value for EABR register.
The LX instruction loads the double-word at aligned addr
Ð
into the X register.
Syntax:
real acc
Ð
A 34-bit value inside either the real part or
the imaginary part of the accumulator.
LX aligned addr
Ð
complex acc A 68-bit value inside the complex accumu-
Ð
lator.
15
11 10
0
00010
aligned addr
Ð
3.5.5.3 General Notes
Operation:
The values of the EABR, PARAM, X, Y, and Z registers are
not changed by the execution of the command list.
À
X 4 (vector ptr) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to vector pointer
Some instructions use the accumulator as a temporary reg-
ister and therefore destroy its contents. In general, the user
should assume that the contents of the accumulator are
unpredictable after an instruction terminates, unless stated
otherwise in the notes section following that instruction’s
formal specification.
[
specification format.
]
Ð
Accumulator is not affected.
LYÐLoad Y Vector Pointer
The LY instruction loads the double-word at aligned addr
Ð
into the Y register.
Non-complex instructions that use the accumulator, can use
either the real or the imaginary parts, or both. In general,
when an integer or real data type is to be read, it is taken
from the real part. An extended-precision real data type is
taken from the imaginary part. When a non-complex data
type is loaded into the accumulator (by the LEA instruction
or within other instructions prior to saving it into memory), it
is written to both real and imaginary parts.
Syntax:
LY aligned addr
Ð
15
7
10
0
00011
aligned addr
Ð
Rounding is implemented by copying PARAM.RND into bit
position 14 of both the real and the imaginary part of the
accumulator, performing the requested operation, and trun-
cating the contents of the accumulator upon storing results
to memory. In Multiply-and-Add instructions and some of the
special instructions, this is done transparently on each vec-
tor element iteration. In Multiply-and-Accumulate instruc-
tions, when PARAM.CLR is ‘‘0’’, the previous content of the
accumulator is used, so that rounding control is actually per-
formed when the accumulator is first loaded and not when
the multiply operations is executed. On the other hand, if
PARAM.CLR is ‘‘1’’, the PARAM.RND value is copied into
bit 14 of the cleared accumulator, so that rounding control is
done at the same time that the multiply operation is execut-
ed.
Operation:
À
Y 4 (vector ptr) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to vector pointer
[
specification format.
]
Ð
Accumulator is not affected.
LZÐLoad Z Vector Pointer
The LZ instruction loads the double-word at aligned addr
Ð
into the Z register.
Syntax:
LZ aligned addr
Ð
15
11 10
0
Rounding is performed only for real, aligned-real and com-
plex data types. In operations on complex operands, the
order of accumulation is as follows: the result of the multipli-
cation with the real part of the X operand is added first to
00100
aligned addr
Ð
42
3.0 Functional Description (Continued)
Operation:
LREPEATÐLoad Repeat Register
À
The LREPEAT instruction loads the double-word at
Z 4 (vector ptr) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to vector pointer
aligned addr into the REPEAT register.
Ð
Syntax:
[
specification format.
]
Ð
LREPEAT aligned addr
Ð
Accumulator is not affected.
15
11 10
0
LAÐLoad Accumulator
00110
aligned addr
Ð
The LA instruction loads the complex value at aligned
Ð
addr into the A accumulator as a complex value.
Operation:
À
Syntax:
REPEAT 4 (repeat reg) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to the REPEAT
LA aligned addr
Ð
15
11 10
0
[
]
Ð
register format.
00101
aligned addr
Ð
Accumulator is not affected.
Operation:
LEABRÐLoad External Address Base Register
À
The LEABR instruction loads the double-word at
[
]
mem aligned addr into the EABR register.
(complex) A 4 (complex) mem[aligned addr];
Ó
Notes: The real and imaginary parts are placed in bits 15 through 30 of the
Ð
Syntax:
LEABR aligned addr
Ð
real and imaginary parts of the accumulator.
When PARAM.RND is set to ‘‘1’’, bit 14 of the real and imaginary
parts is set to ‘‘1’’, in order to implement rounding upon subsequent
additions into the accumulator. Otherwise, it is cleared to ‘‘0’’.
15
11 10
0
00111
aligned addr
Ð
LEAÐLoad Extended Accumulator
Operation:
The LEA instruction loads the accumulator with the extend-
[ ]
ed value specified by X 0 .
À
EABR 4 (eabr reg) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to vector pointer
Both the real and the imaginary parts of the accumulator are
loaded.
[
]
specification format, that is, bit positions 0 through 16 must be speci-
Ð
Syntax:
fied as ‘‘0’.
EXEC LEA
Accumulator is not affected.
15
11 10
0
3.5.5.5 Store Register Instructions
SXÐStore X Vector Pointer
10000
101 0011 0011
The SX instruction stores the contents of the X register into
Operation:
the double-word at aligned addr.
Ð
Syntax:
À
extended X;
A 4 (extended) X 0 ;
SX aligned addr
Ð
[ ]
Ó
Note: Bits 1 through 31 of the memory location are read into bit positions 0
15
11 10
0
through 30 of the accumulator.
01010
aligned addr
Ð
LPARAMÐLoad Parameters Register
Operation:
The LPARAM instruction loads the double-word at
À
aligned addr into the PARAM register.
Ð
Syntax:
(vector ptr) mem[aligned addr] 4 X;
Ó
Note: Accumulator is not affected.
LPARAM aligned addr
Ð
SXLÐStore X Vector Pointer Lower Half
15
11 10
0
The SXL instruction stores the contents of the lower-half of
00000
aligned addr
Ð
[
the X register into the word at mem addr
]
.
Operation:
Syntax:
À
SXL addr
PARAM 4 (param reg) mem[aligned addr];
Ó
Notes: The value at mem aligned addr should conform to this register
15
11 10
0
[
]
format. The value written into PARAM.LENGTH must be greater
Ð
11100
addr
then 0.
Accumulator is not affected.
43
3.0 Functional Description (Continued)
Operation:
Operation:
À
À
mem[aligned addr] 4 X.low;
Ó
Note: Accumulator is not affected.
(complex mem[aligned addr] 4 (complex) A;
Ó
Notes: Bits 15 through 30 of the real and imaginary parts of the accumulator
are placed in the real and imaginary parts of the complex value at
SXHÐStore X Vector Pointer Higher Half
The SXH instruction stores the contents of the higher-half of
[
mem aligned addr
]
.
Ð
Accumulator is not affected.
[
the X register into the word at mem addr
]
.
SEAÐStore Extended Accumulator
Syntax:
The SEA stores the contents of bits 0–30 of the imaginary
accumulator as an extended value into a DSPM memory
SXH addr
[ ]
location specified by Z 0 .
15
11 10
0
Bit 0 of this memory location is loaded with ‘‘0’’.
11101
addr
Syntax:
EXEC SEA
Operation:
À
15
11 10
0
mem[aligned addr] 4 X.high;
Ó
Note: Accumulator is not affected.
10000
101 0011 0110
Operation:
SYÐStore Y Vector Pointer
À
The SY instruction stores the contents of the Y register into
extended Z;
the double-word at aligned addr.
Ð
Syntax:
Z[0] 4 (extended) A;
Ó
Note: Accumulator is not affected.
SY aligned addr
Ð
SREPEATÐStore Repeat Register
15
11 10
0
The SREPEAT instruction stores the contents of the
[
REPEAT register in the double-word at mem aligned
01011
aligned addr
Ð
Ð
]
addr
.
Operation:
Syntax:
À
SREPEAT aligned addr
Ð
(vector ptr) mem[aligned addr] 4 Y;
Ó
Note: Accumulator is not affected.
15
11 10
0
01110
aligned addr
Ð
SZÐStore Z Vector Pointer
The SZ instruction stores the contents of the Z register into
Operation:
the double-word at aligned addr.
Ð
Syntax:
À
(repeat reg) mem[aligned addr] 4 REPEAT;
Ó
Note: Accumulator is not affected.
SZ aligned addr
Ð
15
11 10
0
SOVFÐStore and Clear OVF Register
01100
aligned addr
Ð
The SOVF instruction stores the contents of the OVF regis-
[
]
ter in the word at mem addr . The OVF register is then
cleared to ‘‘0’’.
Operation:
À
Syntax:
(vector pointer mem[aligned addr] 4 Z;
Ó
Note: Accumulator is not affected.
SOVF addr
15
11 10
0
SAÐStore Accumulator
01001
addr
The SA instruction stores the contents of the A accumulator
[
as a complex value into mem aligned addr
]
.
Operation:
Ð
Syntax:
À
(ovf reg) mem[aligned addr] 4 OVF;
Ó
Note: Accumulator is not affected.
SA aligned addr
Ð
15
11 10
0
3.5.5.6 Adjust Register Instructions
INCXÐIncrement X Vector Pointer
01101
aligned addr
Ð
The INCX instruction increments the X vector pointer by one
element, according to the increment and the wrap.
44
3.0 Functional Description (Continued)
Syntax:
Syntax:
EXEC INCX
EXEC DECY
15
11 10
0
15
11 10
0
10000
100 0101 1001
10000
101 0010 1111
Operation:
Operation:
À
DECY
À
À
Y.ADDR 4 &Y 11];
Ó
Note: Accumlator is not affected.
X.ADDR 4 &X[1];
Ó
Note: Accumulator is not affected.
INCYÐIncrement Y Vector Pointer
DECZÐDecrement Z Vector Pointer
The INCY instruction increments the Y vector pointer by one
element, according to the increment and the wrap.
The DECZ instruction decrements the Z vector by one ele-
ment, according to the increment and the wrap.
Syntax:
Syntax:
EXEC INCY
EXEC DECZ
15
11 10
0
15
11 10
0
10000
100 0101 1011
10000
101 0011 0001
Operation:
Operation:
À
À
Y.ADDR 4 &Y[1];
Ó
Note: Accumulator is not affected.
Z.ADDR 4 &Z[11];
Ó
Note: Accumulator is not affected.
3.5.5.7 Flow Control Instructions
NOPRÐNo Operation
INCZÐIncrement Z Vector Pointer
The INCZ instruction increments the Z vector pointer by one
element, according to the increment and the wrap.
Syntax:
The NOPR command passes control to the next command
in the command list. No operation is performed.
EXEC INCZ
Syntax:
15
11 10
0
NOPR
10000
100 0101 1101
15
11 10
0
Operation:
11010
00000000
À
Z.ADDR 4 &Z[1];
Note: Accumulator is not affected.
Ó
Note: Accumulator is not affected.
HALTÐTerminate Command-List Execution
The HALT command terminates execution of the command
list. No further commands are executed. This event is made
visible to the CPU core, as specified in Section 3.6.
DECXÐDecrement X Vector Pointer
The DECX instruction decrements the X vector pointer by
one element, according to the increment and the wrap.
Syntax:
Syntax:
HALT
EXEC DECX
15
11 10
0
15
11 10
0
11001
00000000000
10000
101 0010 1101
Note: Accumulator is not affected.
DJNZÐDecrement and Jump If Not Zero
Operation:
The DJNZ command is used to implement loops and
branches in the command list. The value of the REPE-
AT.COUNT field is decremented by 1 and compared to 0. If
it is not equal to 0, then execution of the command list con-
tinues with the command located in the RAM address speci-
fied by the REPEAT.TARGET field. When the
REPEAT.COUNT field is equal to 0, then execution contin-
ues with the next command in the command list.
À
b
X.ADDR 4 &X[ 1]
Ó
Note: Accumulator is not affected.
DECYÐDecrement Y Vector Pointer
The DECY instruction decrements the Y vector pointer by
one element, according to the increment and the wrap.
The DSPM has only one REPEAT register. To nest loops,
user must save the contents of the REPEAT register before
starting an inner loop, and restore it at the end of the inner
loop.
45
3.0 Functional Description (Continued)
Syntax:
Syntax:
EXEC DJNZ
EXEC VRGATH
15
11 10
0
15
11 10
0
10000
101 0110 1100
10000
100 0011 1010
Note: Accumulator is not affected.
Operation:
DBPTÐDebug Breakpoint
À
real X, Z;
The DBPT instruction is used for implementing software de-
bug breakpoint in the DSPM command-list. Whenever there
is an attempt to execute a DBPT instruction, the NMIS-
TAT.UND bit is set to ‘‘1’’, (See Section 3.4.4).
integer X.ADDR, Y;
k
for (n 4 0; n
À
Z[n] 4 mem[(X.ADDR0Y[n]) & 0xFFFF];
LENG; n00)
Syntax:
Ó
EXEC DBPT
Ó
15
11 10
0
VRSCATÐVector Real Scatter
The VRSCAT instruction scatters contiguous elements of
the X real vector, and places them in non-contiguous loca-
tions in the Z real vector, as specified by the Y integer vec-
tor.
10000
111 1111 1110
Note: Accumulator is not affected.
3.5.5.8 Internal Memory Move Instructions
VRMOVÐVector Real Move
Syntax:
The VRMOV instruction copies the real X vector to the real
Z vector.
EXEC VRSCAT
15
11 10
0
Syntax:
EXEC VRMOV
10000
100 0100 0000
Operation:
15
11 10
0
À
10000
101 0010 1011
real X, Z;
integer Z.ADDR, Y;
Operation:
k
À
for (n40; n
À
mem[Z.ADDR0Y[n]) & 0xFFFF] 4 X[n];
LENG; n00)
real X, Z;
k
for (n 4 0; n
À
Z[n] 4 X[n];
LENG; n00)
Ó
Ó
Ó
3.5.5.9 External Memory Move Instructions
VXLOADÐVector External Load
Ó
VARMOVÐVector Aligned Real Move
The VXLOAD instruction loads a vector from external mem-
ory into the Z vector. The external memory address is speci-
fied in the EABR and X registers.
The VARMOV instruction copies the aligned real X vector to
the aligned real Z vector.
Syntax:
Syntax:
EXEC VARMOV
EXEC VXLOAD
15
11 10
0
15
11 10
0
10000
100 0011 1000
10000
100 0100 1111
Operation:
Operation:
À
VXLOAD
À
aligned real X, Z;
real X, Z;
k
ext address EABR;
for (n 4 0; n
À
LENG; n00)
k
for (n40; n LENG; n00)
Z[n].low 4 X[n].low;
Z[n].high 4 X[n].high;
À
Z[n] 4 ext mem[EABR 0 (ext address)
2*&X[n]]
Ó
Ó
Ó
Ó
VRGATHÐVector Real Gather
VXSTOREÐVector External Store
The VRGATH instruction gathers non-contiguous elements
of the X real vector, as specified by the Y integer vector, and
places them in contiguous locations in the Z real vector.
The VXSTORE instruction stores the Z vector into an exter-
nal memory vector. The external memory address is speci-
fied in the EABR and X registers.
46
3.0 Functional Description (Continued)
Syntax:
The allowed values in PARAM.OP are:
EXEC VXSTORE
k
l
op
Operation
15
11 10
0
e
a
b
011010
100111
001000
100000
111000
011000
001100
ADD
SUB
BIC
Z
Z
Z
Z
Z
Z
Z
X
X
Y
Y
e
e
e
e
e
e
10000
100 0101 0101
X & Y
X & Y
Operation:
AND
OR
À
X
X
Y
Y
l
real X, Z;
Z
XOR
INV
Y
ext address EABR;
k
for (n40; n
À
LENG; n00)
VAROPÐVector Aligned Real Op
ext mem[EABR 0 (ext address)
2*&Z[n]] 4 X[n];
The VAROP instruction performs one of 7 operations be-
tween corresponding elements of the X and Y aligned vec-
tors, and writes the result in the coresponding place in the Z
output vector. The operation to be performed is specified in
PARAM.OP field.
Ó
Ó
VXGATHÐVector External Gather
The VXGATH instruction gathers non-contiguous elements
of the external memory vector, as specified by the Y integer
vector, and places them in contiguous locations in the Z real
vector. The external memory address is specified in the
EABR and X registers.
Syntax:
EXEC VAROP
15
11 10
0
10000
100 0001 1010
Syntax:
Operation:
EXEC VXGATH
À
15
11 10
0
aligned real X,Y,Z;
k
10000
100 0100 0110
for (n40; n
À
LENG; n00)
Operation:
k
l
Z[n].low 4 (real) (X[n].low
Y[n].low);
Z[n].high 4 (real) (X[n].high
op
À
real X, Z;
k
l
op
ext address EABR;
integer X.ADDR, Y;
Y[n].high);
Ó
Ó
Note: The allowed values in PARAM.OP are the same as those in VROP.
3.5.5.11 Multiply-and-Accumulate Instructions
VRMACÐVector Real Multiply and Accumulate
k
for (n40; n
À
Z[n]4ext mem
LENG; n00)
[EABR0(ext address)2*((X.ADDR0(integer)Y[n])
& 0xFFFF)];
The VRMAC instruction performs a convolution sum of the
X and Y real vectors. The previous value of the accumulator
is used and the result stored in Z[0].
Ó
Ó
3.5.5.10 Arithmetic/Logical Instructions
VROPÐVector Real Op
Syntax:
EXEC VRMAC
The VROP instruction performs one of 7 operations be-
tween corresponding elements of the X and Y real vectors,
and writes the result in the corresponding place in the Z
output vector. The operation to be performed is specified in
PARAM.OP field.
15
11 10
0
10000
100 0000 0111
Operation:
Syntax:
À
EXEC VROP
real X,Y,Z;
real acc A;
15
11 10
0
k
for (n40; n
À
A 4 A 0 X[n] * Y[n];
LENG; n00)
10000
101 0110 1000
Operation:
Ó
Z[0] 4 (real) A;
Ó
Note: When PARAM.CLR is set to ‘‘1’’, A is cleared to ‘‘0’’ prior to the first
À
real X,Y,Z;
k
for (n40; n
À
Z[n] 4 (real) (X[n]
LENG; n00)
a
addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is replaced
b
by a ‘‘ ’’ sign.
k
l
Y[n]);
op
Ó
Ó
47
3.0 Functional Description (Continued)
VARMACÐVector Aligned Real Multiply
and Accumulate
Operation:
À
The VARMAC instruction performs a convolution sum of the
X and Y real vectors. The previous value of the accumulator
is used and the result is stored in Z[0].
real X,Y,Z;
real acc A;
A 4 (real acc) Z[0];
Syntax:
k
for (n41; n
À
LENG; n00)
EXEC VARMAC
A 4 A 0 X[n 1 1] * Y[n 1 1];
Z[n] 4 (real) A;
15
11 10
0
A 4 (real acc) Z[n];
10000
100 0000 0000
Ó
Ó
Note: When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is replaced by a ‘‘ ’’
Operation:
a
b
sign. The LENG parameter for this operation must be greater than 1.
À
aligned real X,Y;
real Z;
3.5.5.12 Multiply-and-Add Instructions
real acc A;
VAIMADÐVector Aligned Integer Multiply and Add
k
for (n40; n
À
A 4 A 0 X[n].low * Y[n].low 0
X[n].high * Y[n].high ;
Ó
Z[0] 4 (real) A;
LENG; n00)
The VAIMAD instruction multiplies corresponding elements
of the X and Y integer vectors, and adds or subtracts the
result, as an integer value, to the integer vector Z. This re-
sult is placed in the Z output vector.
Syntax:
Ó
Note: When PARAM.CLR is set to ‘‘1’’, A is cleared to ‘‘0’’ prior to the first
EXEC VAIMAD
15
11 10
0
a
addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is replaced
b
by a ‘‘ ’’ sign.
10000
100 0001 0100
VCMACÐVector Complex Multiply and Accumulate
Operation:
The VCMAC instruction performs a convolution sum of the
X and Y complex vectors. The previous value of the accu-
À
[ ]
mulator is used, and the result is stored in Z 0 .
aligned integer X,Y;
integer Z;
Syntax:
k
for (n40; n
À
LENG; n00)
EXEC VCMAC
Z[2n] 4 (integer) (Z[2n] 0 X[n].low *
Y[n].low);
Z[2n01] 4 (integer) (Z[2n01] 0 X[n].high
* Y[n].high);
15
11 10
0
10000
100 0111 0101
Operation:
Ó
À
Ó
Note: When PARAM.CLR is set to ‘‘1’’, only multiplication is done without
complex X,Y,Z;
complex acc A;
a
addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is replaced
k
b
by a ‘‘ ’’ sign.
for (n40; n
À
A 4 A 0 X[n] * Y[n];
LENG; n00)
VRMADÐVector Real Multiply and Add
The VRMAD instruction multiplies corresponding elements
of the X and Y real vectors and adds or subtracts the result
to the real vector Z. This result is placed in the Z output
vector.
Ó
Z[0] 4 (complex) A;
Ó
Note: When PARAM.COJ is set to ‘‘1’’, X n is multiplexed by the conjugate
[
]
of Y n . When PARAM.CLR is set to ‘‘1’’, A is cleared to ‘‘0’’ prior to
Syntax:
[
]
the first addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is
a
EXEC VRMAD
b
replaced by a ‘‘ ’’ sign.
15
11 10
0
VRLATPÐVector Real Lattice Propagate
The VRLATP instruction is used for implementing lattice and
inverse lattice filter operations. This instruction is used to
update the propagating values of vector Z.
10000
100 0011 0011
Syntax:
EXEC VRLATP
15
11 10
0
10000
100 0010 1100
48
3.0 Functional Description (Continued)
Operation:
3.5.5.13 Clipping and Min/Max Instructions
À
VARABSÐVector Aligned Real Absolute Value
real X,Y,Z;
The VARABS instruction computes the absolute value of
each element in the real vector X and places the result in
the corresponding place in the Y output vector.
k
for (n40; n
À
Z[n] 4 (real) (Z[n] 0 X[n] * Y[n]);
LENG; n00)
Syntax:
Ó
EXEC VARABS
Ó
Note: When PARAM.CLR is set to ‘‘1’’, only multiplication is performed,
15
11 10
0
a
without addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is
b
replaced by a ‘‘ ’’ sign.
10000
100 0001 1111
VARMADÐVector Aligned Real Multiply and Add
Operation:
The VARMAD instruction multiplies corresponding elements
of the X and Y real vectors and adds or subtracts the result
to the real vector Z. This result is placed in the Z output
vector.
À
aligned real X,Z;
k
for (n40; n
À
LENG; n00)
Syntax:
Z[n].low 4 abs (X[n].low);
Z[n].high 4 abs (X[n].high);
EXEC VARMAD
Ó
15
11 10
0
Ó
Note: There is no representation for the absolute value of 0x8000. Whenev-
er an absolute value of 0x8000 is needed, OVF.SAT is set to ‘‘1’’, and
the maximum positive number 0x7FFF is returned.
10000
100 0000 1110
Operation:
À
VARMINÐVector Aligned Real Minimum
aligned real X,Y,Z;
The VARMIN instruction compares corresponding elements
of the X and Y real vectors, and writes the smaller of the two
in the corresponding place in the Z integer vector.
k
for (n40; n
À
LENG; n00)
Z[n].low 4 (real) (Z[n].low 0 X[n].low *
Y[n].low);
Z[n].high 4 (real) (Z[n].high 0 X[n].high
Syntax:
EXEC VARMIN
* Y[n].high);
Ó
Ó
15
11 10
0
10000
100 0101 1111
Note: When PARAM.CLR is set to ‘‘1’’, only multiplication is performed,
a
without addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’ sign is
Operation:
À
b
replaced by a ‘‘ ’’ sign.
aligned real X,Y,Z;
VCMADÐVector Complex Multiply and Add
k
for (n40; n
À
LENG; n00)
The VCMAD instruction multiplies the corresponding ele-
ments of the X and Y complex vectors and adds or sub-
tracts the result to the complex vector Z. This result is
placed in the Z output vector.
Z[n].low 4 min (X[n].low ,Y[n].low);
Z[n].high 4 min (X[n].high ,Y[n].high);
Ó
Syntax:
Ó
EXEC VCMAD
VARMAXÐVector Aligned Real Maximum
The VARMAX instruction compares corresponding ele-
ments of the X and Y real vectors, and writes the larger of
the two in the corresponding place in the Z integer vector.
15
11 10
0
10000
100 1110 0000
Operation:
Syntax:
À
EXEC VARMAX
complex X,Y,Z;
15
11 10
0
k
for (n40; n
À
Z[n] 4 (complex) (Z[n] 0 X[n] * Y[n]);
LENG; n00)
10000
100 0110 0110
Ó
Ó
Note: When PARAM.COJ is set to ‘‘1’’, X[n] is multiplied by the conjugate
of Y[n]. When PARAM.CLR is set to ‘‘1’’, only multiplication is per-
a
formed, without addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘ ’’
b
sign is replaced by a ‘‘ ’’ sign.
49
3.0 Functional Description (Continued)
Operation:
Operation:
À
À
[ ]
aligned real X,Y,Z;
integer Y, Z 1 ;
extended temp, Z[0];
real X;
k
for (n40; n
À
LENG; n00)
real acc A;
Z[n].low 4 max (X[n].low , Y[n].low);
Z[n].high 4 max (X[n].high , Y[n].high);
A 4 (extended acc) ((extended)A);
temp 4 Z[0];
Ó
Ó
l
if (A
À
temp)
VRFMAXÐVector Real Find Maximum
temp 4 (extended) A;
[ ]
The VRFMAX instruction scans the X real vector and re-
turns the address of the element with maximum value. The
[ ]
resulting address is placed in Z 0 .
Z 1 4 &X[0];
Ó
Z[0] 4 temp;
Ó
Note: The Y vector must hold the following values: Y 0 must be 0x7fff, Y 1
Syntax:
EXEC VRFMAX
[
]
[ ]
[
]
must be 0x0001, and Y 2 must be 0x4000.
3.5.5.14 Special Instructions
ESHLÐExtended Shift Left
15
11 10
0
10000
100 0010 0100
Operation:
À
real X;
The ESHL instruction performs a shift-left operation on ex-
tended-precision data in the accumulator, and stores the
more significant half of the result as a real value into the first
element of the real Z vector.
integer Z;
internal register real tempX;
Syntax:
internal register integer tempA;
EXEC ESHL
tempX 4 X[0];
tempA 4 &X[0];
15
11 10
0
k
for (n41; n
À
LENG; n00)
10000
101 0110 0100
l
Operation:
if (X[n]
À
tempX)
À
tempX 4 X[n];
tempA 4 &X[n];
real acc A;
A 4 (real acc) ((extended)A);
Ó
l
k
1) for (n41; n LENG; n00)
if (LENG
À
Ó
Z[0] 4 tempA;
Ó
Note: The LENG parameter for this operation must be greater than 1.
A 4 A 0 A;
Ó
Z[0] 4 (real) A;
Ó
EFMAXÐExtended Find Maximum
Note: The LENG parameter for this operation must be greater than 0. When
LENG equals 1, only the real part of the accumulator is updated.
When LENG is greater than 1, both the real and the imaginary parts of
the accumulator are updated to the same value.
The EFMAX instruction implements a single iteration of
maximum search loop. The extended value in the accumula-
tor is compared with the first element of the extended Z
vector. The larger value is stored back into the Z vector. In
case the larger value was the accumulator, then the value of
X.ADDR is stored in the second location of the Z-vector (as
an integer).
VCPOLYÐVector Complex Polynomial
The VCPOLY instruction performs one iteration of evaluat-
ing polynomials with real coefficients, for a vector of com-
plex-valued arguments.
Syntax:
EXEC EFMAX
15
11 10
0
10000
101 0100 1011
50
3.0 Functional Description (Continued)
Syntax:
cients are given as real values, as well as the output result.
However, the accumulation is performed using extended-
precision arithmetic.
EXEC VCPOLY
15
11 10
0
Syntax:
EXEC VESIIR
10000
101 0001 1000
Operation:
15
11 10
0
À
10000
101 0011 0111
complex X,Z;
real Y;
Operation:
complex temp;
À
temp.re 4 (real) Y[0] * X[0].re;
temp.im 4 0;
real X,Y,Z;
real acc A;
k
k
LENG; n00)
for (n40; n
À
Z[n] 4 (complex) Z[n] * X[n01] 0 temp;
LENG; n00)
for (n40; n
À
A 4 (real acc) ((extended)A);
Ó
Z[LENG].re 4 (real) (Z[LENG].re *
A 4 (real acc) (A * X[n])) 0 Y[n02];
Z[n] 4 (real) A;
Ó
X[LENG01].re 0 Y[0] * temp.re);
Y.ADDR 4 &Y[1];
Ó
Ó
Note: The LENG parameter for this operation must be greater than 1.
[
]
Note: The term (A * X n ) is a 32-bit by 16-bit multiplication. During the
conversion of this product to a real accumulator data type, rounding
Ð
is done if PARAM.RND is ‘‘1’’. During the conversion of A to a real
VESIIRÐVector Extended Single-Pole IIR
e
0x0. The result with other values of Y 0 are unpredictable. Y 1
[
data type, the result is rounded if Y 0
]
[
]
]
0x0080, or truncated if Y 0
]
e
must be specified as 0x7fff.
[
[
The VESIIR instruction performs a special form of an Infi-
nite-Impulse Response (IIR) filter. The samples and coeffi-
TL/EE/11732–18
FIGURE 3-8. DSP Module Block Diagram
51
3.0 Functional Description (Continued)
3.6 SYSTEM INTERFACE
Either an external single-phase clock signal or a crystal can
be used as the clock source. If a single-phase clock source
is used, only the connection to OSCIN1 is required;
OSCOUT1 should be left unconnected or loaded with no
more then 5 pF of stray capacitance.
This section provides general information on the
NS32AM162 interface to the external world. Descriptions of
the CPU requirements as well as the various bus character-
istics are provided here. Details on other device characteris-
tics including timing are given in Chapter 4.
When operation with
a crystal is desired, special care
should be taken to minimize stray capacitance and induc-
tance. The crystal, as well as the external components,
should be placed in close proximity to OSCIN1 and
OSCOUT1 pins to keep the printed circuit trace lengths to
an absolute minimum. Figure 3-9 shows the external crystal
interconnections. Table 3-2 provides the crystal characteris-
tics and the values of R, C, and L components, including
stray capacitance.
3.6.1 Power and Grounding
The NS32AM162 requires a single 5V power supply, applied
pins. These pins should be connected together
on the V
CC
by a power (V ) plane on the printed circuit board.
CC
The grounding connections are made on the GND pins.
These pins should be connected together by a ground
(GND) plane on the printed circuit board.
For optimal noise immunity, the power and ground pins
should be connected to V and ground planes respective-
CC
ly. If V and ground planes are not used, single conductors
CC
should be run directly from each V
pin to a power point,
CC
and from each GND pin to a ground point. Daisy-chained
connections should be avoided.
Decoupling capacitors should also be used to keep the
noise level to a minimum. Standard 0.1 mF ceramic capaci-
tors can be used for this purpose. They should attach to
V
, GND pins as close as possible to the NS32AM162.
CC
During prototype using wire-wrap or similar methods, the
capacitors should be soldered directly to the power pins of
the NS32AM162 socket, or as close as possible, with very
short leads.
TL/EE/11732–19
FIGURE 3-9. High Frequency Crystal Connections
Design Notes
3.6.2.2 Low Frequency Clock Oscillator
When constructing a board using high frequency clocks with
multiple lines switching, special care should be taken to
avoid resonances on signal lines. A separate power and
ground layer is recommended. This is true when designing
boards for the NS32AM162. Switching times of under 5 ns
on some lines are possible. Resonant frequencies should
be maintained well above the 200 MHz frequency range on
signal paths by keeping traces short and inductance low.
Loading capacitance at the end of a transmission line con-
tributes to the resonant frequency and should be minimized
if possible. Capacitors should be located as close as possi-
ble across each power and ground pair near the
NS32AM162.
The NS32AM162 provides an internal oscillator that inter-
acts with an external clock Low-Frequency source through
two signals; OSCIN2 and OSCOUT2.
Either an external single-phase clock signal or a resonator
can be used as the clock source. If a single-phase clock
source is used, only the connection to OSCIN2 is required;
OSCOUT2 should be left unconnected or loaded with no
more then 5 pF of stray capacitance.
When operation with
a crystal is desired, special care
should be taken to minimize stray capacitances and induc-
tance. The resonator, as well as the external components,
should be placed in close proximity to OSCIN2 and
OSCOUT2 pins to keep the printed circuit trace lengths to
an absolute minimum. Figure 3-10 shows the external crys-
tal interconnections. Table 3-3 provides the crystal charac-
teristics and the values of R, and C components, including
stray capacitance.
3.6.2 Clocking
3.6.2.1 High Speed Clock Oscillator
The NS32AM162 provides an internal oscillator that inter-
acts with an external High-Speed clock source through two
signals; OSCIN1 and OSCOUT1.
52
3.0 Functional Description (Continued)
TABLE 3-2. High-Frequency Oscillator Circuit
Component
Value
Tolerance
Units
XTAL
Resonance
Third Overtone
Type
40.96
(parallel)
AT-Cut
50
MHz
Maximum Series Resistance
Maximum Shunt Capacitance
X
7
150k
51
pF
R1
R2
C1
C2
C3
L
10%
5%
X
X
20
10%
10%
20%
10%
pF
pF
pF
mH
20
1000
1.8
TABLE 3-3. Low Frequency Oscillator Circuit
Component
Value
Tolerance Units
RESONATOR Ceramic Resonator 455
kHz
X
R1
R2
C1
C2
1M
4.7k
100
100
10%
10%
20%
20%
X
pF
pF
TL/EE/11732–20
FIGURE 3-10. Low Frequency Resonator Connections
TL/EE/11732–21
FIGURE 3-11. Recommended Reset Connections
53
3.0 Functional Description (Continued)
3.6.3 Power Down Mode
carded; and any pending interrupts and traps are eliminated.
The internal latch for the edge-sensitive NMI signal is
cleared.
The Clock Generator Control register (CLKCTL) has two
control bits: PDM and DHFO. The DHFO controls the high-
frequency oscillator. When ‘‘0’’, the high-frequency oscilla-
tor is operating. When CLKCTL.DHFO is ‘‘1’’, the high-fre-
quency oscillator is disabled. The PDM bit changes the
mode of operation. When CLKCTL.PDM is ‘‘0’’, the proces-
sor is in normal operation mode, where all the modules op-
erate from the high-frequency oscillator. When
CLKCTL.PDM is ‘‘1’’, the NS32AM162 is in down power
mode, where some of the modules are not operating, and
others operate from the low-frequency oscillator. In the
power down mode, DRAM refresh cycles are done at a rate
of (/4 of Crystal-2 frequency, and the core operates from a
clock whose frequency is (/8 of Crystal-2. Accesses to the
following modules are not allowed during low power mode:
On application of power, RST must be held low for at least
is stable. This is to ensure that all on-chip
50 ms after V
CC
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 50 ms. See Figures 3-12 and 3-13.
ICU
#
#
TL/EE/11732–22
FIGURE 3-12. Power-On Reset Requirements
CODEC
PWM generator
#
DRAM read and write cycles.
#
When changing from normal operation mode to power down
mode, the user must set CLKCNTL.PDM to ‘‘1’’, and only
then set CLKCNTL.DHFO to ‘‘1’’. When changing from pow-
er down mode to normal operation mode, the user must
clear CLKCNTL.DHFO to ‘‘0’’, and only then clear
CLKCNTL.PDM.
TL/EE/11732–23
FIGURE 3-13. General Reset Timing
While in the Reset state, the CPU drives the signals CRD,
CWR and CFS inactive.
The internal CPU clock and CTTL run at half the frequency
of the signal on the OSCIN1 pin. CCLK is active (high).
The transition between normal operation mode and power
down mode occurs after a new value is written into
The PSR is reset to 0. The following conditions are present
after reset due to the PSR being reset to 0:
CLKCTL.PDM. The NS32AM162 may delay this transition, if
a DRAM refresh cycle is in process. The CLKCTL.PDM bit
will change its value only when the transition is done. Note
however that it is usually not needed to wait until the tran-
sition is done, since it is guaranteed that the processor will
change its mode when the DRAM refresh cycle is over.
Tracing is disabled.
Supervisor mode is enabled.
Supervisor stack space is used when the TOS addressing
mode is indicated.
3.6.4 Resetting
No trace traps are pending.
The RST input pin is used to reset the NS32AM162. The
CPU samples RST on the falling edge of CTTL.
Only NMI is enabled. Maskable interrupts are disabled.
Note that vector/non-vectored interrupts have not been se-
Whenever a low level is detected, the CPU responds imme-
diately. Any instruction being executed is terminated; any
results that have not yet been written to memory are dis-
[ ]
I instruc-
tion must be executed to enable vectored interrupts. If non-
lected. While interrupts are disabled, a SETCFG
[ ]
vectored interrupts are required, a SETCFG without the
must be executed.
I
54
4.0 Device Specifications
4.1 NS32AM162 PIN DESCRIPTIONS
OSCOUT2
Crystal2 Clock Output (455 KHz). This
line is used as the return path for the low
frequency crystal. When an external
clock source is used, OSCOUT2 should
be left unconnected or loaded with no
more than 5 pF of stray capacitance.
The following is a brief description of all NS32AM162 pins.
4.1.2 Input Signals
RST
Reset Input. Schmitt triggered, asyn-
chronous signal used to generate a CPU
reset.
PC0/A12
PC1/A13
PC2/A14
PC3/A15
PC4/A16
PC5/MRD
Output Port/External ROM Address
Line A12. Output Port, bit 0 in Internal
ROM mode, A12 in External ROM and
Development modes.
INT3
External Interrupt. Schmitt triggered. A
High-to-Low transition requests a maska-
ble interrupt.
OSCIN1
OSCIN2
CDIN
Crystal1/External
Clock
Input
Output Port/External ROM Address
Line A13. Output Port, bit 1 in Internal
ROM mode, A13 in External ROM and
Development modes.
(40.96 MHz). Input from a crystal or an
external clock source.
Crystal2/External
Clock
Input
(455 KHz). Input from a crystal or an ex-
ternal clock source.
Output Port/External ROM Address
Line A14. Output Port, bit 2 in Internal
ROM mode, A14 in External ROM and
Development modes.
Data In from CODEC. Data is input from
CODEC via this pin.
Output Port/External ROM Address
Line A15. Output Port, bit 3 in Internal
ROM mode, A15 in External ROM and
Development modes.
Note: After reset this pin is configured as
an output, until the MCFG register is set
to the appropriate value.
4.1.3 Output Signals
Output Port/External ROM Address
Line A16. Output Port, bit 4 in Internal
ROM mode, A16 in External ROM and
Development modes.
A1–A11
Address Bus. These are the 11 least sig-
nificant bits of the memory address bus.
During DRAM accesses these are the
row and column address bits.
Output Port/External ROM OE Signal.
Output Port, bit 5 in Internal ROM mode,
external memory Output Enable control
in External ROM and Development
modes.
RAS
Row Address Strobe for DRAM Control
and Refresh. During DRAM accesses
controls DRAM’s row address latches;
signals the beginning of a DRAM bus cy-
cle. Activated also during DRAM refresh
cycles.
4.1.4 Input/Output Signals
CAS
Column Address Strobe for DRAM
Control and Refresh. During DRAM ac-
cesses controls DRAM’s column address
latches. Activated also during DRAM re-
fresh cycles.
D0–D1
Data Bus Bits 0 and 1. Data bit 0 is the
l.s.b.
D2/RA12
Data Bus Bit 2/DRAM Row Address
Line A12. Data bit 2. Row Address Line
12 in Internal ROM mode. Address line
12 is asserted valid during DRAM ac-
cesses when RAS is activated.
DWE
DRAM Write/Read Control. Activated
during DRAM write bus cycles. Enables
writing data to the DRAM.
D3–D7
Data Bus Bits 3 to 7.
CFS0
CODEC0 Frame Sync. Starts a new en-
code and decode cycle.
PA0/MWR0
Port A, Bit Programmable/External
RAM WE/Signal. Port A, bit 0 in Internal
and External ROM modes, WE signal in
Development mode, activated during ex-
ternal memory write cycles in order to en-
able writing of data to the memory’s even
bytes.
CDOUT
CCLK
Data Out to CODEC. Data is output to
the CODEC via this pin.
CODEC Master ClockÐ
CODEC’s Clock input for the switched-
capacitor filters and CODEC.
PA1/MWR1
Port A, Bit Programmable/External
RAM WE Signal. Port A, bit 1 in Internal
and External ROM modes, WE signal in
Development mode, activated during ex-
ternal memory write cycles in order to en-
able writing of data to the memory’s odd
bytes.
PWM/CFS1
PWM
Generator
Output/CODEC1
Frame Sync. When one CODEC is
usedÐPulse Width Modulator output sig-
nal. This signal has a fixed frequency and
a variable duty cycle.
When two CODECs are usedÐ
CODEC1’s Frame Sync input. Starts a
new encode and decode cycle.
PA2/CTTL
Port A, Bit Programmable/CPU Clock.
Port A, bit 2 in Internal and External ROM
modes, CTTL clock in Development
mode, this clock is similar to internal
PHI1. The skew between CCTL rising
edge and PHI1 rising edge is kept to a
minimum.
OSCOUT1
Crystal1 Clock Output (40.96 MHz).
This line is used as the return path for the
high frequency crystal. When an external
clock source is used, OSCOUT1 should
be left unconnected or loaded with no
more than 5 pF of stray capacitance.
55
4.0 Device Specifications (Continued)
PA3/NSF
Port A, Bit Programmable/Non-Se-
quential Fetch Status. Port A, bit 3 in
Internal and External ROM modes, NSF
in Development mode. NSF is a status
signal activated during Non-Sequential
Instruction Fetches (meaningful if T1 is
also activated).
PA7/A18
Port A, Bit Programmable/External
Address Line A18. Port A, bit 7 in Inter-
nal and External ROM modes, address
bit 18 in Development mode.
PB0–PB7/
D8–D15
Port B, Bit Programmable/Extended
Data Bus Bit 8 through 15. Port B bits 0
to 7 in Internal ROM mode, Data odd
byte in External ROM and Development
modes.
PA4/T1
Port A, Bit Programmable/T1 (First bus
transaction’s cycle). Port A, bit 4 in Inter-
nal and External ROM modes, T1 in De-
velopment mode. T1 is activated at the
beginning of any core or DSPM bus
transaction.
PC6/IOWR/
MODE0
Output Port/External IO Write Con-
trol/Mode Control. Output Port, bit 6 in
internal ROM mode, external IO write
control in External ROM and Develop-
ment modes.
PA5/DDIN
PA6/A17
Port A, Bit Programmable/Data Direc-
tion. Port A, bit 5 in Internal and External
ROM modes, DDIN in Development
mode. DDIN is a status signal indicating
the direction of the data transfer during a
bus cycle.
Synchronize bit 0, sampled upon reset to
determine the mode of operation.
PC7/IORD/
MODE1
Output Port/External IO Read Con-
trol/Mode Control. Output Port, bit 7 in
Internal ROM mode, external IO read
control in External ROM and Develop-
ment modes.
Port A, Bit Programmable/External
Address Line A17. Port A, bit 6 in Inter-
nal and External ROM modes, address
bit 17 in Development mode.
Synchronize bit 1, sampled upon reset to
determine the mode of operation.
68-Pin PCC Package
TL/EE/11732–24
Top View
Order Number NS32AM162V-20 or NS32AM163V-20
NS Package Number V68A
FIGURE 4-1. Connection Diagram
56
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature
§
§
a
0 C to 70 C
Temperature under Bias
§
§
All Input or Output Voltages
with Respect to GND
b
a
0.5V to 6.5V
4.3 ELECTRICAL CHARACTERISTICS
e
a
0 C to 70 C, V
e
CC
e
g
5V 10% GND
T
0V.
Conditions
§
§
A
Symbol
Parameter
Min
Typ
Max
Units
a
V
V
V
Logical 1 Input Voltage
Logical 0 Input Voltage
Logical 1 Output Voltage
2.0
V
V
0.5
0.5
V
V
V
IH
CC
b
0.5
2.4
0.8
IL
e b
e b
I
I
400 mA
400 mA
OH
OH
VPWMH
PWM Logical 1 Voltage
(Note 1)
OH
b
a
V
0.5
V
V
V
CC
CC
e
e
V
OL
Logical 0 Output Voltage
I
I
4 mA
0.45
OL
VPWML
PWM Logical 0 Voltage
(Note 1)
400 mA
OL
b
a
0.5
0.5
VX1H
VX2H
OSCIN1/OSCIN2 Input
High Voltage (Note 2)
4.2
V
VX1L
VX2L
OSCIN1/OSCIN2 Input
Low Voltage (Note 2)
1.0
V
s
s
b
b
I
I
Input Load Current
0V
0V
V
V
V
20
20
20
20
mA
mA
L
IN
CC
s
s
(Off)
Output Leakage Current
(I/O Pins in Input Mode)
V
CC
O
OUT
e
I
I
Active Supply Current
(High Power Mode)
I
0,
CCH
CCL
OUT
e
T
25 C
200
2.5
mA
§
5V
A
e
e
OSCIN1
40.96 MHz
V
CC
e
Active Supply Current
(Low Power Mode)
I
OUT
0,
e
e
5V
T
25 C
§
mA
V
A
e
OSCIN2
455 KHz
V
CC
VHYS
VHh
Hysteresis Loop Width
(Note 1)
0.5
Max (3.5,
High Level Input Voltage
V
V
V
b
V
CC
1.5)
VHl
Low Level Input Voltage
0.7
0.7
VMODh
MODE0 and MODE1
Max (3.5,
b
1.5)
High Level Input Voltage
V
CC
VMOD1
MODE0 and MODE1
V
Low Level Input Voltage
Note 1: Guaranteed by design.
Note 2: When an external single-phase clock signal is used, the Min value of VX1H, VX2H is 4.5V, and the Max value of VX1L, VX2L is 0.5V.
57
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
illustrated in Figures 4-2, 4-3 and 4-4 unless specifically
stated otherwise. CTTL and all other output signals capaci-
tive load is assumed to be 50 pF. OSCIN1 crystal frequency
is 40.96 MHz. OSCIN2 ceramic resonator frequency is
455 KHz.
All the timing specification given in this section refer to 0.8V
or 2.0V on the rising or falling edges of all the signals as
TL/EE/11732–25
FIGURE 4-2. Synchronous Output Signals Specification
TL/EE/11732–26
FIGURE 4-3. Synchronous Input Signals Specification
TL/EE/11732–27
FIGURE 4-4. Asynchronous Signals Specification
Abbreviations:
L.E. - Leading Edge
R.E. - Rising Edge
T.E. - Trailing Edge
F.E. - Falling Edge
TL/EE/11732–28
FIGURE 4-4a. PWM Output Signal Specification
TL/EE/11732–29
FIGURE 4-4b. Hysteresis Inputs Definition
58
4.0 Device Specifications (Continued)
4.4.2 Synchronous Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32AM162-20
NS32AM162
Max
Symbol
Figure
Description
Reference Conditions
Units
Min
tCTp
4-15
4-15
4-15
4-10
4-10
4-8
CTTL Clock Period (Note 1)
CTTL High Time
R.E. CTTL to Next R.E. CTTL
At 2.0V (Both Edges)
At 0.8V (Both Edges)
After R.E. CTTL
48.8
17582.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
b
tCTh
tCTp/2
tCTp/2
5
5
b
tCT1
CTTL Low Time
tCCLKa
tCCLKia
tCFSa
tCFSia
tAv
CCLK Active
13.0
13.0
25.0
25.0
12.0
13.0
13.0
13.0
CCLK Inactive
After R.E. CTTL
CFS0, CFS1/Active
CFS0, CFS1/Inactive
Address Valid (Note 5)
D(0:15) Valid
After R.E. CTTL
4-8
After R.E. CTTL
4-5a
4-5c
4-5c
After R.E. CTTL T1 or T3
After R.E. CTTL T2
After R.E. CTTL T1
After R.E. CTTL
tDv
tDf
D(0:15) Float (Note 4)
CDOUT Valid
tCDOv
4-8
4-9
tCDOh
tDDINv
tT1a
4-10
CDOUT Hold
After R.E. CTTL
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-11a
4-11a
4-11a
4-11a
4-11a
4-5a
DDIN Valid
After R.E. CTTL T1
After R.E. CTTL T1
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T4
After R.E. CTTL T1 or T3RF
After R.E. CTTL T4 or T4RF
After R.E. CTTL T3 or T1RF
After R.E. CTTL T4 or T4RF
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T2
After R.E. CTTL T4
After R.E. CTTL T2
13.0
13.0
13.0
13.0
13.0
T1 Active
tT1ia
T1 Inactive
tNSFa
NSF Active
tNSFia
tRASa
tRASia
tCASa
tCASia
tDWEa
tDWEia
tMRDa
tMRDia
tIORDa
tIORDia
tMWRa
tMWRia
tIOWRa
tIOWRia
tPABCv
NSF Inactive
b
b
b
b
a
a
a
a
RAS Active (Note 2)
Ras Inactive (Note 4)
CAS Active (Note 2)
CAS Inactive (Note 4)
DRAM Write Enable Active
DRAM Write Enable Inactive
MRD Active
tCTp/2
tCTp/2
tCTp/2
tCTp/2
6
6
6
6
tCTp/2
tCTp/2
tCTp/2
tCTp/2
16
16
16
16
4-5a
4-5a
4-5a
4-5c
13.0
4-5c
13.0
13.0
13.0
13.0
13.0
13.0
13.0
13.0
13.0
13.0
4-11a
4-11a
4-11b
4-11b
4-12a
4-12a
4-12b
4-12b
4-13a
MRD Inactive
IORD Active
IORD Inactive
MWR Active
MWR Inactive
IOWR Active
IOWR Inactive
PA, PB and PC Valid
59
4.0 Device Specifications (Continued)
4.4.2 Synchronous Timing Tables (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32AM162-20 (Continued)
NS32AM162
Max
25.0
Symbol
Figure
Description
Reference Conditions
Units
Min
tPWMv
tRASLa
tRASLia
tCASLa
tCASLia
4-13b
4-7
PWM Valid
After R.E. CTTL
ns
ms
ms
ms
ms
b
tX2p 0.2
DRAM L.P. RAS Active
DRAM L.P. RAS Inactive
DRAM L.P. CAS Active
DRAM L.P. CAS Inactive
After R.E. OSCIN2
After R.E. OSCIN2
After R.E. OSCIN2
After R.E. OSCIN2
b
tX2p 0.2
4-7
b
tX2p 0.2
4-7
b
tX2p 0.2
4-7
Note 1: tCTp can be only 48.8 ns (normal operation) or 17582 ns (power down mode).
4.4.2.2 Input Signals
NS32AM162
Symbol
Figure
Description
Reference Conditions
Units
Min
Max
tX1p
tX1h
tX11
tX2p
tX2h
tX2l
4-15
4-15
4-15
4-15
4-15
4-15
4-5a
4-5a
OSCIN1 Clock Period
R.E. OSCIN1
24.4
ns
ns
ns
ms
ms
ms
ns
ns
ns
b
OSCIN1 High (External Clock)
OSCIN1 Low (External Clock)
OSCIN2 Clock Period
OSCIN2 High (External Clock)
OSCIN2 Low (External Clock)
Data In Setup
At 4.2V (Both Edges)
At 1.0V (Both Edges)
R.E. OSCIN2
tX1p/2
tX1p/2
5
5
b
2.2
At 4.2V (Both Edges)
At 1.0V (Both Edges)
Before R.E. CTTL T4
After R.E. CTTL T4
Before R.E. CTTL
0.8
0.8
tDIs
11.0
2.0
tDIh
tCDIs
Data In Hold (Note 3)
4-8
4-9
CDIN Setup
11.0
tCDIh
4-8
4-9
CDIN Hold
After R.E. CTTL
2.0
ns
tPABs
tPABh
tRSTw
tPWR
4-14
4-14
4-16
4-17
PA and PB Data in Setup
PA and PB in Hold
Before R.E. CTTL T4
After R.E. CTTL T4
At 0.8V (Both Edges)
11.0
2.0
50
ns
ns
ms
ms
RST Pulse Width
Power Stable to R.E. of RST (Note 4)
After V Reaches 4.5V
CC
50
Note 2: Address setup before RAS, Address setup before CAS and Data Setup before CA are at least 9 ns, guaranteed by design.
Note 3: tDIh is always less than or equal to tMRDia, tIORDIa and tCRDia, guaranteed by design.
Note 4: Not tested, guaranteed by design.
Note 5: Refers to A(1:18) in Development mode, to A(1:16) in External ROM mode, to A(1:11) in Internal ROM mode.
60
4.0 Device Specifications (Continued)
4.4.3 TIMING DIAGRAMS
TL/EE/11732–30
FIGURE 4-5a. DRAM Read Cycle Timing (Internal ROM Mode Only)
TL/EE/11732–31
FIGURE 4-5b. DRAM Read Cycle Timing (External ROM or Development Modes)
61
4.0 Device Specifications (Continued)
TL/EE/11732–32
FIGURE 4-5c. DRAM Write Cycle Timing (Internal ROM Mode Only)
TL/EE/11732–33
FIGURE 4-5d. DRAM Write Cycle Timing (External ROM or Development Modes)
TL/EE/11732–34
FIGURE 4-6. DRAM Refresh Cycle Timing (In Normal Operation Mode)
62
4.0 Device Specifications (Continued)
TL/EE/11732–35
TL/EE/11732–36
TL/EE/11732–37
FIGURE 4-7. DRAM Power Down Refresh
FIGURE 4-8. CODEC Long Frame Timing, 8 KHz Sampling Rate
FIGURE 4-9. CODEC Short Frame Timing, 8 KHz Sampling Rate
63
4.0 Device Specifications (Continued)
TL/EE/11732–38
FIGURE 4-10. CDOUT Hold Timing
TL/EE/11732–39
FIGURE 4-11a. External Memory Read Timing
64
4.0 Device Specifications (Continued)
TL/EE/11732–40
FIGURE 4-11b. I/O Read Cycle
TL/EE/11732–41
FIGURE 4-12a. External Memory WriteÐCycle Timing
65
4.0 Device Specifications (Continued)
TL/EE/11732–42
FIGURE 4-12b. I/O Write Cycle Timing
TL/EE/11732–43
FIGURE 4-13a. Port A, Port B and Port C Timing
TL/EE/11732–44
FIGURE 4-13b. PWM Output Timing
TL/EE/11732–45
FIGURE 4-14. Port A and Port B Input Timing
66
4.0 Device Specifications (Continued)
TL/EE/11732–46
FIGURE 4-15. CTTL, OSCIN1 and OSCIN2 Timing
TL/EE/11732–47
FIGURE 4-16. Non Power On Reset
TL/EE/11732–48
FIGURE 4-17. Power On Reset
67
Appendix A: Instruction Formats
NOTATIONS
e
e
T
B
Translated
Backward
e
i
Integer Type Field
e
e
00: None
B
00 (Byte)
U/W
e
e
W
D
01 (Word)
01: While Match
11: Until Match
11 (Double Word)
e
e
f
Floating-Point Type Field
7
0
e
e
F
L
1 (Std. Floating: 32 bits)
0 (Long Floating: 64 bits)
cond
1
0
0
0
1
1
0
op
Operation Code
Format 0
7
Valid encodings shown with each format.
Bcond
(BR)
e
gen, gen 1, gen 2
General Addressing Mode Field
See Section 2.4.2 for encodings.
0
e
e
reg
General Purpose Register Number
Condition Code Field
op
0
cond
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
EQual: Z
Format 1
e
Not Equal: Z
Carry Set: C
Carry Clear: C
0
BSR
Ð0000
Ð0001
Ð0100
Ð0101
Ð0110
Ð0111
ENTER
EXIT
NOP
WAIT
DIA
Ð1000
Ð1001
Ð1010
Ð1011
Ð1100
Ð1101
Ð1110
Ð1111
e
1
RET
e
0
RETT
RETI
SAVE
e
Higher: L
Lower or Same: L
1
e
0
RESTORE
FLAG
SVC
e
e
Greater Than: N
Less or Equal: N
1
0
BPT
e
Flag Set: F
1
15
8
7
0
0
0
e
Flag Clear: F
0
e
e
0
LOwer: L
0 and Z
gen
short
op
1
1
i
i
i
e
e
Higher or Same: L
1 or Z
1
Format 2
e
e
Less Than: N
0 and Z
0
e
e
1
Greater or Equal: N
1 or Z
ADDQ
CMPQ
SPR
Ð000
Ð001
Ð010
Ð011
ACB
Ð100
Ð101
Ð110
MOVQ
LPR
(Unconditionally True)
(Unconditionally False)
Scond
e
short
Short Immediate Value. May contain
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ, ACB
15
8 7
gen
op
Format 3
1
1
1
1
1
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPR
e
0000
UPSR
BICPSR
JUMP
Ð0010
Ð0100
Ð0110
ADJSP
JSR
Ð1010
Ð1100
Ð1110
e
0001–0111
(Reserved)
e
e
e
e
e
e
e
e
1000
1001
1010
1011
1100
1101
1110
1111
FP
SP
SB
BISPSR
CASE
Trap (UND) on XXX1, 1000
15
8 7
(Reserved)
(Reserved)
PSR
gen 1
gen 2
Format 4
op
INTBASE
MOD
ADD
CMP
BIC
Ð0000
Ð0001
Ð0010
Ð0100
Ð0101
Ð0110
SUB
Ð1000
ADDR
AND
Ð1001
Ð1010
Ð1100
Ð1101
Ð1110
Options: in String Instructions
ADDC
MOV
OR
SUBC
TBIT
XOR
U/W
B
T
68
Appendix A: Instruction Formats (Continued)
23
16 15
8 7
0
0 0 0 0 0 short
0
op
i
0 0 0 0 1 1 1 0
Format 5
TL/EE/11732–50
Format 10
Always
b
b
b
b
b
b
b
b
MOVS
0000
0001
0010
0011
0100
0110
0111
BITWT
TBITS
1000
1001
1010
1011
1100
1101
1110
Trap (UND)
b
b
b
b
b
b
CMPS
SETCFG
SKPS
BBAND
SBITPS
BBFOR
SBITS
BBSTOD
BBOR
TL/EE/11732–51
MOVMP
BBXOR
No Operation on 1111
Format 13
Always
Trap (UND)
23
16 15
8 7
0
gen 1
gen 2
op
i
0 1 0 0 1 1 1 0
Format 6
TL/EE/11732–52
b
b
b
b
b
b
b
b
b
b
b
b
b
b
ROT
0000
0001
0010
0100
0101
0110
1000
NOT
1001
1011
1011
1100
1101
1110
1111
Format 14
Always
ASH
Trap (UND)
SUBP
ABS
Trap (UND)
CBIT
Trap (UND)
LSH
COM
SBIT
IBIT
TL/EE/11732–53
NEG
ADDP
Format 15
Always
23
16 15
8 7
0
Trap (UND)
gen 1
gen 2
op
i
1 1 0 0 1 1 1 0
Format 7
TL/EE/11732–54
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
MOVM
0000
0001
0010
0011
0100
0101
0110
0111
MUL
1000
1001
1010
1011
1100
1101
1110
1111
CMPM
MEI
Format 16
Always
INSS
Trap (UND)
DEI
Trap (UND)
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
QUO
REM
MOD
DIV
TL/EE/11732–55
TL/EE/11732–49
Format 8
b
b
b
b
b
b
EXT
0 00
0 01
0 10
0 11
INDEX
FFS
1 00
1 01
CVTP
INS
CHECK
b
b
Trap (UND) on 1 10 and 1 11
69
Appendix A: Instruction Formats (Continued)
Format 17
Implied Immediate Encodings:
7
Trap (UND)
Always
0
0
0
r7
r6
r5
r4
r3
r2
r1
r0
r7
Register Mask, appended to SAVE, ENTER
TL/EE/11732–56
7
7
Format 18
Always
ro
r1
r2
r3
r4
r5
r6
Trap (UND)
Register Mask, appended to RESTORE, EXIT
TL/EE/11732–57
b
length 1
offset
Format 19
Always
Trap (UND)
Offset/Length Modifier appended to INSS, EXTS
Note 1: Opcode not defined; CPU treats like MOVf. First operand has access class of read; second operand has access class of write; f-field selects 32-bit or
64-bit data.
Note 2: Opcode not defined; CPU treats like ADDf. First operand has access class of read; second operand has access class of read-modify-write. f-field selects
32-bit or 64-bit data.
Note 3: Reserved opcode; execution of this opcode will generate an undefined result.
70
Appendix B: Instruction Execution Times
This section provides the necessary information to calculate
the instruction execution times for the NS32AM162.
TiÐ The time required to transfer an integer value to or
from the FPU.
The following assumptions are made:
B.1.1 Equations
Y
The entire instruction, with all displacements and imme-
diate operands, is assumed to be present in the instruc-
tion queue when needed.
The following equations assume that:
Memory accesses occur at full speed.
#
Any wait states should be reflected in the calculations of
TOPB, TOPW and TOPD.
#
Y
Interference from instruction prefetches, which is very
dependent upon the preceding instruction(s), is ignored.
This assumption will tend to affect the timing estimate
in an optimistic direction.
Note: When multiple writes are performed during the execution of an in-
struction, wait states occurring during intermediate write transactions
may be partially hidden by the internal execution. Therefore, a certain
number of wait states can be inserted with no effect on the execution
time. For example, in the case of the MOVSi instructions each wait
state on write operations subtracts 1 clock cycle per write bus access,
from the TCY of the instruction, since updating the pointers occurs in
parallel with the write operation. This means that wait states can be
added to write cycles without changing the execution time of the in-
struction, up to a maximum of 13 wait states on writes for MOVSB and
MOVSW, and 4 wait states on writes for MOVSD.
Y
It is assumed that all memory operand transfers are
completed before the next instruction begins execution.
In the case of an operand of access class rmw in
memory, this is pessimistic, as the Write transfer occurs
in parallel with the execution of the next instruction.
It is assumed that there is no overlap between the
fetch of an operand and the following sequences of mi-
crocode. This is pessimistic, as the fetch of Operand 1
will generally occur in parallel with the effective address
calculation of Operand 2, and the fetch of Operand 2
will occur in parallel with the execution phase of the in-
struction.
Y
TEAÐ TEA values for the various addressing modes are
provided in the following table.
TEA TABLE
Addressing
Mode
TEA
Notes
Y
Where possible, the values of operands are taken into
consideration when they affect instruction timing, and a
range of times is given. Where this is not done, the
worst case is assumed.
Value
IMMEDIATE,
4
ABSOLUTE
a
MEMORY RELATIVE
REGISTER
7
TOPD
2
B.1 BASIC INSTRUCTIONS
Execution times for basic and floating-point instructions are
given in Table B-1. The parameters needed for the various
calculations are defined below.
REGISTER RELATIVE,
MEMORY SPACE
5
TEAÐ The time required to calculate an operand’s Effec-
tive Address. For a Register or Immediate oper-
and, this includes the fetch of that operand.
TOP OF STACK
4
2
3
Access Class Write
Access Class Read
Access Class RMW
TEA1Ð TEA value for the GEN or GEN1 operand.
TEA2Ð TEA value for the GEN2 operand.
a
TI2
SCALED INDEXED
TI1
TOPBÐ The time needed to read or write a memory byte.
TOPWÐ The time needed to read or write a memory word.
e
TI1
TEA of the basemode except:
e
if basemode is REGISTER then TI1
5
TOPDÐ The time needed to read or write a memory dou-
ble-word.
e
if basemode is TOP OF STACK then TI1
TI2 depends on the scale factor:
4
TOPiÐ The time needed to read or write a memory oper-
and, where the operand size is given by the opera-
tion length of the instruction. It is always equiva-
lent to either TOPB, TOPW or TOPD.
e
if byte indexing TI1
if word indexing TI2
5
e
7
e
if double-word indexing TI2
8
TCYÐ Internal processing overhead, in clock cycles.
e
if quad-word indexing TI2
10
LÐ Internal processing whose duration depends on
the operation length. The number of clock cycles
is derived by multiplying this value by the number
of bytes in the operation length.
TOPBÐ If operand is in a register or is immediate then
e
TOPB
else TOPB
TOPWÐ If operand is in a register or is immediate then
0
e
3
NCYCÐ Number of bus cycles performed by the CPU to
fetch or store an operand. NCYC depends on the
operand size and alignment.
e
TOPW
0
e
b
1
else TOPW
4
NCYC
#
TOPDÐ If operand is in a register or is immediate then
fÐ This parameter is related to the floating-point op-
erand size.
e
TOPD
0
e
b
1
TfÐ The time required to transfer 32 bits of floating
point value to or from the FPU.
else TOPD
4
NCYC
#
71
Appendix B: Instruction Execution Times (Continued)
k
k
k
l
Memory
TOPiÐ If operand is in a register or is immediate then
M
e
TOPi
0
e
e
l
x
Any Addressing Mode
e
else if i
else if i
byte then TOPi
word then TOPi
TOPB
TOPW
l
ab a and b represent the addressing modes of operand
1 and 2 respectively. Both a and b can be any ad-
e
k
l
dressing mode (e.g., MR means memory to CPU
register).
e
e
TOPD
else (i
double-word) then TOPi
e
e
1
LÐ If i (operation length)
byte then L
Note: Unless otherwise specified the TCY value for immediate addressing is
e
e
else if i
word then L
2
the same as for CPU register addressing.
e
e
else (i
double-word) L
4
B.1.3. Calculation of the Execution Time TEX for Basic
Instructions
e
fÐ If standard floating (32 bits): f
1
e
If long floating (64 bits): f
2
The execution time for a basic instruction is obtained by
performing the following steps:
e
TfÐ Tf
4
e
e
e
e
TiÐ If integer
If integer
byte or word, then Ti
double-word, then Ti
2
4
1. Find the desired instruction in Table B-1.
2. Calculate the values of TEA, TOPB, etc. using the num-
bers in the table and the equations given in the previous
sections.
B.1.2 Notes on Table Use
Ý
Ý
Values in the TEA1 and TEA2 columns indicate whether
effective addresses need to be calculated.
3. The result derived by adding together these values is the
execution time TEX in clock cycles.
A value of 1 indicates that address calculation time is re-
quired for the corresponding operand. A 0 indicates that the
operand is either missing, or it is in a register and the in-
struction has an optimized form which eliminates the TEA
calculation for it.
EXAMPLE
Calculate TEX for the instruction CMPW R0, TOS.
Operand 1 is in a register; Operand 2 is in memory. This
means that we must use the table values corresponding to
k
l
the xM case as given in the Notes column.
In the L column, multiply the entry by the operation length in
bytes (1, 2 or 4).
Ý
Ý
Ý
Only the TEA1, TEA2, TOPi and TCY columns have
values assigned for the CMPi instruction. Therefore, they
are the only ones that need to be calculated to find TEX.
The blank columns are irrelevant to this instruction.
In the TCY column, special notations sometimes appear:
n1
x
n2 means n1 minimum, n2 maximum
n1%n2 means that the instruction flushes the instruction
queue after n1 clock cycles and nonsequentially fetches the
next instruction. The value n2 indicates the number of clock
cycles for the internal execution of the instruction (including
n1).
k
l
case. This means that effective address times have to be
Ý
Ý
Both TEA1 and TEA2 columns contain 1 for the xM
k
l
calculated for both operands. (For the MR case, the
Register operand would have required no TEA time, there-
fore only the Memory operand TEA would have been neces-
sary.) From the equations:
The effective number of cycles (TCY) must take into ac-
) required to fetch the portion of the
fetch
count the time (T
e
TEA1 (Register mode)
2.
next instruction including the basic encoding and the index
bytes. This time depends on the size and the alignment of
this portion.
e
TEA2 (Top of Stack mode, access class read)
2.
Ý
The TOPi column represents potential operand transfers
to or from memory. For a Compare instruction, each oper-
and is read once, for a total of two operand transfers.
If only one memory cycle is required, then:
e
a
a
T
TCY
n1
6
fetch
e
TOPi (Word, Register)
e
0,
3 (assuming the operand aligned)
If more than one memory cycle is required, then:
TOPi (Word, TOS)
e
e
a
a
T
TCY
In the notes column, notations held within angle brackets
k l
n1
5
fetch
Total TOPi
3
TCY is the time required for internal operation within the
CPU. The TCY value for this case is 3.
indicate alternatives in the operand addressing modes
which affect the execution time. A table entry which is af-
fected by the operand addressing may have multiple values,
corresponding to the alternatives. These addressing nota-
tions are:
e
a
a
a
e
a
a
a
3
TEX
e
TEA1
10 machine cycles.
If the CPU is running at 20 MHz then a machine cycle (clock
TEA2
TOPi
TCY
2
2
3
c
cycle) is 50 ns. Therefore, this instruction would take 10
50 ns, or 0.5 ms, to execute.
k l
I
Immediate
k
l
CPU Register
R
72
Appendix B: Instruction Execution Times (Continued)
TABLE B-1. Basic Instructions
Ý
Ý
Ý
Ý
Ý
Ý
Ý
L
Mnemonic
TEA1
TEA2
TOPB
TOPW
TOPD
TOPi
TCY
Notes
k
l
ABSi
1
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
2
2
Ð
Ð
9
8
SCR
SCR
0
0
k
k
k
k
l
l
l
l
ACBi
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
2
Ð
Ð
Ð
Ð
Ð
Ð
16
M
M
R
R
no branch
branch
no branch
branch
15%20
18
17%22
k
k
k
l
xM
ADDi
1
1
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
Ð
3
4
4
l
MR
l
RR
k
k
k
l
xM
ADDCi
1
1
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
Ð
3
4
4
l
MR
l
RR
ADDPi
ADDQi
ADDR
1
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
3
3
Ð
Ð
16
18
No Carry
Carry
k
k
l
M
Ð
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
Ð
Ð
Ð
6
4
l
R
k
k
l
xM
1
1
1
Ð
Ð
Ð
Ð
Ð
1
Ð
Ð
Ð
Ð
Ð
2
3
l
xR
ADJSPi
ANDi
1
Ð
Ð
Ð
Ð
1
Ð
6
k
k
k
l
l
l
RR
1
1
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
Ð
3
4
4
xM
MR
ASHi
1
1
1
Ð
Ð
2
Ð
14
x
7
6%10
45
Bcond
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
no branch
branch
k
k
k
l
xM
BICi
1
1
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
Ð
3
4
4
l
MR
l
RR
73
Appendix B: Instruction Execution Times (Continued)
TABLE B-1. Basic Instructions (Continued)
Ý
Ý
Ý
Ý
Ý
Ý
Ý
L
Mnemonic
BICPSRB
BICPSRW
BISPSRB
BISPSRW
BPT
TEA1
TEA2
Ð
TOPB
1
TOPW
TOPD
Ð
Ð
Ð
Ð
4
TOPi
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
TCY
18%22
30%34
18%22
30%34
40
Notes
1
1
Ð
1
Ð
Ð
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
Ð
Ð
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
Ð
2
BR
Ð
Ð
Ð
Ð
Ð
1
4%10
6%16
4%9
BSR
Ð
CASEi
Ð
Ð
k
k
l
xM
l
xR
CBITi
1
1
1
2
Ð
Ð
Ð
Ð
1
1
Ð
Ð
15
7
Ð
Ð
CHECKi
CMPi
1
1
1
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
3
3
Ð
Ð
Ð
7
high
low
ok
10
11
k
k
k
l
xM
l
MR
l
RR
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
1
Ð
Ð
Ð
3
3
3
Ð
Ð
Ð
Ð
e
in block
Ý
of elements
CMPMi
CMPQi
CMPSi
n
a
24
1
1
Ð
Ð
Ð
2 * n
Ð
9 * n
k
k
l
M
l
R
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
Ð
Ð
3
Ð
Ð
3
e
not Translated
Ý
n
of elements,
a
a
Ð
Ð
Ð
Ð
Ð
2 * n
Ð
35 * n
38 * n
53
53
CMPST
COMi
CVTP
DEIi
Ð
1
Ð
1
n
Ð
Ð
Ð
Ð
Ð
1
2 * n
2
Ð
Ð
Ð
Translated
Ð
Ð
7
1
1
Ð
7
k
k
l
xM
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
5
1
16
16
38
31
l
Ð
xR
DIA
Ð
1
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
Ð
3%7
DIVi
16
58
x
68
e
registers saved
Ý
ENTER
n
of general
a
a
a
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
n
1
1
Ð
Ð
Ð
Ð
4 * n
18
17
e
registers restored
Ý
of general
EXIT
EXTi
n
a
n
5 * n
1
1
1
1
Ð
Ð
Ð
Ð
1
1
1
Ð
Ð
field in memory
field in register
Ð
1197 x 5219
x
EXTSi
FFSi
1
1
1
1
Ð
2
Ð
Ð
1
1
1
Ð
26
x
x
36
Ð
24
24
28
FLAG
Ð
Ð
Ð
Ð
Ð
Ð
Ð
4
Ð
3
Ð
Ð
Ð
Ð
6
no trap
trap
44
k
k
l
xM
l
xR
IBITi
1
1
1
2
Ð
Ð
Ð
Ð
1
Ð
Ð
17
9
Ð
Ð
Ð
74
Appendix B: Instruction Execution Times (Continued)
TABLE B-1. Basic Instructions (Continued)
Ý
Ý
Ý
Ý
Ý
Ý
Ý
L
Mnemonic
INDEXi
INSi
TEA1
TEA2
TOPB
TOPW
TOPD
TOPi
TCY
Notes
1
1
Ð
Ð
Ð
2
16
25
1
1
1
Ð
Ð
Ð
Ð
2
1
1
Ð
Ð
x
field in memory
field in register
Ð
Ð
2298 x 9369
39 x 49
INSSi
JSR
1
1
1
1
1
1
1
1
Ð
Ð
Ð
1
Ð
Ð
Ð
Ð
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
1
1
Ð
Ð
Ð
Ð
Ð
16
16
1
5%15
JUMP
LPRi
LSHi
MEIi
Ð
Ð
Ð
Ð
Ð
Ð
1
2%6
19
x
x
23
33
2
14
45
1
Ð
Ð
4
MODi
MOVi
1
3
54
x
1
3
3
73
k
k
k
l
xM
l
MR
l
RR
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
e
in block
Ý
of elements
MOVMi
n
a
1
1
Ð
Ð
Ð
2 * n
Ð
3 * n
20
k
k
l
M
l
R
MOVQi
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
Ð
Ð
2
Ð
Ð
3
e
no options
Ý
elements
MOVSB, W
n
a
a
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2 * n
2 * n
Ð
Ð
14 * n
24 * n
59
54
B, W and/or U
option in effect
e
no options
Ý
of elements
MOVSD
n
a
a
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2 * n
2 * n
Ð
Ð
10 * n
24 * n
59
54
B, W and/or U
option in effect
a
MOVST
MOVXBD
MOVXBW
MOVXWD
MOVZBD
MOVZBW
MOVZWD
MULi
Ð
1
Ð
1
n
1
Ð
Ð
1
Ð
1
2 * n
Ð
Ð
Ð
Ð
Ð
Ð
3
Ð
Ð
Ð
Ð
Ð
Ð
Ð
16
Ð
Ð
Ð
27 * n
54
Translated
6
1
1
1
Ð
1
6
6
5
5
5
1
1
Ð
1
1
1
1
Ð
1
1
1
1
1
Ð
1
1
1
Ð
Ð
Ð
Ð
Ð
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
15
5
NEGi
1
1
2
NOP
Ð
1
Ð
1
Ð
2
3
NOTi
5
k
k
k
l
xM
l
MR
l
RR
ORi
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
3
4
4
Ð
Ð
Ð
Ð
QUOi
1
1
Ð
Ð
Ð
3
16
49
x
55
75
Appendix B: Instruction Execution Times (Continued)
TABLE B-1. Basic Instructions (Continued)
Ý
Ý
Ý
Ý
Ý
Ý
Ý
L
Mnemonic
REMi
TEA1
TEA2
TOPB
TOPW
TOPD
TOPi
TCY
Notes
1
1
Ð
Ð
Ð
3
16
Ð
Ð
57
x
62
12
e
registers restored
Ý
RESTORE
n
of general
a
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
n
1
Ð
Ð
5 * n
RET
2%8
RETI
Ð
Ð
Ð
Ð
1
2
2
2
2
3
Ð
Ð
Ð
Ð
60
60
Non-Cascaded
Cascaded
RETT
ROTi
Ð
1
Ð
1
Ð
1
2
2
Ð
2
Ð
Ð
45
Ð
Ð
14
x
9
45
13
Scondi
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
1
1
Ð
Ð
False
True
10
e
registers saved
Ý
SAVE
SBITi
n
of general
a
Ð
Ð
Ð
Ð
n
Ð
Ð
4 * n
k
k
l
xM
1
1
1
2
Ð
Ð
Ð
Ð
1
1
Ð
Ð
15
l
Ð
Ð
7
xR
SETCFG
SKPSi
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
n
Ð
Ð
15
e
not Translated
Ý
n
of elements,
a
27 * n
30 * n
51
a
SKPST
SPRi
Ð
1
Ð
Ð
n
Ð
Ð
Ð
Ð
n
1
Ð
Ð
51
Translated
Ð
21
x
3
4
4
27
k
k
k
l
xM
l
MR
l
RR
SUBi
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
k
k
k
l
xM
l
MR
l
RR
SUBCi
SUBPi
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
3
4
4
Ð
Ð
Ð
Ð
1
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
3
3
Ð
Ð
16
18
no carry
carry
SVC
TBIti
Ð
Ð
Ð
2
4
Ð
Ð
40
k
k
l
xM
1
1
1
1
Ð
Ð
Ð
Ð
1
1
Ð
Ð
14
4
l
Ð
Ð
xR
e
interrupt/reset
WAIT
XORi
?
until an
Ð
Ð
Ð
Ð
Ð
Ð
Ð
6
x
?
k
k
k
l
xM
l
MR
l
RR
1
1
1
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
3
1
Ð
Ð
Ð
3
4
4
Ð
Ð
Ð
Ð
76
Appendix B: Instruction Execution Times (Continued)
B.2 SPECIAL GRAPHICS INSTRUCTIONS
Twaitrdd The number of wait states applied for a Read
operation on destination data.
This section provides the execution times for the special
graphics instructions. Table B-2 lists the average instruction
execution times for different shift values and for a no-wait-
state system design. The ‘‘No Option’’ of each instruction is
used. The effect of wait states on the execution time is rath-
er difficult to evaluate due to the pipelined nature of the read
and write operations.
Twaitwrd The number of wait states applied for a Write op-
eration on destination data.
a
value used for BITBLT timing.
a
Twaitwrd * 2, the
Twaitbt Twaitrds
Twaitrdd * 2
width
height
shift
The width of a BITBLT operation, in words.
The height of a BITBLT operation, in scan lines.
The number of bits of shift applied.
Instructions that have shift amounts, such as BBOR,
BBXOR, BBAND, BBFOR and BITWT, make use of the par-
allel nature of the Series 32000 /EP processors by doing
É
B.2.1 Execution Time Calculation for Special Graphics
Instructions
the actual shift during the reading of the double-word desti-
nation data. This means that if there are wait states on read
operations, these instructions are able to shift further, with-
out impacting the overall execution time. For example, the
total execution time for a BBFOR operation, shifting 8 bits,
with 2 wait states on read operations, is the same as for a
BBFOR operation shifting by 12 bits. This is because a des-
tination read takes 4 clock cycles longer than a no-wait-
state double-word read does. Note that this effect is not
valid for more than 4 wait states because at 4 wait states, all
possible shift values (0–15) are ‘‘hidden’’ during the desti-
nation read.
The execution time for a special graphics instruction is ob-
tained by inserting the appropriate parameters to the equa-
tion for that instruction and evaluating it.
For example, to calculate the execution time of the BBOR
instruction applied to a 10-word wide and 5-line high data
block, assuming a shift count of 15 and a no-wait-state sys-
tem, the following equation from Table B-2 is used.
a
a
b
a b
((shift 8) *
42
(107
44 * (width 2)) * height
width * height)
Substituting the appropriate values to the shift, width and
height parameters yields:
Table B-3 shows the average execution times with wait
states, assuming a shift value of eight unless stated other-
wise. The parameters used in the execution time equations
are defined below.
a
a
b
a
b
((15
45
(107
44 * (10
2)) * 50
8) * 10 * 50)
e
26,492 clocks
or
a
a
a
42
(107
352) * 50
(7 * 500)
Twaitrd The number of wait states applied for a Read
operation.
This represents the ‘‘worst case’’ time for this instruction,
since a shift of greater than 15 bits can be handled by mov-
ing the source and destination pointers by 2 bytes and ad-
justing the shift amount.
Twaitr
The number of wait states applied for a Write op-
eration.
Twaitrds The number of wait states applied for a Read
operation on source data. This also refers to the
number of wait states applied for a table memory
access (in the SBITS instruction, for example).
The ‘‘best case’’ and ‘‘average case’’ times for most in-
structions are the same, due to reading the destination data
during the shifting of the source data.
TABLE B-2. Average Instruction Execution Times with No Wait-States
Number of Clock Cycles
Instruction
Notes
a
a
a
a
b
b
b
e
l
BBOR
42
42
a
(107
(107
44 * (width
44 * (width
2)) *height
2)) *height
Shift
Shift
0
8
x
8
8
8
((shift 8) *width *height )
a
a
a
a
b
b
b
e
l
BBXOR
BBAND
BBFOR
44
44
a
(107
(107
44 * (width
44 * (width
2)) *height
2)) *height
Shift
Shift
0
8
x
x
((shift 8) *width *height )
a
a
a
a
b
b
b
e
l
45
45
a
(111
(111
44 * (width
44 * (width
2)) *height
2)) *height
Shift
Shift
0
8
((shift 8) *width *height )
a
a
a
a
a
a
b
b
b
e
e
l
48
48
48
(61
(74
(74
25 * (width
32 * (width
32 * (width
2)) *height
2)) *height
2))*height
Shift
Shift
Shift
1
0 x
8
8
a
8
b
((shift 8) *width *height )
a
a
a
a
b
b
b
e
l
BBSTOD
66
66
a
(170
(170
60 * (width
60 * (width
2)) *height
2)) *height
Shift
Shift
0
8
x
((shift 8) *width *height )
77
Appendix B: Instruction Execution Times (Continued)
TABLE B-2. Average Instruction Execution Times with No Wait-States (Continued)
Instruction
Number of Clock Cycles
Notes
e
e
l
BITWT
16
28
Shift
Shift
Shift
1
0 x
8
a
a
a
b
8)
28
16
16
(shift
8
MOVMPB,W
MOVMPD,W
SBITS
7 * R2
8 * R2
s
R2 25
l
R2 25
39
42
a
(34 * R2)
SBITP
8
TABLE B-3. Average Instruction Execution Times with Wait-States
Number of Clock Cycles
Instruction
Notes
a
a
a
a
a
a
a
a
a
a
a
a
a
a
b
b
b
BBOR
42
44
45
48
66
((107
((107
((111
2 * Twaitblt)
2 * Twaitblt)
2 * Twaitblt)
(44
(44
(44
Twaitblt) * (width
Twaitblt) * (width
Twaitblt) * (width
2)) *height
2)) *height
2)) *height
BBXOR
BBAND
BBFOR
BBSTOD
BITWIT
a
a
a
b
Twaitblt) * (width 2)) *height
((74
2 * Twaitblt)
(32
a
a
a
a
b
Twaitblt) * (width 2)) *height
((170
2 * Twaitblt)
(60
Twaitwrd
a
a
a
e
e
16
28
Twaitrds
Twaitblt
Twaitrdd
Shift
Shift
1
0 x
8
l
a
a
a
b
MOVMPB,W
16
16
7 * R2
7 * R2
(Twaitwr 1) * R2
a
Twaitwr * R2
Twaitwr
Twaitwr
1
s
1
a
MOVMPD
SBITS
16
8 * R2
s
a
a
a
a
a
2 * Twaitrds)
39
42
(2 * Twaitrdd
(2 * Twaitrdd
2 * Twaitwrd
2 * Twaitrds)
R2 25
l
R2 25
a
a
a
((Twaitrdd Twaitwrd) * R2)
SBITP
8
(34 * R2)
78
Appendix B: Instruction Execution Times (Continued)
B3. COMMAND LIST OPERATIONS
Load Register Instructions
External Memory Move Instructions
e
Assuming EXT.HOLD
0:
Instruction
Cycles
Instruction
Cycles
a
a
a
a
a
a
a
a
a
VXLOAD
(5
W
W
W
k) *leng
k) *leng
k) *leng
2
2
2
LX
3
3
3
3
5
3
3
3
VXSTORE (5
VXGATH (5
LY
LZ
LA
Where:
LEA
e
e
w
Number of wait states in external memory access.
Number of cycles until HLDA is received, in external
LPARAM
LREPEAT
LEABR
k
memory instructions.
Arithmetic/Logic Instructions
Store Register Instructions
Instruction
Instruction
Cycles
Cycles
a
a
VROP
3 *leng
3 *leng
2
4
VAROP
SX
3
3
4
3
3
3
3
3
3
SXL
SXH
SY
Multiply-and-Accumulate Instructions
Instruction
Cycles
SZ
a
a
a
a
VRMAC
VARMAC
VCMAC
VRLATP
2 *leng
2 *leng
4 *leng
4 *leng
7
7
6
5
SA
SEA
SREPEAT
SOVF
Multiply-and-Add Instructions
Instruction
Adjust Register Instructions
Instruction
Cycles
Cycles
a
a
a
a
VAIMAD
VRMAD
VARMAD
VCMAD
6 *leng
4 *leng
4 *leng
4 *leng
2
3
4
6
INCX
INCY
INCZ
DECX
DECY
DECZ
4
4
4
4
4
4
Clipping and Min/Max Instructions
Instruction
Cycles
Flow Control Instructions
Instruction
a
a
a
a
VARABS
VARMIN
VARMAX
VRFMAX
EFMAX
2 *leng
7 *leng
7 *leng
4 *leng
17
5
2
2
6
Cycles
NOPR
HALT
DJNZ
DBPT
2
1
5
3
Special Instructions
Internal Memory Move Instructions
Instruction
Cycles
a
a
a
ESHL
1 *leng
4 *leng
16 *leng
5
15
6
Instruction
Cycles
VCPOLY
VESIIR
a
VRMOV
2 *leng
2 *leng
4 *leng
4 *leng
2
2
4
4
a
a
a
VARMOV
VRGATH
VRSCAT
e
If leng
0 in ESHL instruction, then the timing is 4 cycles.
79
Physical Dimensions inches (millimeters)
68-Pin Plastic Leaded Chip Carrier (V)
Order Number NS32AM162V-20 or NS32AM163V-20
NS Package Number V68A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
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to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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