NS41024L25E-SMD [NSC]
NS41024L25E-SMD;
| 型号： | NS41024L25E-SMD |
| 厂家： | 
National Semiconductor |
| 描述： | NS41024L25E-SMD 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICROCIRCUIT DATA SHEET
Original Creation Date: 11/28/95
Last Update Date: 12/20/96
MDNS41024L25-X REV 0B0
Last Major Revision Date: 11/28/95
1 Megabit Static RAM (128K x 8 bit)
General Description
NS41024L25 is a high performance, low power version CMOS static RAM organized as 131,072 X
8 bits with 25nS address to access time. The NS41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL compatible.
Industry Part Number
NS Part Numbers
NS41024L25
NS41024L25E-SMD
Prime Die
PDM41024W
Controlling Document
5962-8959820MMA
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
1
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
Features
Truth Table:
OE
X
WE
X
CE1
H
*CE2
I/O
MODE
STANDBY
STANDBY
READ
X
L
H
H
H
HI-Z
HI-Z
DOUT
DIN
X
X
X
L
H
L
X
L
L
WRITE
H
H
L
HI-Z
READ
Note: H = Logic "1" state, L = Logic "0" state.
X = Logic "Don't care" state, and Z = high impedance state.
* = only applies to devices with dual CE.
Applications
Graphic Notes: * = This note does not apply for this device.
*1. The parameter is tested with CL = 5pF as shown in Fig. 2. Transition is
measured +200mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
*3. This parameter is sampled.
4. WE is high for a READ cycle. Applies to READ cycle 1 & 2.
5. The device is continously selected. All the Chip Enables are held in their
active state. Applies to READ cycle 1.
6. The address is valid prior to or coincident with the latest occuring Chip
Enable. Applies to READ cycle 2.
*7. Vcc = 5V +10%.
2
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
(Absolute Maximum Ratings)
(Note 1, 2)
Supply Voltage Range (VCC)
-0.5Vdc to +7.0Vdc
DC Input Voltage Range (VIN)
(Note 3)
-0.5Vdc to Vcc +0.5Vdc
DC Output Voltage Range (VOUT)
(Note 3)
-0.5Vdc to Vcc +0.5Vdc
-65 C to +150 C
1.0W
Storage Temperature Range
Maximum Power Dissipation (PD)
Lead Temperature
(Soldering, 10 seconds)
+260 C
Thermal Resistance, Junction to Case (ThetaJC)
Case M
See MIL-STD-1835
-0.5Vdc to Vcc +0.5Vdc
Output Voltage Applied in High Z State
Maximum Junction Temperature (TJ)
(Note 4)
+150 C
Note 1: Stresses above the absolute maximum rating may cause permanent damage to the device.
Extended operation at the maximum levels may degrade performance and affect
reliability.
Note 2: All voltages referenced to VSS (VSS = ground) unless otherwise specified.
Note 3: Negative undershoots to a minimum of -3.0V are allowed with a maximum of 20nS pulse
width.
Note 4: Maximum junction temperature may be increased to +175 C during burn-in and
steady-state life.
Recommended Operating Conditions
Supply Voltage Range (VCC)
Supply Voltage Range (VSS)
High Level Input Voltage Range (VIH)
Low Level Input Voltage Range (VIL)
Case Operating Temperature Range (TC)
3
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
Electrical Characteristics
DC PARAMETERS: ELECTRICAL CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
PIN-
NAME
SUB-
SYMBOL
Iih
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
High Level Input Vcc = 5.5V, Vin = 5.5V
Current
10
uA
uA
uA
1, 2,
3
Iil
Low Level Input
Current
Vcc = 5.5V, Vin = 0.0V
-10
1, 2,
3
Iozh
High Impedance
Output Leakage
Current
Vcc=5.5V, Vo=5.5V, Vil=0.0V,
Vih=5.0V, Vih<OE<Vcc
10
1, 2,
3
Iozl
Low Impedance
Output Leakage
Current
Vcc=5.5V, Vo=0.0V, Vil=0.0V,
Vih=5.0V, Vih<OE<Vcc
-10
2.4
uA
1, 2,
3
Voh
Vol
Output High
Voltage
Ioh=-4.0mA, Vcc=4.5V, Vih=2.2V,
Vil=0.8V
V
V
1, 2,
3
Output Low
Voltage
Iol=8.0mA, Vcc=4.5V, Vih=2.2V,
Vil=0.8V
0.4
1, 2,
3
DC PARAMETERS: Maximum Operating Conditions
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
Icc1
Operating Supply Vcc=5.5V, CE=Vil(max), OE, WE, and
130
mA
mA
mA
1, 2,
3
Current
CE2=Vih, f=1/tAVAV(min)
Icc2
Icc3
Standby Supply
Current TTL
Vcc=5.5V, CE=Vih, CE2=Vil, f=0 HZ
25
10
1, 2,
3
Standby Supply
Current CMOS
Vcc=5.5V, CE>Vcc -0.2V,
Inputs=Vih or Vil, f=0
1, 2,
3
AC PARAMETERS: Capacitance
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
Cin
Input Capacitance Vin=0V, f=1.0 MHz, Tc=+25 C
(A0-A16)
1, 6
1, 6
1, 6
12.0
20.0
14.0
pF
pF
pF
4
4
4
Cclk
Cout
Input Capacitance Vin=0V, f=1.0 MHz, Tc=+25 C
(CE, WE, OE)
Output
Capacitance
Vout=0V, f=1.0 MHz, Tc=+25 C
AC PARAMETERS: ELECTRICAL CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
Functional Tests
2, 7
7, 8A,
8B
tAVAV
Read Cycle Time
3,
4, 8
25
nS
9, 10,
11
4
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
Electrical Characteristics
AC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
PIN-
NAME
SUB-
SYMBOL
tAVQV
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Address Access
Time
3,
4, 8
25
nS
nS
nS
ns
nS
9, 10,
11
tELQV
tOLQV
tAVQX
tELQX
Chip Enable
Access Time
3,
4, 8
25
10
9, 10,
11
Output Enable to
Output Valid
3,
4, 8
9, 10,
11
Output Hold after
Address Change
3,
4, 8
3
3
9, 10,
11
Chip Enable to
Output in Low Z
1,
9, 10,
11
3,
4,
5, 8
tEHQZ
tOLQX
tOHQZ
tAVAV
Chip Disable to
Output in High Z
1,
10
10
nS
nS
nS
9, 10,
11
3,
4,
5, 8
Output Enable to
Output in Low Z
1,
0
9, 10,
11
3,
4,
5, 8
Output Disable to
Output in High Z
1,
9, 10,
11
3,
4,
5, 8
Write Cycle Time
3,
4, 8
25
0
nS
nS
9, 10,
11
tAVWL/
tAVEL
Address Setup to
beginning of
Write
3,
4, 8
9, 10,
11
tWHDX/
tEHDX
Data Hold after
end of Write
3,
0
nS
nS
nS
nS
nS
9, 10,
11
4, 8
tWLWH
tAVWH
tELWH
Write Pulse Width
3,
4, 8
20
20
20
0
9, 10,
11
Address Setup to
end of Write
3,
4, 8
9, 10,
11
Chip Select to
end of Write
3,
4, 8
9, 10,
11
tWHAX/
tEHAX
Address Hold
after end of
Write
3,
4, 8
9, 10,
11
tDVWH/
tDVEH
Data Setup to end
of Write
3,
4, 8
15
nS
9, 10,
11
5
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
Electrical Characteristics
AC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
PIN-
NAME
SUB-
SYMBOL
tWLQZ
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Write Enable to
Output Disable
1,
10
nS
9, 10,
11
3,
4,
5, 8
tWHQX
Output Active
after end of
Write
1,
5
nS
9, 10,
11
3,
4,
5, 8
Data Retention Electrical Characteristics: DC
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
Icc4
Data Retention
Current
Vcc=2.0V, f=0, CE>Vcc -0.2V,
all other inputs=0.2V or Vcc -0.2V
1
mA
1, 2,
3
Data Retention Electrical Characteristics: AC
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V
tCDR
tR
Retention Time
1,
0
nS
nS
9, 10,
11
3,
4, 8
Operation
Recovery Time
1,
25
9, 10,
11
3,
4, 8
Note 1: This parameter is tested initially and after any design or process change which could
affect this parameter, and therefore shall be guaranteed to the limits specified in
table 1.
Note 2: Functional tests shall include the test table and other test patterns used for fault
detection as approved by the qualifying activity. Outputs are measured at Vol < 1.5V,
Voh > 1.5V.
Note 3: For timing waveforms see Figure 4 and for output load circuits, see figure 5.
Note 4: AC measurements assume transition time < 5nS, input levels are from ground to 3.0V,
and output load Cl > 30pF except as noted on figure 5. Timing reference Levels are
1.5V.
Note 5: Transition is measured +500 mV from steady state voltage.
Note 6: Subgroup 4 (Cin and Cout measurements) shall be measured only for initial
qualification and after any process or design changes which may affect input or
output capacitance. Capacitance shall be measured between the designated terminal and
Gnd at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all
input and output terminals tested.
Note 7: For device class M subgroups 7 and 8 tests shall be sufficient to verify the truth
table. For device classed B and S subgroups 7 and 8 tests shall be sufficient to
verify the truth table as approved by the qualifying activity. For device classes Q
and V subgroups 7 and 8 shall include verifying the functionality of the device;
these tests shall have been fault graded in accordance with MIL-STD-883, test method
5012.
Note 8: See figure 4, as applicable.
6
MICROCIRCUIT DATA SHEET
MDNS41024L25-X REV 0B0
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
AN00010A
AN00016A
AN00017A
AN00020A
AN00021A
AN00024A
AN00026A
AN00028A
P000139A
BLOCK DIAGRAM - NS41024, NS4A024, NS4R024
FIGURE 1 - OUTPUT LOAD EQUIVALENT
FIGURE 2 - OUTPUT LOAD EQUIVALENT
READ CYCLE 1 (APPLICATION NOTES)
READ CYCLE 2 (APPLICATION NOTES)
WRITE CYCLE 1 - WRITE ENABLE CONTROLLED
WRITE CYCLE 2 - CHIP ENABLE CONTROLLED
LOW VCC DATA RETENTION WAVEFORM
CERQUAD LCC (E), 32 LEAD (PIN OUT)
See attached graphics following this page.
7
AN00010A
Functional Block Diagram
A0
Decoder
Memory
Matrix
•
•
•
•
•
•
•
•
•
Addresses
•
•
A16
•
• • • •
I/O0
Input
Column I/O
Data
Control
•
•
I/O7
•
•
•
CE1
CE2
WE
OE
Control
NS41024,NS4A024,NS4R024
AN00016A
Output Load Equivalent
+5V
480Ω
D
OUT
255Ω
30 pF
FIG. 1
AN00017A
FIG. 2
Output Load Equivalent
(for tLZCE, tHZWE, tLZWE, tHZWE, tLZOE, tHZOE)
+5V
480Ω
D
OUT
255Ω
5 pF
NS41024
NS41096
NS41256
NS4A024
NS4A028
NS4M096
NS4R024
AN00020A
Read Cycle #1
Notes : 4,5,6 apply
t
RC
ADDR
t
AA
t
OH
D
DATA VALID
PREVIOUS DATA VALID
OUT
NS41024
NS41096
NS41256
NS41257
NS41258
NS4A024
NS4A028
NS4M096
NS4R024
AN00021A
Read Cycle #2
Notes : 1,2,3,4,5,6 apply
t
RC
CE1
CE2
OE
t
t
HZCE
ACE
t
HZOE
t
AOE
t
LZOE
D
HIGH Z
DATA VALID
OUT
t
LZCE
NS41024
NS4A024
NS4R024
AN00024A
Write Cycle #1 (write enable controlled)
t
WC
ADDR
CE2
t
AW
t
t
AH
CW
CE1
WE
t
t
AS
WP2
t
t
DH
DS
D
IN
DATA VALID
t
t
HZWE
LZWE
HIGH Z
D
OUT
NS41024
NS4A024
NS4R024
AN00026A
Write Cycle #2 (chip enable controlled)
t
WC
ADDR
t
AW
t
t
t
AH
AS
CW
CE2
CE1
t
WP1
UNDEFINED
DON'T CARE
WE
t
t
DS
DATA VALID
DH
D
IN
D
OUT
High Z
NS41024
NS4A024
NS4R024
AN00028A
Low Vcc Data Retention Waveform
Data Retention Mode
V
4.5V
4.5V
CC
V
DR
t
t
CDR
R
V
V
DR
IH
CE1
V
IL
DON'T CARE
V
IH
≤ 0.2V
V
IL
CE2
NS41024
NS4A024
NS4R024
P000139A
Pin Configuration
CERQUAD LCC (E)
32LD (pinout)
NS41024
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