NSC800E-3M [NSC]
IC 8-BIT, 2.5 MHz, MICROPROCESSOR, CQCC44, CERAMIC, LCC-44, Microprocessor;
| 型号： | NSC800E-3M |
| 厂家： | 
National Semiconductor |
| 描述： | IC 8-BIT, 2.5 MHz, MICROPROCESSOR, CQCC44, CERAMIC, LCC-44, Microprocessor 时钟 外围集成电路 装置 |
| 文件： | 总76页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1992
NSC800TM High-Performance
Low-Power CMOS Microprocessor
General Description
Features
Y
Fully compatible with Z80 instruction set:
É
The NSC800 is an 8-bit CMOS microprocessor that func-
tions as the central processing unit (CPU) in National Semi-
conductor’s NSC800 microcomputer family. National’s
microCMOS technology used to fabricate this device pro-
vides system designers with performance equivalent to
comparable NMOS products, but with the low power advan-
tage of CMOS. Some of the many system functions incorpo-
rated on the device, are vectored priority interrupts, refresh
control, power-save feature and interrupt acknowledge. The
NSC800 is available in dual-in-line and surface mounted
chip carrier packages.
Powerful set of 158 instructions
10 addressing modes
22 internal registers
Y
Y
Y
Y
Y
Y
Y
Y
Low power: 50 mW at 5V V
Unique power-save feature
Multiplexed bus structure
CC
Schmitt trigger input on reset
On-chip bus controller and clock generator
b
Variable power supply 2.4V 6.0V
On-chip 8-bit dynamic RAM refresh circuitry
The system designer can choose not only from the dedicat-
ed CMOS peripherals that allow direct interfacing to the
NSC800 but from the full line of National’s CMOS products
to allow a low-power system solution. The dedicated periph-
erals include NSC810A RAM I/O Timer, NSC858 UART,
and NSC831 I/O.
Speed: 1.0 ms instruction cycle at 4.0 MHz
NSC800-4 4.0 MHz
NSC800-35 3.5 MHz
NSC800-3
NSC800-1
2.5 MHz
1.0 MHz
Y
Y
Capable of addressing 64k bytes of memory and 256
I/O devices
All devices are available in commercial, industrial and mili-
tary temperature ranges along with two added reliability
flows. The first is an extended burn in test and the second is
the military class C screening in accordance with Method
5004 of MIL-STD-883.
Five interrupt request lines on-chip
Block Diagram
TL/C/5171–73
NSC800TM is a trademark of National Semiconductor Corp.
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Z80É is a registered trademark of Zilog Corp.
C
1995 National Semiconductor Corporation
TL/C/5171
RRD-B30M105/Printed in U. S. A.
Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS
2.0 OPERATING CONDITIONS
9.0 TIMING AND CONTROL
9.5 Bus Access Control
9.6 Interrupt Control
3.0 DC ELECTRICAL CHARACTERISTICS
4.0 AC ELECTRICAL CHARACTERISTICS
NSC800 SOFTWARE
5.0 TIMING WAVEFORMS
NSC800 HARDWARE
10.0 INTRODUCTION
11.0 ADDRESSING MODES
6.0 PIN DESCRIPTIONS
11.1 Register
6.1 Input Signals
11.2 Implied
6.2 Output Signals
6.3 Input/Output Signals
11.3 Immediate
11.4 Immediate Extended
11.5 Direct Addressing
11.6 Register Indirect
11.7 Indexed
7.0 CONNECTION DIAGRAMS
8.0 FUNCTIONAL DESCRIPTION
8.1 Register Array
11.8 Relative
8.2 Dedicated Registers
8.2.1 Program Counter
8.2.2 Stack Pointer
11.9 Modified Page Zero
11.10 Bit
12.0 INSTRUCTION SET
8.2.3 Index Register
8.2.4 Interrupt Register
8.2.5 Refresh Register
12.1 Instruction Set Index/Alphabetical
12.2 Instruction Set Mnemonic Notation
12.3 Assembled Object Code Notation
12.4 8-Bit Loads
8.3 CPU Working and Alternate Register Sets
8.3.1 CPU Working Registers
12.5 16-Bit Loads
8.3.2 Alternate Registers
12.6 8-Bit Arithmetic
8.4 Register Functions
8.4.1 Accumulator
12.7 16-Bit Arithmetic
12.8 Bit Set, Reset, and Test
12.9 Rotate and Shift
8.4.2 F RegisterÐFlags
8.4.3 Carry (C)
12.10 Exchanges
8.4.4 Adds/Subtract (N)
8.4.5 Parity/Overflow (P/V)
8.4.6 Half Carry (H)
12.11 Memory Block Moves and Searches
12.12 Input/Output
12.13 CPU Control
8.4.7 Zero Flag (Z)
12.14 Program Control
8.4.8 Sign Flag (S)
12.15 Instruction Set: Alphabetical Order
12.16 Instruction Set: Numerical Order
8.4.9 Additional General Purpose Registers
8.4.10 Alternate Configurations
13.0 DATA ACQUISITION SYSTEM
8.5 Arithmetic Logic Unit (ALU)
8.6 Instruction Register and Decoder
14.0 NSC800M/883B MIL STD 883/CLASS C
SCREENING
9.0 TIMING AND CONTROL
15.0 BURN-IN CIRCUITS
9.1 Internal Clock Generator
9.2 CPU Timing
16.0 ORDERING INFORMATION
17.0 RELIABILITY INFORMATION
9.3 Initialization
9.4 Power Save Feature
2
1.0 Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
2.0 Operating Conditions
e a
0 C to 70 C
NSC800-1
x
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
§
§
e b
e
a
40 C to 85 C
§
§
a
NSC800-3
x
0 C to 70 C
§
§
b
a
65 C to 150 C
Storage Temperature
§
§
e b
a
40 C to 85 C
§
§
§
55 C to 125 C
Voltage on Any Pin
with Respect to Ground
e b
e b
e
a
§
§
b
a
0.3V to V
CC
0.3V
7V
a
55 C to 125 C
§
NSC800-35/883C
NSC800-4
x
x
Maximum V
CC
a
0 C to 70 C
§
§
Power Dissipation
1W
e b
a
40 C to 85 C
§
§
§
Lead Temp. (Soldering, 10 seconds)
300 C
§
e b a
55 C to 90 C
NSC800-4MIL
x
§
e
e
0V, unless otherwise specified.
g
5V 10%, GND
3.0 DC Electrical Characteristics V
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
V
V
V
V
V
V
Logical 1 Input Voltage
Logical 0 Input Voltage
Hysteresis at RESET IN input
Logical 1 Output Voltage
Logical 1 Output Voltage
Logical 0 Output Voltage
Logical 0 Output Voltage
Input Leakage Current
Output Leakage Current
Active Supply Current
Active Supply Current
Active Supply Current
0.8 V
0
V
CC
IH
CC
0.2 V
V
IL
CC
e
V
5V
0.25
2.4
0.5
V
HY
CC
e b
e b
I
I
I
I
1.0 mA
V
OH1
OH2
OL1
OL2
OUT
OUT
OUT
b
10 mA
V
0.5
V
CC
e
e
2 mA
0
0.4
0.1
V
10 mA
0
V
OUT
s
s
b
b
I
I
I
I
I
0
0
I
V
V
CC
V
CC
10.0
10.0
10.0
10.0
11
mA
mA
mA
mA
IL
IN
IN
s
s
V
OL
CC
CC
CC
e
e
e
e
e
e
0, f
0, f
0, f
2 MHz, T
5 MHz, T
7 MHz,
25 C
8
§
25 C
OUT
OUT
OUT
(XIN)
(XIN)
(XIN)
A
e
e
I
10
15
§
A
I
15
15
2
21
21
5
mA
mA
mA
e
T
A
25 C
§
0, f
e
e
e
I
I
Active Supply Current
Quiescent Current
I
8 MHz, T
25 C
§
CC
Q
OUT
(XIN)
A
e
e
e
0 MHz, T
e
25 C, X
§
e
V
IN
I
0, PS
0, V
IN
0 or V
OUT
CC
e
e
e
0, CLK 1
f
(XIN)
A
IN
e
e
e
5.0 MHz , T
e
e
V
IN
I
Power-Save Current
I
0, PS
0, V
IN
0 or V
PS
OUT
CC
5
7
mA
e
f
25
§
(XIN)
A
C
C
Input Capacitance
6
8
5
10
12
6
pF
pF
V
IN
Output Capacitance
Power Supply Voltage
OUT
V
CC
(Note 2)
2.4
Note 1: Absolute Maximum Ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified under DC Electrical Characteristics.
g
Note 2: CPU operation at lower voltages will reduce the maximum operating speed. Operation at voltages other than 5V 10% is guaranteed by design, not
tested.
3
e
e
0V, unless otherwise specified
g
5V 10%, GND
4.0 AC Electrical Characteristics V
CC
NSC800-1 NSC800-3
Min Max Min Max
NSC800-35
NSC800-4
Symbol
Parameter
Units
Notes
Min
Max Min Max
t
Period at XIN and XOUT 500 3333 200 3333 142
Pins
3333 125 3333
ns
X
T
Period at Clock Output
e
1000 6667 400 6667 284
6667 250 6667
ns
ns
ns
ns
ns
(
2 t )
X
t
t
t
t
Clock Rise Time
Clock Fall Time
Clock Low Time
Clock High Time
110
70
110
60
90
55
80
50
Measured from
R
F
L
10%–90% of signal
Measured from
10%–90% of signal
435
450
150
145
90
85
80
75
50% duty cycle, square
wave input on XIN
50% duty cycle, square
wave input on XIN
H
t
t
t
ALE to Valid Data
ALE to Valid Data
1340
1875
0
490
620
0
340
405
0
300
360
0
ns
ns
ns
Add t for each WAIT STATE
Add t for each WAIT STATE
ACC(OP)
ACC(MR)
AD(0–7) Float after
RD Falling
AFR
t
t
t
BACK Rising to Bus
Enable
1000
50
400
50
300
50
250
50
ns
ns
ns
BABE
BABF
BACL
BACK Falling to
Bus Float
BACK Fall to CLK
Falling
425
125
60
55
t
t
t
BREQ Hold Time
0
100
0
0
50
0
0
50
0
0
45
0
ns
ns
ns
BRH
BRS
CAF
BREQ Set-Up Time
Clock Falling ALE
Falling
70
100
100
80
65
100
90
60
90
90
70
55
80
80
65
t
t
t
t
t
t
t
t
t
Clock Rising to ALE
Rising
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAR
Clock Rising to
Read Rising
CRD
Clock Rising to
Refresh Falling
70
CRF
ALE Falling to INTA
Falling
445
160
95
85
DAI
ALE Falling to
RD Falling
400 575 160 250
900 1010 350 420
100
225
635
140
180
90 160
DAR
ALE Falling to
WR Falling
300 200 265
560
DAW
ALE Falling to BACK
Falling
2460
975
Add t for each WAIT state
D(BACK)1
D(BACK)2
D(I)
Add t for opcode fetch cycles
BREQ Rising to BACK
Rising
500 1610 200 700
540 125 475
ALE Falling to INTR,
NMI, RSTA-C, PS,
BREQ, Inputs Valid
1360
475
284
250
Add t for each WAIT state
Add t for opcode fetch cycles
t
t
Rising PS to
Falling ALE
500 1685 200 760
140
580 125 510
ns
ns
SeeFigure 14 also
DPA
ALE Falling to
550
250
170
125
D(WAIT)
WAIT Input Valid
OPÐ Opcode Fetch
MRÐ Memory Read
4
e
e
0V, unless otherwise specified (Continued)
g
5V 10%, GND
4.0 AC Electrical Characteristics V
CC
NSC800-1
NSC800-3
NSC800-35
NSC800-4
Symbol
Parameter
Units
Notes
Min Max Min Max Min
Max Min Max
T
A(8–15) Hold Time During
Opcode Fetch
0
0
0
0
ns
H(ADH)1
T
A(8–15) Hold Time During 400
Memory or IO, RD and WR
100
85
60
ns
H(ADH)2
T
T
AD(0–7) Hold Time
Write Data Hold Time
Interrupt Hold Time
Interrupt Set-Up Time
Width of NMI Input
Data Hold after Read
100
400
0
60
100
0
35
85
0
30
75
0
ns
ns
ns
ns
ns
ns
ns
H(ADL)
H(WD)
INH
t
t
t
t
t
100
50
0
50
30
0
50
25
0
45
20
0
INS
NMI
RDH
RFLF
RFSH Rising to ALE
Falling
60
50
45
40
t
RD Rising to ALE Rising
(Memory Read)
390
100
50
45
ns
RL(MR)
t
t
AD(0–7) Set-Up Time
300
350
45
70
45
55
40
50
ns
ns
S(AD)
A(8–15), SO, SI, IO/M
Set-Up Time
S(ALE)
t
t
t
t
Write Data Set-Up Time
ALE Width
385
430
0
75
130
0
35
115
0
30
100
0
ns
ns
ns
ns
S(WD)
W(ALE)
WH
WAIT Hold Time
Width of INTR, RSTA-C,
PS, BREQ
500
200
140
125
W(I)
t
INTA Strobe Width
1000
400
225
200
ns
Add two t states for first
INTA of each interrupt
response string Add t for
each WAIT state
W(INTA)
t
t
WR Rising to ALE Rising
450
130
360
70
70
ns
ns
WL
Read Strobe Width During 960
Opcode Fetch
210
185
Add t for each WAIT
State Add t/2 for Memory
Read Cycles
W(RD)
t
t
t
t
t
t
Refresh Strobe Width
WAIT Set-Up Time
WAIT Input Width
Write Strobe Width
XIN to Clock Falling
XIN to Clock Rising
1925
100
550
985
25
725
70
450
60
195
250
5
395
55
ns
ns
ns
ns
ns
ns
W(RFSH)
WS
250
370
15
175
220
W(WAIT)
W(WR)
XCF
Add t for each WAIT state
100
85
95
85
90
90
5
5
80
80
25
15
5
XCR
e
Note 1: Test conditions: t
1000 ns for NSC800-1, 400 ns for NSC800, 285 ns for NSC800-35, 250 ns for NSC800-4.
Note 2: Output timings are measured with a purely capacitive load of 100 pF.
5
5.0 Timing Waveforms
Opcode Fetch Cycle
TL/C/5171–3
Memory Read and Write Cycle
TL/C/5171–4
6
5.0 Timing Waveforms (Continued)
InterruptÐPower-Save Cycle
TL/C/5171–5
Note 1: This t state is the last t state of the last M cycle of any instruction.
Note 2: Response to INTR input.
Note 3: Response to PS input.
Bus Acknowledge Cycle
TL/C/5171–6
*Waveform not drawn to proportion. Use only for specifying test points.
AC Testing Input/Output Waveform
AC Testing Load Circuit
TL/C/5171–7
TL/C/5171–8
7
NSC800 HARDWARE
6.0 Pin Descriptions
6.1 INPUT SIGNALS
CPU stops executing at the end of current instruction and
keeps itself in the low-power mode. Normal operation re-
sumes when PS returns high (see Power Save Feature de-
scription).
Reset Input (RESET IN): Active low. Sets A (8–15) and AD
(0–7) to TRI-STATE (high impedance). Clears the con-
É
tents of PC, I and R registers, disables interrupts, and acti-
vates reset out.
CRYSTAL (X , X
IN
): X can be used as an external
OUT IN
clock input. A crystal can be connected across X and
IN
Bus Request (BREQ): Active low. Used when another de-
vice requests the system bus. The NSC800 recognizes
BREQ at the end of the current machine cycle, and sets
A(8–15), AD(0–7), IO/M, RD, and WR to the high imped-
ance state. RFSH is high during a bus request cycle. The
CPU acknowledges the bus request via the BACK output
signal.
X
to provide a source for the system clock.
OUT
6.2 OUTPUT SIGNALS
Bus Acknowledge (BACK): Active low. BACK indicates to
the bus requesting device that the CPU bus and its control
signals are in the TRI-STATE mode. The requesting device
then commands the bus and its control signals.
Non-Maskable Interrupt (NMI): Active low. The non-mask-
able interrupt, generated by the peripheral device(s), is the
highest priority interrupt. The edge sensitive interrupt re-
quires only a pulse to set an internal flip-flop which gener-
ates the internal interrupt request. The NMI flip-flop is moni-
tored on the same clock edge as the other interrupts. It
must also meet the minimum set-up time spec for the inter-
rupt to be accepted in the current machine instruction.
When the processor accepts the interrupt the flip-flop resets
automatically. Interrupt execution is independent of the in-
terrupt enable flip-flop. NMI execution results in saving the
PC on the stack and automatic branching to restart address
X’0066 in memory.
[
]
Address Bits 8–15 A(8–15) : Active high. These are the
most significant 8 bits of the memory address during a
memory instruction. During an I/O instruction, the port ad-
dress on the lower 8 address bits gets duplicated onto A(8–
15). During a BREQ/BACK cycle, the A(8–15) bus is in the
TRI-STATE mode.
Reset Out (RESET OUT): Active high. When RESET OUT
is high, it indicates the CPU is being reset. This signal is
normally used to reset the peripheral devices.
Input/Output/Memory (IO/M): An active high on the IO/M
output signifies that the current machine cycle is an input/
output cycle. An active low on the IO/M output signifies that
the current machine cycle is a memory cycle. It is TRI-
STATE during BREQ/BACK cycles.
Restart Interrupts, A, B, C (RSTA, RSTB, RSTC): Active
low level sensitive. The CPU recognizes restarts generated
by the peripherals at the end of the current instruction, if
their respective interrupt enable and master enable bits are
set. Execution is identical to NMI except the interrupts vec-
tor to the following restart addresses:
Refresh (RFSH): Active low. The refresh output indicates
that the dynamic RAM refresh cycle is in progress. RFSH
goes low during T3 and T4 states of all M1 cycles. During
the refresh cycle, AD(0–7) has the refresh address and
A(8–15) indicates the interrupt vector register data. RFSH is
high during BREQ/BACK cycles.
Restart
Name
Address (X’)
NMI
0066
003C
0034
002C
0038
Address Latch Enable (ALE): Active high. ALE is active
only during the T1 state of any M cycle and also T3 state of
the M1 cycle. The high to low transition of ALE indicates
that a valid memory, I/O or refresh address is available on
the AD(0–7) lines.
RSTA
RSTB
RSTC
INTR (Mode 1)
Read Strobe (RD): Active low. The CPU receives data via
the AD(0–7) lines on the trailing edge of the RD strobe. The
RD line is in the TRI-STATE mode during BREQ/BACK cy-
cles.
The order of priority is fixed. The list above starts with the
highest priority.
Interrupt Request (INTR): Active low, level sensitive. The
CPU recognizes an interrupt request at the end of the cur-
rent instruction provided that the interrupt enable and mas-
ter interrupt enable bits are set. INTR is the lowest priority
interrupt. Program control selects one of three response
modes which determines the method of servicing INTR in
conjunction with INTA. See Interrupt Control.
Write Strobe (WR): Active low. The CPU sends data via the
AD(0–7) lines while the WR strobe is low. The WR line is in
the TRI-STATE mode during BREQ/BACK cycles.
Clock (CLK): CLK is the output provided for use as a sys-
tem clock. The CLK output is a square wave at one half the
input frequency.
Wait (WAIT): Active low. When set low during RD, WR or
INTA machine cycles (during the WR machine cycle, wait
must be valid prior to write going active) the CPU extends its
machine cycle in increments of t (wait) states. The wait ma-
chine cycle continues until the WAIT input returns high.
Interrupt Acknowledge (INTA): Active low. This signal
strobes the interrupt response vector from the interrupting
peripheral devices onto the AD(0–7) lines. INTA is active
during the M1 cycle immediately following the t state where
the CPU recognized the INTR interrupt request.
The wait strobe input will be accepted only during machine
cycles that have RD, WR or INTA strobes and during the
machine cycle immediately after an interrupt has been ac-
cepted by the CPU. The later cycle has its RD strobe sup-
pressed but it will still accept the wait.
Two of the three interrupt request modes use INTA. In
mode 0 one to four INTA signals strobe a one to four byte
instruction onto the AD(0–7) lines. In mode 2 one INTA sig-
nal strobes the lower byte of an interrupt response vector
onto the bus. In mode 1, INTA is inactive and the CPU re-
sponse to INTR is the same as for an NMI or restart inter-
rupt.
Power-Save (PS): Active low. PS is sampled during the last
t state of the current instruction cycle. When PS is low, the
8
6.0 Pin Descriptions (Continued)
Status (SO, S1): Bus status outputs provide encoded infor-
mation regarding the current M cycle as follows:
6.3 INPUT/OUTPUT SIGNALS
[
]
Multiplexed Address/Data AD(0–7) : Active high
Status
S1
Control
RD WR
At RD Time:
At WR Time:
At Falling Edge Least significant byte of address
Input data to CPU.
Output data from CPU.
Machine Cycle
S0
IO/M
of ALE Time:
during memory reference cycle. 8-bit
port address during I/O reference
cycle.
Opcode Fetch
Memory Read
Memory Write
I/O Read
1
0
1
0
1
0
0
1
1
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
1
1
During BREQ/ High impedance.
BACK Cycle:
I/O Write
Halt*
Internal Operation*
Acknowledge of Int**
*ALE is not suppressed in this cycle.
**This is the cycle that occurs immediately after the CPU accepts an inter-
rupt (RSTA, RSTB, RSTC, INTR, NMI).
Note 1: During halt, CPU continues to do dummy opcode fetch from location
following the halt instruction with a halt status. This is so CPU can continue
to do its dynamic RAM refresh.
Note 2: No early status is provided for interrupt or hardware restarts.
7.0 Connection Diagrams
Dual-In-Line Package
Chip Carrier Package
Top View
TL/C/5171–11
Order Number NSC800E or V
See NS Package E44B or V44A
Top View
TL/C/5171–10
Order Number NSC800D or N
See NS Package D40C or N40A
9
8.0 Functional Description
This section reviews the CPU architecture shown below, fo-
cusing on the functional aspects from a hardware perspec-
tive, including timing details.
As illustrated in Figure 1, the NSC800 is an 8-bit parallel
device. The major functional blocks are: the ALU, register
array, interrupt control, timing and control logic. These areas
are connected via the 8-bit internal data bus. Detailed de-
scriptions of these blocks ae provided in the following sec-
tions.
TL/C/5171–9
Note: Applicable pinout for 40-pin
dual-in-line package within parentheses
FIGURE 1. NSC800 CPU Functional Block Diagram
10
8.0 Functional Description (Continued)
8.2.2 Stack Pointer (SP)
8.1 REGISTER ARRAY
The 16-bit stack pointer contains the address of the current
top of stack that is located in external system RAM. The
stack is organized in a last-in, first-out (LIFO) structure. The
pointer decrements before data is pushed onto the stack,
and increments after data is popped from the stack.
The NSC800 register array is divided into two parts: the
dedicated registers and the working registers, as shown in
Figure 2.
Main Reg. Set
â
Alternate Reg. Set
â
V
W V
W
Various operations store or retrieve, data on the stack. This,
along with the usage of subroutine calls and interrupts, al-
lows simple implementation of subroutine and interrupt
nesting as well as alleviating many problems of data manip-
ulation.
Accumulator Flags Accumulator Flags
A
B
D
H
F
C
E
L
A
B
F
Ê
Ê
C
Working
Ê
Ê
Registers
8.2.3 Index Register (IX and IY)
D
H
E
Ê
Ê
Ê
The NSC800 contains two index registers to hold indepen-
dent, 16-bit base addresses used in the indexed addressing
mode. In this mode, an index register, either IX or IY, con-
tains a base address of an area in memory making it a point-
er for data tables.
L
*
Ê
Interrupt
Vector I
Memory
Refresh R
In all instructions employing indexed modes of operation,
another byte acts as a signed two’s complement displace-
ment. This addressing mode enables easy data table ma-
nipulations.
Index Register IX
Index Register IY
Stack Pointer SP
Program Counter PC
Dedicated
Registers
8.2.4 Interrupt Register (I)
–
When the NSC800 provides a Mode 2 response to INTR,
the action taken is an indirect call to the memory location
containing the service routine address. The pointer to the
address of the service routine is formed by two bytes, the
high-byte is from the I Register and the low-byte is from the
interrupting peripheral. The peripheral always provides an
FIGURE 2. NSC800 Register Array
8.2 DEDICATED REGISTERS
There are 6 dedicated registers in the NSC800: two 8-bit
and four 16-bit registers (see Figure 3).
e
even address for the lower byte (LSB 0). When the proc-
Although their contents are under program control, the pro-
gram has no control over their operational functions, unlike
the CPU working registers. The function of each dedicated
register is described as follows:
essor receives the lower byte from the peripheral it concate-
nates it in the following manner:
I Register
External byte
8 bits
0
CPU Dedicated Registers
Program Counter PC
Stack Pointer SP
(16)
(16)
(16)
(16)
(8)
u
The LSB of the external byte must be zero.
Index Register IX
FIGURE 4a. Interrupt Register
Index Register IY
The even memory location contains the low-order byte, the
next consecutive location contains the high-order byte of
the pointer to the beginning address of the interrupt service
routine.
Interrupt Vector Register I
Memory Refresh Register R
(8)
FIGURE 3. Dedicated Registers
8.2.5 Refresh Register (R)
8.2.1 Program Counter (PC)
For systems that use dynamic memories rather than static
RAM’s, the NSC800 provides an integral 8-bit memory re-
fresh counter. The contents of the register are incremented
after each opcode fetch and are sent out on the lower por-
tion of the address bus, along with a refresh control signal.
This provides a totally transparent refresh cycle and does
not slow down CPU operation.
The program counter contains the 16-bit address of the cur-
rent instruction being fetched from memory. The PC incre-
ments after its contents have been transferred to the ad-
dress lines. When a program jump occurs, the PC receives
the new address which overrides the incrementer.
There are many conditional and unconditional jumps, calls,
and return instructions in the NSC800’s instruction reper-
toire that allow easy manipulation of this register in control-
ling the program execution (i.e. JP NZ nn, JR Zd2, CALL
NC, nn).
The program can read and write to the R register, although
this is usually done only for test purposes.
11
8.0 Functional Description (Continued)
8.3 CPU WORKING AND ALTERNATE REGISTER SETS
8.3.1 CPU Working Registers
8.4 REGISTER FUNCTIONS
8.4.1 Accumulator (A Register)
The portion of the register array shown in Figure 4b repre-
sents the CPU working registers. These sixteen 8-bit regis-
ters are general-purpose registers because they perform a
multitude of functions, depending on the instruction being
executed. They are grouped together also due to the types
of instructions that use them, particularly alternate set oper-
ations.
The A register serves as a source or destination register for
data manipulation instructions. In addition, it serves as the
accumulator for the results of 8-bit arithmetic and logic op-
erations.
The A register also has a special status in some types of
operations; that is, certain addressing modes are reserved
for the A register only, although the function is available for
all the other registers. For example, any register can be
loaded by immediate, register indirect, or indexed address-
ing modes. The A register, however, can also be loaded via
an additional register indirect addressing.
The F (flag) register is a special-purpose register because
its contents are more a result of machine status rather than
program data. The F register is included because of its inter-
action with the A register, and its manipulations in the alter-
nate register set operations.
Another special feature of the A register is that it produces
more efficient memory coding than equivalent instruction
functions directed to other registers. Any register can be
rotated; however, while it requires a two-byte instruction to
normally rotate any register, a single-byte instruction is
available for rotating the contents of the accumulator (A reg-
ister).
8.3.2 Alternate Registers
The NSC800 registers designated as CPU working registers
have one common feature: the existence of a duplicate reg-
ister in an alternate register set. This architectural concept
simplifies programming during operations such as interrupt
response, when the machine status represented by the con-
tents of the registers must be saved.
8.4.2 F Register - Flags
The alternate register concept makes one set of registers
available to the programmer at any given time. Two instruc-
tions (EX AF, A‘F’ and EXX), exchange the current working
set of registers with their alternate set. One exchange be-
tween the A and F registers and their respective duplicates
(A’ and F’) saves the primary status information contained in
the accumulator and the flag register. The second exchange
instruction performs the exchange between the remaining
registers, B, C, D, E, H, and L, and their respective alter-
nates B’, C’, D’, E’, H’, and L’. This essentially saves the
contents of the original complement of registers while pro-
viding the programmer with a usable alternate set.
The NSC800 flag register consists of six status bits that
contain information regarding the results of previous CPU
operations. The register can be read by pushing the con-
tents onto the stack and then reading it, however, it cannot
be written to. It is classified as a register because of its
affiliation with the accumulator and the existence of a dupli-
cate register for use in exchange instructions with the accu-
mulator.
Of the six flags shown in Figure 5, only four can be directly
tested by the programmer via conditional jump, call, and
return instructions. They are the Sign (S), Zero (Z), Parity/
Overflow (P/V), and Carry (C) flags. The Half Carry (H) and
Add/Subtract (N) flags are used for internal operations re-
lated to BCD arithmetic.
CPU Main Working Register Set
Accumulator A
Register B
(8)
(8)
(8)
(8)
Flags F
(8)
(8)
(8)
(8)
Register C
Register E
Register L
Register D
Register H
CPU Alternate Working Register Set
Accumulator A’
Register B’
Register D’
Register H’
(8)
(8)
(8)
(8)
Flags F’
(8)
(8)
(8)
(8)
Register C’
Register E’
Register L’
TL/C/5171–23
FIGURE 5. Flag Register
FIGURE 4b. CPU Working and Alternate Registers
12
8.0 Functional Description (Continued)
8.4.3 Carry (C)
The following operations affect the P/V flag according to
the parity of the result of the operation:
A carry from the highest order bit of the accumulator during
an add instruction, or a borrow generated during a subtrac-
tion instruction sets the carry flag. Specific shift and rotate
instructions also affect this bit.
Logic Operations
#
Rotate and Shift
#
Rotate Digits
#
Two specific instructions in the NSC800 instruction reper-
toire set (SCF) or complement (CCF) the carry flag.
Decimal Adjust
#
Input Register Indirect
#
The following operations affect the P/V flag according to
the overflow result of the operation.
Other operations that affect the C flag are as follows:
Adds
#
Subtracts
#
#
#
#
Adds (16 bit with carry, 8-bit with/without carry)
#
#
#
Logic Operations (always resets C flag)
Subtracts (16 bit with carry, 8-bit with/without carry)
Rotate Accumulator
Increments and Decrements
Rotate and Shifts
Negation of Accumulator
#
The P/V flag has no significance immediately after the fol-
lowing operations.
Decimal Adjust
#
Negation of Accumulator
#
Other operations do not affect the C flag.
Block I/O
#
#
8.4.4 Adds/Subtract (N)
Bit Tests
This flag is used in conjunction with the H flag to ensure that
the proper BCD correction algorithm is used during the deci-
mal adjust instruction (DAA). The correction algorithm de-
pends on whether an add or subtract was previously done
with BCD operands.
In block transfers and compares, the P/V flag indicates the
status of the BC register, always ending in the reset state
after an auto repeat of a block move. Other operations do
not affect the P/V flag.
8.4.6 Half Carry (H)
The operations that set the N flag are:
This flag indicates a BCD carry, or borrow, result from the
low-order four bits of operation. It can be used to correct the
results of a previously packed decimal add, or subtract, op-
eration by use of the Decimal Adjust Instruction (DAA).
Subtractions
#
Decrements (8-bit)
#
Complementing of the Accumulator
#
The following operations affect the H flag:
Block I/O
#
Adds (8-bit)
#
Block Searches
#
Subtracts (8-bit)
#
Negation of the Accumulator
#
The operations that reset the N flag are:
Increments and Decrements
#
Decimal Adjust
#
#
#
Adds
#
#
#
Negation of Accumulator
Increments
Always Set by: Logic AND
Logic Operations
Complement Accumulator
Bit Testing
Rotates
#
#
#
#
Set and Complement Carry
Always Reset By: Logic OR’s and XOR’s
#
Input Register Indirect
Rotates and Shifts
Set Carry
Block Transfers
Load of the I or R Registers
#
Input Register Indirect
Block Transfers
Bit Tests
#
Other operations do not affect the N flag.
Loads of I and R Registers
8.4.5 Parity/Overflow (P/V)
The H flag has no significance immediately after the follow-
ing operations.
The Parity/Overflow flag is a dual-purpose flag that indi-
cates results of logic and arithmetic operations. In logic op-
erations, the P/V flag indicates the parity of the result; the
flag is set (high) if the result is even, reset (low) if the result
is odd. In arithmetic operations, it represents an overflow
condition when the result, interpreted as signed two’s com-
plement arithmetic, is out of range for the eight-bit accumu-
16-bit Adds with/without carry
#
16-Bit Subtracts with carry
#
Complement of the carry
#
Block I/O
#
b
a
lator (i.e. 128 to 127).
Block Searches
#
Other operations do not affect the H flag.
13
8.0 Functional Description (Continued)
8.4.7 Zero Flag (Z)
8.4.9 Additional General-Purpose Registers
Loading a zero in the accumulator or when a zero results
from an operation sets the zero flag.
The other general-purpose registers are the B, C, D, E, H
and L registers and their alternate register set, B’, C’, D’, E’,
H’ and L’. The general-purpose registers can be used inter-
changeably.
The following operations affect the zero flag.
Adds (16-bit with carry, 8-bit with/without carry)
#
In addition, the B and C registers perform special functions
in the NSC800 expanded I/O capabilities, particularly block
I/O operations. In these functions, the C register can ad-
dress I/O ports; the B register provides a counter function
when used in the register indirect address mode.
Subtracts (16-bit with carry, 8-bit with/without carry)
#
Logic Operations
#
Increments and Decrements
#
Rotate and Shifts
#
When used with the special condition jump instruction
(DJNZ) the B register again provides the counter function.
Rotate Digits
#
Decimal Adjust
#
8.4.10 Alternate Configurations
Input Register Indirect
#
The six 8-bit general purpose registers (B,C,D,E,H,L) will
combine to form three 16-bit registers. This occurs by con-
catenating the B and C registers to form the BC register, the
D and E registers form the DE register, and the H and L
registers form the HL register.
Block I/O (always set after auto repeat block I/O)
#
Block Searches
#
Load of I and R Registers
#
Bit Tests
#
Having these 16-bit registers allows 16-bit data handling,
thereby expanding the number of 16-bit registers available
for memory addressing modes. The HL register typically
provides the pointer address for use in register indirect ad-
dressing of the memory.
Negation of Accumulator
#
The Z flag has no signficance immediately after the follow-
ing operations:
Block Transfers
#
Other operations do not affect the zero flag.
The DE register provides a second memory pointer register
for the NSC800’s powerful block transfer operations. The
BC register also provides an assist to the block transfer
operations by acting as a byte-counter for these operations.
8.4.8 Sign Flag (S)
The sign flag stores the state of bit 7 (the most-signifi-
cant bit and sign bit) of the accumulator following an arith-
metic operation. This flag is of use when dealing with signed
numbers.
8.5 ARITHMETIC-LOGIC UNIT (ALU)
The arithmetic, logic and rotate instructions are performed
by the ALU. The ALU internally communicates with the reg-
isters and data buffer on the 8-bit internal data bus.
The sign flag is affected by the following operation accord-
ing to the result:
Adds (16-bit with carry, 8-bit with/without carry)
#
8.6 INSTRUCTION REGISTER AND DECODER
Subtracts (16-bit with carry, 8-bit with/without carry)
#
During an opcode fetch, the first byte of an instruction is
transferred from the data buffer (i.e. its on the internal data
bus) to the instruction register. The instruction register feeds
the instruction decoder, which gated by timing signals, gen-
erates the control signals that read or write data from or to
the registers, control the ALU and provide all required exter-
nal control signals.
Logic Operations
#
Increments and Decrements
#
Rotate and Shifts
#
Rotate Digits
#
Decimal Adjust
#
Input Register Indirect
#
Block Search
#
Load of I and R Registers
#
Negation of Accumulator
#
The S flag has no significance immediately after the follow-
ing operations:
Block I/O
#
Block Transfers
#
Bit Tests
#
Other operations do not affect the sign bit.
14
9.0 Timing and Control
9.1 INTERNAL CLOCK GENERATOR
An inverter oscillator contained on the NSC800 chip pro-
vides all necessary timing signals. The chip operation fre-
quency is equal to one half of the frequency of this oscilla-
tor.
The oscillator frequency can be controlled by one of the
following methods:
f(XTAL)
2
k
2 MHz
1. Leaving the X pin unterminated and driving the X
OUT IN
pin with an externally generated clock as shown in Figure
e
R
1 MX
6. When driving X with a square wave, the minimum
IN
duty cycle is 30% high.
e
C1 20 pF
e
C2 34 pF
(Recommended)
TL/C/5171–14
FIGURE 7. Use Of Crystal
The CPU has a minimum clock frequency input (
@
X ) of
IN
300 kHz, which results in 150 kHz system clock speed. All
registers internal to the chip are static, however there is
dynamic logic which limits the minimum clock speed. The
input clock can be stopped without fear of losing any data or
damaging the part. You stop it in the phase of the clock that
TL/C/5171–13
FIGURE 6. Use of External Clock
2. Connecting a crystal with the proper biasing network be-
as shown in Figure 7. Recommend-
ed crystal is a parallel resonance AT cut crystal.
tween X and X
IN OUT
has X low and CLK OUT high. When restarting the CPU,
IN
precautions must be taken so that the input clock meets
these minimum specification. Once started, the CPU will
continue operation from the same location at which it was
stopped. During DC operation of the CPU, typical current
drain will be 2 mA. This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock. For clock stop circuit, see Figure 8.
Note 1: If the crystal frequency is between 1 MHz and 2 MHz a series
resistor,
R , (470X to 1500X) should be connected between
S
and R, XTAL and C . Additionally, the capacitance of C1
X
OUT
Z
and C2 should be increased by 2 to 3 times the recommended
value. For crystal frequencies less than 1 MHz higher values of
C1 and C2 may be required. Crystal parameters will also affect
the capacitive loading requirements.
TL/C/5171–36
FIGURE 8. Clock Stop Circuit
15
9.0 Timing and Control (Continued)
During an input or output instruction, the CPU duplicates the
]
9.2 CPU TIMING
[
lower half of the address AD(0–7) onto the upper address
The NSC800 uses a multiplexed bus for data and address-
es. The 16-bit address bus is divided into a high-order 8-bit
address bus that handles bits 8–15 of the address, and a
low-order 8-bit multiplexed address/data bus that handles
bits 0–7 of the address and bits 0–7 of the data. Strobe
outputs from the NSC800 (ALE, RD and WR) indicate when
a valid address or data is present on the bus. IO/M indi-
cates whether the ensuing cycle accesses memory or I/O.
[
]
bus A(8–15) . The eight bits of address will stay on A(8–
15) for the entire machine cycle and can be used for chip
selection directly.
Figure 9 illustrates the timing relationship for opcode fetch
cycles with and without a wait state.
TL/C/5171–15
FIGURE 9a. Opcode Fetch Cycles without WAIT States
TL/C/5171–16
FIGURE 9b. Opcode Fetch Cycles with WAIT States
16
9.0 Timing and Control (Continued)
During the opcode fetch, the CPU places the contents of
the PC on the address bus. The falling edge of ALE indi-
cates a valid address on the AD(0–7) lines. The WAIT input
that when it goes inactive, the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(0–7) lines. During t , RFSH goes active and AD(0–
3
is sampled during t and if active causes the NSC800 to
2
insert a wait state (t ). WAIT is sampled again during t so
7) has the dynamic RAM refresh address from register R
and A(8–15) the interrupt vector from register I.
w
w
TL/C/5171–17
FIGURE 10a. Memory Read/Write Cycles without WAIT States
TL/C/5171–18
FIGURE 10b. Memory Read and Write with WAIT States
17
9.0 Timing and Control (Continued)
Figure 10 shows the timing for memory read (other than
Figure 11 shows the timing for input and output cycles with
and without wait states. The CPU automatically inserts one
wait state into each I/O instruction to allow sufficient time
for an I/O port to decode the address.
opcode fetchs) and write cycles with and without a wait
t
state. The RD stobe is widened by
(half the machine
2
state) for memory reads so that the actual latching of the
input data occurs later.
TL/C/5171–19
FIGURE 11a. Input and Output Cycles without WAIT States
TL/C/5171–20
*WAIT state automatically inserted during IO operation.
FIGURE 11b. Input and Output Cycles with WAIT States
18
9.0 Timing and Control (Continued)
9.3 INITIALIZATION
RESET IN initializes the NSC800; RESET OUT initializes the
peripheral components. The Schmitt trigger at the RESET
IN input facilitates using an R-C network reset scheme dur-
ing power up (see Figure 12 ).
To ensure proper power-up conditions for the NSC800, the
following power-up and initialization procedure is recom-
mended:
TL/C/5171–21
1. Apply power (V
and GND) and set RESET IN active
CC
FIGURE 12. Power-On Reset
(low). Allow sufficient time (approximately 30 ms if a crys-
tal is used) for the oscillator and internal clocks to stabi-
lize. RESET IN must remain low for at least 3t state (CLK)
times. RESET OUT goes high as soon as the active
RESET IN signal is clocked into the first flip-flop after the
on-chip Schmitt trigger. RESET OUT signal is available to
reset the peripherals.
9.4 POWER-SAVE FEATURE
The NSC800 provides a unique power-save mode by the
means of the PS pin. PS input is sampled at the last t state
of the last M cycle of an instruction. After recognizing an
active (low) level on PS, The NSC800 stops its internal
clocks, thereby reducing its power dissipation to one half of
operating power, yet maintaining all register values and in-
ternal control status. The NSC800 keeps its oscillator run-
ning, and makes the CLK signal available to the system.
When in power-save the ALE strobe will be stopped high
2. Set RESET IN high. RESET OUT then goes low as the
inactive RESET IN signal is clocked into the first flip-flop
after the on-chip Schmitt trigger. Following this the CPU
initiates the first opcode fetch cycle.
Note: The NSC800 initialization includes: Clear PC to
X’0000 (the first opcode fetch, therefore, is from memory
location X’0000). Clear registers I (Interrupt Vector Base)
and R (Refresh Counter) to X’00. Clear interrupt control reg-
ister bits IEA, IEB and IEC. The interrupt control bit IEI is set
to 1 to maintain INS8080A/Z80A compatibility (see INTER-
RUPTS for more details). The CPU disables maskable inter-
rupts and enters INTR Mode 0. While RESET IN is active
(low), the A(8–15) and AD(0–7) lines go to high impedance
(TRI-STATE) and all CPU strobes go to the inactive state
(see Figure 13 ).
[
]
and the address lines AD(0–7), A(8–15) will indicate the
next machine address. When PS returns high, the opcode
fetch (or M1 cycle) of the CPU begins in a normal manner.
Note this M1 cycle could also be an interrupt acknowledge
cycle if the NSC800 was interrupted simultaneously with PS
(i.e. PS has priority over a simultaneously occurring inter-
rupt). However, interrupts are not accepted during power
save. Figure 14 illustrates the power save timing.
TL/C/5171–74
FIGURE 13. NSC800 Signals During Power-On and Manual Reset
19
9.0 Timing and Control (Continued)
TL/C/5171–28
FIGURE 14. NSC800 Power-Save
TL/C/5171–22
*S0, S1 during BREQ will indicate same machine cycle as during the cycle when BREQ was accepted.
e
t
Z
time states during which bus and control signals are in high impedance mode.
FIGURE 15. Bus Acknowledge Cycle
In the event BREQ is asserted (low) at the end of an instruc-
tion cycle and PS is active simultaneously, the following oc-
curs:
9.6 INTERRUPT CONTROL
The NSC800 has five interrupt/restart inputs, four are mask-
able (RSTA, RSTB, RSTC, and INTR) and one is non-mask-
able (NMI). NMI has the highest priority of all interrupts; the
user cannot disable NMI. After recognizing an active input
on NMI, the CPU stops before the next instruction, pushes
the PC onto the stack, and jumps to address X’0066, where
the user’s interrupt service routine is located (i.e., restart to
memory location X’0066). NMI is intended for interrupts re-
quiring immediate attention, such as power-down, control
panel, etc.
1. The NSC800 will go into BACK cycle.
2. Upon completion of BACK cycle if PS is still active the
CPU will go into power-save mode.
9.5 BUS ACCESS CONTROL
Figure 15 illustrates bus access control in the NSC800. The
external device controller produces an active BREQ signal
that requests the bus. When the CPU responds with BACK
then the bus and related control strobes go to high imped-
ance (TRI-STATE) and the RFSH signal remains high. It
should be noted that (1) BREQ is sampled at the last t state
of any M machine cycle only. (2) The NSC800 will not ac-
knowledge any interrupt/restart requests, and will not pe-
form any dynamic RAM refresh functions until after BREQ
input signal is inactive high. (3) BREQ signal has priority
over all interrupt request signals, should BREQ and interrupt
request become active simultaneously. Therefore, interrupts
latched at the end of the instruction cycle will be serviced
after a simultaneously occurring BREQ. NMI is latched dur-
ing an active BREQ.
RSTA, RSTB and RSTC are restart inputs, which, if enabled,
execute a restart to memory location X’003C, X’0034, and
X’002C, respectively. Note that the CPU response to the
NMI and RST (A, B, C) request input is basically identical,
except for the restored memory location. Unlike NMI, how-
ever, restart request inputs must be enabled.
Figure 16 illustrates NMI and RST interrupt machine cycles.
M1 cycle will be a dummy opcode fetch cycle followed by
M2 and M3 which are stack push operations. The following
instruction then starts from the interrupts restart location.
Note: RD does not go low during this dummy opcode fetch. A unique indica-
tion of INTA can be decoded using 2 ALEs and RD.
20
9.0 Timing and Control (Continued)
TL/C/5171–24
Note 1: This is the only machine cycle that does not have an RD, WR, or INTA strobe but will accept a wait strobe.
FIGURE 16. Non-Maskable and Restart Interrupt Machine Cycle
The NSC800 also provides one more general purpose inter-
rupt request input, INTR. When enabled, the CPU responds
to INTR in one of the three modes defined by instruction
IM0, IM1, and IM2 for modes 0, 1, and 2, respectively. Fol-
lowing reset, the CPU automatically enables mode 0.
dress. The first byte of each entry in the table is the least
significant (low-order) portion of the address. The program-
mer must obviously fill this table with the desired addresses
before any interrupts are to be accepted.
Note that the programmer can change this table at any time
to allow peripherals to be serviced by different service rou-
tines. Once the interrupting device supplies the lower por-
tion of the pointer, the CPU automatically pushes the pro-
gram counter onto the stack, obtains the starting address
from the table and does a jump to this address.
Interrupt (INTR) Mode 0: The CPU responds to an interrupt
request by providing an INTA (interrupt acknowledge)
strobe, which can be used to gate an instruction from a
peripheral onto the data bus. The CPU inserts two wait
states during the first INTA cycle to allow the interrupting
device (or its controller) ample time to gate the instruction
and determine external priorities (Figure 18 ). This can be
any instruction from one to four bytes. The most popular
instruction is one-byte call (restart instruction) or a three-
byte call (CALL NN instruction). If it is a three-byte call, the
CPU issues a total of three INTA strobes. The last two
(which do not include wait states) read NN.
The interrupts have fixed priorities built into the NSC800 as:
NMI
0066
003C
0034
002C
0038
(Highest Priority)
RSTA
RSTB
RSTC
INTR
(Lowest Priority)
Interrupt Enable, Interrupt Disable. The NSC800 has two
types of interrupt inputs, a non-maskable interrupt and four
software maskable interrupts. The non-maskable interrupt
(NMI) cannot be disabled by the programmer and will be
accepted whenever a peripheral device requests an inter-
rupt. The NMI is usually reserved for important functions
that must be serviced when they occur, such as imminent
power failure. The programmer can selectively enable or
disable maskable interrupts (INT, RSTA, RSTB and RSTC).
This selectivity allows the programmer to disable the mask-
able interrupts during periods when timing constraints don’t
allow program interruption.
Note: If the instruction stored in the ICU doesn’t require the PC to be
pushed onto the stack (eq. JP nn), then the PC will not be pushed.
Interrupt (INTR) Mode 1: Similar to restart interrupts ex-
cept the restart location is X’0038 (Figure 18 ).
Interrupt (INTR) Mode 2: With this mode, the programmer
maintains a table that contains the 16-bit starting address of
every interrupt service routine. This table can be located
anywhere in memory. When the CPU accepts a Mode 2
interrupt (Figure 17 ), it forms a 16-bit pointer to obtain the
desired interrupt service routine starting address from the
table. The upper 8 bits of this pointer are from the contents
of the I register. The lower 8 bits of the pointer are supplied
by the interrupting device with the LSB forced to zero. The
programmer must load the interrupt vector prior to the inter-
rupt occurring. The CPU uses the pointer to get the two
adjacent bytes from the interrupt service routine starting ad-
dress table to complete 16-bit service routine starting ad-
There are two interrupt enable flip-flops (IFF and IFF ) on
2
1
the NSC800. Two instructions control these flip-flops. En-
able Interrupt (EI) and Disable Interrupt (DI). The state of
IFF determines the enabling or disabling of the maskable
1
interrupts, while IFF is used as a temporary storage loca-
2
tion for the state of IFF .
1
21
9.0 Timing and Control (Continued)
A reset to the CPU will force both IFF and IFF to the reset
2
to the enable state. When the CPU accepts an interrupt,
both IFF and IFF are automatically reset, inhibiting further
1
state disabling maskable interrupts. They can be enabled by
an EI instruction at any time by the programmer. When an EI
instruction is executed, any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed. This single instruction delay is necessary in
situations where the following instruction is a return instruc-
tion and interrupts must not be allowed until the return has
1
2
interrupts until the programmer wishes to issue a new EI
instruction. Note that for all the previous cases, IFF and
IFF are always equal.
1
2
The function of IFF is to retain the status of IFF when a
2
1
non-maskable interrupt occurs. When a non-maskable inter-
rupt is accepted, IFF is reset to prevent further interrupts
1
until reenabled by the programmer. Thus, after a non-mask-
able interrupt has been accepted, maskable interrupts are
been completed. The EI instruction sets both IFF and IFF
1
2
disabled but the previous state of IFF is saved by IFF
1
2
TL/C/5171–27
FIGURE 17. Interrupt Mode 2
22
9.0 Timing and Control (Continued)
23
9.0 Timing and Control (Continued)
so that the complete state of the CPU just prior to the non-
maskable interrupt may be restored. The method of restor-
ing the status of IFF is through the execution of a Return
1
Operation IFF
IFF
Comment
1
2
Initialize
0
1
0
0
Interrupt Disabled
#
#
#
EI
Non-Maskable Interrupt (RETN) instruction. Since this in-
struction indicates that the non-maskable interrupt service
routine is completed, the contents of IFF are now copied
2
1
0
Interrupt Enabled after
next instruction
back into IFF , so that the status of IFF just prior to the
1
1
acceptance of the non-maskable interrupt will be automati-
cally restored.
#
#
#
Figure 19 depicts the status of the flip flops during a sample
series of interrupt instructions.
INTR
Interrupt Disable and INTR
Being Serviced
Interrupt Control Register. The interrupt control register
(ICR) is a 4-bit, write only register that provides the program-
mer with a second level of maskable control over the four
maskable interrupt inputs.
#
#
#
The ICR is internal to the NSC800 CPU, but is addressed
through the I/O space at I/O address port X’BB. Each bit in
the register controls a mask bit dedicated to each maskable
interrupt, RSTA, RSTB, RSTC and INTR. For an interrupt
request to be accepted on any of these inputs, the corre-
EI
1
1
1
1
Interrupt Enabled after
next instruction
RET
Interrupt Enabled
#
#
e
sponding mask bit in the ICR must be set ( 1) and IFF
1
#
NMI
and IFF must be set. This provides the programmer with
2
control over individual interrupt inputs rather than just a sys-
tem wide enable or disable.
0
1
Interrupt Disabled
#
#
#
RETN
1
0
1
0
Interrupt Enabled
Interrupt Disabled
#
INTR
TL/C/5171–26
Bit
0
Name
IEI
Function
#
#
Interrupt Enable for INTR
Interrupt Enable for RSTC
Interrupt Enable for RSTB
Interrupt Enable for RSTA
1
IEC
IEB
IEA
#
NMI
2
0
0
0
0
Interrupt Disabled and NMI
Being Serviced
3
#
#
For example: In order to enable RSTB, CPU interrupts must
be enabled and IEB must be set.
#
RETN
Interrupt Disabled and INTR
Being Serviced
At reset, IEI bit is set and other mask bits IEA, IEB, IEC are
cleared. This maintains the software compatibility between
NSC800 and Z80A.
#
#
#
Execution of an I/O block move instruction will not affect
the state of the interrupt control bits. The only two instruc-
tions that will modify this write only register are OUT (C), r
and OUT (N), A.
EI
1
1
1
1
Interrupt Enabled after
next instruction
RET
Interrupt Enabled
#
#
#
FIGURE 19. IFF and IFF States Immediately after the
1
2
Operation has been Completed
24
NSC800 SOFTWARE
10.0 Introduction
This chapter provides the reader with a detailed description
of the NSC800 software. Each NSC800 instruction is de-
scribed in terms of opcode, function, flags affected, timing,
and addressing mode.
11.3 IMMEDIATE
The most straightforward way of introducing data to the
CPU registers is via immediate addressing, where the data
is contained in an additional byte of multi-byte instructions.
Example:
Instruction: Load the E register with the constant value
X’7C.
11.0 Addressing Modes
The following sections describe the addressing modes sup-
ported by the NSC800. Note that particular addressing
modes are often restricted to certain types of instructions.
Examples of instructions used in the particular addressing
modes follow each mode description.
Mnemonic: LD
Opcode:
E,X’7C
The 10 addressing modes and 158 instructions provide a
flexible and powerful instruction set.
11.1 REGISTER
The most basic addressing mode is that which addresses
data in the various CPU registers. In these cases, bits in the
opcode select specific registers that are to be addressed by
the instruction.
TL/C/5171–52
In this instruction, the E register is addressed with register
addressing, while the constant X’7C is immediate data in the
second byte of the instruction.
Example:
Instruction: Load register B from register C
11.4 IMMEDIATE EXTENDED
Mnemonic: LD
Opcode:
B,C
As immediate addressing allows 8 bits of data to be sup-
plied by the operand, immediate extended addressing al-
lows 16 bits of data to be supplied by the operand. These
are in two additional bytes of the instruction.
Example:
Instruction: Load the 16-bit IX register with the constant
value X’ABCD.
Mnemonic: LD
Opcode:
IX,X’ABCD
TL/C/5171–50
In this instruction, both the B and C registers are addressed
by opcode bits.
11.2 IMPLIED
The implied addressing mode is an extension to the register
addressing mode. In this mode, a specific register, the accu-
mulator, is used in the execution of the instruction. In partic-
ular, arithmetic operations employ implied addressing, since
the A register is assumed to be the destination register for
the result without being specifically referenced in the op-
code.
Example:
Instruction: Subtract the contents of register D from the
Accumulator (A register)
Mnemonic: SUB
Opcode:
D
TL/C/5171–53
In this instruction, register addressing selects the IX regis-
ter, while the 16-bit quanity X’ABCD is immediate data sup-
plied as immediate extended format.
TL/C/5171–51
In this instruction, the D register is addressed with register
addressing, while the use of the A register is implied by the
opcode.
25
11.0 Addressing Modes (Continued)
11.5 DIRECT ADDRESSING
Indexed addressing is particularly useful in dealing with lists
of data.
Direct addressing is the most straightforward way of ad-
dressing supplies a location in the memory space. Direct
addressing, 16-bits of memory address information in two
bytes of data as part of the instruction. The memory address
could be either data, source of destination, or a location for
program execution, as in program control instructions.
Example:
Instruction: Increment the data in memory location X’1020.
The IY register contains X’1000.
a
(IY X’20)
Mnemonic: INC
Opcode:
Example:
Instruction: Jump to location X’0377
Mnemonic: JP
Opcode:
X’0377
1
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
ÐDefines jump opcode
ÐConstant X’0377
(
This instruction loads the Program Counter (PC) is loaded
with the constant in the second and third bytes of the in-
struction. The program counter contents are transferred via
direct addressing.
TL/C/5171–54
The indexed addressing mode uses the contents of index
registers IX or IY along with the displacement to form a
pointer to memory.
11.6 REGISTER INDIRECT
Next to direct addressing, register indirect addressing pro-
vides the second most straightforward means of addressing
memory. In register indirect addressing, a specified register
pair contains the address of the desired memory location.
The instruction references the register pair and the register
contents define the memory location of the operand.
11.8 RELATIVE
Certain instructions allow memory locations to be ad-
dressed as a position relative to the PC register. These in-
structions allow jumps to memory locations which are off-
sets around the program counter. The offset, together with
the current program location, is determined through a dis-
placement byte included in the instruction. The formation of
this displacement byte is explained more fully in the ‘‘In-
structions Set’’ section.
Example:
Instruction: Add the contents of memory location X’0254 to
the A register. The HL register contains X’0254.
Example:
Mnemonic: ADD
Opcode
A,(HL)
Instruction: Jump to a memory location 7 bytes beyond the
current location.
1
0
0
0
0
1
1
0
a
7
Mnemonic: JR
Opcode:
$
This instruction uses implied addressing of the A and HL
registers and register indirect addressing to access the data
pointed to by the HL register.
0
0
0
1
1
0
0
0
0
1
ÐDefines relative jump
opcode
11.7 INDEXED
The most flexible mode of memory addressing is the in-
dexed mode. This is similar to the register indirect mode of
addressing because one of the two index registers (IX or IY)
contains the base memory address. In addition, a byte of
data included in the instruction acts as a displacement to
the address in the index register.
0
0
0
0
1
0
ÐDisplacement to be
applied to the PC
The program will continue at a location seven locations past
the current PC.
26
11.0 Addressing Modes (Continued)
11.9 MODIFIED PAGE ZERO
Program execution continues at location X’0028 after exe-
cution of a single-byte call employing modified page zero
addressing.
A subset of NSC800 instructions (the Restart instructions)
provides a code-efficient single-byte instruction that allows
CALLs to be performed to any one of eight dedicated loca-
tions in page zero (locations X’0000 to X’00FF). Normally, a
CALL is a 3-byte instruction employing direct memory ad-
dressing.
11.10 BIT
The NSC800 allows setting, resetting, and testing of individ-
ual bits in registers and memory data bytes.
Example:
Example:
Operation: Set bit 2 in the L register
Instruction: Perform a restart call to location X’0028.
Mnemonic: SET
Opcode:
2,L
Mnemonic: RST
Opcode:
X’28
TL/C/5171–56
TL/C/5171–55
Bit addressing allows the selection of bit 2 in the L register
selected by register addressing.
p
t
00H 08H 10H 18H 20H 28H 30H 38H
000 001 010 011 100 101 110 111
27
12.0 Instruction Set
This section details the entire NSC800 instruction set in
terms of
The instructions are grouped in order under the following
functional headings:
Opcode
8-Bit Loads
#
#
Instruction
16-Bit Loads
#
#
Function
8-Bit Arithmetic
#
#
Timing
16-Bit Arithmetic
#
#
Addressing Mode
Bit Set, Reset, and Test
#
#
Rotate and Shift
#
Exchanges
#
Memory Block Moves and Searches
#
Input/Output
#
CPU Control
#
Program Control
#
12.1 Instruction Set Index
Alphabetical
Assembly
Operation
Page
Mnemonic
ADC A,m
ADC A,n
ADC A,r
Add, with carry, memory location contents to Accumulator
Add, with carry, immediate data n to Accumulator
Add, with carry, register r contents to Accumulator
Add, with carry, register pair pp to HL
40
38
36
43
40
38
36
43
43
43
43
41
39
36
1
ADC HL,pp
ADD A,m
ADD A,n
ADD A,r
Add memory location contents to Accumulator
Add immediate data n to Accumulator
1
Add register r contents to Accumulator
Add register pair pp to HL
ADD HL,pp
ADD IX,pp
ADD IY,pp
ADD ss,pp
Add register pair pp to IX
Add register pair pp to IY
Add register pair pp to contents of register pair ss
Logical ‘AND’ memory contents to Accumulator
Logical ‘AND’ immediate data to Accumulator
Logical ‘AND’ register r contents to Accumulator
AND m
AND n
AND r
1
BIT b,m
BIT b,r
Test bit b of location m
Test bit b of register r
45
44
1
1
CALL cc,nn
CALL nn
CCF
Call subroutine at location nn if condition cc is true
Unconditional call to subroutine at location nn
Complement carry flag
56
56
38
42
40
37
50
51
CP m
CP n
CP r
Compare memory contents with Accumulator
Compare immediate data n with Accumulator
Compare register r to contents with Accumulator
Compare location (HL) and Accumulator, decrement HL and BC
Compare location (HL) and Accumulator, decrement HL and BC;
1
CPD
CPDR
e
repeat until BC
0
CPI
Compare location (HL) and Accumulator, increment HL, decrement BC
Compare location (HL) and Accumulator, increment HL, decrement BC;
50
51
CPIR
e
Complement Accumulator (1’s complement)
repeat until BC
0
CPL
37
DAA
Decimal adjust Accumulator
38
42
37
44
DEC m
DEC r
DEC rr
Decrement data in memory location m
Decrement register r contents
1
1
Decrement register pair rr contents
28
12.1 Instruction Set Index (Continued)
Alphabetical
Assembly
Operation
Page
Mnemonic
DI
Disable interrupts
54
56
i
0
DJNZ,d
Decrement B and jump relative B
EI
Enable interrupts
54
50
49
49
50
EX (SP),ss
EX AF,A’F’
EX DE,HL
EXX
Exchange the location (SP) with register ss
Exchange the contents of AF and A’F’
Exchange the contents of DE and HL
Exchange the contents of BC, DE and HL with the contents
of B’C, D’E’ and H’L’, respectively
HALT
Halt (wait for interrupt or reset)
54
IM 0
Set interrupt mode 0
54
55
55
52
52
42
37
43
52
54
52
53
IM 1
Set interrupt mode 1
IM 2
Set interrupt mode 2
IN A,(n)
IN r,(C)
Load Accumulator with input from device (n)
Load register r with input from device (C)
INC m
INC r
INC rr
IND
Increment data in memory location m
Increment register r
1
1
Increment contents of register pair rr
Load location (HL) with input from port (C), decrement HL and B
e
INDR
INI
Load location (HL) with input from port (C), decrement HL and B; repeat until B
Load location (HL) with input from port (C), increment HL, decrement B
Load location (HL) with input from port (C), increment HL, decrement B;
0
INIR
e
repeat until B
0
JP cc,nn
JP nn
Jump to location nn, if condition cc is true
Unconditional jump to location nn
Unconditional jump to location (ss)
55
55
55
55
55
JP (ss)
JR d
a
Unconditional jump relative to PC
a
d, if kk true
d
JR kk,d
Jump relative to PC
LD A,I
Load Accumulator with register I contents
Load Accumulator from location m
32
33
32
32
33
32
33
34
33
32
32
32
35
34
34
50
51
50
51
LD A,m
LD A,R
LD I,A
2
2
Load Accumulator with register R contents
Load register I with Accumulator contents
Load memory with immediate data n
Load memory from register r
LD m ,n
1
LD m ,r
1
LD m ,A
2
Load memory from Accumulator
LD (nn),rr
Load memory location nn with register pair rr
Load register r from memory
LD r,m
LD r,n
1
Load register with immediate data n
Load register R from Accumulator
LD R,A
LD r ,r
Load destination register r from source register r
d s
d
s
LD rr,(nn)
LD rr,nn
LD SP,ss
LDD
Load register pair rr from memory location nn
Load register pair rr with immediate data nn
Load SP from register pair ss
Load location (DE) with location (HL), decrement DE, HL and BC
e
LDDR
LDI
Load location (DE) with location (HL), decrement DE, HL and BC; repeat until BC
Load location (DE) with location (HL), increment DE and HL, decrement BC
Load location (DE) with location (HL), increment DE and HL, decrement BC;
0
LDIR
e
repeat until BC
0
NEG
NOP
Negate Accumulator (2’s complement)
No operation
38
54
29
12.1 Instruction Set Index (Continued)
Alphabetical
Assembly
Operation
Page
Mnemonic
OR m
OR n
OR r
Logical ‘OR’ of memory location contents and accumulator
Logical ‘OR’ of immediate data n and Accumulator
41
39
37
54
53
1
Logical ‘OR’ of register r and Accumulator
e
0
OTDR
OTIR
Load output port (C) with location (HL), decrement HL and B; repeat until B
Load output port (C) with location (HL), increment HL, decrement B;
e
Load output port (C) with register r
repeat until B
0
OUT (C),r
OUT (n),A
OUTD
52
53
53
52
Load output port (n) with Accumulator
Load output port (C) with location (HL), decrement HL and B
Load output port (C) with location (HL), increment HL, decrement B
OUTI
POP qq
Load register pair qq with top of stack
Load top of stack with register pair qq
35
35
PUSH qq
RES b,m
RES b,r
RET
Reset bit b of memory location m
Reset bit b of register r
44
44
56
56
56
57
47
45
45
47
45
45
49
48
46
48
47
45
46
49
57
1
1
Unconditional return from subroutine
Return from subroutine, if cc true
RET cc
RETI
Unconditional return from interrupt
RETN
Unconditional return from non-maskable interrupt
Rotate memory contents left through carry
Rotate register r left through carry
RL m
RL r
1
RLA
Rotate Accumulator left through carry
Rotate memory contents left circular
Rotate register r left circular
RLC m
RLC r
RLCA
RLD
1
Rotate Accumulator left circular
Rotate digit left and right between Accumulator and memory (HL)
Rotate memory contents right through carry
Rotate register r right through carry
Rotate Accumulator right through carry
Rotate memory contents right circular
Rotate register r right circular
RR m
RR r
RRA
1
RRC m
RRC r
RRCA
RRD
1
Rotate Accumulator right circular
Rotate digit right and left between Accumulator and memory (HL)
Restart to location P
RST P
SBC A,m
SBC A,n
SBC A,r
Subtract, with carry, memory contents from Accumulator
Subtract, with carry, immediate data n from Accumulator
Subtract, with carry, register r from Accumulator
Subtract, with carry, register pair pp from HL
Set carry flag
41
39
36
43
38
44
44
48
46
48
46
48
46
40
39
36
1
SBC HL,pp
SCF
SET b,m
SET b,r
Set bit b in memory location m contents
1
1
Set bit b in register r
SLA m
SLA r
Shift memory contents left, arithmetic
Shift register r left, arithmetic
1
SRA m
SRA r
Shift memory contents right, arithmetic
Shift register r right, arithmetic
1
SRL m
SRL r
Shift memory contents right, logical
Shift register r right, logical
1
SUB m
SUB n
SUB r
Subtract memory contents from Accumulator
Subtract immediate data n from Accumulator
Subtract register r from Accumulator
1
XOR m
XOR n
XOR r
Exclusive ‘OR’ memory contents and Accumulator
Exclusive ‘OR’ immediate data n and Accumulator
Exclusive ‘OR’ register r and Accumulator
42
39
37
1
30
12.0 Instruction Set (Continued)
12.2 INSTRUCTION SET MNEMONIC NOTATION
12.3 ASSEMBLED OBJECT CODE NOTATION
Register Codes:
In the following instruction set listing, the notations used are
shown below.
r
Register
rp
00
01
10
11
Register
BC
rs
00
01
10
11
Register
BC
000
001
010
011
B
C
D
E
b:
Designates one bit in a register or memory location.
Bit address mode uses this indicator.
DE
DE
HL
HL
cc:
Designates condition codes used in conditional
Jumps, Calls, and Return instruction; may be:
SP
AF
e
e
e
e
e
e
e
e
e
Non-Zero (Z flag 0)
NZ
Z
100
101
111
H
L
pp
00
01
10
11
Register
BC
qq
00
01
10
11
Register
BC
e
Zero (Z flag 1)
e
Non-Carry (C flag 0)
NC
C
A
DE
DE
e
Carry (C flag 1)
Parity Odd or No Overflow (P/V 0)
IX
HL
e
PO
PE
P
SP
AF
e
Parity Even or Overflow (P/V 1)
e
Positive (S 0)
Conditions Codes:
e
Negative (S 1)
M
cc
000
001
010
011
100
101
110
111
kk
Mnemonic
True Flag Condition
d:
Designates an 8-bit signed complement displace-
ment. Relative or indexed address modes use this
indicator.
e
e
e
e
NZ
Z
Z
0
1
0
1
Z
NC
C
kk:
Subset of cc condition codes used in conjunction with
conditional relative jumps; may be NZ, Z, NC or C.
C
C
e
e
0
PO
P/V
P/V
0
1
a
a
m : Designates (HL), (IX d) or (IY d). Register indirect
1
or indexed address modes use this indicator.
PE
e
e
P
S
S
m : Designates (BC), (DE) or (nn). Register indirect or di-
2
rect address modes use this indicator.
M
1
Mnemonic
True Flag Condition
n:
Any 8-bit binary number.
e
e
e
e
00
NZ
Z
Z
Z
C
C
0
1
0
1
nn: Any 16-bit binary number.
01
p:
Designates restart vectors and may be the hex values
0, 8, 10, 18, 20, 28, 30 or 38. Restart instructions
employing the modified page zero addressing mode
use this indicator.
10
NC
C
11
Restart Addresses:
pp: Designates the BC, DE, SP or any 16-bit register used
as a destination operand in 16-bit arithmetic opera-
tions employing the register address mode.
t
T
000
001
010
011
100
101
110
111
X’00
X’08
X’10
X’18
X’20
X’28
X’30
X’38
qq: Designates BC, DE, HL, A, F, IX, or IY during opera-
tions employing register address mode.
r:
Designates A, B, C, D, E, H or L. Register addressing
modes use this indicator.
rr:
ss:
Designates BC, DE, HL, SP, IX or IY. Register ad-
dressing modes use this indicator.
Designates HL, IX or IY. Register addressing modes
use this indicator.
X : Subscript L indicates the lower-order byte of a 16-bit
L
register.
X :
H
Subscript H indicates the high-order byte of a 16-bit
register.
( ):
parentheses indicate the contents are considered a
pointer address to a memory or I/O location.
31
12.4 8-Bit Loads
REGISTER TO REGISTER
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
LD
r , r
d s
Load register r with r :
s
d
0
1
0
1
1
1
1
1
r
d w
6
r
No flags affected
s
7
5
4
3
2
1
0
Timing:
M cycles Ð 2
T states Ð 9 (4, 5)
Register
0
1
r
r
s
d
Addressing Mode:
LD R, A
Load Refresh register (R) with contents of the Accumulator.
Timing:
M cycles Ð 1
T states Ð 4
Register
Addressing Mode:
LD A, I
Load Accumulator with the contents of the I register.
R
w
6
A
No flags affected
7
5
4
3
2
1
0
1
1
1
0
1
1
0
1
A
w
I
S: Set if negative result
Z: Set if zero result
H: Reset
0
1
0
0
1
1
1
1
Timing:
M cycles Ð 2
P/V: Set according to IFF (zero if
2
interrupt occurs during opera-
tion)
T states Ð 9 (4, 5)
Register
Addressing Mode:
LD r, n
Load register r with immediate data n.
No flags affected
N: Reset
C: Not affected
7
6
5
4
3
2
1
0
r
w
n
1
1
1
0
1
1
0
1
7
6
5
4
3
2
1
0
0
0
r
1
1
0
0
1
0
1
0
1
1
1
Timing:
M cycles Ð 2
n
T states Ð 9 (4, 5)
Register
Timing:
M cycles Ð 2
Addressing Mode:
LD I, A
Load Interrupt vector register (I) with the contents of A.
No flags affected
T states Ð 7 (4, 3)
Addressing Mode:
Source Ð Immediate
Destination Ð Register
I
w
A
REGISTER TO MEMORY
LD m , r
Load memory from reigster r.
7
6
5
4
3
2
1
0
1
1
1
1
0
1
1
0
1
m
1 w
6
r
No flags affected
0
1
0
0
0
1
1
1
7
5
4
3
2
1
0
Timing:
M cycles Ð 2
0
1
1
1
0
r
LD (HL), r
T states Ð 9 (4, 5)
Register
Timing:
M cycles Ð 2
Addressing Mode:
LD A, R
Load Accumulator with contents of R register.
T states Ð 7 (4,3)
Addressing Mode:
Source Ð Register
Destination Ð Register Indirect
A
w
R
S: Set if negative result
Z: Set if zero result
H: Reset
7
6
5
4
3
2
1
0
a
LD (IX d), r(for N
e
e
0)
1)
X
1
1
N
X
1
1
1
0
1
a
LD (IY d), r(for N
X
P/V: Set according to IFF (zero if
2
0
1
1
1
0
r
interrupt occurs during opera-
tion)
d
N: Reset
C: Not affected
Timing:
M cycles Ð 2
T states Ð 19 (4, 4, 3, 5, 3)
Source Ð Register
Addressing Mode:
Destination Ð Indexed
32
12.4 8-Bit Loads (Continued)
LD
m , A
2
MEMORY TO REGISTER
LD r, m
Load register r from memory location m .
Load memory from the Accumulator.
1
m
2 w
6
A
No flags affected
1
7
5
4
3
2
1
0
r
w
m
No flags affected
1
0
0
0
0
0
0
1
0
LD (BC), A
LD (DE), A
7
6
5
4
3
2
1
0
0
1
r
1
1
0
LD R, (HL)
0
0
0
1
0
0
1
0
Timing:
M cyclesÐ2
Timing:
M cycles Ð 2
T statesÐ7 (4, 3)
T states Ð 7 (4, 3)
Addressing Mode:
SourceÐRegister Indirect
DestinationÐRegister
Addressing Mode:
Source Ð Register (Implied)
Destination Ð Register Indirect
7
6
5
4
3
2
1
0
a
a
e
e
LD r, (IX
LD r, (IY
d) (for N
d) (for N
0)
1)
X
7
6
5
4
3
2
1
0
1
1
N
X
1
1
1
0
1
X
0
0
1
1
0
0
1
0
LD (nn), A
0
1
r
1
1
0
n (low-order byte)
n (high-order byte)
d
Timing:
M cyclesÐ5
Timing:
M cycles Ð 4
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
T states Ð 3 (4, 3, 3, 3)
Source Ð Register (Implied)
Destination Ð Direct
Addressing Mode:
Addressing Mode:
DestinationÐRegister
LD
A, m
2
LD
m , n
1
Load the Accumulator from memory location m .
2
Load memory with immediate data.
A
w
6
m
No flags affected
2
m
1 w
6
n
No flags affected
7
5
4
3
2
1
0
LD A, (BC)
7
5
4
3
2
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
LD(HL), n
0
0
0
1
1
0
1
0
LD A, (DE)
n
Timing:
M cyclesÐ2
Timing:
M cyclesÐ3
T statesÐ7 (4, 3)
T statesÐ10 (4, 3, 3)
SourceÐImmediate
DestinationÐRegister Indirect
Addressing Mode:
SourceÐRegister Indirect
DestinationÐRegister (Implied)
Addressing Mode:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
a
a
e
e
LD (IX
LD (IY
d), n(for N
d), n(for N
0)
1)
0
0
1
1
1
0
1
0
LD A, (nn)
X
1
1
N
X
1
1
1
0
1
X
n (low-order byte)
n (high-order byte)
0
0
1
1
0
1
1
0
d
Timing:
M cyclesÐ4
T statesÐ13 (4, 3, 3, 3)
n
Addressing Mode:
SourceÐImmediate Extended
DestinationÐRegister (Implied)
Timing:
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐImmediate
Addressing Mode:
DestinationÐIndexed
33
12.5 16-Bit Loads
REGISTER TO REGISTER
REGISTER TO MEMORY
LD (nn), rr
Load memory location nn with contents of 16-bit register, rr.
LD
rr, nn
Load 16-bit register pair with immediate data.
rr,
w
6
nn
No flags affected
(nn)
(nn
7
w
rr
No flags affected
L
7
5
4
3
2
1
0
a
1)
LD BC, nn
LD DE, nn
LD HL, nn
LD SP, nn
w
4
rr
H
6
5
3
2
1
0
0
0
rp
0
0
0
1
LD (nn), HL
0
0
1
0
0
0
1
0
(note an alternate
opcode below)
n (low-order byte)
n (high-order byte)
n (low-order byte)
n (high-order byte)
Timing:
M cyclesÐ3
T statesÐ10 (4, 3, 3)
SourceÐImmediate Extended
DestinationÐRegister
Timing:
M cyclesÐ5
Addressing Mode:
T statesÐ16 (4, 3, 3, 3, 3)
SourceÐRegister
Addressing Mode:
7
6
5
4
3
2
1
0
e
e
DestinationÐDirect
LD IX, nn (for N
LD IY, nn (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
7
6
5
4
3
2
1
0
LD (nn), BC
LD (nn), DE
LD (nn), HL
LD (nn), SP
X
1
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
0
1
rp
0
0
1
1
n (low-order byte)
n (high-order byte)
n (low-order byte)
n (high-order byte)
Timing:
M cyclesÐ4
T statesÐ14 (4, 4, 3, 3)
Timing:
M cyclesÐ6
Addressing Mode:
SourceÐImmediate Extended
DestinationÐRegister
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐRegister
Addressing Mode:
LD
SP, ss
DestinationÐDirect
Load the SP from 16-bit register ss.
7
6
5
4
3
2
1
0
e
LD (nn), IX (for N
0)
X
SP
w
6
ss
No flags affected
1
1
N
X
1
1
1
0
1
e
7
5
4
3
2
1
0
LD (nn) IY (for N
1)
X
1
1
1
1
1
0
0
1
LD SP, HL
0
0
1
0
0
0
1
0
Timing:
M cyclesÐ1
n (low-order byte)
n (high-order byte)
T statesÐ6
Addressing Mode:
SourceÐRegister
DestinationÐRegister (Implied)
7
6
5
4
3
2
1
0
Timing:
M cyclesÐ6
e
e
LD SP, IX (for N
LD SP, IY (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐRegister
X
Addressing Mode:
1
1
1
1
1
0
0
1
DestinationÐDirect
Timing:
M cyclesÐ2
T statesÐ10 (4, 6)
SourceÐRegister
Addressing Mode:
DestinationÐRegister (Implied)
34
12.5 16-Bit Loads (Continued)
7
6
5
4
3
2
1
0
LD BC, (nn)
LD DE, (nn)
LD HL, (nn)
LD SP, (nn)
PUSH
qq
1
1
1
0
1
1
0
1
Push the contents of register pair qq onto the memory
stack.
(SP – 1)
(SP – 2)
w
w
qq
No flags affected
0
1
rp
0
0
1
1
H
qq
L
b
2
SP
w
6
SP
n (low-order byte)
n (high-order byte)
7
5
4
3
2
1
0
PUSH BC
PUSH DE
1
1
rs
0
1
0
1
PUSH HL
PUSH AF
Timing:
M cyclesÐ6
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐDirect
Timing:
M cyclesÐ3
Addressing Mode:
T statesÐ11 (5, 3, 3)
SourceÐRegister
DestinationÐRegister Indirect
(Stack)
DestinationÐRegister
Addressing Mode:
7
6
5
4
3
2
1
0
e
LD IX, (nn)(for N
0)
X
1
1
N
X
1
1
1
0
1
e
LD IY, (nn) (for N
1)
X
7
6
5
4
3
2
1
0
0
0
1
0
1
0
1
0
e
e
PUSH IX (for N
PUSH IY (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
X
n (low-order byte)
n (high-order byte)
1
1
1
0
0
1
0
1
Timing:
M cyclesÐ3
T statesÐ15 (4, 5, 3, 3)
SourceÐRegister
Timing:
M cyclesÐ6
Addressing Mode:
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐDirect
DestinationÐRegister Indirect
(Stack)
Addressing Mode:
DestinationÐRegister
MEMORY TO REGISTER
LD rr, (nn)
Load 16-bit register from memory location nn.
No flags affected
POP
Pop the contents of the memory stack to register qq.
No flags affected
qq
qqL w (SP)
a
qqH w (SP 1)
rrL w (nn)
a
SP
w
6
SP
2
a
rrH w (nn 1)
7
5
4
3
2
1
0
POP BC
POP DE
POP HL
POP AF
7
6
5
4
3
2
1
0
LD HL, (nn)
1
1
rs
0
0
0
1
0
0
1
0
1
0
1
0
(note an alternate
opcode below)
n (low-order byte)
n (high-order byte)
Timing:
M cyclesÐ3
T statesÐ10 (4, 3, 3)
Addressing Mode:
SourceÐRegister Indirect
(Stack)
Timing:
M cyclesÐ5
T statesÐ16 (4, 3, 3, 3, 3)
SourceÐDirect
DestinationÐRegister
Addressing Mode:
7
6
5
4
3
2
1
0
e
e
POP IX (for N
POP IY (for N
0)
1)
DestinationÐRegister
X
1
1
N
X
1
1
1
0
1
X
1
1
1
0
0
0
0
1
Timing:
M cyclesÐ4
T statesÐ14 (4, 4, 3, 3)
Addressing Mode:
SourceÐRegister Indirect
(Stack)
DestinationÐRegister
35
12.6 8-Bit Arithmetic
REGISTER ADDRESSING ARITHMETIC
7
6
5
4
3
2
1
0
1
0
0
0
1
r
Hex
Value
In
Hex
Value Number
Timing:
M cyclesÐ1
C
Op Before
DAA
H
C
In
Added
To
T statesÐ4
Before
DAA
After
DAA
Upper
Digit
Lower
Digit
Addressing Mode:
SourceÐRegister
DestinationÐImplied
Byte
(Bits 7-4)
(Bits 3-0)
SUB
r
0
0
0
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0
0
1
0
0
1
0
0
1
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
00
06
06
60
66
66
60
66
66
0
0
0
1
1
1
1
1
1
Subtract the contents of register r from the Accumulator.
b
A
w
A
r
S: Set if result is negative
Z: Set if result is zero
ADD
ADC
INC
0
0
0
1
1
1
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
7
6
5
4
3
2
1
0
SUB
SBC
DEC
NEG
0
0
1
1
0-9
0-8
7-F
6-F
0
1
0
1
0-9
6-F
0-9
6-F
00
FA
A0
9A
0
0
1
1
1
0
0
1
0
r
Timing:
M cyclesÐ1
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐImplied
ADD
A, r
Add contents of register r to the
Accumulator.
SBC
A, r
a
A
w
A
r
S: Set if negative result
Z: Set if zero result
Subtract contents of register r and the carry bit C from the
Accumulator.
H: Set if carry from bit 3
b
b
CY
A
w
A
r
S: Set if result is negative
Z: Set if result is zero
P/V: Set according to overflow
condition
H: Set if borrow from bit 4
N: Reset
P/V: Set if result exceeds 8-bit 2’s
complement range
C: Set if carry from bit 7
7
6
5
4
3
2
1
0
N: Set
1
0
0
0
0
r
C: Set according to borrow
7
6
5
4
3
2
1
0
Timing:
M cyclesÐ1
1
0
0
1
1
r
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐImplied
Timing:
M cyclesÐ1
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐImplied
ADC
A, r
Add contents of register r, plus the carry flag, to the Accu-
mulator.
AND
r
a
a
CY
A
w
A
r
S: Set if negative result
Z: Set if zero result
Logically AND the contents of the r register and the Accu-
mulator.
H: Set if carry from bit 3
A
w
A ! r
S: Set if result is negative
Z: Set if result is zero
H: Set
P/V: Set if result exceeds 2’s com-
plement range
N: Reset
P/V: Set if result parity is even
N: Reset
C: Set if carry from bit 7
C: Reset
36
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
0
0
r
0
0
r
1
0
0
Timing:
M cyclesÐ1
Timing:
M cyclesÐ1
T statesÐ4
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐImplied
Addressing Mode:
SourceÐRegister
DestinationÐRegister
OR
r
CP
r
Logically OR the contents of the r register and the Accumu-
lator.
Compare the contents of register r with the Accumulator
and set the flags accordingly.
b
A
w
A ¶ r
S: Set if result is negative
Z: Set if result is zero
H: Reset
A
r
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result parity is even
N: Reset
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Reset
C: Set according to borrow
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
1
0
r
1
0
1
1
1
r
Timing:
M cyclesÐ1
Timing:
M cyclesÐ1
T statesÐ4
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐImplied
Addressing Mode:
SourceÐRegister
DestinationÐImplied
XOR
r
DEC
r
Logically exclusively OR the contents of the r register with
the Accumulator.
Decrement the contents of register r.
b
Z
A
w
A
r
S: Set if result is negative
Z: Set if result is zero
H: Reset
r
w
r
1
S: Set if result is negative
Z: Set if result is zero
H: Set according to a borrow from
bit 4
P/V: Set if result parity is even
N: Reset
P/V: Set only if r was X’80 prior to
operation
C: Reset
N: Set
7
6
5
4
3
2
1
0
C: N/A
1
0
1
0
1
r
7
6
5
4
3
2
1
0
Timing:
M cyclesÐ1
0
0
r
1
0
1
T statesÐ4
Timing:
M cyclesÐ1
Addressing Mode:
SourceÐRegister
DestinationÐImplied
T statesÐ4
Addressing Mode:
SourceÐRegister
DestinationÐRegister
INC
r
Increment register r.
CPL
a
r
w
r
1
S: Set if result is negative
Z: Set if result is zero
Complement the Accumulator (1’s complement).
A
w
A
S: N/A
Z: N/A
H: Set
H: Set if carry from bit 3
P/V: Set only if r was X’7F before
operation
P/V: N/A
N: Set
N: Reset
C: N/A
C: N/A
37
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
DAA
0
0
1
0
1
1
1
1
Adjust the Accumulator for BCD addition and subtraction
operations. To be executed after BCD data has been oper-
ated upon the standard binary ADD, ADC, INC, SUB, SBC,
DEC or NEG instructions (see ‘‘Register Addressing Arith-
metic’’ table).
Timing:
M cyclesÐ1
T statesÐ4
Implied
Addressing Mode:
ÐÐÐ
S: Set according to bit 7 of result
Z: Set if result is zero
NEG
Negate the Accumulator (2’s complement).
H: Set according to instructions
P/V: Set according to parity of result
N: N/A
b
A
w
0
A
S: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 4
C: Set according to instructions
7
6
5
4
3
2
1
0
P/V: Set only if Accumulator was
X’80 prior to operation
0
0
1
0
0
1
1
1
N: Set
Timing:
M cyclesÐ1
C: Set only if Accumulator was not
X’00 prior to operation
T statesÐ4
Implied
Addressing Mode:
7
6
5
4
3
2
1
0
IMMEDIATELY ADDRESSED ARITHMETIC
ADD A, n
1
1
1
0
1
1
0
1
0
1
0
0
0
1
0
0
Add the immediate data n to the Accumulator.
a
A
w
A
n
S: Set if result is negative
Z: Set if result is zero
Timing:
M cyclesÐ2
T statesÐ8 (4, 4)
Implied
H: Set if carry from bit 3
Addressing Mode:
P/V: Set if result exceeds 8-bit 2’s
complement range
CCF
Complement the carry flag.
N: Reset
CY
w
CY
S: N/A
C: Set if carry from bit 7
Z: N/A
7
6
5
4
3
2
1
0
H: Previous carry
1
1
0
0
0
1
1
0
P/V: N/A
N: Reset
n
C: Complement of previous carry
Timing:
M cyclesÐ2
7
6
5
4
3
2
1
0
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
0
0
1
1
1
1
1
1
Addressing Mode:
Timing:
M cyclesÐ1
T statesÐ4
Implied
ADC
A, n
Addressing Mode:
Add, with carry, the immediate data n and the Accumulator.
SCF
a
a
CY
A
w
A
n
S: Set if result is negative
Z: Set if result is zero
Set the carry flag.
CY
w
1
S: N/A
Z: N/A
H: Reset
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
P/V: N/A
N: Reset
C: Set
N: Reset
C: Set according to carry from bit
7
7
6
5
4
3
2
1
0
0
0
1
1
0
1
1
1
Timing:
M cyclesÐ1
T statesÐ4
Implied
Addressing Mode:
38
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
AND
n
1
1
0
0
1
1
1
0
The immediate data n is logically AND’ed to the Accumula-
tor.
A
w
A ! n
S: Set if result is negative
Z: Set if result is zero
H: Set
n
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
P/V: Set if result parity is even
N: Reset
Addressing Mode:
C: Reset
SUB
n
7
6
5
4
3
2
1
0
Subtract the immediate data n from the Accumulator.
1
1
1
0
0
1
1
0
b
A
w
A
n
S: Set if result is negative
Z: Set if result is zero
n
H: Set if borrow from bit 4
Timing:
M cyclesÐ2
P/V: Set if result exceeds 8-bit 2’s
complement range
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
N: Set
Addressing Mode:
C: Set according to borrow
condition
OR
n
7
6
5
4
3
2
1
0
The immediate data n is logically OR’ed to the contents of
the Accumulator.
1
1
0
1
0
1
1
0
A
w
A ¶ s
S: Set if result is negative
Z: Set if result is zero
H: Reset
n
Timing:
M cyclesÐ2
P/V: Set if result parity is even
N: Reset
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
Addressing Mode:
C: Reset
7
6
5
4
3
2
1
0
SBC
A, n
1
1
1
1
0
1
1
0
Subtract, with carry, the immediate data n from the Accumu-
lator.
n
b
b
CY
A
w
A
n
S: Set if result is negative
Z: Set if result is zero
Timing:
M cyclesÐ2
H: Set if borrow from bit 4
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
P/V: Set if result exceeds 8-bit 2’s
complement range
Addressing Mode:
N: Set
XOR
n
C: Set according to borrow
condition
The immediate data n is exclusively OR’ed with the Accu-
mulator.
7
6
5
4
3
2
1
0
Z
A
w
A
n
S: Set if result is negative
Z: Set if result is zero
H: Reset
1
1
0
1
1
1
1
0
n
P/V: Set if result parity is even
N: Reset
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
C: Reset
Addressing Mode:
39
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
a
a
e
e
ADD A, (IX
ADD A, (IY
d) (for N
d) (for N
0)
1)
X
1
1
1
0
1
1
1
0
1
1
N
1
1
1
0
1
X
X
n
1
0
0
0
0
1
1
0
Timing:
M cyclesÐ2
d
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
Timing:
M cyclesÐ5
Addressing Mode:
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
Addressing Mode:
CP
n
DestinationÐImplied
Compare the immediate data n with the contents of the Ac-
cumulator via subtraction and return the appropriate flags.
The contents of the Accumulator are not affected.
ADC
A, m
1
Add the contents of the memory location m plus the carry
1
to the Accumulator.
b
A
n
S: Set if result is negative
Z: Set if result is zero
a
a
A
w
A
m
1
CY S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow condi-
tion
N: Reset
C: Set according to carry from bit
7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
ADC A, (HL)
n
Timing:
M cyclesÐ2
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
T statesÐ7 (4, 3)
Immediate
Addressing Mode:
SourceÐRegister Indirect
DestinationÐImplied
Addressing Mode:
7
6
5
4
3
2
1
0
MEMORY ADDRESSED ARITHMETIC
ADD A, m1
a
a
e
e
ADC A, (IX
ADC A, (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
X
Add the contents of the memory location m to the Accumu-
1
lator.
1
0
0
0
1
1
1
0
a
A
w
A
m
1
S: Set if result is negative
Z: Set if result is zero
d
H: Set if carry from bit 3
Timing:
M cyclesÐ5
P/V: Set if result exceeds 8-bit 2’s
complement range
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
Addressing Mode:
N: Reset
DestinationÐImplied
C: Set according to carry from bit
7
SUB
m
1
Subtract the contents of memory location m from the Ac-
1
cumulator.
7
6
5
4
3
2
1
0
1
0
0
0
0
1
1
0
ADD A, (HL)
b
A
w
A
m
1
S: Set if result is negative
Z: Set if result is zero
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
H: Set if borrow from bit 4
Addressing Mode:
SourceÐRegister Indirect
DestinationÐImplied
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow condi-
tion
40
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
AND
m
1
1
0
0
1
0
1
1
0
SUB (HL)
The data in memory location m is logically AND’ed to the
1
Accumulator.
Timing:
M cyclesÐ2
A
w
A ! m
S: Set if result is negative
Z: Set if result is zero
H: Set
1
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
Addressing Mode:
P/V: Set if result parity is even
N: Reset
7
6
5
4
3
2
1
0
a
a
e
e
SUB (IX
SUB (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
C: Reset
X
7
6
5
4
3
2
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
AND (HL)
d
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
Timing:
M cyclesÐ5
Addressing Mode:
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
Addressing Mode:
7
6
5
4
3
2
1
0
a
a
e
e
DestinationÐImplied
AND (IX
AND (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
SBC
A, m
1
X
Subtract, with carry, the contents of memory location m
from the Accumulator.
1
1
0
1
0
0
1
1
0
b
b
A
w
A
m
1
CY S: Set if result is negative
Z: Set if result is zero
d
H: Set if carry from bit 3
Timing:
M cyclesÐ5
P/V: Set if result exceeds 8-bit 2’s
complement range
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
Addressing Mode:
N: Set
DestinationÐImplied
C: Set according to borrow
condition
OR
m
1
The data in memory location m is logically OR’ed with the
1
Accumulator.
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
SBC A, (HL)
A
w
A ¶ m
S: Set if result is negative
Z: Set if result is zero
H: Reset
1
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
P/V: Set if result parity is even
N: Reset
Addressing Mode:
SourceÐRegister Indirect
DestinationÐImplied
7
6
5
4
3
2
1
0
C: Reset
a
a
e
e
SBC A, (IX
SBC A, (IY
d) (for N
d) (for N
0)
1)
X
7
6
5
4
3
2
1
0
1
1
N
X
1
1
1
0
1
X
1
0
1
1
0
1
1
0
OR (HL)
1
0
0
1
1
1
1
0
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indexed
DestinationÐImplied
d
Addressing Mode:
Timing:
M cyclesÐ5
7
6
5
4
3
2
1
0
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
a
a
e
e
OR (IX
OR (IY
d) (for N
d) (for N
0)
1)
X
Addressing Mode:
1
1
N
X
1
1
1
0
1
X
DestinationÐImplied
1
0
1
1
0
1
1
0
d
Timing:
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
Addressing Mode:
DestinationÐImplied
41
12.6 8-Bit Arithmetic (Continued)
Timing:
M cyclesÐ5
XOR
m
1
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
The data in memory location m is exclusively OR’ed with
1
the data in the Accumulator.
Addressing Mode:
Z
DestinationÐImplied
A
w
A
m
1
S: Set if result is negative
Z: Set if result is zero
H: Reset
INC
m
1
Increment data in memory location m .
1
P/V: Set if result parity is even
N: Reset
a
m
1 w
m
1
1
S: Set if result is negative
Z: Set if result is zero
C: Reset
H: Set according to carry from bit
3
7
6
5
4
3
2
1
0
P/V: Set if data was X’7F before op-
eration
1
0
1
0
1
1
1
0
XOR (HL)
Timing:
M cyclesÐ2
N: Reset
C: N/A
T statesÐ7 (4, 3)
SourceÐRegister Indexed
DestinationÐImplied
Addressing Mode:
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
0
INC (HL)
7
6
5
4
3
2
1
0
a
a
e
e
XOR (IX
XOR (IY
d) (for N
d) (for N
0)
1)
X
Timing:
M cyclesÐ3
1
1
N
X
1
1
1
0
1
X
T statesÐ11 (4, 4, 3)
SourceÐRegister Indexed
DestinationÐRegister Indexed
Addressing Mode:
1
0
1
0
1
1
1
0
7
6
5
4
3
2
1
0
d
a
a
e
e
INC (IX
INC (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
Timing:
M cyclesÐ5
X
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
0
0
1
1
0
1
0
0
Addressing Mode:
DestinationÐImplied
d
CP
m
1
Timing:
M cyclesÐ6
Compare the data in memory location m with the data in
1
the Accumulator via subtraction.
T statesÐ23 (4, 4, 3, 5, 4, 3)
SourceÐIndexed
Addressing Mode:
b
A
m
S: Set if result is negative
Z: Set if result is zero
1
DestinationÐIndexed
H: Set if borrow from bit 4
DEC
m
1
P/V: Set if result exceeds 8-bit 2’s
complement range
Decrement data in memory location m .
1
b
m
1 w
m
1
1
S: Set if result is negative
Z: Set if result is zero
N: Set
C: Set according to borrow
condition
H: Set according to borrow from
bit 4
7
6
5
4
3
2
1
0
P/V: Set only if m was X’80 before
1
operation
1
0
1
1
1
1
1
0
CP (HL)
N: Set
Timing:
M cyclesÐ2
C: N/A
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
Addressing Mode:
7
6
5
4
3
2
1
0
a
a
e
e
CP (IX
CP (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
X
1
0
1
1
1
1
1
0
d
42
P/V: Set if result exceeds 16-bit 2’s
complement range
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
N: Reset
0
0
1
1
0
1
0
1
DEC (HL)
C: Set if carry out of bit 15
7
6
5
4
3
2
1
0
Timing:
M cycles Ð 3
T states Ð 11 (4, 4, 3)
Source Ð Register Indexed
1
1
1
0
1
1
0
1
Addressing Mode:
Destination
dexed
Ð
Register In-
0
1
pp
1
0
1
0
Timing:
M cycles Ð 4
7
6
5
4
3
2
1
0
a
e
e
DEC (IX
DEC (IY
d) (for N
d) (for N
0)
1)
X
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
1
1
N
X
1
1
1
0
1
a
Addressing Mode:
X
0
0
1
1
0
1
0
1
SBC
HL, pp
Subtract, with carry, the contents of the 16-bit pp register
from the 16-bit HL register.
d
Timing:
M cycles Ð 6
b
b
CY
HL
w
HL
pp
T states Ð 23 (4, 4, 3, 5, 4, 3)
Source Ð Indexed
S: Set if result is negative
Z: Set if result is zero
Addressing Mode:
Destination Ð Indexed
H: Set according to borrow from
bit 12
12.7 16-Bit Arithmetic
ss, pp
P/V: Set if result exceeds 16-bit 2’s
complement range
ADD
N: Set
Add the contents of the 16-bit register rp or pp to the con-
tents of the 16-bit register ss.
C: Set according to borrow condi-
tion
a
ss
w
w
ss
or
ss
rp
S: N/A
7
6
5
4
3
2
1
0
Z: N/A
a
ss
pp
H: Set if carry from bit 11
P/V: N/A
1
1
1
0
1
1
0
1
0
1
pp
0
0
1
0
N: Reset
C: Set if carry from bit 15
Timing:
M cycles Ð 4
7
6
5
4
3
2
1
0
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
0
0
rp
1
0
0
1
ADD HL, rp
Addressing Mode:
Timing:
M cycles Ð 3
T states Ð 11 (4, 4, 3)
Source Ð Register
Destination Ð Register
INC
rr
Addressing Mode:
Increment the contents of the 16-bit register rr.
a
rr
w
6
rr
1
No flags affected
7
6
5
4
3
2
1
0
7
5
4
3
2
1
0
INC BC
INC DE
INC HL
INC SP
e
e
ADD IX, pp (for N
ADD IY, pp (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
0
0
rp
0
0
1
1
X
0
0
pp
1
0
0
1
Timing:
M cycles Ð 4
Timing:
M cycles Ð 1
T states Ð 6
Register
0
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
Addressing Mode:
Addressing Mode:
7
6
5
4
3
2
1
e
e
INC IX (for N
0)
1)
X
ADC
HL, pp
1
1
N
1
1
1
0
1
X
INC IY (for N
X
The contents of the 16-bit register pp are added, with the
carry bit, to the HL register.
0
0
1
0
0
0
1
1
a
a
CY
HL
w
HL
pp
Timing:
M cycles Ð 2
S: Set if result is negative
Z: Set if result is zero
T states Ð 10 (4, 6)
Register
Addressing Mode:
H: Set according to carry out of bit
11
43
7
6
5
4
3
2
1
0
12.7 16-Bit Arithmetic (Continued)
1
1
0
0
1
0
1
1
DEC
rr
Decrement the contents of the 16-bit register rr.
0
1
b
r
b
rr
w
6
rr
1
No flags affected
7
5
4
3
2
1
0
DEC BC
DEC DE
DEC HL
DEC SP
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
0
0
rp
1
0
1
1
Addressing Mode:
MEMORY
SET
b, m
1
Timing:
M cycles Ð 1
T states Ð 6
Register
0
Bit b in memory location m is set.
1
m
1b w
6
1
No flags affected
Addressing Mode:
7
5
4
3
2
1
0
7
6
5
4
3
2
1
e
e
DEC IX (for N
0)
1)
X
1
1
0
0
1
0
1
1
SET b, (HL)
1
1
N
X
1
1
1
0
1
DEC IY (for N
X
1
1
b
1
1
0
0
0
1
0
1
0
1
1
Timing:
M cycles Ð 4
Timing:
M cycles Ð 2
T states Ð 15 (4, 4, 4, 3)
Bit/Register Indirect
T states Ð 10 (4, 6)
Register
Addressing Mode:
Addressing Mode:
7
6
5
4
3
2
1
0
a
SET b, (IX d) (for N
e
e
0)
1)
X
12.8 Bit Set, Reset, and Test
REGISTER
1
1
N
X
1
1
1
0
1
a
SET b, (IY d) (for N
X
1
1
1
1
0
0
1
0
1
1
0
SET
b, r
Bit b in register r is set.
d
R
b w
6
1
No flags affected
7
5
4
3
2
1
0
b
1
1
1
1
0
0
1
0
1
1
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Bit/Indexed
1
1
b
r
Addressing Mode:
RES b, m
Bit b in memory location m is reset.
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
1
1
Addressing Mode:
RES b, r
Bit b in register r is reset.
m
1b w
6
0
No flags affected
7
5
4
3
2
1
0
1
1
0
0
1
0
1
1
RES b, (HL)
r
b w
6
0
No flags affected
7
5
4
3
2
1
0
1
0
b
1
1
0
1
1
0
0
1
0
1
1
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Bit/Register Indirect
1
0
b
r
Addressing Mode:
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
7
6
5
4
3
2
1 0
a
RES b, (IX d) (for N
e
e
0)
1)
X
1
1
N
X
1
1
1
0
1
Addressing Mode:
BIT b, r
Bit b in register r is tested with the result put in the Z flag.
a
RES b, (IY d) (for N
X
1
1
1
0
0
0
1
0
1
1
1
Z
w
r
b
S: Undefined
Z: Inverse of tested bit
H: Set
d
b
1
0
P/V: Undefined
N: Reset
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Bit/Indexed
C: N/A
Addressing Mode:
44
7
6
5
4
3
2
1
0
12.8 Bit Set, Reset, and Test (Continued)
0
0
0
0
0
1
1
1
RLCA
BIT
B, m
1
Bit b in memory location m is tested via the Z flag.
1
Timing:
M cycles Ð 1
T states Ð 4
Implied
Z
w
m
S: Undefined
Z: Inverse of tested bit
H: Set
1b
Addressing Mode:
(Note RLCA does not affect S, Z, or P/V flags.)
RL
Rotate register r left through carry.
P/V: Undefined
N: Reset
r
C: N/A
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
BIT b, (HL)
0
1
b
1
1
0
TL/C/5171–58
Timing:
M cycles Ð 3
S: Set if result is negative
T states Ð 12 (4, 4, 4)
Bit/Register Indirect
Z: Set if result is zero
H: Reset
Addressing Mode:
7
6
5
4
3
2
1
0
a
BIT b, (IX d) (for N
e
e
P/V: Set if result parity is even
N: Reset
0)
1)
X
1
1
N
X
1
1
1
0
1
a
BIT b, (IY d) (for N
X
C: Set according to bit 7 of r
1
0
1
1
0
0
1
0
1
1
1
1
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
RL r
d
0
0
0
1
0
r
(Note alternate for
A register below)
b
0
Timing:
M cycles Ð 5
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
T states Ð 20 (4, 4, 3, 5, 4)
Bit/Indexed
Addressing Mode:
Addressing Mode:
7
6
5
4
3
2
1
0
12.9 Rotate and Shift
REGISTER
0
0
0
1
0
1
1
1
RLA
Timing:
M cycles Ð 1
T states Ð 4
Implied
RLC
r
Rotate register r left circular.
Addressing Mode:
(Note RLA does not affect S, Z, or P/V flags.)
RRC
Rotate register r right circular.
r
TL/C/5171–57
S: Set if result is negative
Z: Set if result is zero
H: Reset
TL/C/5171–59
P/V: Set if result parity is even
N: Reset
S: Set if result is negative
Z: Set if result is zero
H: Reset
C: Set according to bit 7 of r
7
6
5
4
3
2
1
0
P/V: Set if result parity is even
N: Reset
1
1
0
0
1
0
1
1
RLC r
C: Set according to bit 0 of r
0
0
0
0
0
r
(Note alternate for
A register below)
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
Addressing Mode:
45
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
P/V: Set if result parity is even
N: Reset
1
1
0
0
1
0
1
1
RRC r
C: Set according to bit 7 of r
7
6
5
4
3
2
1
0
0
0
0
0
1
r
(Note alternate for
A register below)
1
1
0
0
1
0
1
1
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
0
0
1
0
0
r
Addressing Mode:
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
7
6
5
4
3
2
1
0
Addressing Mode:
SRA
Shift register r right arithmetic.
0
0
0
0
1
1
1
1
RRCA
r
Timing:
M cycles Ð 1
T states Ð 4
Implied
Addressing Mode:
(Note RRCA does not affect S, Z, or P/V flags.)
RR
Rotate register r right through carry.
r
TL/C/5171–62
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
TL/C/5171–60
C: Set according to bit 0 of r
S: Set if result is negative
7
6
5
4
3
2
1
0
Z: Set if result is zero
H: Reset
1
1
0
0
1
0
1
1
P/V: Set if result parity is even
N: Reset
0
0
1
0
1
r
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
C: Set according to bit 0 of r
7
6
5
4
3
2
1
0
Addressing Mode:
SRL
Shift register r right logical.
1
1
0
0
1
0
0
1
RR r
r
0
0
0
1
1
r
(Note alternate for
A register below)
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
Addressing Mode:
TL/C/5171–63
7
6
5
4
3
2
1
0
S: Reset
Z: Set if result is zero
H: Reset
0
0
0
1
1
1
1
1
RRA
Timing:
M cycles Ð 1
T states Ð 4
Implied
P/V: Set if result parity is even
N: Reset
Addressing Mode:
C: Set according to bit 0 of r
(Note RRA does not affect S, Z, or P/V flags.)
SLA
Shift register r left arithmetric.
7
6
5
4
3
2
1
0
r
1
1
0
0
1
0
1
1
0
0
1
1
1
r
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
TL/C/5171–61
Addressing Mode:
S: Set if result is negative
Z: Set if result is zero
H: Reset
46
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
MEMORY
1
1
0
0
1
0
1
1
RL (HL)
RLC
m
1
Rotate date in memory location m left circular.
1
0
0
0
1
0
1
1
0
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
0
Addressing Mode:
7
6
5
4
3
2
1
a
e
0)
RL (IX d) (for N
X
TL/C/5171–64
1
1
N
X
1
1
1
0
1
a
e
RL (IY d) (for NX 1)
S: Set if result is negative
Z: Set if result is zero
H: Reset
1
0
1
0
0
0
0
1
0
0
1
1
P/V: Set if result parity is even
N: Reset
d
C: Set according to bit 7 of m
1
1
1
1
0
7
6
5
4
3
2
1
0
Timing:
M cycles Ð 6
1
1
0
0
1
0
1
1
RLC (HL)
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
RRC
Rotate the data in memory location m right circular.
0
0
0
0
0
1
1
0
m
1
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register indirect
0
1
Addressing Mode:
7
6
5
4
3
2
1
a
e
RLC (IX d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
a
RLC (IY d) (for N
e
X
1
0
1
0
0
0
0
1
0
0
1
1
TL/C/5171–66
d
S: Set if result is negative
Z: Set if result is zero
H: Reset
0
1
1
0
P/V: Set if result parity is even
N: Reset
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
C: Set according to bit 0 of m
Addressing Mode:
RL
1
7
6
5
4
3
2
1
0
m
1
1
1
0
0
1
0
1
1
1
RRC (HL)
Rotate the data in memory location m left though carry.
1
0
0
0
0
1
1
0
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
Addressing Mode:
7
6
5
4
3
2
1
0
TL/C/5171–65
S: Set if result is negative
Z: Set if result is zero
H: Reset
a
a
e
e
RRC (IX
RRC (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
0
1
1
X
1
1
0
0
0
0
1
1
1
0
P/V: Set if result parity is even
N: Reset
d
0
0
1
1
C: Set according to bit 7 of m
1
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
47
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
RR
m
1
a
a
e
e
SLA (IX
SLA (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
Rotate the data in memory location m right through the
1
carry.
X
1
1
0
1
0
0
1
0
0
1
1
1
1
0
d
0
0
Timing:
M cycles Ð 6
TL/C/5171–67
S: Set if result is negative
Z: Set if result is zero
H: Reset
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
SRA
Shift the data in memory location m right arithmetic.
m
1
1
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of m
1
7
6
5
4
3
2
1
0
TL/C/5171–69
1
1
0
0
1
0
1
1
0
RR (HL)
S: Set if result is negative
Z: Set if result is zero
H: Reset
0
0
0
1
1
1
1
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
P/V: Set if result parity is even
N: Reset
Addressing Mode:
7
6
5
4
3
2
1
0
C: Set according to bit 0 of m
1
a
a
e
e
RR (IX
RR (IY
d) (for N
d) (for N
0)
1)
X
7
6
5
4
3
2
1
0
1
1
N
X
1
1
1
0
0
1
1
X
1
1
0
0
1
0
1
1
SRA (HL)
1
1
0
0
0
1
1
1
0
0
0
1
0
1
1
1
0
d
Timing:
M cycles Ð 4
0
0
1
1
1
T states Ð 15 (4, 4, 4, 3)
Register Indirect
Addressing Mode:
Timing:
M cycles Ð 6
7
6
5
4
3
2
1
0
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
a
a
e
e
SRA (IX
SRA (IY
d) (for N
d) (for N
0)
1)
X
Addressing Mode:
SLA
Shift the data in memory location m left arithmetic.
1
1
N
X
1
1
1
0
0
1
1
X
m
1
1
1
0
1
0
0
1
1
1
0
1
d
0
0
1
1
Timing:
M cycles Ð 6
TL/C/5171–68
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
S: Set if result is negative
Z: Set if result is zero
H: Reset
Addressing Mode:
SRL
Shift right logical the data in memory location m .
m
1
1
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of m
1
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
1
SLA (HL)
TL/C/5171–70
0
0
1
0
0
1
0
S: Reset
Z: Set if result is zero
H: Reset
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
P/V: Set if result parity is even
N: Reset
Addressing Mode:
C: Set according to bit 0 of m
1
48
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
RRD
1
1
0
0
1
0
1
1
SRL (HL)
Rotate digit right and left between the Accumulator and
memory (HL).
0
0
1
1
1
1
1
0
Timing:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
Addressing Mode:
TL/C/5171–72
7
6
5
4
3
2
1
0
a
a
e
e
SRL (IX
SRL (IY
d) (for N
d) (for N
0)
1)
X
1
1
N
X
1
1
1
0
0
1
1
S: Set if result is negative
Z: Set if result is zero
H: Reset
X
1
1
0
1
0
1
1
1
1
0
d
P/V: Set if result parity is even
N: Reset
0
0
1
1
C: N/A
Timing:
M cycles Ð 6
7
6
5
4
3
2
1
0
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
1
1
1
0
1
1
0
1
Addressing Mode:
0
1
1
0
0
1
1
1
REGISTER/MEMORY
RLD
Timing:
M cycles Ð 5
T states Ð 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
Rotate digit left and right between the Accumulator and
memory (HL).
Addressing Mode:
12.10 Exchanges
REGISTER/REGISTER
EX
DE, HL
TL/C/5171–71
Exchange the contents of the 16-bit register pairs DE and
HL.
S: Set if result is negative
Z: Set if result is zero
H: Reset
DE
Ý
6
HL
No flags affected
7
5
4
3
2
1
0
1
1
1
0
1
0
1
1
P/V: Set if result parity is even
N: Reset
Timing:
M cycles Ð 1
T states Ð 4
Register
C: N/A
Addressing Mode:
EX AF, A’F’
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
The contents of the Accumulator and flag register are ex-
changed with their corresponding alternate registers, that is
A and F are exchanged with A’ and F’.
0
1
1
0
1
1
1
1
Timing:
M cycles Ð 5
A
F
Ý
Ý
A’
F’
5
No flags affected
T states Ð 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
Addressing Mode:
7
6
4
3
2
1
0
0
0
0
0
1
0
0
0
Timing:
M cycles Ð 1
T states Ð 4
Register
Addressing Mode:
49
LDD
12.10 Exchanges (Continued)
Move data from memory location (HL) to memory location
(DE), and decrement memory pointer and byte counter BC.
EXX
Exchange the contents of the BC, DE, and HL registers with
their corresponding alternate register.
(DE)
w
(HL)
S: N/A
Z: N/A
H: Reset
b
DE
HL
BC
w
w
w
DE
1
BC
DE
HL
7
Ý
Ý
Ý
B’C’
D’E’
H’L’
4
No flags affected
b
b
HL
BC
1
b
1 i0, other-
1
P/V: Set if BC
wise reset
6
5
3
2
1
0
N: Reset
C: N/A
0
1
1
0
1
1
0
0
1
7
6
5
4
3
2
1
Timing:
M cycles Ð 1
T states Ð 4
Implied
1
1
1
0
1
1
1
0
1
Addressing Mode:
REGISTER/MEMORY
EX (SP), ss
1
0
1
0
0
0
0
Timing:
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
Exchange the two bytes at the top of the external memory
stack with the 16-bit register ss.
Addressing Mode:
CPI
(SP)
(SP
7
Ý
1)
SS
No flags affected
L
Compare data in memory location (HL) to the Accumulator,
increment the memory pointer, and decrement the byte
counter. The Z flag is set if the comparison is equal.
a
Ý
4
SS
H
6
5
3
2
1
0
1
1
1
0
0
0
1
1
EX (SP), HL
b
A
(HL)
S: Set if result of comparison sub-
tract is negative
a
b
HBCL w HBLC
w
w
1
1
Timing:
M cycles Ð 5
Z: Set if result of comparison is
zero
T states Ð 19 (4, 3, 4, 3, 5)
Register/Register Indirect
Z
1
Addressing Mode:
e
if A
(HL)
H: Set according to borrow from
bit 4
7
6
5
4
3
2
1
0
e
e
EX (SP), IX (for N
0)
1)
X
1
1
N
X
1
1
1
0
0
1
1
b
P/V: Set if BC
reset
1i 0, otherwise
EX (SP),IY (for N
X
1
1
1
0
0
1
N: Set
Timing:
M cycles Ð 6
C: N/A
T states Ð 23 (4, 4, 3, 4, 3, 5)
Register/Register Indirect
7
6
5
4
3
2
1
0
Addressing Mode:
1
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
12.11 Memory Block Moves and
Searches
SINGLE OPERATIONS
LDI
Timing:
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
Addressing Mode:
CPD
Move data from memory location (HL) to memory location
(DE), increment memory pointers, and decrement byte
counter BC.
Compare data in memory location (HL) to the Accumulator,
and decrement the memory pointer and byte counter. The Z
flag is set if the comparison is equal.
(DE)
w
(HL)
S: N/A
Z: N/A
H: Reset
b
A
(HL)
S: Set if result is negative
a
DE
HL
BC
w
w
w
DE
1
b
b
HL
BC
w
w
HL
BC
1
Z: Set if result of comparison is
zero
a
b
HL
BC
1
1
b
1 i0, other-
1
P/V: Set if BC
wise reset
H: Set according to borrow from
bit 4
Z
w
1
e
N: Reset
C: N/A
0
if A
(HL)
P/V: Set if BC
reset
1i 0, otherwise
b
7
6
5
4
3
2
1
N: Set
1
1
1
0
1
0
1
0
1
C: N/A
1
0
1
0
0
0
0
Timing:
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
Addressing Mode:
50
12.11 Memory Block Moves and Searches (Continued)
7
6
5
4
3
2
1
0
CPIR
1
1
1
0
1
1
0
1
Compare data in memory location (HL) to the Accumulator,
increment the memory, decrement the byte counter BC, and
1
0
1
0
1
0
0
1
e
repeat until BC
0 or (HL) equals A.
b
A
(HL)
S: Set if sign of subtraction per-
formed for comparison is nega-
tive
Timing:
M cycles Ð 4
a
b
HL
BC
w
w
HL
BC
1
T states Ð 16 (4, 4, 3, 5)
Register Indirect
1
Addressing Mode:
e
Z: Set if A
(HL), otherwise reset
e
Repeat until BC
0
REPEAT OPERATIONS
LDIR
H: Set according to borrow from
bit 4
e
or A
(HL)
i
0, otherwise
b
P/V: Set if BC
reset
1
Move data from memory location (HL) to memory location
(DE), increment memory pointers, decrement byte counter
e
N: Set
BC, and repeat until BC
0.
C: N/A
(DE)
w
(HL)
S: N/A
7
6
5
4
3
2
1
0
a
DE
HL
BC
w
w
DE
1
Z: N/A
a
b
HL
BC
1
H: Reset
P/V: Reset
N: Reset
C: N/A
1
1
1
1
1
0
1
1
0
0
1
w
1
0
1
0
0
1
Repeat until
i
e
BC
0
Timing:
For BC
0
0
M cycles Ð 5
7
6
5
4
3
2
1
0
T states Ð 21 (4, 4, 3, 5, 5)
M cycles Ð 4
e
For BC
1
1
1
0
1
1
0
1
0
1
0
1
T states Ð 16 (4, 4, 3, 5)
Register Indirect
1
0
0
0
Addressing Mode:
For BCi
0
M cycles Ð 5
(Note that each repeat is accomplished by a decrement of
the PC, so that refresh, etc. continues for each cycle.)
Timing:
T states Ð 21 (4, 4, 3, 5, 5)
e
For BC 0 M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
CPDR
Compare data in memory location (HL) to the contents of
the Accumulator, decrement the memory pointer and byte
counter BC, and repeat until BC
the Accumulator.
Addressing Mode:
e
0, or until (HL) equals
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
b
A
(HL)
S: Set if sign of subtraction per-
formed for comparison is nega-
tive
LDDR
b
b
HL
BC
w
w
HL
BC
1
Move data from memory location (HL) to memory location
(DE), decrement memory pointers and byte counter BC, and
1
Z: Set according to equality of A
and (HL), set if true
e
Repeat until BC
0
e
repeat until BC
0.
e
or A
(HL)
(DE)
w
(HL)
S: N/A
Z: N/A
H: Set according to borrow from
bit 4
b
DE
HL
BC
w
w
w
DE
1
i
0, otherwise
b
P/V: Set if BC
reset
1
b
b
HL
BC
1
H: Reset
P/V: Reset
N: Reset
C: N/A
1
N: Set
Repeat until
C: N/A
e
BC
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
1
0
0
i
Timing:
For BC
0
0
M cycles Ð 5
Timing:
For BCi
0
M cycles Ð 5
T states Ð 21 (4, 4, 3, 5, 5)
M cycles Ð 4
T states Ð 21 (4, 4, 3, 5, 5)
e
For BC
e
For BC 0 M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
T states Ð 16 (4, 4, 3, 5)
Register Indirect
Addressing Mode:
Addressing Mode:
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
51
12.12 Input/Output
A, (n)
P/V: Undefined
N: Set
IN
Input data to the Accumulator from the I/O device at ad-
dress N.
C: N/A
7
6
5
4
3
2
1
0
A
w
6
(n)
No flags affected
7
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
n
Timing:
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
Timing:
M cycles Ð 3
Addressing Mode:
Implied/Source Ð Register In-
direct
T states Ð 11 (4, 3, 4)
Source Ð Direct
Addressing Mode:
Destination Ð Register Indirect
Destination Ð Register
OUTI
IN
r, (C)
Output data from memory location (HL) to the I/O device at
port address (C), increment the memory pointer, and decre-
ment the byte counter B.
Input data to register r from the I/O device addressed by the
e
contents of register C. If r 110 only flags are affected.
r
w
(C)
S: Set if result is negative
Z: Set if result is zero
H: Reset
(C)
w
(HL)
S: Undefined
b
b
e
1 0, otherwise reset
B
w
HL w
B
1
Z: Set if B
H: Undefined
P/V: Undefined
N: Set
a
HL
1
P/V: Set if result parity is even
N: Reset
C: N/A
C: N/A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
0
1
r
0
0
0
1
0
1
0
0
0
1
1
Timing:
M cycles Ð 3
Timing:
M cycles Ð 4
T states Ð 12 (4, 4, 4)
Source Ð Register Indirect
Destination Ð Register
T states Ð 16 (4, 5, 3, 4)
Addressing Mode:
Addressing Mode:
Implied/Source Ð Register In-
direct
OUT
(C), r
Destination Ð Register Indirect
Output register r to the I/O device addressed by the con-
tents of register C.
IND
Input data from I/O device at port address (C) to memory
location (HL), and decrement HL memory pointer and byte
counter B.
(C)
w
6
r
No flags affected
7
5
4
3
2
1
0
1
1
1
0
1
1
0
1
(HL)
w
w HL
(C)
S: Undefined
b
b
e
1 0, otherwise reset
HL
B
1
Z: Set if B
H: Undefined
P/V: Undefined
N: Set
0
1
r
0
0
1
b
B
w
1
Timing:
M cycles Ð 3
T states Ð 12 (4, 4, 4)
Source Ð Register
C: N/A
Addressing Mode:
7
6
5
4
3
2
1
0
Destination Ð Register Indirect
1
1
1
0
1
1
0
1
INI
Input data from the I/O device addressed by the contents of
register C to the memory location pointed to by the contents
of the HL register. The HL pointer is incremented and the
byte counter B is decremented.
1
0
1
0
1
0
1
0
Timing:
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
(HL)
w
B
(C)
S: Undefined
Addressing Mode:
Implied/Source Ð Register In-
direct
b
b
e
1 0, otherwise reset
B
w
HL w
1
Z: Set if B
a
HL
1
H: Undefined
Destination Ð Register Indirect
52
12.12 Input/Output (Continued)
7
6
5
4
3
2
1
0
OUT
(n), A
1
1
1
0
1
1
0
1
Output the Accumulator to the I/O device at address n.
(n)
w
6
A
No flags affected
1
0
1
1
0
0
1
0
7
5
4
3
2
1
0
i
1
1
0
1
0
0
1
1
Timing:
For B
0
M cycles Ð 5
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
n
e
For B
0
T states Ð 16 (4, 5, 3, 4)
Timing:
M cycles Ð 3
Addressing Mode:
Implied/Source Ð Register In-
direct
T states Ð 11 (4, 3, 4)
Source Ð Register
Destination Ð Direct
Addressing Mode:
Destination Ð Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be per-
formed.)
OUTD
Data is output from memory location (HL) to the I/O device
at port address (C), and the HL memory pointer and byte
counter B are decremented.
OTIR
Data is output to the I/O device at port address (C) from
memory location (HL), the HL memory pointer is increment-
ed, and the byte counter B is decremented. The cycles are
e
(C)
w
(HL)
S: Undefined
b
b
e
1 0, otherwise reset
B
w
HL w
B
1
Z: Set if B
H: Undefined
P/V: Undefined
N: Set
b
HL
1
repeated until B
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
C: N/A
(C)
HL
w
w
(HL)
S: Undefined
H: Undefined
Z: Set
7
6
5
4
3
2
1
0
a
HL
1
1
1
1
0
1
1
0
1
b
B
w
B
1
e
Repeat until B
0
P/V: Undefined
N: Set
1
0
1
0
1
0
1
1
Timing:
M cycles Ð 4
C: N/A
T states Ð 16 (4, 5, 3, 4)
7
6
5
4
3
2
1
0
Addressing Mode:
Implied/Source Ð Register In-
direct
1
1
1
0
1
1
0
1
Destination Ð Register Indirect
1
0
1
1
0
0
1
1
INIR
i
Timing:
For B
0
M cycles Ð 5
Data is input from the I/O device at port address (C) to
memory location (HL), the HL memory pointer is increment-
ed, and the byte counter B is decremented. The cycle is
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
e
For B
0
e
repeated until B
0.
T states Ð 16 (4, 5, 3, 4)
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
Addressing Mode:
Implied/Source Ð Register In-
direct
Destination Ð Register Indirect
(HL)
w
w HL
(C)
S: Undefined
Z: Set
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be per-
formed.)
a
HL
B
1
b
w
B
1
H: Undefined
P/V: Undefined
N: Set
e
Repeat until B
0
C: N/A
53
12.12 Input/Output (Continued)
12.13 CPU Control
NOP
INDR
Data is input from the I/O device at address (C) to memory
location (HL), then the HL memory pointer is byte counter B
The CPU performs no operation.
Ð Ð Ð
No flags affected
e
are decremented. The cycle is repeated until B
0.
7
6
5
4
3
2
1
0
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
0
0
0
0
0
0
0
0
Timing:
M cycles Ð 1
(HL)
w
w HL
(C)
S: Undefined
Z: Set
T states Ð 4
N/A
b
HL
B
1
Addressing Mode:
b
w
B
1
H: Undefined
P/V: Undefined
N: Set
HALT
e
Repeat until B
0
The CPU halts execution of the program. Dummy op-code
fetches are performed from the next memory location to
keep the refresh circuits active until the CPU is interrupted
or reset from the halted state.
C: N/A
7
6
5
4
3
2
1
0
Ð Ð Ð
No flags affected
1
1
1
0
1
1
0
1
7
6
5
4
3
2
1
0
0
1
1
1
0
1
1
0
1
0
1
1
0
0
1
0
i
Timing:
M cycles Ð 1
Timing:
For B
0
M cycles Ð 5
T states Ð 4
N/A
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
e
Addressing Mode:
For B
0
T states Ð 16 (4, 5, 3, 4)
DI
Addressing Mode:
Implied/Source Ð Register In-
direct
Disable system level interrupts.
IFF1 w
IFF2 w
0
0
No flags affected
Destination Ð Register Indirect
(Note that after each data transfer cycle, interrupts may be
recognized and two refresh cycles are performed.)
7
6
5
4
3
2
1
0
1
1
1
1
0
0
1
1
OTDR
Timing:
M cycles Ð 1
Data is output from memory location (HL) to the I/O device
at port address (C), then the HL memory pointer and byte
T states Ð 4
N/A
e
counter B are decremented. The cycle is repeated until B
0.
Addressing Mode:
EI
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
The system level interrupts are enabled. During execution of
this instruction, and the next one, the maskable interrupts
will be disabled.
(C)
HL
w
w
(HL)
S: Undefined
Z: Set
IFF1 w
IFF2 w
1
1
No flags affected
b
HL
1
b
B
w
B
1
H: Undefined
P/V: Undefined
N: Set
7
6
5
4
3
2
1
0
e
Repeat until B
0
1
1
1
1
1
0
1
1
C: N/A
Timing:
M cycles Ð 1
7
6
5
4
3
2
1
0
T states Ð 4
N/A
Addressing Mode:
IM
The CPU is placed in interrupt mode 0.
Ð Ð Ð No flags affected
1
1
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
i
Timing:
For B
0
M cycles Ð 5
7
6
5
4
3
2
1
0
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
e
For B
0
1
1
1
0
1
1
0
1
T states Ð 16 (4, 5, 3, 4)
0
1
0
0
0
1
1
0
Addressing Mode:
Implied/Source Ð Register In-
direct
Timing:
M cycles Ð 2
Destination Ð Register Indirect
T states Ð 8 (4, 4)
N/A
(Note that after each data transfer cycle the NSC800 will
accept interrupts and perform two refresh cycles.)
Addressing Mode:
54
7
6
5
4
3
2
1
0
12.13 CPU Control (Continued)
e
e
JP (IX) (for N
JP (IY) (for N
0)
1)
X
1
1
N
X
1
1
1
0
1
IM
The CPU is placed in interrupt mode 1.
Ð Ð Ð No flags affected
1
X
1
1
1
0
1
0
0
1
7
6
5
4
3
2
1
0
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register Indirect
1
1
1
0
1
1
0
1
Addressing Mode:
JP cc, nn
0
1
0
1
0
1
1
0
Conditionally jump to program location nn based on testable
flag states.
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
N/A
If cc true,
PC nn,
otherwise continue
No flags affected
Addressing Mode:
IM
The CPU is placed in interrupt mode 2.
Ð Ð Ð No flags affected
w
2
7
6
5
4
3
2
1
0
1
1
cc
0
1
0
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
n (low-order byte)
n (high-order byte)
0
1
0
1
1
1
1
0
Timing:
M cycles Ð 2
Timing:
M cycles Ð 3
T states Ð 8 (4, 4)
N/A
T states Ð 10 (4, 3, 3)
Direct
Addressing Mode:
Addressing Mode:
JR
d
12.14 Program Control
JUMPS
Unconditional jump to program location calculated with re-
spect to the program counter and the displacement d.
JP
nn
a
PC
w
6
PC
d
No flags affected
Unconditional jump to program location nn.
7
5
4
3
2
1
0
PC
w
6
nn
No flags affected
0
0
0
1
1
0
0
0
7
5
4
3
2
1
0
1
1
0
0
0
0
1
1
b
d 2
Timing:
M cycles Ð 3
n (low-order byte)
n (high-order byte)
T states Ð 12 (4, 3, 5)
PC Relative
Addressing Mode:
JR kk, d
Timing:
M cycles Ð 3
Conditionally jump to program location calculated with re-
spect to the program counter and the displacement d,
based on limited testable flag states.
T states Ð 10 (4, 3, 3)
Direct
Addressing Mode:
If kk true,
PC PC
otherwise continue
No flags affected
JP
(ss)
a
w
d,
Unconditional jump to program location pointed to by regis-
ter ss.
7
6
5
4
3
2
1
0
PC
w
6
ss
No flags affected
7
5
4
3
2
1
0
0
0
1
kk
0
0
0
1
1
1
0
1
0
0
1
JP (HL)
b
d
2
Timing:
M cycles Ð 1
T states Ð 4
Timing:
if kk met
(true)
M cycles Ð 3
Addressing Mode:
Register Indirect
T states Ð 12 (4, 3, 5)
M cycles Ð 2
if kk not met
(not true)
T states Ð 7 (4, 3)
PC Relative
Addressing Mode:
55
12.14 Program Control (Continued)
DJNZ
d
RETURNS
RET
Decrement the B register and conditionally jump to program
location calculated with respect to the program counter and
the displacement d, based on the contents of the B register.
Unconditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack.
b
B
w
e
B
1
No flags affected
PCL w (SP)
No flags affected
If B
0 continue,
a
PCH w (SP 1)
a
else PC
w
5
PC
d
a
SP
w
6
SP
2
7
6
4
3
2
1
0
7
5
4
3
2
1
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
Timing:
M cycles Ð 3
b
d
2
T states Ð 10 (4, 3, 3)
Register Indirect
i
Timing:
If B
0
M cycles Ð 3
Addressing Mode:
RET cc
T states Ð 13 (5, 3, 5)
M cycles Ð 2
e
If B
0
Conditional return from subroutine or other return to pro-
gram location pointed to by the top of the stack.
T states Ð 8 (5, 3)
PC Relative
Addressing Mode:
If cc true,
No flags affected
CALLS
PCL w (SP)
a
PCH w (SP 1)
CALL
nn
a
SP
w
else continue
SP
2,
Unconditional call to subroutine at location nn.
b
(SP 1)
w
w
b
PC
PC
2
No flags affected
H
L
7
6
5
4
3
2
1
0
b
(SP 2)
1
1
cc
0
0
0
SP
PC
7
w
w
6
SP
nn
Timing:
If cc true
M cycles Ð 3
5
4
3
2
1
0
T states Ð 11 (5, 3, 3)
M cycles Ð 1
1
1
0
0
1
1
0
1
If cc not true
T states Ð 5
n (low-order byte)
n (high-order byte)
Addressing Mode:
Register Indirect
RETI
Unconditional return from interrupt handling subroutine.
Functionally identical to RET instruction. Unique opcode al-
lows monitoring by external hardware.
Timing:
M Cycles Ð 5
T states Ð 17 (4, 3, 4, 3, 3)
Direct
PCL w (SP)
No flags affected
Addressing Mode:
a
PCH w (SP 1)
CALL
cc, nn
a
SP
w
6
SP
2
Conditional call to subroutine at location nn based on test-
able flag stages.
7
5
4
3
2
1
0
1
1
1
0
1
1
0
1
If cc true,
No flags affected
b
(SP 1)
w
w
b
PC
PC
2
H
L
0
1
0
0
1
1
0
1
b
(SP 2)
SP
PC
w
w
SP
Timing:
M cycles Ð 4
nn,
T states Ð 14 (4, 4, 3, 3)
Register Indirect
else continue
Addressing Mode:
7
6
5
4
3
2
1
0
1
1
cc
1
0
0
n (low-order byte)
n (high-order byte)
Timing:
If cc true
M cycles Ð 5
T states 17 (4, 3, 4, 3, 3)
M cycles Ð 3
If cc not true
T states Ð 10 (4, 3, 3)
Direct
Addressing Mode:
56
12.14 Program Control (Continued)
RETN
RESTARTS
RST
Unconditional return from non-maskable interrupt handling
subroutine. Functionally similar to RET instruction, except
interrupt enable state is restored to that prior to non-mask-
able interrupt.
P
The present contents of the PC are pushed onto the memo-
ry stack and the PC is loaded with dedicated program loca-
tions as determined by the specific restart executed.
PCL w (SP)
No flags affected
b
(SP 1)
w
w
b
PC
PC
2
No flags affected
H
a
PCH w (SP 1)
b
(SP 2)
L
a
SP
w
IFF1 w IFF
SP
2
SP
w
PCH w
PCL w
SP
2
0
7
6
5
4
3
2
1
0
P
1
1
1
0
0
1
1
0
1
7
6
5
4
3
2
1
0
1
1
t
1
1
1
0
1
0
0
1
0
1
Timing:
M cycles Ð 3
Timing:
M cycles Ð 4
T states Ð 11 (5, 3, 3)
Modified Page Zero
T states Ð 14 (4, 4, 3, 3)
Register Indirect
Addressing Mode:
Addressing Mode:
p
t
00H 08H 10H 18H 20H 28H 30H 38H
000 001 010 011 100 101 110 111
57
12.15 Instruction Set: Alphabetical Order
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
BIT
A, (HL)
8E
DD 8Ed
FD 8Ed
8F
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
0, B
CB 40
a
A, (IX d)
0, C
0, D
0, E
CB 41
a
A, (IY d)
CB 42
A, A
CB 43
A, B
88
0, H
0, L
CB 44
A, C
89
CB 45
A, D
8A
1, (HL)
CB 4E
a
A, E
8B
1, (IX d)
DD CBd4E
FD CBd4E
CB 4F
a
1, (IY d)
A, H
8C
A, L
8D
1, A
1, B
1, C
1, D
1, E
A, n
CE n
ED 4A
ED 5A
ED 6A
ED 7A
86
CB 48
HL, BC
HL, DE
HL, HL
HL, SP
A, (HL)
CB 49
CB 4A
CB 4B
1, H
1, L
CB 4C
CB 4D
CB 56
a
A, (IX d)
DD 86d
FD 86d
87
2, (HL)
a
A, (IY d)
a
2, (IX d)
DD CBd56
FD CBd56
CB 57
a
2, (IY d)
A, A
A, B
80
2, A
2, B
2, C
2, D
2, E
A, C
81
CB 50
A, D
82
CB 51
A, E
83
CB 52
A, H
84
CB 53
A, L
85
2, H
2, L
CB 54
A, n
C6 n
09
CB 55
HL, BC
HL, DE
HL, HL
HL, SP
IX, BC
IX, DE
IX, IX
IX, SP
IY, BC
IY, DE
IY, IY
IY, SP
(HL)
3, (HL)
CB 5E
a
19
3, (IX d)
DD CBd5E
FD CBd5E
CB 5F
a
3, (IY d)
29
39
3, A
3, B
3, C
3, D
3, E
DD 09
DD 19
DD 29
DD 39
FD 09
FD 19
FD 29
FD 39
A6
CB 58
CB 59
CB 5A
CB 5B
3, H
3, L
CB 5C
CB 5D
CB 66
4, (HL)
a
4, (IX d)
DD CBd66
FD CBd66
CB 67
a
4, (IY d)
a
(IX d)
DD A6d
FD A6d
A7
4, A
4, B
4, C
4, D
4, E
a
(IY d)
CB 60
A
CB 61
B
A0
CB 62
C
A1
CB 63
D
A2
4, H
4, L
CB 64
E
A3
CB 65
H
A4
5, (HL)
CB 6E
a
L
A5
5, (IX d)
DD CBd6E
FD CBd6E
CB 6F
a
5, (IY d)
n
E6 n
CB 46
DD CBd46
FD CBd46
CB 47
signed displacement
0, (HL)
5, A
5, B
5, C
5, D
a
BIT
0, (IX d)
CB 68
a
0, (IY d)
BIT
CB 69
BIT
0, A
CB 6A
e
(nn) address of memory location
e
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
58
12.15 Instruction Set: Alphabetical Order (Continued)
BIT
5, E
CB 6B
CB 6C
CB 6D
CB 76
DD CBd76
FD CBd76
CB 77
CB 70
CB 71
CB 72
CB 73
CB 74
CB 75
CB 7E
DD CBd7E
FD CBd7E
CB 7F
CB 78
CB 79
CB 7A
CB 7B
CB 7C
CB 7D
DCnn
FCnn
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DI
A
3D
BIT
5, H
B
05
BIT
5, L
BC
C
0B
BIT
6, (HL)
0D
a
BIT
6, (IX d)
D
15
a
6, (IY d)
BIT
DE
E
1B
BIT
6, A
6, B
6, C
6, D
6, E
1D
BIT
H
25
BIT
HL
IX
IY
L
2B
BIT
DD 2B
FD 2B
2D
BIT
BIT
6, H
6, L
BIT
SP
3B
BIT
7, (HL)
F3
a
BIT
7, (IX d)
DJNZ
EI
d2
10 d2
FB
a
7, (IY d)
BIT
BIT
7, A
EX
(SP), HL
(SP), IX
(SP), IY
AF, A’F’
DE, HL
E3
BIT
7, B
EX
DD E3
FD E3
08
BIT
7, C
EX
BIT
7, D
EX
BIT
7, E
EX
EB
BIT
7, H
EXX
HALT
IM
D9
BIT
7, L
76
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CCF
CP
C, nn
M, nn
NC, nn
nn
0
ED 46
ED 56
ED 5E
ED78
DB n
ED 40
ED 48
ED 50
ED 58
ED 60
ED 68
34
IM
1
D4nn
IM
2
CDnn
C4nn
IN
A, (C)
A, (n)
B, (C)
C, (C)
D, (C)
E, (C)
H, (C)
L, (C)
(HL)
NZ, nn
P, nn
PE, nn
PO, nn
Z, nn
IN
F4nn
IN
ECnn
E4nn
IN
IN
CCnn
3F
IN
IN
(HL)
BE
IN
a
CP
(IX d)
DD BEd
FD BEd
BF
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
IND
INDR
INI
a
(IY d)
a
CP
(IX d)
DD 34d
FD 34d
3C
a
(IY d)
CP
A
B
C
D
E
H
L
CP
B8
A
CP
B9
B
04
CP
BA
BC
C
03
CP
BB
0C
CP
BC
D
14
CP
BD
DE
E
13
CP
n
FE n
1C
CPD
CPDR
CPI
ED A9
ED B9
ED A1
ED B1
2F
H
24
HL
IX
IY
L
23
DD 23
FD 23
2C
CPIR
CPL
DAA
DEC
DEC
DEC
27
SP
33
(HL)
35
ED AA
ED BA
ED A2
a
(IX d)
DD 35d
FD 35d
e
signed displacement
a
(IY d)
e
(nn) Address of memory location
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
59
12.15 Instruction Set: Alphabetical Order (Continued)
INIR
JP
ED B2
E9
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
A, (HL)
7E
a
(HL)
A, (IX d)
DD 7Ed
FD 7Ed
3Ann
7F
a
JP
(IX)
DD E9
FD E9
DAnn
FAnn
A, (IY d)
JP
(IY)
A, (nn)
A, A
A, B
A, C
A, D
A, E
JP
C, nn
JP
M, nn
NC, nn
nn
78
JP
D2nn
79
JP
C3nn
7A
JP
NZ, nn
P, nn
C2nn
7B
JP
F2nn
A, H
A, I
7C
JP
PE, nn
PO, nn
Z, nn
EAnn
ED 57
7D
JP
E2nn
A, L
JP
CAnn
38 d2
18 d2
30 d2
20 d2
28 d2
02
A, n
3E n
46
JR
JR
JR
JR
JR
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
C, d2
B, (HL)
a
d2
B, (IX d)
DD 46d
FD 46d
47
a
B, (IY d)
NC, d2
NZ, d2
Z, d2
B, A
B, B
40
(BC), A
(DE), A
(HL), A
(HL), B
(HL), C
(HL), D
(HL), E
(HL), H
(HL), L
(HL), n
B, C
41
12
B, D
42
77
B, E
43
70
B, H
44
71
B, L
45
72
B, n
06 n
ED 4B
01nn
4E
73
BC, (nn)
BC, nn
C, (HL)
74
75
a
36 n
C, (IX d)
DD 4Ed
FD 4Ed
4F
a
a
C, (IY d)
(IX d), A
DD 77d
DD 70d
DD 71d
DD 72d
DD 73d
DD 74d
DD 75d
DD 36dn
FD 77d
FD 70d
FD 71d
FD 72d
FD 73d
FD 74d
FD 75d
FD 36dn
32nn
a
(IX d), B
C, A
C, B
C, C
C, D
C, E
C, H
C, L
a
(IX d), C
48
a
(IX d), D
49
a
(IX d), E
4A
a
(IX d), H
4B
a
(IX d), L
4C
a
(IX d), n
4D
a
(IY d), A
C, n
0E n
56
a
(IY d), B
D, (HL)
a
a
(IY d), C
D, (IX d)
DD 56d
FD 56d
57
a
a
D, (IY d)
(IY d), D
a
(IY d), E
D, A
a
(IY d), H
D, B
50
a
(IY d), L
D, C
51
a
(IY d), n
(nn), A
D, D
52
D, E
53
(nn), BC
(nn), DE
(nn), HL
(nn), IX
(nn), IY
(nn), SP
A, (BC)
A, (DE)
ED 43nn
ED 53nn
22nn
D, H
54
D, L
55
D, n
16 n
ED 5Bnn
11nn
5E
DD 22nn
FD 22nn
ED 73nn
0A
DE, (nn)
DE, nn
E, (HL)
a
E, (IX d)
DD 5Ed
FD 5Ed
a
E, (IY d)
1A
e
(nn) Address of memory location
e
signed displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
60
12.15 Instruction Set: Alphabetical Order (Continued)
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDD
LDDR
LDI
LDIR
NEG
NOP
OR
OR
OR
OR
OR
E, A
E, B
E, C
E, D
E, E
E, H
E, L
5F
58
OR
C
D
E
H
L
B1
OR
B2
59
OR
B3
5A
OR
B4
5B
OR
B5
5C
OR
n
F6 n
5D
OTDR
OTIR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTD
OUTI
POP
POP
POP
POP
POP
POP
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
ED BB
ED B3
ED 79
ED 41
ED 49
ED 51
ED 59
ED 61
ED 69
D3 n
E, n
1E n
66
H, (HL)
(C), A
(C), B
(C), C
(C), D
(C), E
(C), H
(C), L
n, A
a
H, (IX d)
DD 66d
FD 66d
67
a
H, (IY d)
H, A
H, B
60
H, C
61
H, D
62
H, E
63
H, H
64
ED AB
ED A3
F1
H, L
65
H, n
26 n
AF
BC
DE
HL
IX
HL, (nn)
HL, nn
I, A
2Ann
21nn
ED 47
DD 2Ann
DD 21nn
FD 2Ann
FD 21nn
6E
C1
D1
E1
IX, (nn)
IX, nn
IY, (nn)
IY, nn
L, (HL)
DD E1
FD E1
F5
IY
AF
BC
DE
HL
IX
C5
D5
a
L, (IX d)
DD 6Ed
FD 6Ed
6F
E5
a
L, (IY d)
DD E5
FD E5
CB 86
DD CBd86
FD CBd86
CB 87
CB 80
CB 81
CB 82
CB 83
CB 84
CB 85
CB 8E
DD CBd8E
FD CBd8E
CB 8F
CB 88
CB 89
CB 8A
CB 8B
CB 8C
CB 8D
CB 96
DD CBd96
FD CBd96
L, A
IY
L, B
68
0, (HL)
a
0, (IX d)
a
0, (IY d)
L, C
69
L, D
6A
L, E
6B
0, A
0, B
0, C
0, D
0, E
L, H
6C
L, L
6D
L, n
2E n
ED 7Bnn
F9
SP, (nn)
SP, HL
SP, IX
SP, IY
SP, nn
0, H
0, L
DD F9
FD F9
31nn
ED A8
ED B8
ED A0
ED B0
ED n
00
1, (HL)
a
1, (IX d)
a
1, (IY d)
1, A
1, B
1, C
1, D
1, E
(HL)
B6
1, H
1, L
a
(IX d)
DD B6d
FD B6d
B7
a
(IY d)
2, (HL)
a
2, (IX d)
a
2, (IY d)
A
B
B0
e
(nn) Address of memory location
e
signed displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
61
12.15 Instruction Set: Alphabetical Order (Continued)
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
2, A
2, B
2, C
2, D
2, E
CB 97
CB 90
RES
RES
RES
RES
RET
RET
RET
RET
RET
RET
RET
RET
RET
RETI
RETN
RL
7, D
7, E
7, H
7, L
CB BA
CB BB
CB BC
CB BD
C9
CB 91
CB 92
CB 93
2, H
2, L
CB 94
C
D8
CB 95
M
F8
3, (HL)
CB 9E
NC
NZ
P
D0
a
3, (IX d)
DD CBd9E
FD CBd9E
CB 9F
C0
a
3, (IY d)
F0
3, A
3, B
3, C
3, D
3, E
PE
PO
Z
E8
CB 98
E0
CB 99
C8
CB 9A
ED 4D
ED 45
CB 16
DD CBd16
FD CBd16
CB 17
CB 10
CB 11
CB 12
CB 13
CB 14
CB 15
17
CB 9B
3, H
3, L
CB 9C
(HL)
a
(IX d)
a
(IY d)
CB 9D
RL
4, (HL)
CB A6
RL
a
4, (IX d)
DD CBdA6
FD CBdA6
CB A7
RL
A
B
C
D
E
H
L
a
4, (IY d)
RL
4, A
4, B
4, C
4, D
4, E
RL
CB A0
RL
CB A1
RL
CB A2
RL
CB A3
RL
4, H
4, L
CB A4
RLA
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLCA
RLD
RR
CB A5
(HL)
a
(IX d)
a
(IY d)
CB 06
DD CBd06
FD CBd06
CB 07
CB 00
CB 01
CB 02
CB 03
CB 04
CB 05
07
5, (HL)
CB AE
a
5, (IX d)
DD CBdAE
FD CBdAE
CB AF
a
5, (IY d)
A
B
C
D
E
H
L
5, A
5, B
5, C
5, D
5, E
CB A8
CB A9
CB AA
CB AB
5, H
5, L
CB AC
CB AD
6, (HL)
CB B6
ED 6F
CB 1E
DD CBd1E
FD CBd1E
CB 1F
CB 18
CB 19
CB 1A
CB 1B
CB 1C
CB 1D
1F
a
6, (IX d)
DD CBdB6
FD CBdB6
CB B7
(HL)
a
(IX d)
a
(IY d)
a
6, (IY d)
RR
6, A
6, B
6, C
6, D
6, E
RR
CB B0
RR
A
B
C
D
E
H
L
CB B1
RR
CB B2
RR
CB B3
RR
6, H
6, L
CB B4
RR
CB B5
RR
7, (HL)
CB BE
RR
a
7, (IX d)
DD CBdBE
FD CBdBE
CB BF
RRA
RRC
RRC
RRC
RRC
a
7, (IY d)
(HL)
a
(IX d)
a
(IY d)
CB OE
DD CBd0E
FD CBd0E
CB 0F
7, A
7, B
7, C
CB B8
CB B9
A
e
(nn) Address of memory location
e
signed displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
62
12.15 Instruction Set: Alphabetical Order (Continued)
a
RRC
RRC
RRC
RRC
RRC
RRC
RRCA
RRD
RST
RST
RST
RST
RST
RST
RST
RST
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SCF
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
B
C
D
E
H
L
CB 08
CB 09
CB 0A
CB 0B
CB 0C
CB 0D
0F
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
2, (IX d)
DD CBdD6
FD CBdD6
CB D7
a
2, (IY d)
2, A
2, B
2, C
2, D
2, E
CB D0
CB D1
CB D2
CB D3
ED 67
C7
2, H
2, L
CB D4
0
CB D5
08H
10H
18H
20H
28H
30H
38H
A, (HL)
CF
3, (HL)
CB DE
a
D7
3, (IX d)
DD CBdDE
FD CBdDE
CB DF
a
3, (IY d)
DF
E7
3, A
3, B
3, C
3, D
3, E
EF
CB D8
F7
CB D9
FF
CB DA
9E
CB DB
a
A, (IX d)
DD 9Ed
FD 9Ed
9F
3, H
3, L
CB DC
CB DD
CB E6
a
A, (IY d)
A, A
4, (HL)
a
A, B
98
4, (IX d)
DD CBdE6
FD CBdE6
CB E7
a
4, (IY d)
A, C
99
A, D
9A
4, A
4, B
4, C
4, D
4, E
A, E
9B
CB E0
A, H
9C
CB E1
A, L
9D
CB E2
A, n
DE n
CB E3
HL, BC
HL, DE
HL, HL
HL, SP
ED 42
ED 52
ED 62
ED 72
37
4, H
4, L
CB E4
CB E5
5, (HL)
CB EE
a
5, (IX d)
DD CBdEE
FD CBdEE
CB EF
a
5, (IY d)
0, (HL)
CB C6
DD CBdC6
FD CBdC6
CB C7
CB C0
CB C1
CB C2
CB C3
CB C4
CB C5
CB CE
DD CBdCE
FD CBdCE
CB CF
CB C8
CB C9
CB CA
CB CB
CB CC
CB CD
CB D6
5, A
5, B
5, C
5, D
5, E
a
0, (IX d)
CB E8
a
0, (IY d)
CB E9
0, A
0, B
0, C
0, D
0, E
CB EA
CB EB
5, H
5, L
CB EC
CB ED
6, (HL)
CB F6
a
0, H
0, L
6, (IX d)
DD CBdF6
FD CBdF6
CB F7
a
6, (IY d)
1, (HL)
6, A
6, B
6, C
6, D
6, E
a
1, (IX d)
CB F0
a
1, (IY d)
CB F1
1, A
1, B
1, C
1, D
1, E
CB F2
CB F3
6, H
6, L
CB F4
CB F5
7, (HL)
CB FE
a
1, H
1, L
7, (IX d)
DD CBdFE
FD CBdFE
CB FF
a
7, (IY d)
2, (HL)
7, A
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
63
12.15 Instruction Set: Alphabetical Order (Continued)
SET
SET
SET
SET
SET
SET
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRL
SRL
SRL
7, B
7, C
7, D
7, E
7, H
7, L
(HL)
CB F8
SRL
SRL
SRL
SRL
SRL
SRL
SRL
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
A
CB 3F
CB 38
CB 39
CB 3A
CB 3B
CB 3C
CB 3D
96
CB F9
B
CB FA
C
CB FB
D
CB FC
CB FD
CB 26
E
H
L
a
(IX d)
DD CBd26
FD CBd26
CB 27
(HL)
a
(IY d)
a
(IX d)
DD 96d
FD 96d
97
a
(IY d)
A
B
CB 20
A
C
CB 21
B
90
D
CB 22
C
91
E
CB 23
D
92
H
CB 24
E
93
L
CB 25
H
94
(HL)
CB 2E
L
95
a
(IX d)
DD CBd2E
FD CBd2E
CB 2F
n
D6 n
AE
a
(IY d)
(HL)
a
A
(IX d)
DD AEd
FD AEd
AF
a
(IY d)
B
CB 28
C
CB 29
A
B
C
D
E
H
L
D
CB 2A
A8
E
CB 2B
A9
H
CB 2C
AA
L
CB 2D
AB
(HL)
CB 3E
AC
a
(IX d)
DD CBd3E
FD CBd3E
AD
a
(IY d)
n
EE n
12.16 Instruction Set: Numerical Order
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
00
NOP
15
DEC D
2Ann
2B
LD HL,(nn)
DEC HL
INC L
01nn
02
LD BC,nn
LD (BC),A
INC BC
INC B
16n
17
LD D,n
RLA
2C
03
18d2
19
JR d2
2D
DEC L
04
ADD HL,DE
LD A,(DE)
DEC DE
INC E
2En
2F
LD L,n
05
DEC B
1A
CPL
06n
07
LD B,n
1B
30d2
31nn
32nn
33
JR NC,d2
LD SP,nn
LD (nn),A
INC SP
INC (HL)
DEC (HL)
LD (HL),n
SCF
RLCA
1C
08
EX AF,A’F’
ADD HL,BC
LD A,(BC)
DEC BC
INC C
1D
DEC E
09
1En
1F
LD E,n
0A
RRA
34
0B
20d2
21nn
22nn
23
JR NZ,d2
LD HL,nn
LD (nn),HL
INC HL
INC H
35
0C
0D
0En
0F
36n
37
DEC C
LD C,n
38
JR C,d2
ADD HL,SP
LD A,(nn)
DEC SP
INC A
RRCA
24
39
10d2
11nn
12
DJNZ d2
LD DE,nn
LD (DE),A
INC DE
INC D
25
DEC H
3Ann
3B
26n
27
LD H, n
DAA
3C
13
28d2
29
JR Z,d2
ADD HL,HL
3D
DEC A
14
3En
LD A,n
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8 bit)
64
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
CCF
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
LD (HL),H
LD (HL),L
HALT
A9
XOR C
XOR D
XOR E
XOR H
XOR L
XOR (HL)
XOR A
OR B
LD B,B
LD B,C
LD B,D
LD B,E
LD B,H
LD B,L
AA
AB
LD (HL),A
LD A,B
AC
AD
LD A,C
AE
LD A,D
AF
LD B,(HL)
LD B,A
LD C,B
LD C,C
LD C,D
LD C,E
LD C,H
LD C,L
LD C,(HL)
LD C,A
LD D,B
LD D,C
LD D,D
LD D,E
LD D,H
LD D,L
LD D,(HL)
LD D,A
LD E,B
LD E,C
LD E,D
LD E,E
LD E,H
LD E,L
LD A,E
B0
LD A,H
B1
OR C
LD A,L
B2
OR D
LD A,(HL)
LD A,A
B3
OR E
B4
OR H
ADD A,B
ADD A,C
ADD A,D
ADD A,E
ADD A,H
ADD A,L
ADD A,(HL)
ADD A,A
ADC A,B
ADC A,C
ADC A,D
ADC A,E
ADC A,H
ADC A,L
ADC A,(HL)
ADC A,A
SUB B
B5
OR L
B6
OR (HL)
OR A
B7
B8
CP B
B9
CP C
BA
CP D
BB
CP E
BC
CP H
BD
CP L
BE
CP (HL)
CP A
BF
C0
RET NZ
POP BC
JP NZ,nn
JP nn
C1
C2nn
C3nn
C4nn
C5
CALL NZ,nn
PUSH BC
ADD A,n
RST 0
RET Z
RET
SUB C
C6n
C7
SUB D
LD E,(HL)
LD E,A
LD H,B
LD H,C
LD H,D
LD H,E
LD H,H
LD H,L
LD H,(HL)
LD H,A
LD L,B
SUB E
C8
SUB H
C9
SUB L
CAnn
CB00
CB01
CB02
CB03
CB04
CB05
CB06
CB07
CB08
CB09
CB0A
CB0B
CB0C
CB0D
CB0E
CB0F
CB10
CB11
CB12
JP Z,nn
RLC B
RLC C
RLC D
RLC E
RLC H
RLC L
RLC (HL)
RLC A
RRC B
RRC C
RRC D
RRC E
RRC H
RRC L
RRC (HL)
RRC A
RL B
SUB (HL)
SUB A
SBC A,B
SBC A,C
SBC A,D
SBC A,E
SBC A,H
SBC A,L
SBC A,(HL)
SBC A,A
AND B
LD L,C
LD L,D
LD L,E
LD L,H
LD L,L
AND C
AND D
LD L,(HL)
LD L,A
AND E
AND H
LD (HL),B
LD (HL),C
LD (HL),D
LD (HL),E
AND L
AND (HL)
AND A
RL C
XOR B
RL D
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8-bit)
65
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
CB13
CB14
CB15
CB16
CB17
CB18
CB19
CB1A
CB1B
CB1C
CB1D
CB1E
CB1F
CB20
CB21
CB22
CB23
CB24
CB25
CB26
CB27
CB28
CB29
CB2A
CB2B
CB2C
CB2D
CB2E
CB2F
CB38
CB39
CB3A
CB3B
CB3C
CB3D
CB3E
CB3F
CB40
CB41
CB42
CB43
CB44
CB45
CB46
CB47
CB48
CB49
CB4A
CB4B
CB4C
CB4D
CB4E
RL E
CB4F
CB50
CB51
CB52
CB53
CB54
CB55
CB56
CB57
CB58
CB59
CB5A
CB5B
CB5C
CB5D
CB5E
CB5F
CB60
CB61
CB62
CB63
CB64
CB65
CB66
CB67
CB68
CB69
CB6A
CB6B
CB6C
CB6D
CB6E
CB6F
CB70
CB71
CB72
CB73
CB74
CB75
CB76
CB77
CB78
CB79
CB7A
CB7B
CB7C
CB7D
CB7E
CB7F
CB80
CB81
CB82
BIT 1,A
BIT 2,B
BIT 2,C
BIT 2,D
BIT 2,E
BIT 2,H
BIT 2,L
BIT 2,(HL)
BIT 2,A
BIT 3,B
BIT 3,C
BIT 3,D
BIT 3,E
BIT 3,H
BIT 3,L
BIT 3,(HL)
BIT 3,A
BIT 4,B
BIT 4,C
BIT 4,D
BIT 4,E
BIT 4,H
BIT 4,L
BIT 4,(HL)
BIT 4,A
BIT 5,B
BIT 5,C
BIT 5,D
BIT 5,E
BIT 5,H
BIT 5,L
BIT 5,(HL)
BIT 5,A
BIT 6,B
BIT 6,C
BIT 6,D
BIT 6,E
BIT 6,H
BIT 6,L
BIT 6,(HL)
BIT 6,A
BIT 7,B
BIT 7,C
BIT 7,D
BIT 7,E
BIT 7,H
BIT 7,L
BIT 7,(HL)
BIT 7,A
RES 0,B
RES 0,C
RES 0,D
CB83
CB84
CB85
CB86
CB87
CB88
CB89
CB8A
CB8B
CB8C
CB8D
CB8E
CB8F
CB90
CB91
CB92
CB93
CB94
CB95
CB96
CB97
CB98
CB99
CB9A
CB9B
CB9C
CB9D
CB9E
CB9F
CBA0
CBA1
CBA2
CBA3
CBA4
CBA5
CBA6
CBA7
CBA8
CBA9
CBAA
CBAB
CBAC
CBAD
CBAE
CBAF
CBB0
CBB1
CBB2
CBB3
CBB4
CBB5
CBB6
RES 0,E
RES 0,H
RES 0,L
RES 0,(HL)
RES 0,A
RES 1,B
RES 1,C
RES 1,D
RES 1,E
RES 1,H
RES 1,L
RES 1,(HL)
RES 1,A
RES 2,B
RES 2,C
RES 2,D
RES 2,E
RES 2,H
RES 2,L
RES 2,(HL)
RES 2,A
RES 3,B
RES 3,C
RES 3,D
RES 3,E
RES 3,H
RES 3,L
RES 3,(HL)
RES 3,A
RES 4,B
RES 4,C
RES 4,D
RES 4,E
RES 4,H
RES 4,L
RES 4,(HL)
RES 4,A
RES 5,B
RES 5,C
RES 5,D
RES 5,E
RES 5,H
RES 5,L
RES 5,(HL)
RES 5,A
RES 6,B
RES 6,C
RES 6,D
RES 6,E
RES 6,H
RES 6,L
RES 6,(HL)
RL H
RL L
RL (HL)
RL A
RR B
RR C
RR D
RR E
RR H
RR L
RR (HL)
RR A
SLA B
SLA C
SLA D
SLA E
SLA H
SLA L
SLA (HL)
SLA A
SRA B
SRA C
SRA D
SRA E
SRA H
SRA L
SRA (HL)
SRA A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SRL (HL)
SRL A
BIT 0,B
BIT 0,C
BIT 0,D
BIT 0,E
BIT 0,H
BIT 0,L
BIT 0,(HL)
BIT 0,A
BIT 1,B
BIT 1,C
BIT 1,D
BIT 1,E
BIT 1,H
BIT 1,L
BIT 1,(HL)
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8-bit)
66
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
a
LD H,(IX d)
a
LD L,(IX d)
a
LD (IX d),B
a
LD (IX d),C
a
LD (IX d),D
a
LD (IX d),E
a
LD (IX d),H
a
LD (IX d),L
a
LD (IX d),A
a
LD A,(IX d)
a
ADD A,(IX d)
a
ADC A,(IX d)
a
SUB (IX d)
a
SBC A,(IX d)
a
AND (IX d)
a
XOR (IX d)
CBB7
CBB8
CBB9
CBBA
CBBB
CBBC
CBBD
CBBE
CBBF
CBC0
CBC1
CBC2
CBC3
CBC4
CBC5
CBC6
CBC7
CBC8
CBC9
CBCA
CBCB
CBCC
CBCD
CBCE
CBCF
CBD0
CBD1
CBD2
CBD3
CBD4
CBD5
CBD6
CBD7
CBD8
CBD9
CBDA
CBDB
CBDC
CBDD
CBDE
CBDF
CBE0
CBE1
CBE2
CBE3
CBE4
CBE5
CBE6
CBE7
CBE8
CBE9
CBEA
CBEB
RES 6,A
RES 7,B
RES 7,C
RES 7,D
RES 7,E
RES 7,H
RES 7,L
RES 7,(HL)
RES 7,A
SET 0,B
SET 0,C
SET 0,D
SET 0,E
SET 0,H
SET 0,L
SET 0,(HL)
SET 0,A
SET 1,B
SET 1,C
SET 1,D
SET 1,E
SET 1,H
SET 1,L
SET 1,(HL)
SET 1,A
SET 2,B
SET 2,C
SET 2,D
SET 2,E
SET 2,H
SET 2,L
SET 2,(HL)
SET 2,A
SET 3,B
SET 3,C
SET 3,D
SET 3,E
SET 3,H
SET 3,L
SET 3,(HL)
SET 3,A
SET 4,B
SET 4,C
SET 4,D
SET 4,E
SET 4,H
SET 4,L
SET 4,(HL)
SET 4,A
SET 5,B
SET 5,C
SET 5,D
SET 5,E
CBEC
CBED
CBEE
CBEF
CBF0
CBF1
CBF2
CBF3
CBF4
CBF5
CBF6
CBF7
CBF8
CBF9
CBFA
CBFB
CBFC
CBFD
CBFE
CBFF
CCnn
CDnn
CEn
SET 5,H
SET 5,L
SET 5,(HL)
SET 5,A
SET 6,B
SET 6,C
SET 6,D
SET 6,E
SET 6,H
SET 6,L
SET 6,(HL)
SET 6,A
SET 7,B
SET 7,C
SET 7,D
SET 7,E
SET 7,H
SET 7,L
SET 7,(HL)
SET 7,A
CALL Z,nn
CALL nn
ADC A,n
RST 8
DD66d
DD6Ed
DD70d
DD71d
DD72d
DD73d
DD74d
DD75d
DD77d
DD7Ed
DD86d
DD8Ed
DD96d
DD9Ed
DDA6d
DDAEd
a
OR (IX d)
a
CP (IX d)
a
RLC (IX d)
DDB6d
DDBEd
DDCBd06
DDCBd0E
DDCBd16
DDCBd1E
DDCBd26
DDCBd2E
DDCBd3E
DDCBd46
DDCBd4E
DDCBd56
DDCBd5E
DDCBd66
DDCBd6E
DDCBd76
DDCBd7E
DDCBd86
DDCBd8E
DDCBd96
DDCBd9E
DDCBdA6
a
RRC (IX d)
a
RL (IX d)
a
RR (IX d)
a
SLA (IX d)
a
SRA (IX d)
a
SRL (IX d)
a
BIT 0,(IX d)
a
BIT 1,(IX d)
CF
D0
RET NC
POP DE
JP NC,nn
OUT (n),A
CALL NC,nn
PUSH DE
SUB n
D1
D2nn
D3n
a
BIT 2,(IX d)
a
BIT 3,(IX d)
D4nn
D5
a
BIT 4,(IX d)
a
BIT 5,(IX d)
a
BIT 6,(IX d)
a
BIT 7,(IX d)
a
RES 0,(IX d)
a
RES 1,(IX d)
a
RES 2,(IX d)
a
RES 3,(IX d)
D6n
D7
RST 10H
RET C
D8
D9
EXX
DAnn
DBn
JP,C,nn
IN A,(n)
DCnn
DD09
DD19
DD21nn
DD22nn
DD23
DD29
DD2Ann
DD2B
DD34d
DD35d
DD36dn
DD39
DD46d
DD4Ed
DD56d
DD5Ed
CALL C,nn
ADD IX,BC
ADD IX,DE
LD IX,nn
LD (nn),IX
INC IX
a
RES 4,(IX d)
a
DDCBdAE RES 5,(IX d)
a
RES 6,(IX d)
DDCBdB6
DDCBdBE RES 7,(IX d)
a
a
SET 0,(IX d)
DDCBdC6
DDCBdCE SET 1,(IX d)
a
ADD IX,IX
LD IX,(nn)
DEC IX
a
SET 2,(IX d)
DDCBdD6
DDCBdDE SET 3,(IX d)
a
a
a
SET 4,(IX d)
INC (IX d)
DDCBdE6
DDCBdEE SET 5,(IX d)
a
a
DEC (IX d)
a
LD (IX d),n
ADD IX,SP
a
SET 6,(IX d)
a
SET 7,(IX d)
DDCBdF6
DDCBdFE
DDE1
a
LD B,(IX d)
POP IX
a
LD C,(IX d)
DDE3
EX (SP),IX
PUSH IX
JP (IX)
a
LD D,(IX d)
DDE5
a
LD E,(IX d)
DDE9
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8-bit)
67
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
a
LD (IY d),E
a
LD (IY d),H
a
LD (IY d),L
a
LD (IY d),A
a
LD A,(IY d)
a
ADD A,(IY d)
a
ADC A,(IY d)
a
SUB (IY d)
a
SBC A,(IY d)
a
AND (IY d)
a
XOR (IY d)
a
OR (IY d)
a
CP (IY d)
POP IY
DDF9
DEn
LD SP,IX
SCB A,n
RST 18H
RET PO
POP HL
ED7Bnn
EDA0
EDA1
EDA2
EDA3
EDA8
EDA9
EDAA
EDAB
EDB0
EDB1
EDB2
EDB3
EDB8
EDB9
EDBA
EDBB
EEn
LD SP,(nn)
LDI
FD73d
FD74d
DF
CPI
FD75d
E0
INI
FD77d
E1
OUTI
FD7Ed
E2nn
E3
JP PO,nn
EX (SP),HL
CALL PO,nn
PUSH HL
AND n
LDD
FD86d
CPD
FD8Ed
E4nn
E5
IND
FD96d
OUTD
LDIR
FD9Ed
E6n
FDA6d
E7
RST 20H
RET PE
CPIR
FDAEd
E8
INIR
FDB6d
E9
JP (HL)
OTIR
FDBEd
EAnn
EB
JP PE,nn
EX DE,HL
CALL PE,nn
IN B,(C)
LDDR
FDE1
CPDR
FDE3
EX (SP), IY
PUSH IY
JP (IY)
ECnn
ED40
ED41
ED42
ED43nn
ED44
ED45
ED46
ED47
ED48
ED49
ED4A
ED4Bnn
ED4D
ED50
ED51
ED52
ED53nn
ED56
ED57
ED58
ED59
ED5A
ED5Bnn
ED5E
ED60
ED61
ED62
ED67
ED68
ED69
ED6A
ED6F
ED72
ED73nn
ED78
ED79
ED7A
INDR
FDE5
OTDR
XOR n
RST 28H
RET P
POP AF
JP P,nn
DI
FDE9
OUT (C),B
SBC HL,BC
LD (nn),BC
NEG
FDF9
LD SP,IY
a
RLC (IY d)
a
RRC (IY d)
a
RL (IY d)
a
RR (IY d)
a
SLA (IY d)
a
SRA (IY d)
a
SRL (IY d)
a
BIT 0,(IY d)
a
BIT 1,(IY d)
a
BIT 2,(IY d)
a
BIT 3,(IY d)
a
BIT 4,(IY d)
a
BIT 5,(IY d)
a
BIT 6,(IY d)
EF
FDCBd06
FDCBd0E
FDCBd16
FDCBd1E
FDCBd26
FDCBd2E
FDCBd3E
FDCBd46
FDCBd4E
FDCBd56
FDCBd5E
FDCBd66
FDCBd6E
FDCBd76
FDCBd7E
FDCBd86
FDCBd8E
FDCBd96
FDCBd9E
FDCBdA6
FDCBdAE
FDCBdB6
FDCBdBE
FDCBdC6
F0
F1
RETN
F2nn
F3
IM 0
LD I,A
F4nn
F5
CALL P,nn
PUSH AF
OR n
IN C,(C)
OUT (C),C
ADC HL,BC
LD BC,(nn)
RETI
F6n
F7
RST 30H
RET M
LD SP,HL
JP M,nn
EI
F8
F9
IN D,(C)
FAnn
FB
OUT (C),D
SBC HL,DE
LD (nn),DE
IM 1
FCnn
FD09
FD19
FD21nn
FD22nn
FD23
FD29
FD2Ann
FD2B
FD34d
FD35d
FD36dn
FD39
FD46d
FD4Ed
FD56d
FD5Ed
FD66d
FD6Ed
FD70d
FD71d
FD72d
CALL M,nn
ADD IY,BC
ADD IY,DE
LD IY,nn
LD (nn),IY
INC IY
ADD IY,IY
LD IY,(nn)
DEC IY
a
BIT 7,(IY d)
a
RES 0,(IY d)
a
RES 1,(IY d)
a
RES 2,(IY d)
a
RES 3,(IY d)
LD A,I
IN E,(C)
OUT (C), E
ADC HL,DE
LD DE,(nn)
IM 2
a
RES 4,(IY d)
a
RES 5,(IY d)
a
RES 6,(IY d)
a
a
RES 7,(IY d)
a
SET 0,(IY d)
IN H,(C)
INC (IY d)
a
OUT (C),H
SBC HL,HL
RRD
DEC (IY d)
a
LD (IY d),n
ADD IY,SP
a
FDCBdCE SET 1,(IY d)
a
SET 2,(IY d)
FDCBdD6
FDCBdDE SET 3,(IY d)
a
LD B,(IY d)
a
IN L,(C)
a
a
SET 4,(IY d)
a
SET 5,(IY d)
a
SET 6,(IY d)
a
SET 7,(IY d)
OUT (C),L
ADC HL,HL
RLD
LD C,(IY d)
FDCBdE6
FDCBdEE
FDCBdF6
FDCBdFE
FEn
a
LD D,(IY d)
a
LD E,(IY d)
a
SBC HL,SP
LD (nn),SP
IN A,(C)
LD H,(IY d)
a
LD L,(IY d)
CP n
a
LD (IY d),B
FF
RST 38H
a
LD (IY d),C
a
LD (IY d),D
OUT (C),A
ADC HL,SP
e
(nn) Address of memory location
e
displacement
d
e
nn Data (16 bit)
e b
d 2
d2
e
n
Data (8-bit)
68
13.0 Data Acquisition System
A natural application for the NSC800 is one that requires
remote operation. Since power consumption is low if the
system consists of only CMOS components, the entire
package can conceivably operate from only a battery power
source. In the application described herein, the only source
of power will be from a battery pack composed of a stacked
array of NiCad batteries (see Figure 20).
the need for battery operation or at least battery backup. At
some fixed times or at some particular time durations, the
system takes readings by selecting one of the analog input
channels, commands the A/D to perform a conversion,
reads the data, and then formats it for transmission; or, the
system checks the readings against set points and trans-
mits a warning if the set points are exceeded. With the addi-
tion of the RTC, the host need not command the remote
system to take these readings each time it is necessary.
The NSC800 could simply set up the RTC to interrupt it at a
previously defined time and when the interrupt occurs, make
the readings. The resultant values could be stored in the
NSC810A for later correlation. In the example of tempera-
ture monitoring in a building, it might be desired to know the
high and low temperatures for a 12-hour period. After com-
piling the information, the system could dump the data to
the host over the communications link. Note from the sche-
matic that the current for the communication link is supplied
by the host to remove the constant current drain from the
battery supply.
The application is that of a remote data acquisition system.
Extensive use is made of some of the other LSI CMOS com-
ponents manufactured by National: notably the ADC0816
and MM58167. The ADC0816 is a 16-channel analog-to-
digital converter which operates from a 5V source. The
MM58167 is a microprocessor-compatible real-time clock
(RTC). The schematic for this system is shown in Figure 20.
All the necessary features of the system are contained in six
integrated circuits: NSC800, NSC810A, NSC831, HN6136P,
ADC0816, and MM58167. Some other small scale integra-
tion CMOS components are used for normal interface re-
quirements. To reduce component count, linear selection
techniques are used to generate chip selects for the
NSC810A and NSC831. Included also is a current loop com-
munication link to enable the remote system to transfer data
collected to a host system.
The required clocks for the two peripheral devices are gen-
erated by the two timers in the NSC810A. Through the use
of various divisors, the master clock generated by the
NSC800 is divided down to produce the clocks. Four exam-
ples are shown in the table following Figure 20.
In order to keep component count low and maximize effec-
tiveness, many of the features of the NSC800 family have
been utilized. The RAM section of the NSC810A is used as
a data buffer to store intermediate measurements and as
scratch pad memory for calculations. Both timers contained
in the NSC810A are used to produce the clocks required by
the A/D converter and the RTC. The Power-Save feature of
the NSC800 makes it possible to reduce system power con-
sumption when it is not necessary to collect any data. One
of the analog input channels of the A/D is connected to the
battery pack to enable the CPU to monitor its own voltage
supply and notify the host that a battery change is needed.
All the crystal frequencies are standard frequencies. The
various divisors listed are selected to produce, from the
master clock frequency of the NSC800, an exact 32,768 Hz
clock for the MM58167 and a clock within the operating
range of the A/D converter.
The MM58167 is a programmable real-time clock that is
microprocessor compatible. Its data format is BCD. It allows
the system to program its interrupt register to produce an
interrupt output either on a time of day match (which in-
cludes the day of the week, the date and month) and/or
every month, week, day, hour, minute, second, or tenth of a
second. With this capability added to the system, precise
time of day measurements are possible without having the
CPU do timekeeping. The interrupt output can be connect-
ed, through the use of one port bit of the NSC810A, to put
the CPU in the power-save mode and reenable it at a preset
time. The interrupt output is also connected to one of the
hardware restart inputs (RSTB) to enable time duration
measurements. This power-down mode of operation would
not be possible if the NSC800 had the duties of timekeep-
In operation, the NSC800 makes readings on various input
conditions through the ADC0816. The type of devices con-
nected to the A/D input depends on the nature of the re-
mote environment. For example, the duties of the remote
system might be to monitor temperature variations in a large
building. In this case, the analog inputs would be connected
to temperature transducers. If the system is situated in a
process control environment, it might be monitoring fluid
flow, temperatures, fluid levels, etc. In either case, operation
would be necessary even if a power failure occurred, thus
69
13.0 Data Acquisition System (Continued)
70
13.0 Data Acquisition System (Continued)
ing. When in the power-save mode, the system power re-
quirements are decreased by about 50%, thus extending
battery life.
signal which is connected to the RSTA interrupt input of the
NSC800.
When operating, the system shown consumes about 125
mw. When in the power-save mode, power consumption is
decreased to about 70 mw. If, as is likely, the system is in
the power-save mode most of the time, battery life can be
quite long depending on the amp-hour rating of the batteries
incorporated into the system. For example, if the battery
pack is rated at 5 amp-hours, the system should be able to
operate for about 400-500 hours before a battery charge or
change is required.
Communication with the peripheral devices (MM58167 and
ADC0816) is accomplished through the I/O ports of the
NSC810A and NSC831. The peripheral devices are not con-
nected to the bus of the NSC800 as they are not directly
compatible with a multiplexed bus structure. Therefore, ad-
ditional components would be required to place them on the
microprocessor bus. Writing data into the MM58167 is per-
formed by first putting the desired data on Port A, followed
by selecting the address of the internal register and applying
the chip select through the use of Port B. A bit set and clear
operation is performed to emulate a pulse on the bit of Port
B connected to the WR input of the MM58167. For a read
operation, the same sequence of operations is performed
except that Port A is set for the input mode of operation and
the RD line is pulsed. Similar techniques are used to read
converted data from the A/D converter. When a conversion
is desired, the CPU selects a channel and commands the
ADC0816 to start a conversion. When the conversion is
complete, the converter will produce an End-of-Conversion
As shown in the schematic (refer to Figure 20), analog input
IN0 is connected to the battery source. In this way, the CPU
can monitor its own power source and notify the host that it
needs a battery replacement or charge. Since the battery
source shown is a stacked array of 7 NiCads producing
8.4V, the converter input is connected in the middle so that
it can take a reading on two or three of the cells. Since
NiCad batteries have a relatively constant voltage output
until very nearly discharged, the CPU can sense that the
‘‘knee’’ of the discharge curve has been reached and notify
the host.
Typical Timer Output Frequencies
Crystal Frequency
CPU Clock Output
Timer 0 Output
262.144 kHz
Timer 1 Output
2.097152 MHz
1.048576 MHz
1.638400 MHz
2.097152 MHz
2.457600 MHz
32.768 kHz
e
8
e
divisor
4
divisor
3.276800 MHz
4.194304 MHz
4.915200 MHz
327.680 kHz
e
32.768 kHz
e
10
divisor
5
divisor
262.144 kHz
e
32.768 kHz
e
8
divisor
8
divisor
491.520 kHz
e
32.768 kHz
e
15
divisor
5
divisor
71
14.0 NSC800M/883B MIL-STD-833
Class C Screening
National Semiconductor offers the NSC800D and NSC800E
with full class B screening per MIL-STD-883 for Military/
Aerospace programs requiring high reliability. In addition,
this screening is available for all of the key NSC800 periph-
eral devices.
Electrical testing is performed in accordance with
RESTS800X, which tests or guarantees all of the electrical
performance characteristics of the NSC800 data sheet. A
copy of the current revision of RETS800X is available upon
request.
100% Screening Flow
MIL-STD-883 Method/Condition
Test
Requirement
Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Fine Leak
2010B
100%
100%
100%
100%
100%
100%
100%
@
a
b
1008 C 24 Hrs.
150 C
§
a
1010 C 10 Cycles 65 C/ 150 C
§
2001 E 30,000 G’s, Y1 Axis
1014 A or B
§
Gross Leak
1014C
@
a
125 C (using
Burn-In
1015 160 Hrs.
§
burn-in circuits shown below)
a
10% Max
Final Electrical
PDA
25 C DC per RETS800X
100%
§
a
b
a
125 C AC and DC per RETS800X
§
55 C AC and DC per RETS800X
100%
100%
§
25 C AC per RETS800X
§
100%
QA Acceptance
Quality Conformance
External Visual
5005
Sample Per
Method 5005
100%
2009
15.0 Burn-In Circuits
5240HR
5241HR
NSC800E/883B (Leadless Chip Carrier)
NSC800D/883B (Dual-In-Line)
TL/C/5171–32
Top View
TL/C/5171–33
All resistors 2.7 kX unless marked otherwise.
g
Note 1: All resistors are (/4W
5% unless otherwise specified.
k
Note 2: All clocks 0V to 3V, 50% duty cycle, in phase with
1 ms rise and fall time.
Note 3: Device to be cooled down under power after burn-in.
72
16.0 Ordering Information
NSC800
X
X
X
X
a e
a
MIL-STD-883 Screening (Note 1)
/A
A
Reliability Screening
e
/883
e
b a
Industrial Temperature ( 40 C to 85 C)
I
§
§
e
b a
Military Temperature ( 55 C to 125 C)
M
§
§
e
b a
Special Temperature ( 55 C to 90 C)
MIL
No Designation
§
§
Commercial Temperature (0 C to 70 C)
e
a
§
§
b
b
b
b
e
4 MHz Clock
4
e
35
3.5 MHz Clock Output
e
e
3
1
2.5 MHz Clock Output
1 MHz Clock Output
e
e
e
e
D
N
E
V
Ceramic Package
Plastic Package
Ceramic Leadless Chip Carrier (LCC)
Plastic Leaded Chip Carrier (PCC)
Note 1: Do not specify a temperature option; all parts are screened to military temperature.
17.0 Reliability Information
Gate Count 2750
Transistor Count 11,000
73
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number NSC800N
NS Package Number N40A
Hermetic Dual-In-Line Package (D)
Order Number NSC800D
NS Package Number D40C
74
Physical Dimensions inches (millimeters) (Continued)
Leadless Chip Carrier Package (E)
Order Number NSC800E
NS Package Number E44A
75
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number NSC800V
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明