OPA2835 [NSC]
Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp;
| 型号： | OPA2835 |
| 厂家： | 
National Semiconductor |
| 描述： | Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp |
| 文件： | 总53页 (文件大小：2066K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA835
OPA2835
www.ti.com
SLOS713E –JANUARY 2011–REVISED JULY 2013
Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp
Check for Samples: OPA835, OPA2835
1
FEATURES
DESCRIPTION
Fabricated using the industry-leading BiCom-3x
•
Ultra Low Power
(SiGe complimentary bipolar) process, the OPA835
and OPA2835 are single and dual ultra low-power,
rail-to-rail output, negative rail input, voltage-feedback
operational amplifiers designed to operate over a
power supply range of 2.5 V to 5.5 V Single Supply
and ±1.25 V to ±2.75 V dual supply. Consuming only
250 µA per channel and a unity gain bandwidth of 56
MHz, these amplifiers set an industry leading power-
to-performance ratio for rail-to-rail amplifiers.
–
–
–
Supply Voltage: 2.5 V to 5.5 V
Quiescent Current: 250 µA (typ)
Power Down Mode: 0.5 µA (typ)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bandwidth: 56 MHz
Slew Rate: 160 V/µs
Rise Time: 10 ns (2 VSTEP
)
Settling Time: 45 ns (2VSTEP
)
For battery powered portable applications where
power is of key importance, the OPA835's and
OPA2835's low power consumption and high
frequency performance offers designers performance
versus power not attainable in other devices. Coupled
with a power savings mode to reduce current to <1.5
μA, the device offers an attractive solution for high
frequency amplifiers in battery powered applications.
Overdrive Recovery Time: 195 ns
SNR: 0.00015% (–116.4dBc) at 1 kHz (1 VRMS
)
THD: 0.00003% (–130 dBc) at 1 kHz (1 VRMS
)
HD2/HD3: –70 dBc/–73 dBc at 1 MHz (2 VPP
)
Input Voltage Noise: 9.3 nV/√Hz (f = 100 kHz)
Input Offset Voltage: 100 µV (500 µV max)
CMRR: 113 dB
The OPA835 and OPA2835 are offered in following
package options:
Output Current Drive: 40 mA
RRO – Rail-to-Rail Output
•
OPA835 Single: SOT23-6 (DBV), and 10 pin
WQFN (RUN) with integrated gain resistors.
Input Voltage Range: –0.2 V to 3.9 V
(5 V supply)
•
OPA2835 Dual: SOIC-8 (D), VSSOP (MSOP) -10
(DGS), 10 pin WQFN (RUN), and 10 pin UQFN
(RMC).
•
Operating Temperature Range:
–40°C–125°C
The OPA835 RUN package option includes
integrated gain setting resistors for smallest possible
footprint on a printed circuit board (≈ 2mm x 2mm).
By adding circuit traces on the PCB, gains of +1, -1, -
1.33, +2, +2.33, -3, +4, -4, +5, -5.33, +6.33, -7, +8
and inverting attenuations of -0.1429, -0.1875, -0.25,
-0.33, -0.75 can be achieved. See Application
Information section for details.
APPLICATIONS
•
•
•
•
•
•
•
Low Power Signal Conditioning
Audio ADC Input Buffer
Low Power SAR and ΔΣ ADC Driver
Portable Systems
Low Power Systems
The devices are characterized for operation over the
extended industrial temperature range –40°C to
125°C.
High Density Systems
Ultrasonic Flow Meter
0
OPA835 Related Products
2.7V
VSIG
VSIG
-20
2.7V
VS+
0V
1.35V
100
2.2nF
4.02k
4.02k
DESCRIPTION
SINGLES
DUALS
OPA2830
OPA2836
TRIPLES
QUADS
OPA4830
—
5V
2.5V
REF
2k
VIN
-40
-60
VDD
OPA835
VS-
+In
Rail-to-Rail
—
—
—
ADS8326
-In
Rail-to-Rail, Low
Power
OPA836
2k
2k
-80
Rail-to-Rail, Fixed
Gain
OPA832
OPA690
OPA820
OPA2832 OPA3832
OPA2690 OPA3690
—
—
-100
-120
-140
General-Purpose, High
Slew Rate
Low-Noise, DC
Precision
OPA2822
—
OPA4820
0
20,000
40,000
60,000
80,000
100,000
120,000
Frequency (Hz)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
OPA835
OPA2835
SLOS713E –JANUARY 2011–REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1)
CHANNEL
COUNT
PACKAGE –
LEAD
PACKAGE
DESIGNATOR
PRODUCT
OPA835
1
1
2
2
2
2
SOT23-6
WQFN-10
SOIC-8
DBV
RUN
D
OPA2835
VSSOP-10
WQFN-10
UQFN-10
DGS
RUN
RMC
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
UNITS
VS– to VS+
Supply voltage
5.5
VI
VID
II
Input voltage
VS– - 0.7V to VS+ + 0.7V
Differential input voltage
Continuous input current
Continuous output current
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature range
Storage temperature range
HBM
1 V
0.85 mA
IO
60 mA
See Thermal Characteristics Specification
TJ
150°C
–40°C to 125°C
–65°C to 150°C
6 kV
TA
Tstg
ESD ratings CDM
1 kV
MM
200 V
THERMAL INFORMATION
OPA835
OPA2835
VSSOP
THERMAL METRIC(1)
SOT23-6
WQFN-10
(RUN)
SOT23-6
(D)
(MSOP) - 10 WQFN-10 UQFN-10
UNITS
(DBV)
6 PINS
194
(DGS)
10 PINS
206
(RUN)
10 PINS
145.8
75.1
(RMC)
10 PINS
143.2
49.0
10 PINS
145.8
75.1
8 PINS
150.1
83.8
68.4
33.0
67.9
n/a
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
129.2
39.4
75.3
38.9
96.2
38.9
61.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.6
13.5
12.9
13.5
3.3
ψJB
38.9
104.5
n/a
94.6
104.5
n/a
61.9
θJCbot
n/a
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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Product Folder Links: OPA835 OPA2835
OPA835
OPA2835
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SLOS713E –JANUARY 2011–REVISED JULY 2013
SPECIFICATIONS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply. TA = 25°C. Unless otherwise noted
TEST
PARAMETER
AC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
VOUT = 100 mVPP, G = 1
51
22.5
7.2
VOUT = 100 mVPP, G = 2
VOUT = 100 mVPP, G = 5
VOUT = 100 mVPP, G = 10
VOUT = 100 mVPP, G = 10
VOUT = 1 VPP, G = 1
Small-signal bandwidth
MHz
C
3
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1dB flatness
Slew rate, Rise/Fall
30
MHz
MHz
MHz
V/µs
ns
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
24
VOUT = 1 VPP, G = 2
4
110/130
9.5/9
35/30
60/65
120/90
0.5/0.2
-133
-110
-73
Rise/Fall time
Settling time to 1%, Rise/Fall
Settling time to 0.1%, Rise/Fall
Settling time to 0.01%, Rise/Fall
Overshoot/Undershoot
ns
VOUT = 1VSTEP, G = 2
ns
ns
%
f = 10 kHz, VIN_CM = mid-supply – 0.5V
f = 100 kHz, VIN_CM = mid-supply – 0.5V
f = 1 MHz, VIN_CM = mid-supply – 0.5V
f = 10 kHz, VIN_CM = mid-supply – 0.5V
f = 100 kHz, VIN_CM = mid-supply – 0.5V
f = 1 MHz, VIN_CM = mid-supply – 0.5V
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
dBc
dBc
-137
-125
-78
2nd Order Intermodulation Distortion
3rd Order Intermodulation Distortion
Input voltage noise
-75
dBc
dBc
f = 1 MHz, 200 kHz Tone Spacing, VOUT Envelope = 1
VPP, VIN_CM = mid-supply – 0.5V
-81
f = 100 KHz
9.3
nV/√Hz
Hz
Voltage Noise 1/f corner frequency
Input current noise
147
f = 1 MHz
0.45
14.7
140/125
0.028
pA/√Hz
kHz
Current Noise 1/f corner frequency
Overdrive recovery time, Over/Under
Closed-loop output impedance
Overdrive = 0.5 V
f = 100 kHz
ns
Ω
Channel to channel crosstalk
(OPA2835)
f = 10 kHz
-120
dB
C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Copyright © 2011–2013, Texas Instruments Incorporated
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OPA2835
SLOS713E –JANUARY 2011–REVISED JULY 2013
www.ti.com
SPECIFICATIONS: VS+ = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply. TA = 25°C. Unless otherwise noted
TEST
PARAMETER
DC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
Open-loop voltage gain (AOL
Input referred offset voltage
Input offset voltage drift(2)
)
100
120
dB
A
A
TA = 25°C
±100
±500
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
±880
µV
±1040
B
±1850
±8.5
±1.4
±1.5
±9
±13.5
400
µV/°C
nA
B
A
B
±2.25
200
50
47
45
45
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
410
Input bias current
425
530
±0.25
±0.175
±0.185
±13
±1.4
Input bias current drift(2)
Input offset current
±1.05
±1.1
nA/°C
nA
B
A
B
±100
±100
±100
±100
±1.230
±0.940
±0.940
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
±13
±13
±13
±0.205
±0.155
±0.155
Input offset current drift(2)
nA/°C
B
INPUT
TA = 25°C, <3dB degradation in CMRR limit
–0.2
–0.2
1.6
0
0
V
V
V
V
A
B
A
B
Common-mode input range low
Common-mode input range high
TA = –40°C to 125°C, <3dB degradation in
CMRR limit
TA = 25°C, <3dB degradation in CMRR limit
1.5
1.5
88
TA = –40°C to 125°C, <3dB degradation in
CMRR limit
1.6
Common-mode rejection ratio
Input impedance common mode
Input impedance differential mode
OUTPUT
110
200||1.2
200||1
dB
A
C
C
kΩ || pF
kΩ || pF
TA = 25°C, G = 5
0.15
0.15
2.5
0.2
0.2
V
V
A
B
A
B
C
A
B
Linear output voltage low
Linear output voltage high
TA = –40°C to 125°C, G = 5
TA = 25°C, G = 5
2.45
2.45
V
TA = –40°C to 125°C, G = 5
2.5
V
Output saturation voltage, High / Low TA = 25°C, G = 5
45/13
±35
mV
mA
mA
TA = 25°C
Linear output current drive
±25
±20
TA = –40°C to 125°C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
4
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: OPA835 OPA2835
OPA835
OPA2835
www.ti.com
SLOS713E –JANUARY 2011–REVISED JULY 2013
SPECIFICATIONS: VS+ = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = +2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply. TA = 25°C. Unless otherwise noted
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
GAIN SETTING RESISTORS (OPA835IRUN ONLY)
Resistor FB1 to FB2
DC resistance
DC resistance
DC resistance
DC resistance
DC resistance
2376
1782
594
2400
1800
600
2424
1818
606
±1
Ω
Ω
A
A
A
A
C
Resistor FB2 to FB3
Resistor FB3 to FB4
Ω
Resistor Tolerance
%
Resistor Temperature Coefficient
POWER SUPPLY
<10
PPM
Specified operating voltage
2.5
175
135
88
5.5
340
345
V
B
A
B
A
TA = 25°C
245
105
µA
µA
dB
Quiescent operating current per
amplifer
TA = –40°C to 125°C
Power supply rejection (±PSRR)
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold
Disable voltage threshold
Powerdown pin bias current
Powerdown quiescent current
Specified "on" above VS–+ 2.1 V
1.4
1.4
20
2.1
V
V
A
A
A
A
Specified "off" below VS–+ 0.7 V
PD = 0.5 V
0.7
500
1.5
nA
µA
PD = 0.5 V
0.5
Time from PD = high to VOUT = 90% of final
value
Turn-on time delay
Turn-off time delay
250
50
ns
ns
C
C
Time from PD = low to VOUT = 10% of original
value
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OPA2835
SLOS713E –JANUARY 2011–REVISED JULY 2013
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SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
TEST
PARAMETER
AC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
VOUT = 100 mVPP, G = 1
56
22.5
VOUT = 100 mVPP, G = 2
VOUT = 100 mVPP, G = 5
VOUT = 100 mVPP, G = 10
VOUT = 100 mVPP, G = 10
VOUT = 2 VPP, G = 1
Small-signal bandwidth
MHz
C
7.4
3.1
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1dB flatness
Slew rate, Rise/Fall
31
MHz
MHz
MHz
V/µs
ns
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
31
VOUT = 2 VPP, G=2
14.5
160/260
10/7
Rise/Fall time
Settling time to 1%, Rise/Fall
Settling time to 0.1%, Rise/Fall
Settling time to 0.01%, Rise/Fall
Overshoot/Undershoot
45/45
50/55
82/85
2.5/1.5
–135
–105
-70
ns
VOUT = 2 V Step, G = 2
ns
ns
%
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
dBc
dBc
–139
–122
-73
2nd Order Intermodulation Distortion
3rd Order Intermodulation Distortion
–70
dBc
dBc
%
f = 1 MHz, 200 kHz Tone Spacing,
VOUT Envelope = 2 VPP
–83
0.00015
-116.4
0.00003
-130
Signal to Noise Ratio, SNR
f = 1kHz, VOUT = 1 VRMS, 22kHz bandwidth
C
dBc
%
C
C
C
C
C
C
C
C
Total Harmonic Distortion, THD
f = 1kHz, VOUT = 1 VRMS
f = 100 KHz
dBc
nV/√Hz
Hz
Input voltage noise
9.3
Voltage Noise 1/f corner frequency
Input current noise
147
f = 1 MHz
0.45
pA/√Hz
Hz
Current Noise 1/f corner frequency
Overdrive recovery time, Over/Under
Closed-loop output impedance
14.7
Overdrive = 0.5 V
f = 100 kHz
195/135
0.028
ns
Ω
Channel to channel crosstalk
(OPA2835)
f = 10 kHz
-120
dB
C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
6
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: OPA835 OPA2835
OPA835
OPA2835
www.ti.com
SLOS713E –JANUARY 2011–REVISED JULY 2013
SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5 V, VS– = 0 V, VO = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
TEST
PARAMETER
DC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
Open-loop voltage gain (AOL
Input referred offset voltage
Input offset voltage drift(2)
)
100
120
dB
A
A
TA = 25°C
±100
±500
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
±880
µV
±1040
B
±1850
±8.5
±1.4
±1.5
±9
±13.5
400
µV/°C
nA
B
A
B
±2.25
200
50
47
45
45
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
410
Input bias current
425
530
±0.25
±0.175
±0.185
±13
±1.4
Input bias current drift(2)
Input offset current
±1.05
±1.1
nA/°C
nA
B
A
B
±100
±100
±100
±100
±1.23
±0.94
±0.94
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
±13
±13
±13
±0.205
±0.155
±0.155
Input offset current drift(2)
nA/°C
B
INPUT
TA = 25°C, <3dB degradation in CMRR limit
–0.2
–0.2
0
0
V
A
B
A
B
A
C
C
Common-mode input range low
Common-mode input range high
TA = –40°C to 125°C, <3dB degradation in CMRR limit
TA = 25°C, <3dB degradation in CMRR limit
V
V
3.8
3.8
91
3.9
TA = –40°C to 125°C, <3dB degradation in CMRR limit
3.9
V
Common-mode rejection ratio
Input impedance common mode
Input impedance differential mode
OUTPUT
113
dB
200||1.2
200||1
kΩ || pF
kΩ || pF
TA = 25°C, G = 5
0.15
0.15
4.8
0.2
0.2
V
V
A
B
A
B
C
A
B
Linear output voltage low
Linear output voltage high
TA = –40°C to 125°C, G = 5
TA = 25°C, G = 5
4.75
4.75
V
TA = –40°C to 125°C, G = 5
4.8
V
Output saturation voltage, High / Low TA = 25°C, G = 5
70/25
±40
mV
mA
mA
TA = 25°C
Linear output current drive
±30
±25
TA = –40°C to 125°C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: OPA835 OPA2835
OPA835
OPA2835
SLOS713E –JANUARY 2011–REVISED JULY 2013
www.ti.com
SPECIFICATIONS: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +5 V, VS– = 0 V, VO = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(1)
GAIN SETTING RESISTORS (OPA835IRUN ONLY)
Resistor FB1 to FB2
DC resistance
DC resistance
DC resistance
DC resistance
DC resistance
2376
1782
594
2400
1800
600
2424
1818
606
±1
Ω
Ω
A
A
A
A
C
Resistor FB2 to FB3
Resistor FB3 to FB4
Ω
Resistor Tolerance
%
Resistor Temperature Coefficient
POWER SUPPLY
<10
PPM
Specified operating voltage
2.5
200
150
90
5.5
350
365
V
B
A
B
A
TA = 25°C
250
110
µA
µA
dB
Quiescent operating current per
amplifier
TA = –40°C to 125°C
Power supply rejection (±PSRR)
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold
Disable voltage threshold
Powerdown pin bias current
Powerdown quiescent current
Turn-on time delay
Specified "on" above VS–+ 2.1 V
Specified "off" below VS–+ 0.7 V
PD = 0.5 V
1.4
1.4
20
2.1
V
V
A
A
A
A
C
C
0.7
500
1.5
nA
µA
ns
ns
PD = 0.5 V
0.5
200
60
Time from PD = high to VOUT = 90% of final value
Time from PD = low to VOUT = 10% of original value
Turn-off time delay
8
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SLOS713E –JANUARY 2011–REVISED JULY 2013
DEVICE INFORMATION
PIN CONFIGURATIONS
OPA835 (TOP VIEW)
SOT23-6 (DBV)
OPA835 (TOP VIEW)
WFQN-10 (RUN)
VS+
VS+
VOUT
1
2
3
6
5
4
VOUT
FB1
FB2
1
2
3
4
9
8
7
6
10
2.4k
VS-
PD
+ -
-
+
VIN+
VIN-
VIN-
1.8k
600
FB3
FB4
VIN+
PD
5
VS-
OPA2835 (TOP VIEW)
SOIC-8 (D)
OPA2835 (TOP VIEW)
VSSOP (MSOP) -10 (DGS)
VOUT1
VIN1-
VIN1+
VS-
VOUT1
1
2
3
4
8
7
1
2
3
4
5
10
9
VS+
VS+
VIN1-
VOUT2
VIN2-
VIN2+
PD2
VOUT2
VIN2-
-
-
+
+
6
5
VIN1+
VS-
8
7
6
-
-
+
+
VIN2+
PD1
OPA2835 (TOP VIEW)
WQFN-10 (RUN), UQFN-10 (RMC)
VS+
VOUT1
1
2
3
4
9
8
7
6
VOUT2
10
-
+
-
+
VIN1-
VIN2-
VIN2+
VIN1+
PD2
PD1
5
VS-
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PIN FUNCTIONS
PIN
DESCRIPTION
NUMBER
NAME
OPA835 DBV PACKAGE
1
2
3
4
5
6
VOUT
Amplifier output
VS–
VIN+
VIN–
PD
Negative power supply input
Amplifier non-inverting input
Amplifier inverting input
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
VS+
Positive power supply input
OPA835 RUN PACKAGE
1
2
VOUT
Amplifier output
VIN–
VIN+
PD
Amplifier inverting input
3
Amplifier non-inverting input
4
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
Negative power supply input
5
VS–
FB4
FB3
FB2
FB1
VS+
6
Connection to bottom of 250 Ω internal gain setting resistors
Connection to junction of 750 and 250 Ω internal gain setting resistors
Connection to junction of 1k and 750 Ω internal gain setting resistors
Connection to top of 1kΩ internal gain setting resistors
Positive power supply input
7
8
9
10
OPA2835 D PACKAGE
1
2
3
4
5
6
7
8
VOUT1
Amplifier 1 output
VIN1–
VIN1+
VS–
Amplifier 1 inverting input
Amplifier 1 non-inverting input
Negative power supply input
Amplifier 2 non-inverting input
Amplifier 2 inverting input
Amplifier 2 output
VIN2+
VIN2–
VOUT2
VS+
Positive power supply input
OPA2835 DSG PACKAGE
1
2
VOUT1
VIN1–
VIN1+
VS–
Amplifier 1 output
Amplifier 1 inverting input
3
Amplifier 1 non-inverting input
4
Negative power supply input
5
PD1
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
6
PD2
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
7
VIN2+
VIN2–
VOUT2
VS+
Amplifier 2 non-inverting input
Amplifier 2 inverting input
Amplifier 2 output
8
9
10
Positive power supply input
OPA2835 RUN AND RMC PACKAGES
1
2
3
4
5
6
7
VOUT1
VIN1–
VIN1+
PD1
VS–
Amplifier 1 output
Amplifier 1 inverting input
Amplifier 1 non-inverting input
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
Negative power supply input
PD2
VIN2+
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
Amplifier 2 non-inverting input
10
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SLOS713E –JANUARY 2011–REVISED JULY 2013
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NUMBER
NAME
VIN2–
VOUT2
VS+
8
9
Amplifier 2 inverting input
Amplifier 2 output
10
Positive power supply input
SPACER
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7 V, VS– = 0 V, VOUT = 1 Vpp, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply unless otherwise noted. TA = 25°C.
Table of Graphs
FIGURES
Small Signal Frequency Response
Large Signal Frequency Response
Noninverting Pulse Response
Inverting Pulse Response
Slew rate
Figure 1
Figure 2
Figure 3
Figure 4
vs Output Voltage Step
Figure 5
Output Overdrive Recovery
Harmonic Distortion
Figure 6
vs Frequency
Figure 7
Harmonic Distortion
vs Load Resistance
vs Output Voltage
vs Gain
Figure 8
Harmonic Distortion
Figure 9
Harmonic Distortion
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Output Voltage Swing
Output Saturation Voltage
Output Impedance
vs Load Resistance
vs Load Current
vs Frequency
Frequency Response with Capacitive Load
Series Output Resistor
Input Referred Noise
vs Capacitive Load
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Open Loop Gain
Common Mode/Power Supply Rejection Ratios
Crosstalk
Power Down Response
Input Offset Voltage
Input Offset Voltage
vs Free-Air Temperature
vs Free-Air Temperature
Input Offset Voltage Drift
Input Offset Current
Input Offset Current
Input Offset Current Drift
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V
21
18
15
12
9
21
18
15
12
9
V
V
= 2.7 V,
S
V
V
= 2.7 V,
G = 10
S
G = 10
G = 5
= 1 Vpp,
OUT
= 100 mVpp,
OUT
= 2 kW
R
= 2 kW
L
R
L
G = 5
6
6
G = 2
G = 2
G = 1
G = -1
10M
3
3
0
0
-3
-3
G = 1
-6
-9
-6
-9
G = -1
1M
100M
100k
1M
10M
f - Frequency - Hz
100M
100k
f - Frequency - Hz
Figure 1. Small Signal Frequency Response
Figure 2. Large Signal Frequency Response
3
2.5
2
V
= 2.7 V,
S
V
= 2.7 V,
S
G = -1,
G = 1,
R
= 2 kW
F
L
2.5
R
= 0 W
F
L
R
= 2 kW
R
= 2 kW
V
= 2 Vpp
OUT
2
1.5
1
1.5
1
V
= 1.5 Vpp
OUT
V
= 0.5 Vpp
OUT
0.5
0
0.5
0
V
OUT
= 0.5 Vpp
0
500
t - Time - ns
1000
0
500
t - Time - ns
1000
Figure 3. Noninverting Pulse Response
Figure 4. Inverting Pulse Response
140
120
100
80
0.75
0.5
3.75
3.25
V
= 2.7 V,
S
V
= 2.7 V,
S
V
IN
G = 2,
G = 5,
R
= 2 kW
F
L
R
R
= 2 kW,
V
F
L
OUT
2.75
2.25
1.75
1.25
0.75
0.25
-0.25
R
= 2 kW
= 2 kW
Falling
Rising
0.25
60
40
0
20
0
-0.75
-1.25
-0.25
0.5
0.6
0.7
0.8
0.9
1
0
500
1000
1500
2000
Output Voltage Step - V
t - Time - ns
Figure 5. Slew Rate vs Output Voltage Step
Figure 6. Output Overdrive Recovery
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
-30
-40
-50
-55
-60
-65
-70
-75
-80
V
= 2.7 V,
V
= 2.7 V,
S
S
G = 1,
f = 1 MHz,
G = 1,
V
= 1 Vpp,
OUT
-50
R
V
= 0 W
F
R
R
= 0 W,
F
L
= 1 Vpp
OUT
= 2 kW
-60
-70
-80
HD
2
-90
HD
2
-100
-110
-120
-130
-140
HD
3
HD
3
-85
-90
100
1k
- Load Resistance - W
10k
1M
10M
10k
100k
R
f - Frequency - Hz
LOAD
Figure 7. Harmonic Distortion vs Frequency
Figure 8. Harmonic Distortion vs Load Resistance
-30
-40
-50
-60
-70
-80
-90
-40
-45
-50
-55
-60
-65
-70
-75
-80
V
= 2.7 V,
V
= 2.7 V,
S
S
G = 1,
f = 1 MHz,
G = 1,
f = 1 MHz,
V
R
R
= 0 W,
= 2 kW
= 1 Vpp,
F
L
OUT
R
= 2 kW
L
HD
3
HD
2
HD
2
HD
3
-85
-90
1
2
3
4
5
Gain - V/V
6
7
8
9
10
0
1
2
V
- Output Voltage - Vpp
O
Figure 9. Harmonic Distortion vs Output Voltage
Figure 10. Harmonic Distortion vs Gain
1
3
V
= 2.7 V,
V
= 2.7 V,
S
S
G = 5,
= 2 kW
G = 5,
= 2 kW
R
R
F
2.5
F
V
= High
OUT
V
= High
2
1.5
1
0.1
OUT
V
= Low
OUT
0.01
0.5
0
V
= Low
OUT
0.001
10
100
1k
- Load Resistance - W
10k
0.1
1
10
- Load Current - mA
100
I
R
L
L
Figure 11. Output Voltage Swing vs Load Resistance
Figure 12. Output Saturation Voltage vs Load Current
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
1000
100
10
3
V
= 2.7 V,
S
G = 1
C
= 10 pF
0
L
R
= 0 W
O
C
R
= 100 pF
L
C
= 22 pF
L
= 40.2 W
O
R
= 76.8 W
O
-3
-6
C
= 220 pF
L
C
= 1 pF
L
R
= 24.9 W
O
1
0.1
R
= 0 W
O
C
= 560 pF
L
R
= 13 W
O
V
= 2.7 V,
S
C
= 1000 pF
G = 1,
L
R
= 0 W
R
= 10 W
F
L
O
R
= 2 kW
0.01
10k
-9
100k
1M
10M
100M
100k
1G
10M
100M
1G
1M
f - Frequency - Hz
f - Frequency - Hz
Figure 13. Output Impedance vs Frequency
Figure 14. Frequency Response with Capacitive Load
100
100
V
= 2.7 V,
V
= 2.7 V
S
S
G = 1,
R
R
= 0 W,
F
L
= 2 kW
Voltage Noise
10
10
1
Current Noise
1
10
0.1
10
100
1000
100
1k
10k
f - Frequency - Hz
100k
1M
10M
C
- Capacitive Load - pF
LOAD
Figure 15. Series Output Resistor vs Capacitive Load
Figure 16. Input Referred Noise vs Frequency
0
-10
-20
-30
-40
-50
140
130
120
110
100
90
0
V
= 2.7 V
S
V
= 2.7 V
S
-50
Open Loop Gain Phase
-100
-150
-200
-250
-300
80
PSRR
70
Open Loop Gain Magnitude
60
CMRR
50
40
30
20
10
-60
-70
-80
0
-10
-20
-350
-400
-30
-40
1
10
100
1k
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
f - Frequency - Hz
f - Frequency - Hz
Figure 17. Open Loop Gain vs Frequency
Figure 18. Common Mode/Power Supply Rejection Ratios
vs Frequency
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
3
2.5
2
V
= 2.7 V,
S
G = 2,
−80
−90
R
R
= 2 kW
F
L
V
= 2 kW
PD
−100
1.5
1
V
OUT
−110
−120
0.5
0
−130
−140
20
100
1k
10k 100k
Frequency (Hz)
1M
10M 50M
0
500
t - Time - ns
1000
Figure 19. Crosstalk vs Frequency
Figure 20. Power Down Response
800
600
400
200
0
1600
1400
1200
1000
800
600
400
200
0
1412
1143
962
582
-200
-400
-600
-800
395
158
112
52
26
17
2 1 0 0 0 0
13
4
0
0
0
1
-40
-20
0
20
40
60
80
100
120
T
- Free-Air Temperature - °C
A
V
- Offset Voltage - mV
OS
Figure 21. Input Offset Voltage
Figure 22. Input Offset Voltage vs Free-Air Temperature
3.5
3
1200
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
967
904
1000
800
600
400
2.5
2
772
695
1.5
1
402
369
213
174
200
0
0.5
0
80
81
36
37
24
32
31
13 16
14
4
9
3
4
-5 -4.5 -4 -3.5 -3-2.5 -2-1.5 -1-0.5 0 0.5 1 1.5 2 2.5
- Drift - mV/°C
3 3.5 4 4.5 5
V
OS
I
- Offset Current - nA
OS
Figure 23. Input Offset Voltage Drift
Figure 24. Input Offset Current
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
7
6
5
4
3
100
80
60
40
20
0
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
-20
-40
-60
2
1
0
-80
-100
-250 -200-150-100-50
0
50 100 150 200 250 300 350 400 450 500 550
- Drift - pA/°C
-40
-20
0
20
40
60
80
100
120
I
OS
T
- Free-Air Temperature - °C
A
Figure 25. Input Offset Current vs Free-Air Temperature
Figure 26. Input Offset Current Drift
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5 V, VS– = 0 V, VOUT = 2 Vpp, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, Input and
Output Referenced to mid-supply unless otherwise noted. TA = 25°C.
Table of Graphs
FIGURES
Small Signal Frequency Response
Large Signal Frequency Response
Noninverting Pulse Response
Inverting Pulse Response
Slew rate
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
vs Output Voltage Step
Output Overdrive Recovery
Harmonic Distortion
vs Frequency
Harmonic Distortion
vs Load Resistance
vs Output Voltage
vs Gain
Harmonic Distortion
Harmonic Distortion
Output Voltage Swing
Output Saturation Voltage
Output Impedance
vs Load Resistance
vs Load Current
vs Frequency
Frequency Response with Capacitive Load
Series Output Resistor
Input Referred Noise
vs Capacitive Load
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Open Loop Gain
Common Mode/Power Supply Rejection Ratios
Crosstalk
Power Down Response
Input Offset Voltage
Input Offset Voltage
vs Free-Air Temperature
vs Free-Air Temperature
Input Offset Voltage Drift
Input Offset Current
Input Offset Current
Input Offset Current Drift
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V
21
18
15
12
9
21
18
15
12
9
V
V
= 5 V,
V
V
= 5 V,
S
S
G = 10
G = 10
G = 5
= 100 mVpp,
= 2 Vpp,
OUT
= 2 kW
OUT
R
R
= 2 kW
L
L
G = 5
6
6
G = 2
G = 2
3
3
G = -1
G = 1
0
0
-3
-3
G = 1
-6
-9
-6
-9
G = -1
100k
1M
10M
100M
1M
10M
100M
100k
f - Frequency - Hz
f - Frequency - Hz
Figure 27. Small Signal Frequency Response
Figure 28. Large Signal Frequency Response
5
4.5
4
5
4.5
4
V
= 5 V,
S
G = -1,
R
= 2 kW
V
= 4 Vpp
F
L
OUT
R
= 2 kW
V
= 4 Vpp
OUT
3.5
3
3.5
3
V
= 5 V,
S
G = 1,
R
= 0 W
2.5
2
2.5
2
F
L
V
= 0.5 Vpp
OUT
R
= 2 kW
1.5
1
1.5
1
0.5
0
0.5
0
V
= 0.5 Vpp
OUT
0
500
t - Time - ns
1000
0
500
t - Time - ns
1000
Figure 29. Noninverting Pulse Response
Figure 30. Inverting Pulse Response
300
250
200
150
100
50
6.25
5.75
5.25
4.75
4.25
3.75
3.25
2.75
2.25
1.75
1.25
0.75
0.25
-0.25
1.25
1
V
S
= 5 V,
V
= 5 V,
V
S
IN
G = 5,
G = 2,
Falling
V
OUT
R
R
= 2 kW,
R
= 2 kW
F
L
F
L
= 2 kW
R
= 2 kW
0.75
0.5
Rising
0.25
0
-0.75
-1.25
0
0
-0.25
1
2
3
4
500
0
1000
1500
2000
Output Voltage Step - V
t - Time - ns
Figure 31. Slew Rate vs Output Voltage Step
Figure 32. Output Overdrive Recovery
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
-30
-50
-55
-60
-65
-70
-75
-80
-85
-90
V
= 5 V,
V
= 5 V,
S
S
-40
-50
G = 1,
f = 1 MHz,
G = 1,
V
= 2 Vpp,
OUT
R
V
= 0 W
F
R
R
= 0 W,
F
L
= 2 Vpp
OUT
-60
= 2 kW
-70
HD
2
-80
-90
HD
2
HD
-100
-110
-120
-130
-140
3
HD
3
10k
100k
1M
10M
100
1k
- Load Resistance - W
10k
f - Frequency - Hz
R
LOAD
Figure 33. Harmonic Distortion vs Frequency
Figure 34. Harmonic Distortion vs Load Resistance
-40
-45
-50
-55
-60
-65
-70
-75
-80
-40
-45
-50
-55
-60
-65
-70
-75
-80
V
= 5 V,
V
= 5 V,
S
S
G = 1,
f = 1 MHz,
G = 1,
f = 1 MHz,
V
R
R
= 0 W,
= 2 kW
= 2 Vpp,
F
L
OUT
R
= 2 kW
HD
L
3
HD
3
HD
2
HD
2
-85
-90
-85
-90
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
Gain - V/V
V
- Output Voltage - Vpp
O
Figure 35. Harmonic Distortion vs Output Voltage
Figure 36. Harmonic Distortion vs Gain
1
5
4
V
= 5 V,
V
= 5 V,
S
S
G = 5,
= 2 kW
G = 5,
= 2 kW
V
= High
OUT
R
R
F
F
3
2
V
= High
OUT
0.1
V
= Low
OUT
1
0
V
= Low
OUT
0.01
0.1
1
10
- Load Current - mA
100
10
100
1k
- Load Resistance - W
10k
I
L
R
L
Figure 37. Output Voltage Swing vs Load Resistance
Figure 38. Output Saturation Voltage vs Load Current
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
3
V
= 5 V,
V
= 5 V,
S
S
100
G = 1
G = 1,
R
= 0 W
F
L
R
= 2 kW
0
10
C
= 10 pF
C
R
= 100 pF
L
L
R
= 0 W
= 40.2 W
O
O
C
R
= 220 pF
C
= 1 pF
L
L
-3
-6
1
= 24.9 W
R
= 0 W
O
O
C
= 560 pF
L
C
= 22 pF
L
R
= 13 W
O
R
= 76.8 W
O
0.1
C
= 1000 pF
L
R
= 10 W
O
0.01
10K
-9
100k
100K
1M 10M
f - Frequency - Hz
100M
1G
10M
1M
100M
1G
f - Frequency - Hz
Figure 39. Output Impedance vs Frequency
Figure 40. Frequency Response with Capacitive Load
100
100
V
= 5 V,
V
= 5 V
S
S
G = 1,
R
R
= 0 W,
F
L
= 2 kW
Voltage Noise
10
10
1
Current Noise
1
10
0.1
10
100
1000
100
1k
10k
f - Frequency - Hz
100k
1M
10M
C
- Capacitive Load - pF
LOAD
Figure 41. Series Output Resistor vs Capacitive Load
Figure 42. Input Referred Noise vs Frequency
140
130
120
110
100
0
0
V
= 5 V
S
V
= 5 V
S
-50
-10
-20
-30
-40
-50
Open Loop Gain Phase
-100
-150
-200
-250
-300
-350
-400
PSRR
90
80
70
60
50
40
30
20
10
0
CMRR
Open Loop Gain Magnitude
-60
-70
-80
-10
-20
-30
-40
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
10M 100M
1G
f - Frequency - Hz
f - Frequency - Hz
Figure 43. Open Loop Gain vs Frequency
Figure 44. Common Mode/Power Supply Rejection Ratios
vs Frequency
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
5
4.5
4
V
= 5 V,
S
G = 2,
V
PD
−80
−90
R
R
= 2 kW
F
L
= 2 kW
3.5
3
V
OUT
−100
2.5
2
−110
−120
1.5
1
−130
0.5
0
−140
20
0
500
t - Time - ns
1000
100
1k
10k 100k
Frequency (Hz)
1M
10M 50M
Figure 45. Crosstalk vs Frequency
Figure 46. Power Down Response
1600
1400
1200
1000
800
800
600
400
200
0
1404
1156
965
590
-200
-400
-600
-800
600
377
400
170
108
200
53
26
11
13
2
0
0
0
1
3
1 0 0 0 0
0
100
120
-40
-20
0
20
40
80
60
T
- Free-Air Temperature - °C
A
V
- Offset Voltage - mV
OS
Figure 47. Input Offset Voltage
Figure 48. Input Offset Voltage vs Free-Air Temperature
3.5
1000
948
895
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
900
800
700
600
500
400
300
200
3
2.5
2
754
715
397
1.5
1
382
205
188
94
0.5
0
75
100
0
34
36
26
31
5 3
37
14
20
9
7
5
-5 -4.5 -4 -3.5 -3-2.5 -2-1.5 -1-0.5 0 0.5 1 1.5 2 2.5
3 3.5 4 4.5 5
V
- Drift - mV/°C
OS
I
- Offset Current - nA
OS
Figure 49. Input Offset Voltage Drift
Figure 50. Input Offset Current
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
100
80
9
8
7
6
5
4
3
2
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
60
40
20
0
-20
-40
-60
-80
-100
1
0
40
-250 -200-150-100-50
0
50 100 150 200 250 300 350 400 450 500 550
- Drift - pA/°C
-20
0
-40
20
60
80
120
100
I
OS
T
- Free-Air Temperature - °C
A
Figure 51. Input Offset Current vs Free-Air Temperature
Figure 52. Input Offset Current Drift
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APPLICATION INFORMATION
The following circuits show application information for the OPA835 and OPA2835. For simplicity, power supply
decoupling capacitors are not shown in these diagrams.
Non-Inverting Amplifier
The OPA835 and OPA2835 can be used as non-inverting amplifiers with signal input to the non-inverting input,
VIN+. A basic block diagram of the circuit is shown in Figure 53.
If we set VIN = VREF + VSIG, then
æ
ö
÷
ø
RF
V
OUT
= VSIG 1 +
+ VREF
ç
RG
è
(1)
RF
G = 1 +
RG
The signal gain of the circuit is set by:
, and VREF provides a reference around which the input and
output signals swing. Output signals are in-phase with the input signals.
The OPA835 and OPA2835 are designed for the nominal value of RF to be 2kΩ in gains other than +1. This
gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 2kΩ
should be used as a default unless other design goals require changing to other values All test circuits used to
collect data for this data sheet had RF = 2kΩ for all gains other than +1. Gain of +1 is a special case where RF is
shorted and RG is left open.
V
SIG
V
V
S+
REF
V
IN
V
OPA835
R
OUT
G
GV
SIG
V
V
REF
REF
V
S-
R
F
Figure 53. Non-Inverting Amplifier
Inverting Amplifier
The OPA835 and OPA2835 can be used as inverting amplifiers with signal input to the inverting input, VIN-
,
through the gain setting resistor RG. A basic block diagram of the circuit is shown in Figure 54.
If we set VIN = VREF + VSIG, then
æ
SIG ç
è
ö
÷
ø
-RF
V
= V
+ V
REF
OUT
RG
(2)
-RF
G =
RG
The signal gain of the circuit is set by:
and VREF provides a reference point around which the input
and output signals swing. Output signals are 180˚ out-of-phase with the input signals. The nominal value of RF
should be 2kΩ for inverting gains.
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V
S+
V
REF
V
SIG
V
REF
V
OPA835
OUT
R
G
GV
V
IN
SIG
V
REF
V
S-
R
F
Figure 54. Inverting Amplifier
Attenuators
The non-inverting circuit of Figure 53 has minimum gain of 1. To implement attenuation, a resistor divider can be
placed in series with the positive input, and the amplifier set for gain of 1 by shorting VOUT to VIN- and removing
RG. Since the op amp input is high impedance, the attenuation is set by the resistor divider.
The inverting circuit of Figure 54 can be used as an attenuator by making RG larger than RF. The attenuation is
simply the resistor ratio. For example a 10:1 attenuator can be implemented with RF = 2 kΩ and RG = 20 kΩ.
Single Ended to Differential Amplifier
Figure 55 shows an amplifier circuit that is used to convert single-ended signals to differential, and provides gain
and level shifting. This circuit can be used for converting signals to differential in applications like line drivers for
CAT 5 cabling or driving differential input SAR and ΔΣ ADCs.
By setting VIN = VREF + VSIG, then
R
F
V
= G x V + V
IN REF
and V
OUT-
= -G x V + V Where: G = 1 +
IN REF
OUT+
R
G
(3)
The differential signal gain of the circuit is 2x G, and VREF provides a reference around which the output signal
swings. The differential output signal is in-phase with the single ended input signal.
RO
G x VSIG
VOUT+ VREF
VSIG
VREF
R1
OPA835
2R
2R
VIN
+
VREF
VREF
RO
-G x VSIG
VOUT- VREF
+
OPA835
RG
RF
Figure 55. Single Ended to Differential Amplifier
Line termination on the output can be accomplished with resistors RO. The impedance seen differential from the
line will be 2x RO. For example if 100 Ω CAT 5 cable is used with double termination, the amplifier is typically set
for a differential gain of 2 V/V (6 dB) with RF = 0 Ω (short) RG = ∞Ω (open), 2R = 2 kΩ, R1 = 0 Ω, R = 1 kΩ to
balance the input bias currents, and RO = 49.9 Ω for output line termination. This configuration is shown in
Figure 56.
For driving a differential input ADC the situation is similar, but the output resistors, RO, are typically chosen along
with a capacitor across the ADC input for optimum filtering and settling time performance.
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49.9
VSIG
VOUT+ VREF
VSIG
OPA835
2k
2k
VIN
VREF
+
VREF
49.9
-VSIG
VOUT- VREF
+
OPA835
1k
Figure 56. CAT 5 Line Driver with Gain = 2 V/V (6 dB)
Differential to Signal Ended Amplifier
Figure 57 shows a differential amplifier that is used to convert differential signals to single-ended and provides
gain (or attenuation) and level shifting. This circuit can be used in applications like a line receiver for converting a
differential signal from a CAT 5 cable to single-ended.
If we set VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG-, then
æ
ç
è
ö
÷
ø
RF
VOUT
=
V
- V
´
+ VREF
(
)
IN+
IN-
RG
(4)
RF
G =
RG
The signal gain of the circuit is set by:
, VCM is rejected, and VREF provides a level shift around which
the output signal swings. The single ended output signal is in-phase with the differential input signal.
V
SIG-
R
F
V
CM
R
G
V
IN-
V
OPA835
R
OUT
G
V
IN+
V
G[(V
V
+)-(V
)]
SIG-
SIG
SIG+
R
F
REF
V
CM
V
REF
Figure 57. Differential to Single Ended Amplifier
Line termination can be accomplished with a resistor shunt across the input. The impedance seen differential
from the line will be the resistor value in parallel with the amplifier circuit. For low gain and low line impedance
the resistor value to add is approximately the impedance of the line. For example, if 100 Ω CAT5 cable is used
with a gain of 1 amplifier and RF = RG = 2 kΩ, adding a 100 Ω shunt across the input will give a differential
impedance of 99 Ω; this should be adequate for most applications.
For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance; so 0.1%
tolerance will provide about 60 dB CMRR.
Differential to Differential Amplifier
Figure 58 shows a differential amplifier that is used to amplify differential signals. This circuit has high input
impedance and is often used in differential line driver applications where the signal source is a high impedance
driver like a differential DAC that needs to drive a line.
If we set VIN± = VCM + VSIG± then
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æ
ö
÷
ø
2RF
RG
V
= V
´ 1 +
+ VCM
ç
IN±
OUT ±
è
(5)
2RF
RG
G = 1 +
The signal gain of the circuit is set by:
, and VCM passes with unity gain. The amplifier in essence
combines two non-inverting amplifiers into one differential amplifier with the RG resistor shared, which makes RG
effectively ½ its value when calculating the gain. The output signals are in-phase with the input signals.
V
IN-
V
OPA835
OUT-
GV
V
SIG-
V
SIG-
CM
V
CM
R
F
R
G
R
F
GV
SIG+
V
V
SIG+
CM
V
CM
V
OPA835
OUT+
V
IN+
Figure 58. Differential to Differential Amplifier
Instrumentation Amplifier
Figure 59 is an instrumentation amplifier that combines the high input impedance of the differential to differential
amplifier circuit and the common-mode rejection of the differential to single-ended amplifier circuit. This circuit is
often used in applications where high input impedance is required like taps from a differential line or in cases
where the signal source is a high impedance.
If we set VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG-, then
æ
ö æ
ö
÷
ø
2R
RF2
RG2
F1 ÷ ç
V
=
V
IN+ - V
´ 1 +
+ V
REF
(
)
ç
IN-
OUT
RG1
è
ø è
(6)
The signal gain of the circuit is set by:
æ
ö æ
ö
÷
ø
2R
RF2
F1 ÷ ç
RG1
G = 1 +
ç
RG2
è
ø è
, VCM is rejected, and VREF provides a level shift around which the output signal
swings. The single ended output signal is in-phase with the differential input signal.
V
IN-
OPA835
V
SIG-
R
F2
V
CM
R
G2
R
F1
R
V
OUT
R
OPA835
G1
G2
R
F1
G[(V
V
+)-(V
)]
SIG
SIG-
V
SIG+
R
F2
REF
V
CM
OPA835
V
REF
V
IN+
Figure 59. Instrumentation Amplifier
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Integrated solutions are available, but the OPA835 provides a much lower power high frequency solution. For
best CMRR performance, resistors must be matched. A rule of thumb is CMRR ≈ the resistor tolerance; so 0.1%
tolerance will provide about 60 dB CMRR.
Gain Setting with OPA835 RUN Integrated Resistors
The OPA835 RUN package option includes integrated gain setting resistors for smallest possible footprint on a
printed circuit board (≈ 2mm x 2mm). By adding circuit traces on the PCB, gains of +1, -1, -1.33, +2, +2.33, -3,
+4, -4, +5, -5.33, +6.33, -7, +8 and inverting attenuations of -0.1429, -0.1875, -0.25, -0.33, -0.75 can be
achieved.
Figure 60 shows a simplified view of how the OPA835IRUN integrated gain setting network is implemented.
Table 1 shows the required pin connections for various non-inverting and inverting gains (reference Figure 53
and Figure 54). Table 2 shows the required pin connections for various attenuations using the inverting amplifier
architecture (reference Figure 54). Due to ESD protection devices being used on all pins, the absolute maximum
and minimum input voltage range, VS– - 0.7V to VS+ + 0.7V, applies to the gain setting resistors, and so
attenuation of large input voltages will require external resistors to implement.
The gain setting resistors are laser trimmed to 1% tolerance with nominal values of 2.4 kΩ, 1.8 kΩ, and 600 Ω.
They have excellent temperature coefficient and gain tracking is superior to using external gain setting resistors.
The 800 Ω and 1.25 pF capacitor in parallel with the 2.4 kΩ gain setting resistor provide compensation for best
stability and pulse response.
FB1
9
FB2
8
FB3
7
FB4
6
2.4 k
1.8 k
600
800 1.25 pF
Figure 60. OPA835IRUN Gain Setting Network
Table 1. Gains Setting
Non-inverting Gain
(Figure 53)
Inverting Gain
(Figure 54)
Short Pins
Short Pins
Short Pins
Short Pins
1 V/V (0 dB)
2 V/V (6.02 dB)
2.33 V/V (7.36 dB)
4 V/V (12.04 dB)
5 V/V (13.98 dB)
-
1 to 9
1 to 9
1 to 9
1 to 8
1 to 9
1 to 9
1 to 9
-
-1 V/V (0 dB)
2 to 8
2 to 8
6 to GND
7 to GND
6 to GND
7 to 8
-
-1.33 V/V (2.5 dB)
-3 V/V (9.54 dB)
-4 V/V (12.04 dB)
-
2 to 7
-
2 to 7 or 8
2 to 6 or 8
2 to 7
6 to GND
7 to GND
-
6.33 V/V (16.03 dB) -5.33 V/V (14.54 dB)
6 to 8
8 V/V (18.06 dB)
-7 V/V (16.90 dB)
6 to GND
Table 2. Attenuator Settings
Inverting Gain
(Figure 54)
Short Pins
Short Pins
Short Pins
Short Pins
-0.75 V/V (-2.5 dB)
-0.333 V/V (-9.54 dB)
-0.25 V/V (-12.04 dB)
-0.1875 V/V (-14.54 dB)
-0.1429 V/V (-16.90 dB)
1 to 7
1 to 6
1 to 6
1 to 7
1 to 6
2 to 8
2 to 7
9 to GND
8 to GND
7 to 8
-
-
2 to 7 or 8
2 to 6 or 8
2 to 7
9 to GND
9 to GND
-
6 to 8
9 to GND
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Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier, with high CMRR, it is important to not violate the input
common-mode voltage range (VICR) of an op amp.
Common-mode input range low and high specifications in the table data use CMRR to set the limit. The limits are
chosen to ensure CMRR will not degrade more than 3dB below its limit if the input voltage is kept within the
specified range. The limits cover all process variations and most parts will be better than specified. The typical
specifications are from 0.2V below the negative rail to 1.1V below the positive rail.
Assuming the op amp is in linear operation the voltage difference between the input pins is very small (ideally
0V) and input common-mode voltage can be analyzed at either input pin and the other input pin is assumed to
be at the same potential. The voltage at VIN+ is easy to evaluate. In non-inverting configuration, Figure 53, the
input signal, VIN, must not violate the VICR. In inverting configuration, Figure 53, the reference voltage, VREF
needs to be within the VICR
,
.
The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For with
single 5 V supply, the linear input voltage range is –0.2 V to 3.9 V and with 2.7 V supply it is –0.2 V to 1.6 V. The
delta from each power supply rail is the same in either case; –0.2 V and 1.1 V.
Output Voltage Range
The OPA835 and OPA2835 are rail-to-rail output (RRO) op amps. Rail-to-rail output typically means the output
voltage can swing to within a couple hundred milli-volts of the supply rails. There are different ways to specify
this; one is with the output still in linear operation and another is with the output saturated. Saturated output
voltages are closer to the power supply rails than linear outputs, but the signal is not a linear representation of
the input. Linear output is a better representation of how well a device performs when used as a linear amplifier.
Both saturation and linear operation limits are affected by the current in the output, where higher currents lead to
more loss in the output transistors.
Data in the ELECTRICAL SPECIFICATIONS tables list both linear and saturated output voltage specifications
with 2kΩ load. Figure 11 and Figure 37 show saturated voltage swing limits versus output load resistance and
Figure 12 and Figure 38 show the output saturation voltage versus load current. Given a light load, the output
voltage limits have nearly constant headroom to the power rails and track the power supply voltages. For
example with 2 kΩ load and single 5 V supply the linear output voltage range is 0.15 V to 4.8 V and with 2.7 V
supply it is 0.15 V to 2.5 V. The delta from each power supply rail is the same in either case; 0.15 V and 0.2 V.
With devices like the OPA835 and OPA2835, where the input range is lower than the output range, it is typical
that the input will limit the available signal swing only in non-inverting gain of 1. Signal swing in non-inverting
configurations in gains > +1 and inverting configurations in any gain is generally limited by the output voltage
limits of the op amp.
Split-Supply Operation (±1.25V to ±2.75V)
To facilitate testing with common lab equipment, the OPA835 EVM SLOU314 is built to allow for split-supply
operation. This configuration eases lab testing because the mid-point between the power rails is ground, and
most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment reference
their inputs and outputs to ground.
Figure 61 shows a simple non-inverting configuration analogous to Figure 53 with ±2.5V supply and VREF equal
to ground. The input and output will swing symmetrically around ground. Due to its ease of use, split supply
operation is preferred in systems where signals swing around ground, but it requires generation of two supply
rails.
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+2.5 V
OPA835
-2.5 V
V
R
OUT
G
V
SIG
Load
R
F
Figure 61. Split Supply Operation
Single-Supply Operation (2.5V to 5.5V)
Many newer systems use single power supply to improve efficiency and reduce the cost of the power supply.
OPA835 and OPA2835 are designed for use with single-supply power operation and can be used with single-
supply power with no change in performance from split supply as long as the input and output are biased within
the linear operation of the device.
To change the circuit from split supply to single supply, level shift of all voltages by ½ the difference between the
power supply rails. For example, changing from ±2.5 V split supply to 5 V single supply is shown conceptually in
Figure 62.
5 V
V
R
OPA835
OUT
G
V
SIG
Load
R
F
2.5 V
Figure 62. Single Supply Concept
A more practical circuit will have an amplifier or other circuit before to provide the bias voltage for the input and
the output provides the bias for the next stage.
Figure 63 shows a typical non-inverting amplifier situation. With 5V single supply, a mid supply reference
generator is needed to bias the negative side via RG. To cancel the voltage offset that would otherwise be
caused by the input bias currents, R1 is chosen to be equal to RF in parallel with RG. For example if gain of 2 is
required and RF = 2 kΩ, select RG = 2 kΩ to set the gain and R1 = 1 kΩ for bias current cancellation. The value
for C is dependent on the reference, but at least 0.1µF is recommended to limit noise.
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Signal and bias
from previous stage
V
SIG
2.5 V
5 V
R
1
R
O
V
OPA835
OUT
GV
SIG
R
G
2.5 V
REF
2.5 V
5 V
C
Signal and bias to
next stage
R
F
Figure 63. Non-Inverting Single Supply with Reference
Figure 64 shows a similar non-inverting single supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5V
supply and are used to bias the negative side with their parallel sum equal to the equivalent RG to set the gain.
To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 in is chosen to be
equal to RF in parallel with RG’ in parallel with RG” (R1= RF||RG’||RG”). For example if gain of 2 is required and RF
= 2 kΩ, selecting RG’ = RG” = 4 kΩ gives equivalent parallel sum of 2 kΩ, sets the gain to 2, and references the
input to mid supply (2.5 V). R1 is then set to 1kΩ for bias current cancellation. This can be lower cost, but note
the extra current draw required in the resistor divider.
Signal and bias
from previous stage
V
SIG
2.5 V
5 V
R
1
R
O
V
OPA835
R ’
OUT
GV
G
SIG
5 V
2.5 V
R ”
G
Signal and bias to
next stage
R
F
Figure 64. Non-Inverting Single Supply with Resistors
Figure 65 shows a typical inverting amplifier situation. With 5V single supply, a mid supply reference generator is
needed to bias the positive side via R1. To cancel the voltage offset that would otherwise be caused by the input
bias currents, R1 is chosen to be equal to RF in parallel with RG. For example if gain of -2 is required and RF = 2
kΩ, select RG = 1 kΩ to set the gain and R1 = 665 Ω for bias current cancellation. The value for C is dependent
on the reference, but at least 0.1µF is recommended to limit noise into the op amp.
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5 V
R
1
2.5 V
REF
R
5 V
O
V
OPA835
OUT
C
GV
SIG
2.5 V
R
Signal and bias to
next stage
R
F
G
V
SIG
2.5 V
Signal and bias
from previous stage
Figure 65. Inverting Single Supply with Reference
Figure 66 shows a similar inverting single supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5V supply and are
used to bias the positive side. To cancel the voltage offset that would otherwise be caused by the input bias
currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C should be added to limit
coupling of noise into the positive input. For example if gain of –2 is required and RF = 2 kΩ, select RG = 1 kΩ to
set the gain. R1 = R2 = 1.33 kΩ for mid supply voltage bias and for op amp input bias current cancellation. A
good value for C is 0.1µF. This can be lower cost, but note the extra current draw required in the resistor divider.
5 V
5 V
R
1
R
O
OPA835
V
OUT
R
C
2
GV
SIG
2.5 V
Signal and bias to
next stage
R
R
F
G
V
SIG
2.5 V
Signal and bias
from previous stage
Figure 66. Inverting Single Supply with Resistors
Pulse Application with Single-Supply
For pulsed applications, where the signal is at ground and pulses to some positive or negative voltage, the circuit
bias voltage considerations are different than with a signal that swings symmetrical about a reference point and
the circuit configuration should be adjusted accordingly. Figure 67 shows a pulsed situation where the signal is at
ground (0 V) and pulses to a positive value.
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Signal and bias
from previous stage
V
SIG
0 V
5 V
R
1
R
O
V
OPA835
OUT
GV
SIG
R
G
0 V
Signal and bias to
next stage
R
F
Figure 67. Non-Inverting Single Supply with Pulse
If the input signal pulses negative from ground, an inverting amplifier is more appropriate as shown in Figure 68.
A key consideration in both non-inverting and inverting cases is that the input and output voltages are kept within
the limits of the amplifier, and since the VICR of the OPA835 includes the negative supply rail, the op amp lends
itself to this application.
5 V
R
1
R
O
V
OPA835
OUT
GV
SIG
R
G
0 V
Signal and bias to
next stage
Signal and bias
from previous stage
0 V
R
F
V
SIG
Figure 68. Inverting Single Supply with Pulse
Power-Down Operation
The OPA835 and OPA2835 include a power-down mode. Under logic control, the amplifiers can be switched
from normal operation to a standby current of <1.5 µA. When the PD pin is connected high, the amplifier is
active. Connecting PD pin low disables the amplifier, and places the output in a high impedance state. Note: the
op amp’s output in gain of +1 is high impedance similar to a 3-state high impedance gate, but in other gains the
feedback network is a parallel load.
The PD pin must be actively driven high or low and should not be left floating. If the power-down mode is not
used, PD should be tied to the positive supply rail.
PD logic states are TTL with reference to the negative supply rail, VS-. When the op amp is powered from single
supply and ground, driving from logic devices with similar VDD voltages to the op amp should not require any
special consideration. When the op amp is powered from split supply, VS- is below ground and an open collector
type of interface with pull-up resistor is more appropriate. Pull-up resistor values should be lower than 100k and
the drive logic should be negated due to the inverting action of an open collector gate.
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Low Power Applications and the Effects of Resistor Values on Bandwidth
The OPA835 and OPA2835 are designed for the nominal value of RF to be 2 kΩ in gains other than +1. This
gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. It also loads
the amplifier. For example; in gain of 2 with RF = RG = 2 kΩ, RG to ground, and VOUT = 4 V, 1mA of current will
flow through the feedback path to ground. In gain of +1, RG is open and no current will flow to ground. In low
power applications, it is desirable to reduce this current by increasing the gain setting resistors values. Using
larger value gain resistors has two primary side effects (other than lower power) due to their interaction with
parasitic circuit capacitance.
1. Lowers the bandwidth.
2. Lowers the phase margin
(a) This will cause peaking in the frequency response.
(b) And will cause over shoot and ringing in the pulse response.
Figure 69 shows the small signal frequency response on OPA835EVM for non-inverting gain of 2 with RF and RG
equal to 2 kΩ, 10 kΩ, and 100 kΩ. The test was done with RL = 2 kΩ. Due to loading effects of RL, lower values
may reduce the peaking, but higher values will not have a significant effect.
21
V
V
= 5 V,
S
R
= 100 kW
F
= 100 Vpp,
18
15
12
9
OUT
G = 2,
= 2 kW
R
L
R
= 10 kW
F
R
= 2 kW
F
6
R
= 100 kW
F
3
C
= 1 pF
F
0
R
F
= 10 kW
-3
C
= 1 pF
F
-6
-9
0
1
10
100
f - Frequency - MHz
Figure 69. Frequency Response with Various Gain Setting Resistor Values
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in
frequency response is synonymous with overshoot and ringing in pulse response). Adding 1 pF capacitors in
parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 70 shows the
test circuit used.
V
IN
V
R
OPA835
OUT
G
2 kW
R
F
C
F
Figure 70. G=2 Test Circuit for Various Gain Setting Resistor Values
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Driving Capacitive Loads
The OPA835 and OPA2835 can drive up to a nominal capacitive load of 10pF on the output with no special
consideration. When driving capacitive loads greater than this, it is recommended to use a small resister (RO) in
series with the output as close to the device as possible. Without RO, capacitance on the output will interact with
the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that will reduce the
phase margin. This will cause peaking in the frequency response and overshoot and ringing in the pulses
response. Interaction with other parasitic elements may lead to instability or oscillation. Inserting RO will isolate
the phase shift from the loop gain path and restore the phase margin; however, it will also limit the bandwidth.
Figure 71 shows the test circuit and Figure 41 shows the recommended values of RO versus capacitive loads,
CL. See Figure 40 for frequency response with various values.
R
V
O
IN
V
OPA835
OUT
C
2 kW
L
Figure 71. RO versus CL Test Circuit
Active Filters
The OPA835 and OPA2835 can be used to design active filters. Figure 73 and Figure 72 show MFB and Sallen-
Key circuits designed using FilterPro™ http://focus.ti.com/docs/toolsw/folders/print/filterpro.html to implement 2nd
order low-pass butterworth filter circuits. Figure 74 shows the frequency response.
1.82 kW
220 pF
1.82 kW
4.22 kW
OPA835
1.5 nF
Figure 72. MFB 100kHz 2nd Order Low-Pass Butterworth Filter Circuit
2.2 nF
562 W
6.19 kW
OPA835
330 pF
Figure 73. Sallen-Key 100kHz 2nd Order Low-Pass Butterworth Filter Circuit
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V
V
= 5 V,
S
= 100 mV
OUT
pp
0
-10
-20
MFB
Sallen-Key
-30
-40
1k
10k
100k
1M
f - Frequency - Hz
Figure 74. MFB and Sallen-Key 2nd Order Low-Pass Butterworth Filter Response
MFB and Sallen-Key filter circuits offer similar performance. The main difference is the MFB is an inverting
amplifier in the pass band and the Sallen-Key is non-inverting. The primary pro for each is the Sallen-Key in unity
gain has no resistor gain error term, and thus no sensitivity to gain error, while the MFB has inherently better
attenuation properties beyond the bandwidth of the op amp.
Audio Frequency Performance
The OPA835 and OPA2835 provide excellent audio performance with very low quiescent power. To show
performance in the audio band, a 2700 series Audio Analyzer from Audio Precision was used to test THD+N and
FFT at 1 VRMS output voltage. Figure 75 is the test circuit used. Note the 100 pF capacitor to ground on the input
helped to decouple noise pick up in the lab and improved noise performance.
Figure 76 shows the THD+N performance with 100 kΩ and 300 Ω loads, and with no weighting and A-weighting.
With no weighting the THD+N performance is dominated by the noise for both loads. A-weighting provides
filtering that improves the noise so a larger difference can be seen between the loads due to more distortion with
RL = 300 Ω.
Figure 77 and Figure 78 show FFT output with a 1 kHz tone and 100kΩ and 300Ω loads. To show relative
performance of the device versus the test set, one channel has the OPA835 in line between generator output
and analyzer input and the other channel is in “Gen Mon” loopback mode, which internally connects the signal
generator to the analyzer input. With 100 kΩ load, Figure 77, the curves are basically indistinguishable from each
other except for noise, which means the OPA835 cannot be directly measured. With 300Ω load, Figure 78, the
main difference between the curves is OPA835 shows higher even order harmonics, but odd order is masked by
the test set performance.
+2.5 V
OPA835
-2.5 V
V
IN
V
OUT
From AP
To AP
100 pF
10 W
Figure 75. OPA835 AP Analyzer Test Circuit
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0
-10
-90
V
V
= 5 V,
V
V
= 5 V,
S
S
= 1 V
,
= 1 V
,
OUT
RMS
OUT
RMS
-20
G = 1,
R
G = 1,
= 0 W
-95
-100
-105
-110
= 0 W,
R
-30
F
F
No weighting
BW = 80 kHz
-40
R
= 300 W,
L
L
R
= 100 kW
-50
-60
-70
A-weighting
-80
R
R
= 300 W,
= 100 kW
L
L
-90
-100
-110
-120
Gen Mon - 100k
= 100k
-115
-120
R
L
-130
-140
0
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
10
100
1k
f - Frequency - Hz
10k
100k
Figure 76. OPA835 1 Vrms 20 Hz to 80 kHz THD+N
Figure 77. OPA835 and AP Gen Mon 1kHz FFT
Plot; VOUT = 1VRMS, RL = 100kΩ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
V
= 5 V,
S
= 1 V
,
OUT
RMS
G = 1,
= 0 W
R
F
Gen Mon - 300
-100
-110
-120
R
L
= 300
-130
-140
0
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
Figure 78. OPA835 and AP Gen Mon 1kHz FFT Plot;
VOUT = 1VRMS, RL = 300Ω
ADC Driver Performance
The OPA835 provides excellent performance when driving high performance delta-sigma (ΔΣ) and successive
approximation register (SAR) ADCs in low power audio and industrial applications.
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OPA835 and ADS8326 Combined Performance
To show achievable performance, the OPA835 is tested as the drive amplifier for the ADS8326. The ADS8326 is
a 16-bit, micro power, SAR ADC with pseudo-differential inputs and sample rates up to 250kSPS. It offers
excellent noise and distortion performance in a small 8-pin SOIC or VSSOP (MSOP) package. Low power and
small size make the ADS8326 and OPA835 an ideal solution for portable and battery-operated systems, for
remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition.
The circuit shown in Figure 79 is used to test the performance, Figure 80 is the FFT plot with 10kHz input
frequency showing the spectral performance, and the tabulated AC analysis results are in Table 3.
2.7 V
V
SIG
V
SIG
2.7V
0
V
1.35
V
4.02 k
2 k
5 V 2.5 V
V
S+
V
IN
100
2.2 nF
V
REF
OPA835
DD
+In
ADS 8326
-In
4.02 k
V
S-
2k
2k
Figure 79. OPA835 and ADS8326 Test Circuit
0
-20
-40
-60
-80
-100
-120
-140
0
20
40
60
f - Frequency - Hz
80
100
120
Figure 80. ADS8326 and OPA835 10kHz FFT
Table 3. AC Analysis
Tone (Hz)
Signal (dBFS)
SNR (dBc)
THD (dBc)
SINAD (dBc)
SFDR (dBc)
10k
–0.85
81.9
–87.5
80.8
89.9
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Layout Recommendations
OPA835 EVM (SLOU314) should be used as a reference when designing the circuit board. It is recommended to
follow the EVM layout of the external components near to the amplifier, ground plane construction, and power
routing as closely as possible. General guidelines are:
1. Signal routing should be direct and as short as possible into an out of the op amp.
2. The feedback path should be short and direct avoiding vias if possible especially with G = +1.
3. Ground or power planes should be removed from directly under the amplifier’s negative input and output
pins.
4. A series output resistor is recommended to be placed as near to the output pin as possible. See
“Recommended Series Output Resistor vs. Capacitive Load” (Figure 41) for recommended values given
expected capacitive load of design.
5. A 2.2 µF power supply decoupling capacitor should be placed within 2 inches of the device and can be
shared with other op amps. For spit supply, a capacitor is required for both supplies.
6. A 0.1 µF power supply decoupling capacitor should be placed as near to the power supply pins as possible.
Preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses TTL logic levels. If not used it should tied to the positive supply to enable the amplifier. If
used, it must be actively driven. A bypass capacitor is not necessary, but can be used for robustness in noisy
environments.
Spacer
REVISION HISTORY
Changes from Revision D (October 2011) to Revision E
Page
•
•
•
•
•
•
Added RMC package to document ....................................................................................................................................... 1
Added RMC package option to Description section ............................................................................................................. 1
Added RMC to Package/Ordering Information table ............................................................................................................ 2
Added RMC to Thermal Information table ............................................................................................................................ 2
Added RMC designator to OPA2835 RUN pin out diagram ................................................................................................. 9
Added RMC pin definitions to Pin Functions table ............................................................................................................. 10
Changes from Revision A (March 2011) to Revision B
Page
•
Changed OPA835 from product preview to production data ................................................................................................ 1
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Changes from Revision B (May 2011) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added the "The OPA835 RUN package..." text to the DESCRIPTION ................................................................................ 1
Removed Product Preview from all devices except OPA835IRUNT and OPA835IRUNR ................................................... 2
Replaced the TBD values in the Thermal Information table ................................................................................................. 2
Changed - Channel to channel crosstalk (OPA2835) Typ value From: TBD To: -120 dB ................................................... 3
Changed the Common-mode rejection ratio Min value From: 91 dB To: 88 dB .................................................................. 4
Added GAIN SETTING RESISTORS (OPA835IRUN ONLY) .............................................................................................. 5
Changed the Quiescent operating current (TA = 25°C) Min value From: 190 µA To: 175 µA .............................................. 5
Changed the Power supply rejection (±PSRR) Min value From: 91 dB To: 88 dB .............................................................. 5
Changed the Powerdown pin bias current CONDITIONS From: PD = 0.7V To: PD = 0.5V ................................................ 5
Changed the Powerdown quiescent current CONDITIONS From: PD = 0.7V To: PD = 0.5V ............................................. 5
Changed - Channel to channel crosstalk (OPA2835) Typ value From: TBD To: -120 dB ................................................... 6
Changed the Common-mode rejection ratio Min value From: 94 dB To: 91 dB .................................................................. 7
Added GAIN SETTING RESISTORS (OPA835IRUN ONLY) .............................................................................................. 8
Changed the Quiescent operating current (TA = 25°C) Min value From: 215 µA To: 200 µA .............................................. 8
Changed the Power supply rejection (±PSRR) Min value From: 93 dB To: 90 dB .............................................................. 8
Changed the Powerdown quiescent current CONDITIONS From: PD = 0.7V To: PD = 0.5V ............................................. 8
Changed the Powerdown quiescent current CONDITIONS From: PD = 0.7V To: PD = 0.5V ............................................. 8
Changed the OPA835 WQFN-10 (RUN) pinout image ........................................................................................................ 9
Added Figure Crosstalk vs Frequency ................................................................................................................................ 14
Added Figure Crosstalk vs Frequency ................................................................................................................................ 20
Added section Single Ended to Differential Amplifier ......................................................................................................... 24
Changes from Revision C (September 2011) to Revision D
Page
•
•
•
•
•
Removed Product Preview from OPA835IRUNT and OPA835IRUNR ................................................................................ 2
Changed Resistor Temperature Coefficient From: TBD To: <10 ......................................................................................... 5
Changed Quiescent operating current To: Quiescent operating current per amplifer .......................................................... 5
Changed Resistor Temperature Coefficient From: TBD To: <10 ......................................................................................... 8
Changed Quiescent operating current To: Quiescent operating current per amplifer .......................................................... 8
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
OPA2835ID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
2835
2835
2835
2835
2835
2835
2835
2835
QUM
QUM
835
OPA2835IDGS
OPA2835IDGSR
OPA2835IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGS
DGS
D
10
10
8
80
Green (RoHS
& no Sb/Br)
2500
2500
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OPA2835IRMCR
OPA2835IRMCT
OPA2835IRUNR
OPA2835IRUNT
OPA835IDBVR
OPA835IDBVT
OPA835IRUNR
OPA835IRUNT
UQFN
UQFN
QFN
RMC
RMC
RUN
RUN
DBV
DBV
RUN
RUN
10
10
10
10
6
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
SOT-23
SOT-23
QFN
3000
250
Green (RoHS
& no Sb/Br)
6
Green (RoHS
& no Sb/Br)
10
10
3000
250
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
835
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2835IDGSR
OPA2835IDR
VSSOP
SOIC
DGS
D
10
8
2500
2500
3000
250
330.0
330.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
12.4
12.4
9.5
9.5
8.4
8.4
9.0
9.0
8.4
8.4
5.3
6.4
2.3
2.3
2.3
2.3
3.23
3.23
2.3
2.3
3.4
5.2
2.3
2.3
2.3
2.3
3.17
3.17
2.3
2.3
1.4
2.1
8.0
8.0
2.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
OPA2835IRMCR
OPA2835IRMCT
OPA2835IRUNR
OPA2835IRUNT
OPA835IDBVR
OPA835IDBVT
OPA835IRUNR
OPA835IRUNT
UQFN
UQFN
QFN
RMC
RMC
RUN
RUN
DBV
DBV
RUN
RUN
10
10
10
10
6
1.1
1.1
3000
250
1.15
1.15
1.37
1.37
1.15
1.15
QFN
SOT-23
SOT-23
QFN
3000
250
6
10
10
3000
250
QFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2835IDGSR
OPA2835IDR
VSSOP
SOIC
DGS
D
10
8
2500
2500
3000
250
366.0
340.5
205.0
205.0
210.0
210.0
180.0
180.0
210.0
210.0
364.0
338.1
200.0
200.0
185.0
185.0
180.0
180.0
185.0
185.0
50.0
20.6
30.0
30.0
35.0
35.0
18.0
18.0
35.0
35.0
OPA2835IRMCR
OPA2835IRMCT
OPA2835IRUNR
OPA2835IRUNT
OPA835IDBVR
OPA835IDBVT
OPA835IRUNR
OPA835IRUNT
UQFN
UQFN
QFN
RMC
RMC
RUN
RUN
DBV
DBV
RUN
RUN
10
10
10
10
6
3000
250
QFN
SOT-23
SOT-23
QFN
3000
250
6
10
10
3000
250
QFN
Pack Materials-Page 2
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