SCAN182245EFMX [NSC]
Non-Inverting Transceiver with 25OHM Series Resistor Outputs; 非反相收发器25OHM系列电阻输出型号: | SCAN182245EFMX |
厂家: | National Semiconductor |
描述: | Non-Inverting Transceiver with 25OHM Series Resistor Outputs |
文件: | 总18页 (文件大小:224K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
February 1996
SCAN182245A
Non-Inverting Transceiver with
25X Series Resistor Outputs
General Description
Features
Y
High performance BiCMOS technology
The SCAN182245A is a high performance BiCMOS bidirec-
tional line driver featuring separate data inputs organized
into dual 9-bit bytes with byte-oriented output enable and
direction control signals. This device is compliant with
IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI), Test Data Out (TDO), Test Mode Se-
lect (TMS), and Test Clock (TCK).
Y
25X series resistors in outputs eliminate the need for
external terminating resistors
Y
Y
Y
Y
Y
Y
Dual output enable control signals
TRI-STATE outputs for bus-oriented applications
É
25 mil pitch SSOP (Shrink Small Outline Package)
IEEE 1149.1 (JTAG) Compliant
Includes CLAMP, IDCODE and HIGHZ instructions
Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
Y
Y
Power Up TRI-STATE for hot insert
Member of National’s SCAN Products
Connection Diagram
Pin Names
Description
A1
B1
A2
B2
Side A1 Inputs or TRI-STATE Outputs
Side B1 Inputs or TRI-STATE Outputs
Side A2 Inputs or TRI-STATE Outputs
Side B2 Inputs or TRI-STATE Outputs
Output Enable Pins (Active Low)
(0–8)
(0–8)
(0–8)
(0–8)
G1, G2
DIR1, DIR2 Direction of Data Flow Pins
Order Number
Description
SCAN182245ASSC
SCAN182245ASSCX
SCAN182245AFMQB
SSOP in Tubes
SSOP Tape and Reel
Flatpak Military
TL/F/11657–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/11657
RRD-B30M36/Printed in U. S. A.
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Truth Tables
Functional Description
The SCAN182245A consists of two sets of nine non-invert-
ing bidirectional buffers with TRI-STATE outputs and is in-
tended for bus-oriented applications. Direction pins (DIR1
and DIR2) LOW enables data from B ports to A ports, when
HIGH enables data from A ports to B ports. The Output
Enable pins (G1 and G2) when HIGH disables both A and B
ports by placing them in a high impedance condition.
Inputs
A1
(0–8)
B1
(0–8)
²
G1
DIR1
L
L
L
L
H
L
L
H
L
w
w
H
L
H
H
X
H
L
x
H
L
x
Z
Z
Inputs
A2
(0–8)
B2
(0–8)
²
G2
DIR2
L
L
L
L
H
L
L
H
L
w
w
H
L
H
H
X
H
L
x
H
L
x
Z
Z
e
e
e
e
e
H
L
X
Z
²
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Inactive-to-Active transition must occur to enable outputs upon
power-up.
Block Diagrams
A1, B1, G1 and DIR1
TL/F/11657–2
Note: BSR stands for Boundary Scan Register.
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2
Block Diagrams (Continued)
Tap Controller
TL/F/11657–18
A2, B2, G2 and DIR2
TL/F/11657–3
Note: BSR stands for Boundary Scan Register.
3
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Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
qshuieftnicnethoef:8C-bAitPinTsUtrRuEct-iIoRn xfor SAMPLE/PRELOAD. The se-
EXIT1-IR
x
UPDATE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
The BYPASS register is a single bit shift register stage iden-
tical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
TL/F/11657–10
MSB
Instruction Code
x
LSB
Instruction
00000000
10000001
10000010
00000011
01000001
01000010
00100010
10101010
11111111
All Others
EXTEST
SAMPLE/PRELOAD
CLAMP
TL/F/11657–17
SCAN182245A Product IDCODE
(32-Bit Code per IEEE 1149.1)
HIGH-Z
SAMPLE-IN
SAMPLE-OUT
EXTEST-OUT
IDCODE
Part
Manufacturer Required by
Version Entity
Number
ID
1149.1
0000 111111 0000000000 00000001111
MSB
1
LSB
BYPASS
BYPASS
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4
Description of BOUNDARY-SCAN Circuitry (Continued)
Scan Cell TYPE1
TL/F/11657–11
Scan Cell TYPE2
TL/F/11657–12
5
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (80 Bits in Length)
TL/F/11657–32
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6
Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits in Length)
When Sample In is Active
TL/F/11657–33
7
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Description of BOUNDARY-SCAN Circuitry (Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits in Length)
When Sample Out and EXTEST-Out are Active
TL/F/11657–34
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8
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
Scan Cell Type
TYPE1
79
78
77
76
75
74
73
72
DIR1
G1
3
Input
Input
54
TYPE1
TYPE2
TYPE2
TYPE1
TYPE1
TYPE2
TYPE2
AOE
BOE
Internal
Internal
Input
1
1
Control
Signals
DIR2
G2
26
31
Input
AOE
BOE
Internal
Internal
2
2
71
70
69
68
67
66
65
64
63
A1
A1
A1
A1
A1
A1
A1
A1
A1
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
0
1
2
3
4
5
6
7
8
A1–in
62
61
60
59
58
57
56
55
54
A2
A2
A2
A2
A2
A2
A2
A2
A2
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
0
1
2
3
4
5
6
7
8
A2–in
53
52
51
50
49
48
47
46
45
B1
B1
B1
B1
B1
B1
B1
B1
B1
2
4
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
0
1
2
3
4
5
6
7
8
5
7
B1–out
8
10
11
13
14
44
43
42
41
40
39
38
37
36
B2
B2
B2
B2
B2
B2
B2
B2
B2
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
0
1
2
3
4
5
6
7
8
B2–out
35
34
33
32
31
30
29
28
27
B1
B1
B1
B1
B1
B1
B1
B1
B1
2
4
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
0
1
2
3
4
5
6
7
8
5
7
B1–in
8
10
11
13
14
9
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index (Continued)
Bit No.
Pin Name
Pin No.
Pin Type
Scan Cell Type
TYPE1
26
25
24
23
22
21
20
19
18
B2
B2
B2
B2
B2
B2
B2
B2
B2
15
16
18
19
21
22
24
25
27
Input
Input
Input
Input
Input
Input
Input
Input
Input
0
1
2
3
4
5
6
7
8
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B2–in
A1–out
A2–out
17
16
15
14
13
12
11
10
9
A1
A1
A1
A1
A1
A1
A1
A1
A1
55
53
52
50
49
47
46
44
43
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
0
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
0
A2
A2
A2
A2
A2
A2
A2
A2
A2
42
41
39
38
36
35
33
32
30
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
0
1
2
3
4
5
6
7
8
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10
SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane
1
applications. It provides 2nd Level Isolation which indicates
flip-flop. To bring the device out of high impedance, the G
input must receive an inactive-to-active transition, a high-to-
n
that while external circuitry to control the output enable pin
is unnecessary, there may be a need to implement differen-
low transition on G in this case to change the state of the
n
flip-flop. With a low on the Q output of the flip-flop, the NOR
tial length backplane connector pins for V
and GND. As
gate is free to allow propagation of a G signal.
n
CC
well, pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion.
During power-down, the Power-On-Reset circuitry will be-
come active and reset the flip-flop at approximately 1.8V
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure A. It essentially con-
V
. Again, the Q output of the flip-flop returns to a high and
CC
disables the NOR gate from inputs from the G pin. The
n
device will then remain in high impedance for the remaining
trols the G pin until V
n
reaches a known level.
CC
ramp down from 1.8V to 0.0V V
.
CC
During power-up, when V ramps through the 0.0V to 0.7V
CC
range, all internal device circuitry is inactive, leaving output
and I/O pins of the device in high impedance. From approxi-
Some suggestions to help the designer with live insertion
issues:
mately 0.8V to 1.8V V , the Power-On-Reset circuitry,
CC
The G pin can float during power-up until the Power-On-
n
Reset circuitry becomes inactive.
#
(POR), in Figure A becomes active and maintains device
high impedance mode. The POR does this by providing a
low from its output that resets the flip-flop The output, Q, of
the flip-flop then goes high and disables the NOR gate from
The G pin can float on power-down only after the Pow-
n
er-On-Reset has become active.
#
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of Figure B.
an incidental low input on the G pin. After 1.8V V , the
n CC
POR circuitry becomes inactive and ceases to control the
TL/F/11657–19
FIGURE A
TL/F/11657–20
FIGURE B
Section 7, ‘‘Design Consideration for Fault Tolerant Backplanes’’, Application Note AN-881.
1
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
11
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Latchup Source Current
Commercial
Military
b
b
500 mA
300 mA
b
b
a
65 C to 150 C
Storage Temperature
Over Voltage Latchup (I/O)
ESD (HBM) Min.
10V
§
§
a
55 C to 125 C
Ambient Temperature under Bias
2000V
§
§
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Junction Temperature under Bias
Ceramic
Plastic
b
b
a
55 C to 175 C
§
§
§
§
a
55 C to 150 C
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
Recommended Operating
Conditions
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
b
a
30 mA to 5.0 mA
Free Air Ambient Temperature
Military
Commercial
Voltage Applied to Any Output
in the Disabled or
Power-Off State
b
b
a
55 C to 125 C
§
40 C to 85 C
§
a
§
§
b
a
0.5V to 5.5V
Supply Voltage
Military
Commercial
b
in the HIGH State
0.5V to V
CC
a
a
a
4.5V to 5.5V
Current Applied to Output
in LOW State (Max)
a
4.5V to 5.5V
Twice the Rated I (mA)
OL
Minimum Input Edge Rate
Data Input
Enable Input
(DV/Dt)
50 mV/ns
20 mV/ns
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
V
Min
Typ
Max
Units
Conditions
CC
V
IH
2.0
V
V
V
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
V
V
V
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
Output HIGH Voltage
Min
Min
Min
Min
1.2
I
I
I
I
CD
OH
IN
e b
e b
e b
2.5
2.0
2.0
3 mA
OH
OH
OH
Mil
24 mA
32 mA
Comm
V
Output LOW Voltage
Input HIGH Current
OL
e
e
e
e
e
e
Mil
Min
Min
0.8
V
I
I
12 mA
OL
Comm
0.8
5
V
15 mA
OL
I
Max
Max
Max
mA
mA
mA
V
V
V
V
2.7V (Note 1)
IH
IN
IN
IN
IN
All Others
TMS, TDI
5
V
CC
V
CC
5
I
I
I
Input HIGH Current
Breakdown Test
7.0V
BVI
BVIT
IL
Max
Max
7
mA
mA
e
Input HIGH Current
V
5.5V
IN
100
Breakdown Test (I/O)
b
b
e
e
e
Input LOW Current
Max
Max
Max
5
5
mA
mA
mA
V
V
V
0.5V (Note 1)
0.0V
IN
IN
IN
All Others
TMS, TDI
b
385
0.0V
e
ID
V
ID
Input Leakage Test
I
1.9 mA
0.0
4.75
V
All Other Pins Grounded
a
e
e
e
e
I
I
I
I
I
Output Leakage Current
Output Leakage Current
Output Leakage Current
Output Leakage Current
Max
Max
Max
Max
50
mA
mA
mA
mA
V
OUT
V
OUT
V
OUT
V
OUT
2.7V
0.5V
2.7V
0.5V
IH
IL
OZH
a
b
I
50
OZL
50
OZH
OZL
b
50
Note 1: Guaranteed not tested.
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12
DC Electrical Characteristics (Continued)
Symbol
Parameter
V
Min
Typ
Max
Units
mA
Conditions
0.0V
CC
b
b
e
e
e
I
I
I
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Max
Max
100
275
V
V
V
OS
CEX
ZZ
OUT
OUT
OUT
50
mA
V
CC
5.5V
0.0
100
mA
All Others GND
e
e
e
e
e
e
I
I
I
I
Power Supply Current
Power Supply Current
Power Supply Current
Max
Max
Max
Max
Max
Max
250
1.0
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
; TDI, TMS
; TDI, TMS
V
CCH
CCL
CCZ
CCT
OUT
OUT
OUT
OUT
CC
CC
GND
CC
e
65
LOW; TDI, TMS
LOW; TDI, TMS
V
CC
e
65.8
250
1.0
GND
e
e
TDI, TMS
TDI, TMS
V
CC
GND
Additional I /Input
CC
e
e
b
CC
All Other Inputs
Max
Max
2.9
3
mA
mA
V
V
V
2.1V
2.1V
IN
b
TDI, TMS inputs
No Load
V
CC
IN
I
Dynamic I
CC
mA/
MHz
Outputs Open
CCD
Max
0.2
One Bit Toggling, 50% Duty Cycle
AC Electrical Characteristics Normal Operation
Military
Commercial
e b
a
e b
A
a
V
*
T
55 C to 125 C
§
T
40 C to 85 C
§
CC
§
§
A
Symbol
Parameter
Units
e
e
(V)
C
50 pF
C
L
50 pF
L
Min
Typ
Max
Min
Typ
Max
t
t
Propagation Delay
A to B, B to A
1.0
1.5
3.1
4.4
5.2
6.5
PLH
5.0
5.0
5.0
ns
ns
ns
PHL
t
t
Disable Time
1.5
1.5
4.8
5.2
8.6
8.9
PLZ
PHZ
t
t
Enable Time
1.5
1.5
5.5
4.6
9.1
8.2
PZL
PZH
g
*Voltage Range 5.0V 0.5V
13
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AC Electrical Characteristics Scan Test Operation
Military
Commercial
e b
a
e b
A
a
V
*
T
55 C to 125 C
§
T
40 C to 85 C
§
CC
§
§
A
Symbol
Parameter
Units
e
e
(V)
C
50 pF
C
L
50 pF
L
Min
Typ
Max
Min
Typ
Max
t
t
Propagation Delay
TCK to TDO
2.9
4.2
6.1
7.7
10.2
12.1
PLH
5.0
5.0
5.0
ns
ns
ns
ns
PHL
t
t
Disable Time
TCK to TDO
2.1
3.3
5.9
7.4
10.7
12.5
PLZ
PHZ
t
t
Enable Time
TCK to TDO
4.6
2.8
8.7
6.8
13.7
11.5
PZL
PZH
t
t
Propagation Delay
TCK to Data Out
2.8
4.5
6.3
8.2
10.7
13.0
PLH
5.0
5.0
PHL
during Update-DR State
t
t
Propagation Delay
TCK to Data Out
3.3
5.0
7.2
9.3
12.2
14.8
PLH
ns
ns
PHL
during Update-IR State
t
t
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
3.7
5.7
8.4
14.0
17.2
PLH
10.8
PHL
5.0
t
t
Disable Time
2.8
3.5
7.6
8.4
13.9
14.5
PLZ
ns
ns
ns
TCK to Data Out
during Update-DR State
5.0
5.0
PHZ
t
t
Disable Time
3.6
3.8
8.7
9.2
15.1
15.9
PLZ
TCK to Data Out
during Update-IR State
PHZ
t
t
Disable Time
4.0
4.2
9.8
9.9
17.1
16.6
PLZ
TCK to Data Out
during Test Logic
Reset State
PHZ
5.0
t
t
Enable Time
4.4
3.0
9.3
7.5
15.5
13.3
PZL
ns
ns
ns
TCK to Data Out
during Update-DR State
5.0
5.0
PZH
t
t
Enable Time
5.2
3.9
10.7
9.0
17.4
15.4
PZL
TCK to Data Out
during Update-IR State
PZH
t
t
Enable Time
5.7
3.0
12.0
10.2
19.8
17.6
PZL
TCK to Data Out
during Test Logic
Reset State
PZH
5.0
g
*Voltage Range 5.0V 0.5V
All Propagation Delays involving TCK are measured from the falling edge of TCK.
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14
AC Operating Requirements Scan Test Operation
Military
Commercial
e b
a
e b
A
a
V
*
T
A
55 C to 125 C
§
T
40 C to 85 C
§
CC
§
§
Symbol
Parameter
Units
e
e
(V)
C
50 pF
C
L
50 pF
L
Guaranteed Minimum
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
Setup Time
S
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Data to TCK (Note 1)
Hold Time
H
2.5
4.1
1.7
4.2
2.3
3.8
2.3
8.7
1.5
6.7
5.0
Data to TCK (Note 1)
Setup Time, H or L
S
G1, G2 to TCK (Note 2)
Hold Time, H or L
H
TCK to G1, G2 (Note 2)
Setup Time, H or L
S
DIR1, DIR2 to TCK (Note 4)
Hold Time, H or L
H
TCK to DIR1, DIR2 (Note 4)
Setup Time
S
Internal OE to TCK (Note 3)
Hold Time, H or L
H
TCK to Internal OE (Note 3)
Setup Time, H or L
TMS to TCK
S
Hold Time, H or L
TCK to TMS
H
Setup Time, H or L
TDI to TCK
S
Hold Time, H or L
TCK to TDI
H
Pulse Width TCK
H
L
10.2
8.5
W
max
PU
DN
Maximum TCK
50
Clock Frequency
Wait Time,
5.0
0.0
100
100
ns
Power Up to TCK
Power Down Delay
ms
g
*Voltage Range 5.0V 0.5V
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71).
Note 2: Timing pertains to BSR 74 and 78 only.
Note 3: Timing pertains to BSR 72, 73, 76 and 77 only.
Note 4: Timing pertains to BSR 75 and 79 only.
Capacitance
Symbol
e
25 C
Parameter
Typ
5.9
Units
pF
Conditions, T
§
0.0V (G , DIR )
n n
A
e
e
C
C
Input Capacitance
Output Capacitance
V
V
IN
CC
(Note 1)
13.7
pF
5.0V (A , B )
n n
I/O
CC
e
1 MHz, per MIL-STD-883B, Method 3012.
Note 1: C
is measured at frequency f
I/O
15
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Ordering Information
SCAN 18 2245
A
SS
C
X
Serially Controlled Access Network
18-Bit Logic
Special Variations
e
e
X
QB
Tape and Reel
Military grade device with
environmental and burn-in
processing.
Function Type
Technology Designator
Temperature Range
e
e
e
e
e
e
e
T
C
B
E
A
F
TTL Input TTL Output CMOS Device
b
Commercial ( 40 C to
C
§
CMOS Input/Output CMOS Device
Bipolar TTL Device
ECL Device
BiCMOS Device
TTL Input/CMOS Output CMOS Device
a
Military ( 55 C to 125 C)
85 C)
§
e
b a
M
§
§
Package Code
e
e
SS
F
25 mil Pitch (JEDEC) SSOP
25 mil Pitch Ceramic Flatpak
http://www.national.com
16
Physical Dimensions inches (millimeters)
56-Lead SSOP (0.300 Wide) (SS)
×
Order Number SCAN182245ASSC or SCAN182245ASSCX
NS Package Number MS56A
17
http://www.national.com
Physical Dimensions inches (millimeters) (Continued)
56-Lead Ceramic Flatpak (F)
Order Number SCAN182245AFMQB
NS Package Number WA56A
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be reasonably expected to cause the failure of the life
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