SCANSTA101SMX [NSC]
IC SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49, BGA-49, Microprocessor IC:Other;
| 型号： | SCANSTA101SMX |
| 厂家： | 
National Semiconductor |
| 描述： | IC SPECIALTY MICROPROCESSOR CIRCUIT, PBGA49, BGA-49, Microprocessor IC:Other 外围集成电路 |
| 文件： | 总31页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2002
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
Features
n Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
n Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0
n Available as a Silicon Device and Intellectual Property
(IP) model for embedding into VLSI devices
n Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n 16-bit Data Interface (IP scalable to 32-bit)
n 2Kx32 bit dual-port memory addressing for access by
the PPI or the 1149.1 master
n Load-on-the-fly (LotF) and Preload operating modes
supported
n On-Board Sequencer allows multi-vector operations
such as those required to load data into an FPGA
n On-Board Compares support TDI validation against
preloaded expected data
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allow it to adapt to any changes that may occur in 1532
and support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and
reduces the software overhead that is associated with ap-
plying serial patterns with a parallel processor. The SCAN-
STA101 features a generic Parallel Processor Interface
(PPI) which operates by serializing data from the parallel bus
for shifting through the chain of 1149.1 compliant compo-
nents (i.e., scan chain). Writes can be controlled either by
wait states or the DTACK line. Handshaking is accomplished
with either polling or interrupts.
n 32-bit Linear Feedback Shift Register (LFSR) at the Test
Data In (TDI) port
n State, Shift, and BIST macros allow predetermined TMS
sequences to be utilized
n Operates at 3.3v supply voltages w/ 5V tolerant I/O
n Outputs support Power-Down TRI-STATE mode.
SCANSTA101 Architecture
10121502
FIGURE 1.
© 2002 National Semiconductor Corporation
DS101215
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memory. These interfaces consist of the Parallel Processor
Interface (PPI), Serial Scan Interface (SSI), and Test and
Debug Interface. The System Input block is included only to
designate inputs that have global use across the device. The
Test and Debug interface supports BIST, boundary scan,
and internal scan for this device.
SCANSTA101 Architecture (Continued)
Figure 1 shows a high level view of the SCANSTA101 Scan
Master and its interface groups. Table 1 provides a brief
description of each of these interface groups. Table 2 pro-
vides a brief description of the external interfaces. The de-
vice is composed of three interfaces around a dual-port
TABLE 1. Interface Descriptions
Description
Interface
Parallel Processor Interface
Used for configuration, ScanMaster scan chain loads and reads, programmable device
file loads and reads, and status monitoring.
Serial Scan Interface
Performs parallel to serial conversion, sequences and formats the outgoing serial
stream to conform to 1149.1 protocol.
Test and Debug Interface
Interfaces used for manufacturing tests, this includes a JTAG interface and a scan
interface. The three scan interface pins are shared with three of the data pins.
Interface inputs for system control, i.e. clock, reset and output tristate control.
System Inputs
Connection Diagrams
10121540
BGA Package Pinout
(Top View)
10121503
SSOP Package Pinout
(Top View)
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2
TABLE 2. Pin Descriptions
Pin
Description
Name
No.
Pins
4
I/O
VCC
N/A
N/A
I/O
Power
GND
4
Ground
D(15:0)
16
Bidirectional Data Bus. Signals are bonded out for the packaged device.
D15 and D14 are shared pins with SCAN_IN, and SCAN_OUT
respectively.
D(31:16)
(Note 1)
A(4:0)
16
I/O
Bidirectional Data Bus. These signals are not available in the packaged
device.
5
1
I
I
Address Bus
SCK
The system clock that drives all internal timing. TCK_SM is a gated,
divided and buffered version of SCK.
INT
1
1
1
O
I
Interrupt Output
OE
Output enable that tristates all 1149.1 "_SM" outputs when high.
DTACK is used to synchronize asynchronous transfers between the host
and the STA101. When CE is high, DTACK is tristated. When CE is low,
DTACK is enabled. DTACK goes low when data has been registered and
then goes tri-state when the cycle has completed.
R/W defines a PPI cycle. Read when high, write when low.
Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit
mode, are tristated when STB is high. Data valid setup is with respect to
the falling edge of STB and data valid hold is with respect to rising edge of
STB.
DTACK
O
R/W
STB
1
1
I
I
CE
1
I
Chip Enable, when low, enables the PPI for data transfers. CE can remain
low during back-to-back accesses. D(15:0), or D(31:0) in 32-bit mode, and
DTACK are tristated when CE is high.
RST
TDO
1
1
I
Asynchronous reset, when low, initializes the STA101.
Test Data Out is the serial scan output from the STA101. TDO is enabled
when OE is low.
O
TDI
1
1
I
I
Test Data In is the serial scan input to the STA101.
Test Mode Select. The Test Mode Select pin is a serial input used to
accept control logic to the Test & debug interface.
Test Clock Input for 1149.1
TMS
TCK
1
1
1
1
1
1
1
1
I
TRST
I
Test Reset
TDI_SM
TDO_SM
TMS_SM
TCK_SM
TRST0_SM
TRST1_SM
(Note 1)
TRIST_SM
I
Scan Master Test Data Input in the Serial Scan Interface
Scan Master Test Data Output in the Serial Scan Interface
Scan Master Test Mode Select in the Serial Scan Interface
Scan Master Test Clock in the Serial Scan Interface
Scan Master Test Reset output in the Serial Scan Interface
Redundent ScanMaster TRST. This signal is not available for the
packaged device.
O
O
O
O
O
1
O
The TRI-STATE notification pin exerts a high signal when TDO_SM is
TRI-STATED
Note 1: D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged part. These are used in the
32-bit Macro Mode only.
3
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@
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Max Pkg Power Capacity 25˚C
49L BGA
1.47W
Thermal Resistance (θJA
49L BGA
)
85˚C/W
11.8mW/˚C above
+25˚C
Supply Voltage (VCC
)
−0.5V to +4.0V
Package Derating
DC Input Diode Current (IIK
VI = −0.5V
)
−20 mA
ESD Last Passing Voltage (Min)
2000V
DC Input Voltage (VI)
−0.5V to +4.0V
DC Output Diode Current (IOK
VO = −0.5V
)
Recommended Operating
Conditions
−20 mA
−0.5V to +4.0V
50 mA
DC Output Voltage (VO)
Supply Voltage (VCC
)
3.0V to 3.6V
0V to VCC
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Input Voltage (VI)
50 mA
Output Voltage (VO)
0V to VCC
Operating Temperature (TA)
−40˚C to +85˚C
DC Latchup Source or Sink Current
Junction Temperature
Plastic
300 mA
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of SCAN STA products outside of recommended operation
conditions.
+150˚C
Storage Temperature
Lead Temperature (Solder, 4sec)
49L BGA
−65˚C to +150˚C
220˚C
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified.
Symbol
VIH
Parameter
Conditions
Min
Max
Units
Minimum High Input Voltage
Maximum Low Input Voltage
Minimum High Output Voltage
Minimum High Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
VOUT = 0.1V or VCC − 0.1V
VOUT = 0.1V or VCC − 0.1V
IOUT = −100 µA, VIN = VIL or VIH
IOH = −24 mA, VIN = VIL or VIH
2.1
V
V
V
V
VIL
0.8
VOH
VCC-0.2V
2.2
Minimum High Output Voltage,
All other outputs including 1149.1
Maximum Low Output Voltage
Maximum Low Output Voltage,
TDO_SM, TMS_SM, TCK_SM, TRST0_SM
outputs only
IOH = −12 mA, VIN = VIL or VIH
2.4
V
VOL
IOUT = +100 µA, VIN = VIL or VIH
IOL = 24 mA, VIN = VIL or VIH
0.2
0.5
V
V
Maximum Low Output Voltage,
all other outputs including 1149.1
Maximum Input Leakage Current, All pins
except TDI, TMS, TRST, TDI_SM
IOL = 12mA, VIN = VIL or VIH
0.4
5.0
V
IIN
VIN = VCC for TDI, OE, VIN = VCC
,
µA
µA
µA
µA
µA
GND for All Others
IILR
IIH
IOZ
IOFF
Maximum Input Leakage Current, TDI, TMS, VIN = GND
TRST, TDI_SM
-45
-200
5.0
Maximum Input Leakage Current, TDI, TMS, VIN = VCC
TRST, TDI_SM
Maximum TRI-STATE Leakage Current
VIN = VCC, GND, VIN (OE, R/W,
5.0
CE, STB) = VIL, VIH
VCC = 0.0V
Power Off Leakage Current
All pins except TDI, TMS, TRST, and
TDI_SM
5.0
ICC
Maximum Quiescent Supply Current
Maximum Supply Current
Maximum ICC/Input
250
1.2
µA
mA
µA
ICCmax
ICCT
All inputs low
VIN = VCC − 0.6V
250
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4
AC Electrical Characteristics/Operating Requirements Over recommended operating
supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise specified.
Symbol
Parameter
Conditions
# of SCK
Min
Max
Units
(Notes 3, 4)
PARALLEL PROCESSOR INTERFACE (PPI)
tS1
tH1
tD1
tD1
tD1
Set Up Time
Figures 11, 12
Figures 11, 12
Figure 11
0
0
ns
ns
ns
ns
ns
CE, R/W, Addr, Data to STB
Hold Time
CE, R/W, Addr, Data to STB
Propagation Delay
2 or 3
4 or 5
3 or 4
11.5
11.5
11.5
STB low to DTACK low, Register Write
Propagation Delay
Figure 12
STB low to DTACK low, Register Read
Propagation Delay
Figure 11
STB low to DTACK low, Memory Write: 16-bit first
access
tD1
tD1
tD1
Propagation Delay
Figure 11
Figure 12
Figure 12
7 or 8
9 or 10
3 or 4
11.5
11.5
11.5
ns
ns
ns
STB low to DTACK low, Memory Write: 16-bit second
access
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit first
access
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit
second access
tD2
tD2
tD2
Propagation Delay
Figure 11
Figure 12
Figure 11
1 or 2
1 or 2
1 or 2
10.0
10.0
10.0
ns
ns
ns
STB high to DTACK TRISTATE, Register Write
Propagation Delay
STB high to DTACK TRISTATE, Register Read
Propagation Delay
STB high to DTACK TRISTATE, Memory Write:
16-bit first access
tD2
tD2
tD2
Propagation Delay
Figure 11
Figure 12
Figure 12
1 or 2
1 or 2
1 or 2
10.0
10.0
10.0
ns
ns
ns
STB high to DTACK TRISTATE, Memory Write:
16-bit second access
Propagation Delay
STB high to DTACK TRISTATE, Memory Read:
16-bit first access
Propagation Delay
STB high to DTACK TRISTATE, Memory Read:
16-bit second access
tD3
Propagation Delay
Figure 12
Figure 11
1
ns
ns
Output data valid to DTACK low, all read cycles
Propagation Delay
tpHL1
5 or 6
10.5
66
STB low to INT low, register write (clears Interrupt)
Clock Pulse Width, SCK, H or L
Clock Frequency, SCK
tW
3.0
ns
MHz
ns
fMAX
tRELEASE
Release Time, RST to STB
2
Note 3: Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4: An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + t
.
D
For example, for t (STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, t , is 11.5ns. For a SCK with a 100ns period, the absolute
D1
D
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
5
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AC Electrical Characteristics/Operating Requirements Over recommended operating
supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise
specified. (Continued)
Symbol
Parameter
Conditions
Figure 13
Min
Max
11.5
12.0
12.5
15.0
12.5
Units
ns
SERIAL SCAN INTERFACE (SSI)
tD5
Propagation Delay
SCK to TCK_SM
Propagation Delay
SCK to TDO_SM
Propagation Delay
SCK to TMS_SM
tD6
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
ns
tD7
ns
tD8
Propagation Delay - tpLH
SCK to TRIST_SM
Propagation Delay - tpHL
SCK to TRIST_SM
Propagation Delay
SCK to TDO_SM disable
Propagation Delay
SCK to TDO_SM enable
Enable Delay
ns
tD9
ns
tD10
tD11
tEN1
ns
12.5
14.0
ns
12.0
11.0
ns
OE low to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
tDIS1
Disable Delay
Figure 13
ns
OE high to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
tEN2
tDIS2
tDIS3
tS2
Enable Delay
10.0
11.5
12.5
ns
ns
ns
ns
ns
OE low to TRIST_SM
Disable Delay
OE high to TRIST_SM
Disable Delay
RST low to TRST0_SM
Setup Time
Figure 13
Figure 13
3.5
2.0
SCK to TDI_SM
tH2
Hold Time
SCK to TDI_SM
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6
AC Electrical Characteristics/Operating Requirements Over recommended operating
supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise
specified. (Continued)
Symbol
Parameter
Conditions
Min
2.0
1.0
1.0
2.0
10.0
2.5
2.0
Max
Units
ns
TEST & DEBUG INTERFACE TIMING REQUIREMENTS (SCAN)
tS
Setup Time
TMS to TCK
tH
Hold Time
ns
TMS to TCK
tS
Setup Time
ns
TDI to TCK
tH
Hold Time
ns
TDI to TCK
tW
Pulse Width
ns
TCK (H or L)
Reset Pulse Width
TRST (L)
tWL
tREC
fMAX
ns
Recovery Time
TCK from TRST
Maximum Clock Frequency, TCK
ns
25
MHz
7
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Applications/Programmers Reference
TABLE 3. Register Summary
Address
00h
01h
02h
03h
04h
05h
07h
08h
09h
0Ah
0Bh
0Ch
11h
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Mnemonic
START
Register
Active Register Bits
Reset Value
0000h
0800h
0000h
0000h
0043h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Start Register
5
STATUS
INTCTRL
INTSTAT
SETUPR
CLKDIV
Status Register
10
8
Interrupt Control Register
Interrupt Status Register
Setup Register
8
8
Clock Divider Register
TDI_SM LFSR Exponent Register
TDI_SM LSB Seed Register
TDI_SM MSB Seed Register
TDI_SM LSB Result Register
TDI_SM MSB Result Register
Index Register
6
EXPR
3
LSSEDR
MSSEDR
LSRESR
MSRESR
INDEXR
VINDEXR
HTINDEXR
MINDEXR
SINDEXR
BSINDEXR
16
16
16
16
16
16
16
16
16
16
Vector Index Register
Header/Trailer Index Register
Macro Index Register
13h
15h
17h
19h
Sequencer Index Register
Bridge Support Register
TABLE 4. Memory/Register Address Map
A4
A3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
A2
A1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
Function
Base Address Long Word Index Structure/Size
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
Start
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register
16-bit Register (Note 5)
16-bit Register (Note 5)
16-bit Register (Note 5)
16-bit Register (Note 5)
16-bit Register (Note 6)
(Note 7)
Status
N/A
Interrput Control
Interrupt Status
Setup
N/A
N/A
N/A
Clock Divider
N/A
TDI_SM LFSR Exponent
TDI_SM LFSR LSB Seed
TDI_SM LFSR MSB Seed
N/A
N/A
N/A
TDI_SM LFSR LSB Result N/A
TDI_SM LFSR MSB Result N/A
N/A
N/A
Index Register
TDO_SM
N/A
N/A
0
0 - 0x1BF
0 - 0x1BF
0 - 0x1BF
0 - 0x1BF
N/A
TDI_SM
0 x 1C0
0 x 380
0 x 540
N/A
(Note 7)
Expected
(Note 7)
Mask
(Note 7)
Vector Index
Vector 1
16-bit Register
(Note 8) Table 5
0 x 700
0 x 700
0 x 700
0 x 700
N/A
0x0 - 0x1
0x2 - 0x3
0x4 - 0x5
0x6 - 0x7
N/A
Vector 2
Vector 3
Vector 4
1
1
0
0
0
1
1
0
1
0
Header/Trailer Index
Data Header
Data Trailer
Instruction Header
Instruction Trailer
Macro Index
16-bit Register
0 x 708
0 x 728
0 x 748
0 x 768
N/A
0x0 - 0x1F
0x20 - 0x3F
0x40 - 0x5F
0x60 - 0x7F
N/A
Table 6
1
0
1
0
1
16-bit Register
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8
TABLE 4. Memory/Register Address Map (Continued)
A4
A3
A2
A1
A0
Function
Base Address Long Word Index Structure/Size
1
0
1
1
0
Macro 1
0 x 788
0 x 789
0 x 78A . . .
0 x 797
N/A
0x0
Tables 7, 8, 9
Macro 2
0x1
Macro 3 . . .
Macro 16
0x2 . . .
0xF
1
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
Sequencer Index
Sequencer
N/A
16-bit Register
Table 10
0 x 798
0x0 - 0x1F
N/A
Scan Bridge Support Index N/A
Scan Bridge Support 0 x 7B8
16-bit Register
Table 11
0x0 - 0x3F
Note 5: The TDI_SM LFSR result and seed registers require two sequential reads/writes for each register pair.
Note 6: The index register is used to set the individual address pointers. Writine to the index register will set each of the individual address pointers (TDO_SM,
TDI_SM, Expected, and Mask). The individual address pointers will automatically increment with each long word read from TDI_SM or each long word written to the
TDO_SM, Expected, or Mask memory spaces.
Note 7: The actual address is calculated from the base address of the memory area plus the content of its address pointer.
Note 8: The upper two bytes of each vector is ignored. These have been inserted to make the space align on long word boundaries.
TABLE 5. Vector Structure
Bit(s)
Function
0x00 - 0x1F
0x20 - 0x27
0x28 - 0x2E
0x2F
Length (maximum of 4G)
Macro Number (1 of 256) Room for scaleability
Reserved
Preloaded data / Load-on-the-fly (LotF)
Reserved
0x30 - 0x3F
TABLE 6. Header/Trailer Structure
Bit(s)
Function
0x00 - 0x1F
0x20 - 0x3FF
32-bit count (Note 9)
124 bytes (992 bits) header/trailer data
Note 9: Count must be greater than zero if the Header/Trailer Usage bits are not equal to "000" or "111".
TABLE 7. Macro Structure
Bit(s)
Function
0x1F
Compare
0x1E
Use Mask / Compare full length of vector (not including header/trailer)
Post-shift TCK_SM Count
0x1D - 0x1B
0x1A - 0x18
0x17
Pre-shift TCK_SM Count
Sync Bit Support Enable
0x16
Macro Structure Bit 8 Enable (Ignored for the shift macros with or without capture)
Macro Structure bit 7 Enable (Ignored for the shift macros with or without capture)
Header/Trailer Usage
0x15
0x14 - 0x12
0x11
Macro Type bit 1
0x10
Macro Type bit 0
0xF - 0x9
0x8
Last 7 TMS_SM bits
Presented during the falling edge of TCK_SM at terminal count during a Shift macro. Use in
the same manner as other TMS bits for State and BIST Macros.
Loop Bit if Macro type is Shift (for 1149.1 it would be a 0) or BIST
First 7 TMS_SM Bits (LSB is first bit to be shifted out of TMS_SM)
0x7
0x6 - 0x0
TABLE 8. Header / Trailer Usage
Bit 2
Bit 1
Bit 0
Function
0
0
0
Ignore Headers and Trailers
9
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TABLE 8. Header / Trailer Usage (Continued)
Function
Bit 2
Bit 1
Bit 0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Use Instruction Header
Use Instruction Trailer
Use both Instruction Header and Trailer
Use Data Header
Use Data Trailer
Use both Data Header and Trailer
Reserved
TABLE 9. Macro Type bits 10 and 11
Bit 1
Bit 0
Function
BIST Macro
Shift Macro
Function
0
0
1
1
0
1
0
1
Loop on loop bit for Vector count. No Data
Loop on loop bit for vector count. Read data from TDO_SM memory
Loop on loop bit for vector count. Read data from TDO_SM memory
Do not loop on loop bit of macro. No data to be shifted
Shift Macro with Capture
State Macro
TABLE 10. Sequencer Structure
Bit(s)
Function
0x00 - 0x1F
0x20 - 0x2F
0x30 - 0x3F
..x.. - ..x..
Sequence repeat count (up to 255)
Vector repeat count
Vector number
Repeat vector repeat count and vector number
Vector repeat count (up to 255)
Vector number (up to 63)
0x3E0 - 0x3EF
0x3F0 - 0x3FF
TABLE 11. Scan Bridge Support Structure
Bit(s)
Function
0x00 - 0x0F
0x10 - 0x17
0x18 - 0x1F
0x20 - 0x27
0x28 - 0x2F
..x.. - ..x..
Levels of Scan Bridge support to be inserted in the scan chain
Hierarchical Level 0 Scan Bridge Address
Hierarchical Level 0 Scan Bridge LSP
Hierarchical Level 1 Scan Bridge Address
Hierarchical Level 1 Scan Bridge LSP
Hierarchical Level Scan Bridge Address and LSP
Hierarchical Level 125 Scan Bridge Address
Hierarchical Level 125 Scan Bridge LSP
0x7F0 - 0x7F7
0x7F8 - 0x7FF
the PPI and the SSI. There are seven regions of memory as
Module Descriptions
viewed from the processor side. These regions, shown in
Table 4, are TDO_SM, TDI_SM, Expected, Mask, Vector,
Header/Trailer, Macro. Sequencer, and ScanBridge Support.
Each has a pointer which resides in the PPI.
Figure 1 shows a high level view of the STA101 which is
composed of two main modules, the Parallel Processor In-
terface (PPI) and the Serial Scan Interface (SSI) which
interface to each other through a dual-port memory. The PPI
provides a parallel interface for transferring data into and out
of the dual-port memory, and for configuring, controlling and
obtaining the status of the device. The SSI which resides on
the other side of the dual-port memory provides the parallel-
to-serial and serial-to-parallel conversion paths for providing
test data and test control to support the ScanMaster and
IEEE 1532 functions.
The memory is big endian oriented and is viewed as a single
entity from the SSI side and the SSI maintains a pointer. The
dual port memory module does not include any logic outside
of its own macro function, so all the timing and support logic
is included in the following PPI and SSI sections. There will
be no logic included in the STA101 design to utilize the
"busy" indicators to keep the user from overwriting memory
locations. The only area were this could occur in memory
would be the TDI_SM memory space since both the SSI and
PPI can write to this space, but the drivers shouldn’t allow
PPI writes to this area during normal operations.
Dual Port Memory
The dual port memory will be treated as a separate module
in the design to facilitate portability of the RTL of the design
to an FPGA host. The Dual Port Memory module is a 2048 x
32 bit dual-port memory which acts as the buffer between
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MEMORY/REGISTER DECODER
Parallel Processor Interface
The Memory/Register Decoder (MRD) contains all six index
registers (Index, Vector Index, Header/Trailer Index, Macro
Index, Sequencer Index and ScanBridge Support Index) and
four address registers (TDI_SM Address, TDO_SM Address,
Expected Address and Mask Address). In general, both in-
dex and address registers are used to maintain pointers to
their respective memory spaces. The exception is the Index
register which is used to set values in the four address
registers, i.e., writing to the Index register sets each of the
address registers. The value written to each address register
is the sum of its base address and the value written to the
Index register (the offset). All index and address registers,
with the exception of the Index register, will auto-increment
with each access to the corresponding memory space.
The overall function of the PPI is to receive the parallel data
from the processor interface, store the data in its appropriate
register or memory location, act on the data if the data are
PPI control data, provide status data back to the processor
and to provide a read path for result data to the processor. To
perform these functions, the PPI consists of seven main
blocks of logic along with the dual-port memory. These
blocks include the Edge Detector (ED), Processor Interface
Controller (PIC), the Memory/ Register Decoder (MRD), the
Word/Long Word Converter (WLWC), the Control Generator
(CG), the Status/Interrupt Generator (SIG) and the Flag
Generator (FG).
WORD/LONG WORD CONVERTER
The MRD provides the address decode to generate all the
control and status register enables for the CG and the SIG.
The MRD also provides the mux selects for the register or
memory selection for the read capture operation in the
WLWC.
The Word/Long Word Converter (WLWC) has four 16-bit
capture registers, and least significant/ most significant (LS/
MS) word read capture register pair and an LS/MS word
write capture register pair. Each register within the write
register pair has a separate enable to allow for the neces-
sary control to accomplish word to long word conversions
when in the 16-bit mode. In 32-bit mode, these enables will
be driven simultaneously. A mux is provided in front of the
MS word register for the write capture to select between the
32-bit and 16-bit mode external bus. Only one enable and a
mux select is needed to control the read capture register pair
to accomplish the long word to word conversions when in the
16- bit mode. In the 32-bit mode, the mux selection doesn’t
change so 32-bits are always driven. A mux is on either side
of the LS word register for the read capture. The one at the
register output provides for selection between the 32-bit
and16-bit mode. The one at the register input is for selection
between register space and memory space. All the control
for this block is provided by the PIC and MRD with the 16/32
bit mode enable coming from the Setup register.
CONTROL GENERATOR
The Control Generator has the seven control registers within
it. The Start, Interrupt Control, Setup, Clock Divider, TDI_SM
LFSR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM
LFSR MSB Seed registers are all within this block. The CG
will issue a strobe to the SSI when a write has been issued
to the Start or Setup registers so the SSI can react to the
new control data. The strobe will be derived from edge
detecting the enables to the Start or Setup registers. The
"new" data to the SSI are the Use Sequencer bit and three
Use Vector bits from the Start register, and the TDO Default
Value, TRST, ScanBridge Support Initiate/Release, three
Sync Bit Length, and two Test Loop-back bits from the Setup
register.
STATUS/INTERUPT GENERATOR
EDGE DETECTOR
The Status/Interrupt Generator has the four status registers
plus the logic to generate the interrupts and clear the inter-
rupts on a read. The registers are the Status, Interrupt
Status, TDI_SM LSFR LSB Result and TDI_SM LFSR MSB
Result registers. The SIG receives the LFSR result and
strobe signal SSI_LFSR_EN from the SSI and captures the
data in the LSB and MSB registers. The SIG receives the
compare result bit value from the SSI along with the com-
pare result bit clear and the compare result bit load.
The PPI module can support either an asynchronous or
synchronous processor interface. For an asynchronous in-
terface the circuit initially synchronizes STB and CE to the
system clock, SCK, by pipelining these two signals through
two flip-flop stages and then performs an edge detection on
STB and CE. For a synchronous parallel processor interface
this circuit just performs an edge detection. The outputs of
this circuit, one clock wide pulses indicating the detection of
negative and positive edges, will be used by the Processor
Interface Controller (PIC) state machine to start and to end a
processor access.
The SIG receives the 4 memory space flags from the FG
along with their associated load and clear signals so these
bits may be constantly updated. The half-full, half-empty, full
and empty flags will be generated and updated regardless of
the states of their respective interrupt enables. The SIG also
receives the 4 interrupt enables for the flags. The SIG also
receives the sequencer active and 3 vector active signals
from the SSI. These will also be updated regardless of the
enable state.
PROCESSOR INTERFACE CONTROLLER
The Processor Interface Controller (PIC) monitors the in-
coming processor control signals and sets up the appropri-
ate internal control signals to move the data into memory or
an internal register on a write or to move the data out of
memory or out of an internal register on a read. The PIC
edge detects the CE and the STB to start the access. The
PIC provides the control for the word to long word conver-
sion in the WLWC by controlling the three enables and the
mux select (READ_MSW) to the capture registers. The PIC
also controls when the internal read/write enable is issued to
the memory to complete the read/write operation. Timing for
register and memory read and write operations is described
in PPI INTERFACE TIMING.
If an interrupt enable is set then an interrupt will be gener-
ated. If an interrupt occurs at the same time as the interrupt
status is being read, then the interrupt will be set after the
read is complete. All bits in the Interrupt Status register are
cleared when the register is read.
FLAG GENERATOR
The FG takes in the TDI_SM or TDO_SM pointer values
from the PPI address pointers, compares them and gener-
ates the appropriate flags. If a flag condition has occurred, it
is passed along with the corresponding load enable to set
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Parallel Processor Interface
Serial Scan Interface
The Serial Scan Interface consists of the following units:
(Continued)
•
•
•
•
Clock Divider and TCK_SM Control
TAP Tracker
the bit in the status register in the SIG. If the flag condition
changes then the clear for the corresponding bit is passed to
the SIG to clear the flag. The TDO_SM empty and the
TDI_SM full flags are passed to the SSI also. A counter
enable is passed from the SSI indicate to the FG when the
SSI’s pointer value has changed. If a decrement and an
increment occur at the same time to either of the counters,
the counter value will not change.
Pointer Generator
Structure (Sequencer/Vector/Macro/ScanBridge) De-
coder
•
Structure (Sequencer/Vector/Macro/ScanBridge) Control
Registers
•
•
•
•
•
Count Generator
PPI INTERFACE TIMING
Shifter (TDO_SM/TDI_SM/TMS_SM)
Comparator
The processor accesses to SCANSTA101 can be classified
into six categories:
Expected and Mask Registers
•
•
•
•
•
•
register read
Serial Scan Interface Controller (SSIC) and ScanBridge
Controller
register write
16-bit memory read
16-bit memory write
32-bit memory read
32-bit memory write
The clock divider unit divides system clock SCK based on
the programmable divisor set in the clock divider to generate
TCK_SM. The TCK_SM control unit gates TCK_SM if the
TDO_SM buffer is empty.
The TAP Tracker unit keeps track of the target’s TAP con-
troller state. The purpose of the TAP Tracker is to determine
whether the target’s TAP controller is in SIR or SDR state, so
that the necessary PAD bits are inserted.
Register reads and register writes are performed the same
whether the device is in 16-bit mode or 32-bit mode. In 32-bit
mode, only the LS word is used. The MS word is ignored. All
timing for the 16-bit and 32-bit modes are exactly the same.
The shifter block contains two 32-bit shift registers for
TDO_SM and TDI_SM respectively, and a 16-bit shift regis-
ter for TMS_SM.
The 16-bit mode memory write is accomplished by perform-
ing two consecutive register writes with the only difference
being that the actual write occurs on the second access. The
16-bit mode register read consists of two accesses, with the
first access performed similar to the 16-bit register read but
requiring one more clock to complete the memory access.
Since all 32-bits of the memory data are captured on the first
access, the second memory read access is 2 clocks shorter
than the first.
The comparator unit compares the serial input on the
TDI_SM pin with the expected, data bit by bit, if the compare
bit of the Macro Structure is set. However, if compare/mask
bit is set, then the comparator unit compares only those bits
that are unmasked.
Expected and Mask Registers contain the data fetched from
the memory. This data will be used by the comparator to
compare the TDI_SM input with the expected data.
The processor initiates a write cycle by asserting CE fol-
lowed by STB. A set time prior to asserting STB, the R/W is
driven low and the address and data buses are driven by
valid address and data, respectively. After edge detecting the
STB and registering all the inputs, the address is decoded to
determine which internal address within the STA101 will be
written by the processor. The DTACK will be asserted on the
same rising edge of SCK on which the STB’s negative edge
is detected, indicating to the processor that it can deassert
the STB. When the STA101 detects the positive edge of the
STB, it will deassert the DTACK indicating to the processor
that it can start a new cycle. The processor can start a new
cycle by asserting the STB and by driving the address and
data buses with new address and data.
The SSIC provides the timing and control signals to synchro-
nize the operation of the various blocks in the SSI. The
ScanBridge Controller consists of the control logic to set up
the ScanBridge’s hierarchy, if the ScanBridge Support
Initiate/Release bit is enabled, prior to scanning actual test
vectors out of TDO_SM.
CLOCK DIVIDER AND TCK_SM CONTROL
The clock divider will be a binary divider where only one bit
of the clock divider register will be set to one at any given
time. The implementation will ignore bits 0, and 8-15, so the
supported divisors are 2, 4, 8, 16, 32, 64 and 128.
A read cycle is similar to the write cycle except that the
DTACK will not be asserted until the selected address loca-
tion’s contents are loaded. So, for a 16-bit register read it
takes one more clock than it does for a write cycle.
To generate a TCK_SM of frequency SCK/4, the clock di-
vider register should be set to 4 (00000100). This will enable
the gate at the output of bit 2 of the counter to generate a
clock of SCK divided by 4. If in LotF mode, then the TCK_SM
enable from the SSIC will gate TCK_SM when the TDO_SM
buffer is empty.
Accesses to STA101 memory require two consecutive ac-
cesses in the 16-bit external bus mode. The memory writes
are similar to register writes but the only difference is that
processor has to perform two consecutive 16-bit writes to
write to the selected memory location. One important note,
during a memory read, is that DTACK is not asserted until
the contents of the memory is loaded into the capture regis-
ters. For this reason the first read from the memory requires
five clocks which includes the memory access time, while
the second read is done in 3 clock cycles.
TAP TRACKER
The TAP Tracker consists of a 16-bit register to trace the
IEEE Standard 1149.1 state machine. The state machine is
one hot encoded and will continuously track the target’s TAP
Controller based on the TMS_SM sequence. The TAP
Tracker will be used by the ScanBridge support controller to
determine whether the target’s TAP controller is in SIR or
SDR state so that it can insert an appropriate number of pre
and post-PAD bits.
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shifter will skip (7 - pre-shift count) least significant bits. e.g.,
if the pre-shift count is 4, the least significant 3 bits of the
TMS_SM shifter will not be used to drive TMS_SM during
pre-shift. Similarly, if the post-shift is less than 7 then, during
post shift only the number of bits equal to the post-shift count
following the macro structure bit 8 will be used to drive
TMS_SM.
Serial Scan Interface (Continued)
The TAP Tracker will enter Test-Logic Reset state upon
setting the TRST bit (bit 5) in the Setup register or by issuing
a sequence of five TMS_SM high bits.
SHIFTER
The Shifter block contains two 32-bit shift registers for
TDO_SM and TDI_SM respectively, and one 16-bit shift
register for TMS_SM. The TMS_SM shifter block diagram is
shown in Figure 2, the TDO_SM shifter block diagram is
shown in Figure 3, and the TDI_SM shifter block diagram is
shown in Figure 4.
The STA101 memory is organized in big Endian format.
Since a memory write can be accomplished by two consecu-
tive writes to the same location when embedded software
loads the TDO_SM memory, it is assumed that the least
significant 16 bits are written first and then the most signifi-
cant 16 bits. Therefore, when the Sequencer or a Vector is
initialized the SSIC can directly fetch and load the long word
to the TDO_SM shifter without any modification.
Before the start of a vector processing the TMS_SM shifter is
loaded with the least significant 16 bits of the macro struc-
ture. Based on the pre-shift TCK_SM count, the TMS_SM
10121521
FIGURE 2. TMS_SM Shifter
10121522
FIGURE 3. TDO_SM Shifter
Similarly, reading from TDI_SM memory can be accom-
plished by two consecutive reads. When reading from the
TDI_SM memory, the first read will contain the least signifi-
cant 16 bits and the second read the most significant 16 bits.
13
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Serial Scan Interface (Continued)
10121523
FIGURE 4. TDI_SM Shifter
The TDI_SM shifter unit consists of two 32-bit shift registers
as shown in Figure 4. The shift register on top will be used as
an LFSR register. However, before using the TDI_SM LFSR
register, the LFSR Exponent and LFSR Seed registers must
be written with valid data. The LFSR Exponent register must
be written with a 3-bit binary encoded value such that the
corresponding polynomial out of the five available polynomi-
als will be selected. The value written to the LFSR Seed
registers will be used to initialize the TDI_SM LFSR register
to a predetermined state. Once the test vector has com-
pletely scanned in, the final contents of the LFSR register will
be transferred to the LFSR Result registers. The 32-bit shift
register at the bottom will be used to shift in TDI_SM directly
in normal mode or to shift in TMS_SM or TDO_SM in the
loop-back mode. After shifting in every thirty two bits, the
contents of this register will be transferred to the correspond-
ing TDI memory location before the next shift operation.
SHIFTER IMPLEMENTATION
Shift register implementation is illustrated in Figure 5. Shift
out enable for the TMS_SM and TDO_SM shifters is gener-
ated by comparing the clock pulse counter output to the
clock divider - 1. Shift in enable for the TDI_SM shifter is
generated by comparing the clock pulse counter to program-
mable divisor/2 - 1. These enables are gated by the control
signals from SSIC so that data are shifted out (TMS_SM/
TDO_SM) or shifted in (TDI_SM) only when necessary.
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Serial Scan Interface (Continued)
10121524
FIGURE 5. Shift Register Implementation and Timing
COMPARATOR AND EXPECTED/MASK REGISTERS
parator will compare each bit on the TDI_SM input with the
corresponding bit from the expected register. If the mask
feature is enabled, then the comparison is performed only on
those bits that are not masked, i.e., on those bits whose
mask is set to zero. Table 12 shows how Compare and Use
Mask/Compare bits in the Macro Structure will be used.
The One Bit Comparator, when enabled, will compare
TDI_SM input with expected data. When the compare fea-
ture is enabled (pre-load only) the SSIC pre-fetches data into
Expected and Mask registers from the address locations
pertaining to the current vector being processed. The com-
TABLE 12. Compare and Use Mask/Compare Bit Descriptions
Compare
Use Mask/Compare
Description
0
0
1
1
0
1
0
1
Do Not Compare
Compare with Mask
Compare without Mask
Compare with Mask
Results of Compare bit (bit 15 of Status register) stores the
comparison results in the status register. This bit defaults to
fail (zero) and will be updated only after the current vector is
processed. In the case of a single vector the Results of
Compare bit will be set to one (pass) only if all the bits in the
scanned in vector match the expected vector. However, in
the case of the sequencer only the results of final vector
comparison will be taken into account.
Each vector within the sequencer is repeated until the vector
repeat count is exhausted. However, the sequence is re-
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Figure 6 illustrates the compare logic.
Serial Scan Interface (Continued)
peated until either the sequencer repeat count is exhausted
or the compare passes and that the loop of the sequence is
completed.
10121525
FIGURE 6. Compare Logic
After reset and before every sequencer process, flip-flops 1
and 3 are initialized to zero while flip-flop 2 is set to 1. When
the compare feature is enabled flip-flop 1 is continuously
updated with the immediate comparison results (1 for pass
and 0 for fail). Flip-flop 2 is reset to zero when a mismatch
occurs and remains in this state for the remainder of the
current vector processing. When the current vector is com-
pletely processed flip-flop 3 (Results of Compare register)
will be updated with the current status.
SERIAL SCAN INTERFACE CONTROLLER AND
SCANBRIDGE CONTROLLER
The Serial Scan Interface Controller (SSIC) remains in the
Idle state until new data are written to the Start register.
When this event occurs the following operations are per-
formed:
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the sequencer immediately after releasing the Scan-
Bridge support. However, once the ScanBridge support
is released the user may start processing a vector or the
sequencer by writing to the Start register.
Serial Scan Interface (Continued)
1. If the ScanBridge Support Initiate/Release bit was not
set previously and is currently set in the Setup register,
the SSIC initializes the ScanBridge Controller (SBC) to
perform the following steps to set up all ScanBridges in
the hierarchy.
3. If the sequencer is enabled (the Use Sequencer bit in
the Start register is one),
A. Clear the Results of Compare bit and set the Using
Sequencer bit in the Status register.
A. Determine the number of levels of ScanBridge sup-
port to be inserted (from the ScanBridge support
structure)
B. Fetch the sequence repeat count.
C. If the sequence repeat count is zero, the sequence is
complete so reset the Using Sequencer bit and re-
turn to the Idle state, otherwise fetch the next vector
number and its repeat count.
B. Sequence TMS_SM so that all ScanBridges in the
same level of hierarchy enter the SIR state, and then
shift in the address (from the ScanBridge structure)
to select a ScanBridge in the current level of hierar-
chy. The ScanBridge’s TAP controller is then se-
quenced through the Update-IR state.
D. If the vector number is zero, decrement the se-
quence repeat count and return to Step 3c. If the
vector number is illegal, i.e., other than 001, 010,
011, or 100, decrement the sequence repeat count
and return to Step 3c.
C. Sequence TMS_SM so that the selected Scan-
Bridge’s TAP controller enters the SIR state, then
scan in the MODESEL instruction to put its mode
register in the data path.
E. If the vector repeat count is equal to zero, fetch the
next vector number and its repeat count and go to
Step 3d. If the repeat count is non-zero fetch the
vector structure.
D. Sequence the selected ScanBridge’s TAP controller
to enter the Shift-DR state and scan in the LSP
contents (from the ScanBridge structure) into its
mode register. The ScanBridge’s TAP controller is
then sequenced through the Update-DR state.
F. If the pre-load bit in the vector structure is not set,
reset the Using Sequencer bit and return to the Idle
state.
E. Repeat Step 1c, but this time scan in the UNPARK
instruction so that the LSP is inserted into the active
scan chain.
4. If the sequencer is not enabled but a vector is enabled
(the Use Vector bits in the Start register are non-zero),
fetch the current vector structure and set the appropriate
Using Vector bits in the Status register. If neither the
sequencer nor a vector is enabled, return to the Idle
state.
F. Sequence the ScanBridge’s TAP controller to enter
the RTI state (the LSP will not be unparked until its
TAP controller enters RTI).
G. Repeat Steps 1b through 1g to configure the Scan-
Bridges in the remaining hierarchy levels. One set of
pre-PAD and post-PAD bits is added to the patterns
for each hierarchy level between the ScanMaster
and the ScanBridge being configured. The PAD bits
are used to bypass the intermediate levels of hierar-
chy.
5. Fetch the Macro Structure to be used, set the vector/
macro control bits and store the TMS_SM bits in the
Structure Control registers.
6. If the Pre-shift TCK_SM Count is not zero, then enable
TCK_SM and drive TMS_SM using the first seven bits of
the macro until the Pre-shift TCK_SM Count is zero.
During pre-shift, TDO_SM will be driven with it’s previ-
ous value.
H. For the subsequent vectors, if the TAP Tracker en-
ters the
7. If the macro type is State then,
a. SDR state, the STA101 will add one pre-bit for the
PAD register and one post-bit for the bypass reg-
ister for each level of hierarchy.
A. If the Macro Structure Bit 7 is enabled, set TMS_SM
to the bit 7 value of the macro structure and drive
TDO_SM with it’s previous value.
b. SIR state, the STA101 will add one pre-bit for the
PAD register and eight post-bits for the Scan-
Bridge instruction register for each level of hierar-
chy. The eight post-bits will be all ones because
the ScanBridge will be forced into bypass mode.
B. If the Macro Structure Bit 8 is enabled, set TMS_SM
to the bit 8 value of the macro structure and drive
TDO_SM with it’s previous value and then go to Step
10.
C. If the sequencer is being used then, decrement the
vector repeat count and return to Step 3e. If a vector
is being used, return to the Idle state.
I. The PAD bits need to be stripped when loading a
vector into TDI_SM. This will be done by having a
status flag to indicate whether the vector that is being
scanned out has ScanBridge support or not. If the
scanned-out vector has ScanBridge support, then the
PAD bits will be stripped when the TAP Tracker enters
the SDR or SIR states.
8. If the macro type is BIST then,
A. If the Macro Structure Bit 7 is enabled, set the count
length, set TMS_SM to the bit 7 value of the macro
structure and drive TDO_SM with the default value
(Setup register bit 6) until the count length is zero.
2. If the ScanBridge Support Initiate/Release bit was set
previously and is currently reset in the Setup register,
the SSIC will toggle TCK_SM five times while TMS_SM
is held high. This will return all selected ScanBridges to
the wait-for-address state and park the LSPs in the
Test-Logic-Reset state. When the ScanBridge support is
released the user should make sure that the Use Vector
and Use Sequencer bits in the Start register are not set,
such that, the SSIC will not start processing a vector or
B. If the Macro Structure Bit 8 is enabled, set TMS_SM
to the bit 8 value of the macro structure and drive
TDO_SM with the default value (Setup register bit 6)
and then go to Step 10.
C. If the sequencer is being used then, decrement the
vector repeat count and return to Step 3e. If a vector
is being used, return to the Idle state.
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b. If the TAP tracker is in the Shift-DR state and the
number of levels of hierarchy is greater than one,
drive TDO_SM with a post-PAD bit (high) for each
level of hierarchy and while TMS_SM remains set
to the loop bit.
Serial Scan Interface (Continued)
9. If the macro type is Shift or Shift with Capture then,
A. If the macro type is Shift with Capture, enable TDI
capture.
c. For the final level of hierarchy or if there is only
one level of hierarchy, and if the TAP tracker is in
the Shift-IR state, set the count length to eight,
and drive TDO_SM with post-PAD bits (all high)
until the count length is one and while TMS_SM
remains set to the loop bit.
B. If the Sync Bit Support Enable bit is set, fetch sync bit
count, set the count length, set TMS_SM to the loop
bit and drive the TDO_SM high until sync bit count is
zero.
C. If the ScanBridge Support Initiate/Release bit is set,
drive the TDO_SM with pre- PAD bit (high) and while
TMS_SM remains set to the loop bit. Repeat for each
level of hierarchy.
I. If the Sync Bit Support Enable is set, fetch sync bit
count, set the count length, and drive the TDO_SM
high until sync bit count is one and while TMS_SM
remains set to the loop bit.
D. If the Use Data/Instruction Header is enabled, fetch
the header length and data, set the count length, and
drive the TDO_SM with header data until the header
length is zero and while TMS_SM remains set to the
loop bit.
J. Set TMS_SM to the bit 8 of the TMS_SM Macro
Structure sequence and drive TDO_SM with the final
vector bit or trailer bit or post-PAD bit or sync bit. After
shifting out the final vector bit, disable the comparator
and register the comparison results.
E. If the Compare or Mask/Compare is set, enable the
comparator.
10. If the Post-shift TCK_SM Count is not zero, then enable
TCK_SM and drive TMS_SM using the last seven bits of
the macro until the Post-shift TCK_SM Count is zero.
F. Set the vector count length, and drive the TDO_SM
with vector data until the count length is one and
while TMS_SM remains set to the loop bit. In the LotF
mode if the count length is not zero and the TDO
buffer is empty, then gate TCK_SM until more data
are available in the TDO buffer. When TCK_SM is
disabled TMS_SM and TDO_SM will be driven with
their previous values.
11. If the Sequencer is being used,
A. Decrement the sequence repeat count and return to
Step 3c if the Compare or Mask/Compare is enabled
and the results of compare is a fail.
B. Decrement the vector repeat count and return to
Step 3e if the if the Compare or Mask/Compare is
enabled and the results of compare is a pass.
G. If the Use Data/Instruction Trailer is enabled, fetch
the trailer length and data, set the count length, and
drive TDO_SM with trailer data until the trailer length
is one and while TMS_SM remains set to the loop
bit.
C. Decrement the vector repeat count and return to
Step 3e if the Compare or Mask/ Compare is not
enabled.
H. If the ScanBridge Support Initiate/Release bit is set:
12. If the Vector is being used return to the Idle state.
a. If the TAP tracker is in the Shift-IR state and the
number of levels of hierarchy is greater than one,
set the count length to eight, and drive TDO_SM
with post-PAD bits (all high) until the count length
is zero for each level of hierarchy and while
TMS_SM remains set to the loop bit.
MODE REGISTER WRITE TO VECTOR/SEQUENCER START
10121533
FIGURE 7. Timing from Mode Register Write to Vector Start
Figure 7 shows the timing from the processor write to the
start of vector processing, whereas Figure 8 shows the
timing from the processor write to the start of sequencer
processing. A processor write to the Start registers is indi-
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18
support is enabled, then the sync bits and/or header bits
and/or ScanBridge pre-PAD bits will be loaded into the
TDO_SM shifter before processing the actual test vector.
Once the actual test vector is completely shifted out, again
depending on the ScanBridge support and/or the use of
trailers, post-PAD bits and the trailer bits are loaded and
shifted out through the TDO_SM shifter.
Serial Scan Interface (Continued)
cated by a "new data" pulse. On the same SCK rising edge
when the "new data" is detected to be high, the Start or
Setup register contents will be updated with new data. So,
the decoding of the enables takes place during the next
clock cycle to determine whether to process the sequencer
or a vector. Therefore, one clock after the "new data" is
detected, the SSIC starts loading the pointer register on
consecutive cycles with the appropriate addresses to fetch
the Sequencer, Vector and Macro Structures. Once the
headers are decoded and Structure Control Registers are
set up, the SSIC loads the pointer register so that data from
the TDO_SM memory area is fetched and loaded into the
TDO_SM shifter before being shifted out. However if there
are any sync bits and/or header bits and/or ScanBridge
The count length will be decremented by one with each shift.
After shifting out all the current shifter contents the shifter will
be loaded with new data before the falling edge of the next
TCK_SM, if the count length is not exhausted. In the case
where data cannot be loaded from the memory before the
next falling edge of TCK_SM, the TCK_SM will be gated until
the data is available.
10121534
FIGURE 8. Timing from Mode Register to Sequencer Start
WRITING AND READING PARTIAL LONG WORDS
to the scan chain) must be stored and written into the
memory as the least significant bits. This will assure that the
desired bits will be accurately loaded into the TDO_SM
shifter and shifted out to the boundary scan chain. For
instance, to shift a 3-bit (110) sequence the partial long word
should be written to the TDO_SM memory as shown in
Care should be taken when writing a partial long word to
TDO_SM memory or reading a partial long word from
TDI_SM memory. Since the TDO_SM shifter shifts out LSB
first, the valid (meaningful) bits within a partial long word
(i.e., long word containing less than 32 valid bits to be shifted
10121535
FIGURE 9. Writing a Partial Long Word to the TDO_SM Memory
Figure 9 (only the least significant 16 bits are shown). A
subsequent enable and load of the vector structure with the
correct length will initialize the shift operation and only the
bits that are significant will be shifted out to the scan chain.
turning to TDI_SM, the TDI_SM memory will be loaded with
two long words (i.e., two full long words plus a partial long
word containing 5 meaningful bits). If the last 5 bits shifted
back to the TDI_SM shifter are 11010, then upon completion
of the shift operation, the TDI_SM shifter will contain the
following partial long word as shown in Figure 10 (only most
significant 16 bits are shown), which will subsequently be
loaded into the TDI_SM memory.
Data is shifted from the scan chain into the TDI_SM shifter
from MSB to LSB. Consequently, the valid (i.e., meaningful)
bits in a partial long word shifted into the TDI_SM shifter will
reside in the upper significant bit locations. For example, if a
scan operation involves shifting and evaluating 69 bits re-
19
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Serial Scan Interface (Continued)
10121536
FIGURE 10. Reading a Partial Long Word from the TDI_SM Memory
Following a read of a partial long word, the embedded test
tracker state. For shift macros, the TDO_SM output also
depends on the current macro structure’s TMS_SM bit num-
ber as explained below.
software must adjust the position of the valid bits read from
the TDI_SM shifter/buffer or the position of the expected
data to assure that an accurate comparison is made (and the
non-meaningful bits are masked).
TDO_SM IMPLEMENTATION
The behavior of the TDO_SM output depends on the current
macro type that is being processed and the SETUP register
bits 11 and 10, as shown in Table 13, regardless of the TAP
TABLE 13. TDO_SM Output Behavior
SETUP[11:10]
TDO_SM
00
Hold Previous value
01 or 10
11
Default TDO value (Bit 6 of the SETUP register) (Note 10)
High Impedance
Note 10: Default TDO value (bit 6 of the SETUP register) may be set to a 0 when SETUP[11:10]=01 and to a 1 when SETUP[11:10]=10.
For BIST and STATE macros, the TDO_SM output behaves
exactly as shown in the above table, however, for the shift
macros, with or without capture, the TDO_SM output be-
haves as per the table only when the corresponding
TMS_SM output is not driven by the macro structure bit 7 or
8. On each falling edge of the TCK_SM following the
TCK_SM’s falling edge on which the TMS_SM changes
state from bit 6 of the macro structure to the bit 7of the macro
structure, the serial test vector data fetched from the
memory will be presented on the TDO_SM output. On the
falling edge of the TCK_SM on which the final bit of the test
vector is presented on the TDO_SM output, the TMS_SM
will be presented with the macro structure bit 8. On the
consequent TCK_SM falling edges and on the TCK_SM
falling edges before the TMS_SM changes state from bit 6 to
bit 7 of the macro structure the TDO_SM will behave as per
the table above.
Hardware Interface Details
TABLE 14. System Interface Signal Description
Signal Name
SCK
No. of
Bits
1
Pin Type
Driver Type
LVTTL
Freq.
MHz
66
Description
I
System Clock: This is the main clock signal to the STA101.
SCK is used to clock all internal circuitry
RST
1
I,H
LVTTL
N/A
Hardware Reset signal (with hysteresis (H)): This is the
STA101 asynchronous reset signal.This signal resets the
entire STA101 and sets all registers to their respective
default values.
OE
1
I
LVTTL
N/A
Output enable: Tristates all dot1 outputs when high.
TABLE 15. Parallel Processor Interface Signal Descriptions
Signal Name
No. of
Bits
16
Pin Type
Driver Type
Freq.
MHz
N/A
Description
DATA(31:16)
I/O
LVTTL
(weakest
driver)
Bidirectional Data Bus. Not bonded out in packaged part.
These are only used in the 32-bit macro version.
DATA(15:0)
16
5
I/O
I
LVTTL
N/A
N/A
Bidirectional Data Bus.
Address Bus
ADDRESS(4:0)
LVTTL
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20
Hardware Interface Details (Continued)
TABLE 15. Parallel Processor Interface Signal Descriptions (Continued)
Signal Name
No. of
Bits
1
Pin Type
Driver Type
LVTTL
Freq.
MHz
N/A
Description
CE
I
I
I
Chip Enable, when low, enables the PPI for transfers.
DATA(31:0) and DTACK are tristated when CE is high.
Read/Write defines a PPI cycle. Read when high, write when
low.
R/W
STB
1
1
LVTTL
N/A
N/A
LVTTL
Strobe is used for timing all PPI transfers. DATA(31:0) are
tristated when STB is high. Data valid setup is with respect
to the falling edge of STB and data valid hold is with respect
to rising edge of STB.
DTACK
1
O
O/D
N/A
Data Acknowledge (open drain - sustained tristate). DTACK
is used to synchronize asynchronous transfers between the
host and the STA101. During write cycles, DTACK goes low
when data has been registered and then goes to high
impedance when the cycle has been completed. During read
cycles DTACK goes low when data bus is driven with the
valid data and then goes to high impedance when the cycle
has been completed.
INT
1
O
LVTTL
N/A
Interrupt is used to trigger a host interrupt for any of the
defined interrupt events. Signal is active high.
10121537
FIGURE 11. PPI Write Cycle Timing Diagram
21
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Hardware Interface Details (Continued)
10121538
FIGURE 12. PPI Read Cycle Timing Diagram
TABLE 16. Serial Scan Interface Signal Descriptions
Signal Name
No.
Pin Type
Driver Type
Freq.
MHz
Description
TDI_SM
1
1
1
1
1
1
1
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
up to 25 ScanMaster Test Data Input (weak pullup)
up to 25 ScanMaster Test Data Output
up to 25 ScanMaster Test Mode Select
up to 25 ScanMaster Test Clock
TDO_SM
TMS_SM
TCK_SM
O
O
O
O
O
O
TRST0_SM
TRST1_SM
TRIST_SM
N/A
N/A
N/A
ScanMaster Test Reset
Redundant ScanMaster Test Reset (not bonded out)
The tristate notification pin exerts a high when TDO_SM is
tristated.
10121539
FIGURE 13. SSI Timing Diagram
pins with the external data pins. Scan is selected by a user
TEST AND DEBUG INTERFACE
defined instruction through the JTAG port. Note that the scan
chain(s) will not be hooked up to the JTAG tap.
The test and debug interfaces are provided to perform
manufacturing tests. There is a standard JTAG interface
along with a scan interface. The scan interface have shared
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22
Hardware Interface Details (Continued)
TABLE 17. STA101 1149.1 Signal Descriptions
Signal Name
No. of
Pin Type
Driver Type
Freq.
Description
Bits
1
MHz
TDO
TDI
O
I,U
I,U
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
up to 25 STA101 Test Data Out
1
up to 25 STA101 Test Data In (pullup (U))
up to 25 STA101 Test Mode Select (pullup (U))
up to 25 STA101 Test Clock
TMS
TCK
TRST
1
1
1
I,U,H
N/A
STA101 Test Reset (pullup (U) & hysteresis (H))
TABLE 18. STA101 Scan Signal Descriptions
Signal Name
No. of
Bits
1
Pin Type
Driver Type
Freq.
MHz
TBD
TBD
Description
SCAN_EN
SCAN_IN
I
I
Shared TRIST
Shared
STA101 Scan Enable Shared pin with TRIST.
STA101 Scan Data In. Shared pin with DATA15.
1
DATA15
SCAN_OUT
1
O
Shared
TBD
STA101 Scan Data Out. Shared pin with DATA14.
DATA14
SAFE MODE
RESET STRATEGY
This device implements the following design rules to provide
SEU/SEE protection:
The incoming external hardware reset (RST) will be synchro-
nized to the incoming clock (SCK) and is combined with the
soft reset to generate
a synchronized internal reset
•
Triple modular redundancy for TRST0_SM and
TRST1_SM outputs with the help of a TMR D flip-flop .
(SYS_RST_N). During operation, the chip can be reset by
writing a ’1’ to the Reset bit in the Setup register. All logic
throughout the device will be initialized, all control and status
registers will be in a known default state, all PPI memory
address pointers will default to their respective base ad-
dresses, the SSI memory pointer will default to zero, the Tap
Tracker will be reset to TLR, and the clock division counter
will be initialized to all zero’s after deassertion of the internal
reset. The Reset bit in the Setup register is self clearing. The
TRST bit in the Setup register, when set, resets the SSI logic
and drives the TRST0_SM and TRST1_SM to zero.
•
After reset all scan interface outputs are driven to SEU
tolerant safe values as shown below:
TMS_SM = 1
TCK_SM = 0
TDO_SM = Z
TRST0_SM = 0
TRST1_SM = 0
•
The EXTEST and the HIGHZ outputs from the JTAG TAP
controller are gated with TRST to protect the boundary
scan cells from inadvertantly entering the test mode.
Software Interface Details
CLOCK GENERATION AND DISTRIBUTION
REGISTER DEFINITIONS
Input Clock (SCK): Up to 66 MHz
The following sections include descriptions of each addres-
sable register in the ScanMaster memory space. Following
the title of the particular register, the mnemonic for the
register is included in parentheses as well as the physical
address location in hexadecimal notation (value preceded by
$). KEY- RO: Read Only; RW: Read/Write.
Output Clock (TCK_SM): TCK_SM is a divided, registered
version of SCK.
•
Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of
SCK.
•
Frequency: up to 25 MHz
TABLE 19. Start Register (START) ($00)
Field Address
Bit(s)
Type
Reset Value
Reset Source
Offset
15:14
13
RO
RW
RO
RW
RO
RW
Reserved
0
0
0
0
0
0
00b
0b
Onboard Memory BIST
Reserved
SYS_RST
SYS_RST
SYS_RST
12:9
8
0000b
0b
Use Sequencer
7:3
2:0
Reserved Use Vector x (Note 11)
Use Vector x
0000h
000b
Note 11: Reserved Use Vector x for future growth for the number of vectors.
23
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Software Interface Details (Continued)
Onboard Memory BIST
ScanMaster memory BIST enable. This bit is self clearing when BIST result is written
to the Memory BIST Result bit in the Status register.
Initiate on chip memory BIST
’1’
’0’
On chip memory BIST complete
Use Sequencer
Sequencer enable/disable (For preloaded vectors only)
Enable sequencer
’1’
’0’
Disable sequencer
<
>
Use Vector 2:0
Use Vector x designates the vector "x" which is enabled, where "x" is the vector
<
>
number, a binary encoding of bits 2:0 . Only vectors 1 through 4 are valid. Vectors
5 through 7 reserved for future use.
’000’
’001’
’010’
’011’
’100’
No vector enabled
Vector 1 enabled
Vector 2 enabled
Vector 3 enabled
Vector 4 enabled
TABLE 20. Status Register (STATUS) ($01) (Note 12)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15
14
13
12
11
10
9
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
Results of Compare (Note 13)
BIST Running
0
0
0
0
0
0
0
0
0
0
0b
0b
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
Memory BIST Result
TDO Status Half-empty (Note 15)
TDO Status Empty
0b
0b
0b
TDI Status Full
0b
TDI Status Half-full (Note 15)
Using Sequencer
0b
8
0b
7:3
2:0
Reserved Using Vector x (Note 14)
Using Vector x
00000b
000b
SYS_RST
Note 12: Write capability to the register is only for test and debug purposes. Drivers should disable writes to register during normal operation.
Note 13: Results of Compare bit is toggled after a compare is complete and it is set to the mismatch state when sequencer is kicked off again. Remains in last state
until next compare completed or until set to the mismatch.
Note 14: Reserved Using Vector x for future growth for the number of vectors.
Note 15: Half full or half empty designates 56 long words.
Results of Compare
Results of compare between TDI_SM and Expected memory space
Compare match
’1’
’0’
Compare mismatch
BIST Running
Indicates the BIST operation is still active
BIST operation active
’1’
’0’
BIST operation complete or BIST operation not running
ScanMaster memory BIST status results BIST result will be held until overwritten by
next BIST operation.
Memory BIST Result
’1’
Passed memory BIST
’0’
Failed memory BIST
TDO Status Half
TDO_SM memory space status half empty
TDO_SM memory space half empty
TDO_SM memory space not half empty
TDO_SM memory space status empty
TDO_SM memory space empty
’1’
’0’
TDO Status Empty
’1’
’0’
TDO_SM memory space not empty
TDI_SM memory space status full
TDI Status Full
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24
Software Interface Details (Continued)
’1’
’0’
TDI_SM memory space full
TDI_SM memory space not full
TDI Status Half
TDI_SM memory space status half full
TDI_SM memory space half full
’1’
’0’
TDI_SM memory space not half full
Using Sequencer
Sequencer active and processing. Bit cleared when sequence complete.
Sequencer active
’1’
’0’
Sequencer inactive
<
>
Using Vector 2:0
Using Vector x designates the vector "x" currently running, where "x" is the vector
<
>
number, a binary encoding of bits 2:0 . Only vectors 1 through 4 are valid. Vectors
5 through 7 reserved for future use. Field cleared when vectors complete.
’000’
No vector active.
Vector 1 active.
Vector 2 active.
Vector 3 active.
Vector 4 active.
’001’
’010’
’011’
’100’
TABLE 21. Interrupt Control Register (INTCTRL) ($02)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15:13
12
RO
RW
Reserved
0
0
000b
0b
TDO Half-empty Interrupt Enable
(Note 18)
SYS_RST
11
10
9
RW
RW
RW
TDO Empty Interrupt Enable
TDI Full Interrupt Enable
TDI Half-full Interrupt Enable (Note
18)
0
0
0
0b
0b
0b
SYS_RST
SYS_RST
SYS_RST
8
RW
RO
Sequencer Interrupt Enable (Note 17)
Reserved Vector x Interrupt Enable
(Note 16)
0
0
0b
SYS_RST
SYS_RST
7:3
00000b
2:0
RW
Vector x Interrupt Enable (Note 17)
0
000b
Note 16: Reserved Vector x Interrupt Enable for future growth for the number of vectors.
Note 17: Drivers should not allow Sequencer Interrupt Enable and Vector x Interrupt Enable to be set at same time. Sequencer Interrupt Enable has priority over
the Vector x Interrupt Enable.
Note 18: Half full or half empty designates 56 long words.
TDO Half-empty Interrupt Enable TDO_SM memory space half empty interrupt enable
’1’
Enable TDO_SM memory space half empty interrupt
Disable TDO_SM memory space half empty interrupt
TDO_SM memory space empty interrupt enable
Enable TDO_SM memory space empty interrupt
Disable TDO_SM memory space empty interrupt
TDI_SM memory space full interrupt enable
Enable TDI_SM memory space full interrupt
Disable TDI_SM memory space full interrupt
TDI_SM memory space half full interrupt enable
Enable TDI_SM memory space half full interrupt
Disable TDI_SM memory space half full interrupt
Sequencer activity complete interrupt enable
Enable Sequencer activity complete interrupt
Disable Sequencer activity complete interrupt
’0’
TDO Empty Interrupt Enable
’1’
’0’
TDI Full Interrupt Enable
’1’
’0’
TDI Half-full Interrupt Enable
’1’
’0’
Sequencer Interrupt Enable
’1’
’0’
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Software Interface Details (Continued)
<
>
Vector Interrupt Enable 2:0
Vector "x" complete interrupt enable, where "x" is the vector number, a binary
<
>
encoding of bits 2:0 . Only vector interrupts1 through 4 are valid. Vector interrupts 5
through 7 reserved for future use.
No vector interrupt enabled
’000’
’001’
’010’
’011’
’100’
Vector 1 interrupt enabled
Vector 2 interrupt enabled
Vector 3 interrupt enabled
Vector 4 interrupt enabled
TABLE 22. Interrupt Status Register (INTSTAT) ($03) (Note 22)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15:13
12
11
RO
RW
RW
RW
RW
RW
RO
Reserved
0
0
0
0
0
0
0
00b
0b
TDO Half-empty Interrupt (Note 21)
TDO Empty Interrupt
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
1b
10
9
TDI Full Interrupt
0b
TDI Half-full Interrupt (Note 21)
Sequencer Interrupt
0b
8
0b
7:3
Reserved Vector x Interrupt (Notes
19, 20)
00000b
2:0
RW
Vector x Interrupt (Note 20)
0
000b
SYS_RST
Note 19: Reserved Vector x Interrupt for future growth for the number of vectors.
Note 20: Drivers shouldn’t allow Sequencer Interrupt and Vector x Interrupt to be set at same time. Sequencer Interrupt has priority over the Vector x Interrupt.
Note 21: Half full or half empty designates 56 long words.
Note 22: This register is writable in debug mode only.
TDO Half-empty Interrupt
TDO_SM memory space half empty status
TDO_SM memory space half empty
TDO_SM memory space not half empty
TDO_SM memory space empty status
TDO_SM memory space empty
’1’
’0’
TDO Empty Interrupt
’1’
’0’
TDO_SM memory space not empty
TDI_SM memory space full status
TDI Full Interrupt
’1’
TDI_SM memory space full
’0’
TDI_SM memory space not full
TDI Half-full Interrupt
TDI_SM memory space half full status
TDI_SM memory space half full
’1’
’0’
TDI_SM memory space not half full
Sequencer completed status
Sequencer Interrupt
’1’
’0’
Sequencer processing completed
Sequencer processing or not started
Vector "x" completed status, where "x" is the vector number, a binary encoding of bits
<
>
Vector Interrupt 2:0
<
>
2:0 .Only vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future use.
’000’
’001’
’010’
’011’
’100’
No vector completed activity
Vector 1 completed
Vector 2 completed
Vector 3 completed
Vector 4 completed
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Software Interface Details (Continued)
TABLE 23. Setup Register (SETUPR) ($04)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15
14:10
11:10
9:7
6
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
16/32 bit Mode
Reserved
0
0
0
0
0
0
0
0
0
0
0b
00h
00b
000b
1b
SYS_RST
TDO_SM Ctrl
Sync Bit Length
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
Default TDO Value
5
Debug Mode
0b
4
ScanBridge Support Initiate/ Release
0b
3
TRST
0b
2
Reset
0b
1:0
Test Loop-Back
11b
16/32 bit Mode
Selects 16-bit or 32-bit external interface mode
’1’
’0’
32-bit external interface mode (used in macro form only)
16-bit external interface mode
TDO_SM Control bits
<
>
TDO_SM Ctrl 11:10
’00’
Hold previous value
’01’
Default TDO Value
’10’
’11’
Default TDO Value
High impedance
Sync Bit Length "x"
Sync Bit Length bits represents the number of sync bits to be used when the Sync Bit
Support Enable bit (17 in the Macro Structure) is set. Where "x" is the binary encoded
numeric value.
Default TDO Value
The value in this register will be sent out on the TDO_SM pin when performing a BIST
or a STATE Macro.
’1’
Drive TDO_SM to one.
Drive TDO_SM to zero.
Control bit to put STA101 in debug mode
Debug mode.
’0’
Debug Mode
’1’
’0’
Normal mode.
ScanBridge Support
ScanBridge support enable
Initiate/Release
’1’
Enable ScanBridge support
’0’
Disable ScanBridge support
TRST
Processor initiated ScanMaster test reset (on TRST0_SM and TRST1_SM_N). Bit is
cleared by a processor write.
’1’
Set TRST outputs low (active) and reset SSI logic.
Set TRST outputs high
’0’
Reset
Processor commanded synchronous reset to the serial scan logic for 2 clocks. This bit
is self clearing.
’1’
’0’
Reset the entire chip.
Release serial scan logic reset
<
>
Test Loop-Back 1:0
Test loop-back mode bits
’00’
’01’
’10’
’11’
Normal operation
Loop-back TDO_SM to TDI_SM
Loop-back TMS_SM to TDI_SM
All Dot1 (1149.1) pins placed in SEU tolerant safe mode with: TMS_SM = 1, TCK_SM
= 0, TDO_SM = Z, TRST0_SM = 0
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Software Interface Details (Continued)
TABLE 24. Clock Divider Register (CLKDIV) ($05)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15:8
7:1
0
RO
RW
RO
Reserved
Divisor
0
0
0
00h
00h
0b
SYS_RST
Reserved (hard coded) (Note 23)
Note 23: LSB of the Clock Divider register is hard coded to zero.
<
>
Divisor 7:1
Clock divisor for the division of the SCK clock to the serial scan clock.
’0000000’
’0000001’
’0000010’
’0000100’
’0001000’
’0010000’
’0100000’
’1000000’
No serial scan clock generated.
Divide SCK by 2
Divide SCK by 4
Divide SCK by 8
Divide SCK by 16
Divide SCK by 32
Divide SCK by 64
Divide SCK by 128
TABLE 25. TDI_SM LFSR Exponent Register (EXPR) ($07)
Bit(s)
Type
Field
Address
Reset Value
Reset Source
Offset
15:3
2:0
RO
RW
Reserved
LFSR
0
0
0000h
000b
SYS_RST
<
>
LFSR Exponent 2:0
LFSR exponent. Binary encoding for the selection between three polynomials.
No polynomial selected
Polynomial 1: X32 + X7 + X5 + X3 + X2 + X + 1
Polynomial 2: X32 + X28 + X27 + X + 1
’000’
’001’
’010’
’011’
Polynomial 3: X32 + X7 + X6 + X2 + 1
TABLE 26. TDI_SM LFSR LSB Seed Register (LSSEDR) ($08) (Notes 24, 25)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
LSW LFSR Seed
0000h
SYS_RST
<
>
Note 24: LSW LFSR Seed 15:0 is the LS word of the LFSR seed.
Note 25: This register along with register MSSEDR form a register pair and should be read/written with two consecutive read/write accesses.
TABLE 27. TDI_SM LFSR MSB Seed Register (MSSEDR) ($09) (Notes 26, 27)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
MSW LFSR Seed
0000h
SYS_RST
<
>
Note 26: MSW LFSR Seed 15:0 is the MS word of the LFSR seed.
Note 27: This register along with register LSSEDR form a register pair and should be read/ written with two consecutive read/write accesses.
TABLE 28. TDI_SM LFSR LSB Result Register (LSRESR) ($0A) (Notes 28, 29)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
LSW LFSR Result
0000h
SYS_RST
<
>
Note 28: LSW LFSR Result 15:0 is the LS word of the LFSR result.
Note 29: This register along with register MSRESR form a register pair and should be read/written with two consecutive read/write accesses.
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28
Software Interface Details (Continued)
TABLE 29. TDI_SM LFSR MSB Result Register (MSRESR) ($0B) (Notes 30, 31)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
MSW LFSR Result
0000h
SYS_RST
<
>
Note 30: MSW LFSR Result 15:0 is the MS word of the LFSR result.
Note 31: This register along with register LSRESR form a register pair and should be read/ written with two consecutive read/write accesses.
TABLE 30. Index Register (INDEXR) ($0C) (Notes 32, 33, 34)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
Index
0000h
SYS_RST
<
>
Note 32: Index 15:0 sets the individual address memory pointer.
Note 33: Address memory pointer must be on a long word boundary.
Note 34: Writing to this register sets the TDO_SM, TDI_SM, Expected and Mask pointers. These pointers will automatically increment with each long word read from
the TDI_SM space and each long word write to the other TDO_SM, Expected and Mask spaces.
TABLE 31. Vector Index Register (VINDEXR) ($11) (Notes 35, 36)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
Vector Index
0000h
SYS_RST
<
>
Note 35: Vector Index 15:0 sets the Vector address memory pointer.
Note 36: Address memory pointer must be on a long word boundary.
TABLE 32. Header/Trailer Index Register (HTINDEXR) ($13) (Notes 37, 38)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
Header/Trailer Index
0000h
SYS_RST
<
>
Note 37: Header/Trailer Index 15:0 sets the Header/Trailer address memory pointer.
Note 38: Address memory pointer must be on a long word boundary.
TABLE 33. Macro Index Register (MINDEXR) ($15) (Notes 39, 40)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
Macro Index
0000h
SYS_RST
<
>
Note 39: Macro Index 15:0 sets the Macro address memory pointer.
Note 40: Address memory pointer must be on a long word boundary.
TABLE 34. Sequencer Index Register (SINDEXR) ($17) (Notes 41, 42)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
Sequencer Index
0000h
SYS_RST
<
>
Note 41: Sequencer Index 15:0 sets the Sequencer address memory pointer.
Note 42: Address memory pointer must be on a long word boundary.
TABLE 35. ScanBridge Support Index Register (BSINDEXR) ($19) (Notes 43, 44)
Bit(s)
Type
Field
Address
Offset
0
Reset Value
Reset Source
15:0
RW
ScanBridge Index
0000h
SYS_RST
<
>
Note 43: ScanBridge Index 15:0 sets the ScanBridge Support address memory pointer.
Note 44: Address memory pointer must be on a long word boundary.
29
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Testability Details - IEEE 1149.1 Support
An 8 instruction Tap Controller will be used to accomplish the
IEEE 1149.1 support design.
TABLE 36. Supported IEEE 1149.1 Instruction Set
Binary Instruction Code Description
Instruction Mnemonic
EXTEST
000
001
Allows off-chip circuitry and interconnect to be tested.
Allows snapshot of normal operation. Also allows data to be
loaded on parallel output boundary scan registers.
Places device in bypass mode so that there is single shift register
stage between TDI and TDO.
SAMPLE/PRELOAD
BYPASS
111
IDCODE
HIGHZ
010
011
100
Allows scanning of the device identification register.
Tristates all output drivers with the exception of TDO.
Allows the state of the signals driven from component pins to be
determined from the boundary-scan register while the BYPASS
register is selected as the serial path between TDI and TDO.
Enables on chip BIST logic to perform memory BIST.
Allows the assertion of internal test_mode signal to prevent the
asynchronous resets from inadvertantly resetting the flip-flops
during internal scan.
CLAMP
RUNBIST
110
101
SCANTEST
TABLE 37. IDCODE Register Description
Version
Part Number
"1111 1100 0001 0111"
Manufacturer Identity
Start Bit
"0000"
"000 0000 1111"
"1"
TABLE 38. Boundary Scan Register Definition
BSR
Bit#
0
Signal Name
BSR
Bit#
10
Signal Name
BSR
Bit#
20
Signal Name
BSR
Bit#
30
Signal Name
SCK
RST
DTACK
INT
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
TDO_SM
TMS_SM
TCK_SM
TRST0_SM
TDI_SM
OE
1
11
21
31
2
R/W
12
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
22
32
3
STB
13
23
33
4
CE
14
24
34
TRIST
5
ADDRESS[4]
ADDRESS[3]
ADDRESS[2]
ADDRESS[1]
ADDRESS[0]
15
25
6
16
26
7
17
27
8
18
28
9
19
29
BIST SUPPORT
SCAN METHODOLOGy
The memory BIST can be initiated through JTAG interface
using the RUNBIST instruction or by setting the Onboard
Memory BIST bit in the Start register. When the memory
BIST is initiated through the JTAG interface the result of
pass/fail will be set in the Memory BIST Result bit in the
Status register and also in the BIST status register that can
be accessed through the JTAG interface. The BIST status
register is a one bit register and is connected in the serial
path of TDO and TDI when RUNBIST instruction is scanned
into the instruction register. Once the BIST is done the
contents of the BIST status register can be scanned out to
determine whether the memory BIST passed or failed. If the
memory BIST is initiated through the Onboard Memory BIST
bit in the Start register the result of pass/fail will be set only
in the BIST Result bit in the status register. The memory
BIST will initialize the memory to zero.
The STA101 supports internal scan through the shared ports
SCAN_EN, SCAN_IN, SCAN_OUT. Before initiating an in-
ternal scan test the user should scan in SCANTEST instruc-
tion through the JTAG interface so that an internal test-
_mode signal can be asserted. This test_mode signal is
used to prevent the reset from inadvertantly resetting the
flip-flops during internal scan. The test vectors to verify the
scan chain are generated by the Sunrise test tool. The target
for the stuck-at fault coverage is 97% and the achieved fault
coverage is about 99%.
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30
Physical Dimensions inches (millimeters) unless otherwise noted
49-Pin BGA
NS Package Number SLC49A
Ordering Code SCANSTA101SM
(Tape and Reel Ordering Code SCANSTA101SMX)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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SCANSTA111MT/NOPB
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