TP3070AV-XX [NSC]
IC A/MU-LAW, PROGRAMMABLE CODEC, PQCC28, PLASTIC, CC-28, Codec;
| 型号： | TP3070AV-XX |
| 厂家： | 
National Semiconductor |
| 描述： | IC A/MU-LAW, PROGRAMMABLE CODEC, PQCC28, PLASTIC, CC-28, Codec 解码器 编解码器 PC |
| 文件： | 总26页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1994
TP3070, TP3071, TP3070-X
COMBO® II Programmable PCM CODEC/Filter
General Description
Features
n Complete CODEC and FILTER system including:
— Transmit and receive PCM channel filters
— µ-law or A-law companding encoder and decoder
— Receive power amplifier drives 300Ω
— 4.096 MHz serial PCM data (max)
n Programmable Functions:
The TP3070 and TP3071 are second-generation combined
PCM CODEC and Filter devices optimized for digital switch-
ing applications on subscriber line and trunk cards. Using
advanced switched capacitor techniques, COMBO II com-
bines transmit bandpass and receive lowpass channel filters
with a companding PCM encoder and decoder. The devices
are A-law and µ-law selectable and employ a conventional
serial PCM interface capable of being clocked up to
4.096 MHz. A number of programmable functions may be
controlled via a serial control port.
— Transmit gain: 25.4 dB range, 0.1 dB steps
— Receive gain: 25.4 dB range, 0.1 dB steps
— Hybrid balance cancellation filter
— Time-slot assignment; up to 64 slots/frame
— 2 port assignment (TP3070)
— 6 interface latches (TP3070)
— A or µ-law
— Analog loopback
— Digital loopback
n Direct interface to solid-state SLICs
n Simplifies transformer SLIC; single winding secondary
n Standard serial control interface
n 80 mW operating power (typ)
Channel gains are programmable over a 25.4 dB range in
each direction, and a programmable filter is included to en-
able Hybrid Balancing to be adjusted to suit a wide range of
loop impedance conditions. Both transformer and active
SLIC interface circuits with real or complex termination im-
pedances can be balanced by this filter, with cancellation in
excess of 30 dB being readily achievable when measured
across the passband against standard test termination net-
works.
To enable COMBO II to interface to the SLIC control leads, a
number of programmable latches are included; each may be
configured as either an input or an output. The TP3070 pro-
vides 6 latches and the TP3071 5 latches.
n 1.5 mW standby power (typ)
n Designed for CCITT and LSSGR applications
n TTL and CMOS compatible digital interfaces
n Extended temperature versions available for −40˚C to
+85˚C (TP3070V-X)
Note: See also AN-614, COMBO II application guide.
COMBO® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS008635
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Block Diagram
DS008635-1
FIGURE 1.
Connection Diagrams
DS008635-2
Order Number TP3071J
See NS Package Number J20A
Order Number TP3071N
DS008635-4
Order Number TP3070V
(0˚C to +70˚C)
See NS Package Number N20A
Order Number TP3070V-X
(−40˚C to +85˚C)
See NS Package Number V28A
Pin Descriptions
Pin
VCC
Description
+5V 5% power supply.
±
±
VBB
−5V 5% power supply.
GND
Ground. All analog and digital signals are
referenced to this pin.
FSX
Transmit Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
transmit time slot assigned to this device
(non-delayed data timing mode), or the start of
the transmit frame (delayed data timing mode
using the internal time-slot assignment
counter).
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2
Pin Descriptions (Continued)
Pin
Description
CI/O
This is the Control Data I/O pin which is
provided on the TP3071. Serial control
information is shifted to or read from COMBO
II on this pin when CS is low. The direction of
the data is determined by the current
instruction as defined in Table 1.
Pin
FSR
Description
Receive Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
receive time slot assigned to this device
(non-delayed data timing mode), or the start of
the receive frame (delayed data timing mode
using the internal time-slot assignment
counter).
CI
This is a separate Control Input, available only
on the TP3070. It can be connected to CO if
required.
CO
CS
This is a separate Control Output, available
only on the TP3070. It can be connected to CI
if required.
BCLK
MCLK
Bit clock input used to shift PCM data into and
out of the DR and DX pins. BCLK may vary
from 64 kHz to 4.096 MHz in 8 kHz
increments, and must be synchronous with
MCLK.
Chip Select input. When this pin is low, control
information can be written to or read from
COMBO II via the CI/O pin (or CI and CO).
Master clock input used by the switched
capacitor filters and the encoder and decoder
sequencing logic. Must be 512 kHz, 1.536
MHz, 1.544 MHz, 2.048 MHz or 4.096 MHz
and synchronous with BCLK.
IL5–IL0 IL5 through IL0 are available on the TP3070.
IL4 through IL0 are available on the TP3071.
Each Interface Latch I/O pin may be
individually programmed as an input or an
output determined by the state of the
corresponding bit in the Latch Direction
Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched
into the Interface Latch Register (ILR)
VFXI
The Transmit analog high-impedance input.
Voice frequency signals present on this input
are encoded as an A-law or µ-law PCM bit
stream and shifted out on the selected DX pin.
VFRO
The Receive analog power amplifier output,
capable of driving load impedances as low as
300Ω (depending on the peak overload level
required). PCM data received on the assigned
DR pin is decoded and appears at this output
as voice frequency signals.
whenever control data is written to COMBO II,
while CS is low, and the information is shifted
out on the CO (or CI/O) pin. When configured
as outputs, control data written into the ILR
appears at the corresponding IL pins.
MR
NC
This logic input must be pulled low for normal
operation of COMBO II. When pulled
momentarily high (at least 1 µsec.), all
programmable registers in the device are reset
to the states specified under “Power-On
Initialization”.
DX0
DX1
DX1 is available on the TP3070 only; DX0 is
available on all devices. These Transmit Data
TRI-STATE® outputs remain in the high
impedance state except during the assigned
transmit time slot on the assigned port, during
which the transmit PCM data byte is shifted
out on the rising edges of BCLK.
No Connection. Do not connect to this pin. Do
not route traces through this pin.
TSX0
TSX1
TSX1 is available on the TP3070 only; TSX0 is
available on all devices. Normally these
open-drain outputs are floating in a high
impedance state except when a time-slot is
active on one of the DX outputs, when the
appropriate TSX output pulls low to enable a
backplane line-driver.
Functional Description
POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry initial-
izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed to OFF (00000000), the hybrid
balance circuit is turned off, the power amp is disabled and
the device is in the non-delayed timing mode. The Latch Di-
rection Register (LDR) is pre-set with all IL pins programmed
as inputs, placing the SLIC interface pins in a high imped-
ance state. The CI/O pin is set as an input ready for the first
control byte of the initialization sequence. Other initial states
in the Control Register are indicated in Section 2.0.
DR0
DR1
DR1 is available on the TP3070 only; DR0 is
available on all devices. These receive data
inputs are inactive except during the assigned
receive time slot of the assigned port when
the receive PCM data is shifted in on the
falling edges of BCLK.
CCLK
Control Clock input. This clock shifts serial
control information into or out from CI/O or CI
and CO when the CS input is low, depending
on the current instruction. CCLK may be
asynchronous with the other system clocks.
A reset to these same initial conditions may also be forced by
driving the MR pin momentarily high. This may be done ei-
ther when powered-up or down. For normal operation this
pin must be pulled low. If not used, MR should be hard-wired
to ground.
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
3
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A decode cycle begins immediately after the assigned re-
ceive time-slot, and 10 µs later the Decoder DAC output is
updated. The total signal delay is 10 µs plus 120 µs (filter de-
Functional Description (Continued)
POWER-DOWN STATE
lay) plus 62.5 µs (1⁄
µs.
2
frame) which gives approximately 190
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in Table 1. It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the DX0 (and DX1) outputs are in the high
impedance TRI-STATE condition.
PCM INTERFACE
The FSX and FSR frame sync inputs determine the begin-
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of de-
vices (COMBO); time-slots begin nominally coincident with
the rising edge of the appropriate FS input. The alternative is
to use Delayed Data mode, which is similar to short-frame
sync timing on COMBO, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-slot. The
Time-Slot Assignment circuit on the device can only be used
with Delayed Data timing.
The coefficients stored in the Hybrid Balance circuit and the
Gain Control registers, the data in the LDR and ILR, and all
control bits remain unchanged in the power-down state un-
less changed by writing new data via the serial control port,
which remains active. The outputs of the Interface Latches
also remain active, maintaining the ability to monitor and
control the SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VFXI, is a high impedance sum-
ming input which is used as the differencing point for the in-
ternal hybrid balance cancellation signal. No external com-
ponents are necessary to set the gain. Following this circuit
is a programmable gain/attenuation amplifier which is con-
trolled by the contents of the Transmit Gain Register (see
Programmable Functions section). An active pre-filter then
precedes the 3rd order high-pass and 5th order low-pass
switched capacitor filters. The A/D converter has a com-
pressing characteristic according to the standard CCITT A or
µ255 coding laws, which must be selected by a control in-
struction during initialization (see Table 1 and Table 2). A pre-
cision on-chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage arising in the
gain-set amplifier, the filters or the comparator is canceled by
an internal auto-zero circuit.
When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter-
mined by the internal Time-Slot Assignment counters.
Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the selected D
X0/1 output shifts
data out from the PCM register on the rising edges of BCLK.
TSX0 (or TSX1 as appropriate) also pulls low for the first 71⁄
2
bit times of the time-slot to control the TRI-STATE Enable of
a backplane line-driver. Serial PCM data is shifted into the
selected DR0/1 input during each assigned Receive time-slot
on the falling edges of BCLK. DX0 or DX1 and DR0 or DR1
are selectable on the TP3070 only, see Section 6.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 µs (due to
the Transmit Filter) plus 125 µs (due to encoding delay),
which totals 290 µs. Data is shifted out on DX0 or DX1 during
the selected time slot on eight rising edges of BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive PCM Regis-
ter via the DR0 or DR1 pin during the selected time-slot on
the 8 falling edges of BCLK. The Decoder consists of an ex-
panding DAC with either A or µ255 law decoding character-
istic, which is selected by the same control instruction used
to select the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz sample and hold. A
programmable gain amplifier, which must be set by writing to
the Receive Gain Register, is included, and finally a Power
±
Amplifier capable of driving a 300Ω load to 3.5V, a 600Ω
±
±
load to 3.8V or a 15 kΩ load to 4.0V at peak overload.
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4
Functional Description (Continued)
TABLE 1. Programmable Register Instructions
Function
Byte 1 (Note 1)
Byte 2 (Note 1)
7
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
6
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
5
X
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
4
X
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
3
X
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
2
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
Single Byte Power-Up/Down
Write Control Register
None
See Table 2
See Table 2
See Table 4
See Table 4
See Table 3
See Table 3
See Table 8
See Table 8
See Table 7
See Table 7
See Table 6
See Table 6
See Table 6
See Table 6
Read-Back Control Register
Write to Interface Latch Register
Read Interface Latch Register
Write Latch Direction Register
Read Latch Direction Register
Write Receive Gain Register
Read Receive Gain Register
Write Transmit Gain Register
Read Transmit Gain Register
Write Receive Time-Slot/Port
Read-Back Receive Time-Slot/Port
Write Transmit Time-Slot/Port
Read-Back Transmit Time-Slot/Port
Write Hybrid Balance Register 1
Read Hybrid Balance Register 1
Write Hybrid Balance Register 2
Read Hybrid Balance Register 2
Write Hybrid Balance Register 3
Read Hybrid Balance Register 3
Derive from
Optimization
Routine in
TP3077SW
Program
=
Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CI/O pin. X don’t care.
=
=
Note 2: “P” is the power-up/down control bit, see “Power-Up/Down Control” section. (“0” Power Up, “1” Power Down)
Note 3: Other register address codes are invalid and should not be used.
SERIAL CONTROL PORT
strobed in while CS is low, as defined in Table 1. CS must be
kept low, or be taken low again for a further 8 CCLK cycles,
during which the data is shifted onto the CO or CI/O pin on
the rising edges of CCLK. When CS is high the CO or CI/O
pin is in the high-impedance TRI-STATE, enabling the CI/O
pins of many devices to be multiplexed together.
Control information and data are written into or read-back
from COMBO II via the serial control port consisting of the
control clock CCLK, the serial data input/output CI/O, (or
separate input, CI, and output, CO, on the TP3070 only), and
the Chip Select input, CS. All control instructions require 2
bytes, as listed in Table 1, with the exception of a single byte
power-up/down command. The byte 1 bits are used as fol-
lows: bit 7 specifies power up or power down; bits 6, 5, 4 and
3 specify the register address; bit 2 specifies whether the in-
struction is read or write; bit 1 specifies a one or two byte in-
struction; and bit 0 is not used.
If CS returns high during either byte 1 or byte 2 before all
eight CCLK pulses of that byte occur, both the bit count and
byte count are reset and register contents are not affected.
This prevents loss of synchronization in the control interface
as well as corruption of register data due to processor inter-
rupt or other problem. When CS returns low again, the de-
vice will be ready to accept bit 1 of byte 1 of a new instruc-
tion.
To shift control data into COMBO II, CCLK must be pulsed 8
times while CS is low. Data on the CI/O (or CI) input is
shifted into the serial input register on the falling edge of
each CCLK pulse. After all data is shifted in, the contents of
the input shift register are decoded, and may indicate that a
2nd byte of control data will follow. This second byte may ei-
ther be defined by a second byte-wide CS pulse or may fol-
low the first contiguously, i.e. it is not mandatory for CS to re-
turn high between the first and second control bytes. At the
end of CCLK8 in the 2nd control byte the data is loaded into
the appropriate programmable register. CS may remain low
continuously when programming successive registers, if de-
sired. However, CS should be set high when no data trans-
fers are in progress.
Programmable Functions
1.0 POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control in-
structions listed in Table 1 into COMBO II with the “P” bit set
to “0” for power-up or “1” for power-down. Normally it is rec-
ommended that all programmable functions be initially pro-
grammed while the device is powered down. Power state
control can then be included with the last programming in-
struction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the de-
To readback Interface Latch data or status information from
COMBO II, the first byte of the appropriate instruction is
5
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gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Hybrid balance must be disabled for meaningful analog loop-
back function.
Programmable Functions (Continued)
vice is powered-up or down by setting the “P” bit as indi-
cated. When the power-up or down control is entered as a
single byte instruction, bit one (1) must be reset to a 0.
2.4 Digital Loopback
When a power-up command is given, all de-activated circuits
are activated, but the TRI-STATE PCM output(s), DX0 (and
DX1), will remain in the high impedance state until the sec-
ond FSX pulse after power-up.
Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at DX0/1. In digital
loopback, the decoder will remain functional and output a
signal at VFRO. If this is undesirable, the receive output can
be turned off by programming the receive gain register to all
zeros.
2.0 CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to the Control
Register is as shown in Table 1. The second byte has the fol-
lowing bit functions:
TABLE 2. Control Register Byte 2 Functions
3.0 INTERFACE LATCH DIRECTIONS
Bit Number and Name
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3. For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3071, L5 should always
be programmed as an output.
7
6
5
4
3
2
1
0
Function
F
F
MA
IA DN DL AL PP
1
0
=
MCLK 512 kHz
0
0
0
1
=
MCLK 1.536
or 1.544 MHz
=
1
1
0
1
MCLK 2.048 MHz
(Note 4)
=
MCLK 4.096 MHz
Bits L5–L0 must be set by writing the specified instruction to
the LDR with the L bits in the second byte set as follows:
0
1
X
0
Select µ-255 law (Note 4)
A-law, Including Even
Bit Inversion
TABLE 3. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
1
1
0
1
A-law, No Even Bit Inversion
Delayed Data Timing
Non-Delayed Data
Timing (Note 4)
7
6
5
4
3
2
1
0
0
0
Normal Operation
(Note 4)
L0
L1
L2
L3
L4
L5
X
X
1
0
X
1
Digital Loopback
Ln Bit
IL Direction
Input
Analog Loopback
0
1
0
1
Power Amp Enabled in PDN
Output
Power Amp Disabled in
PDN (Note 4)
=
X
don’t care
=
Note 4: State at power-on initialization. (Bit 4 0)
INTERFACE LATCH STATES
2.1 Master Clock Frequency Selection
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4. Latches configured as inputs will sense
the state applied by an external source, such as the
Off-Hook detect output of a SLIC. All bits of the ILR, i.e.
sensed inputs and the programmed state of outputs, can be
read back in the 2nd byte of a READ from the ILR.
A Master clock must be provided to COMBO II for operation
of the filter and coding/decoding functions. The MCLK fre-
quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with
BCLK. Bits F1 and F0 (see Table 2) must be set during initial-
ization to select the correct internal divider.
2.2 Coding Law Selection
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first,
followed immediately by the Latch Direction Register.
Bits “MA” and “IA” in Table 2 permit the selection of µ255
coding or A-law coding, with or without even bit inversion.
2.3 Analog Loopback
TABLE 4. Interface Latch Data Bit Order
Bit Number
Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. In the
analog loopback mode, the Transmit input VFXI is isolated
from the input pin and internally connected to the VFRO out-
put, forming a loop from the Receive PCM Register back to
the Transmit PCM Register. The VFRO pin remains active,
and the programmed settings of the Transmit and Receive
7
6
5
4
3
2
1
0
D0
D1
D2
D3
D4
D5
X
X
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6
Programmable Functions (Continued)
TABLE 5. Coding Law Conventions
True A-law with
A-law without
µ255 law
MSB LSB
even bit inversion
even bit inversion
MSB
LSB
MSB
LSB
=
VIN +Full Scale
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
=
VIN 0V
=
VIN −Full Scale
Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.
TABLE 6. Time-Slot and Port Assignment Instruction
Bit Number and Name
Function
7
6
PS
5
T5
4
3
2
1
0
EN
T4
T3
T2
T1
T0
(Note 6)
0
(Note 7)
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
Disable DX0 Output (Transmit Instruction)
Disable DR0 Input (Receive Instruction)
Disable DX1 Output (Transmit Instruction)
Disable DR1 Input (Receive Instruction)
Enable DX0 Output (Transmit Instruction)
Enable DR0 Input (Receive Instruction)
Enable DX1 Output (Transmit Instruction)
Enable DR1 Input (Receive Instruction)
1
0
1
X
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Note 6: The “PS” bit MUST always be set to 0 for the TP3071.
Note 7: T5 is the MSB of the Time-slot assignment bit field. Time slot bits should be set to “000000” for both transmit and receive when operating in non-delayed
data timing mode.
5.0 TIME-SLOT ASSIGNMENT
Time-Slot Assignment mode requires that the FSX and FSR
pulses must conform to the delayed data timing format
shown in Figure 5.
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot al-
ways begins with the leading (rising) edge of frame sync in-
puts FSX and FSR. Time-Slot Assignment may only be used
with Delayed Data timing; see Figure 5. FSX and FSR may
have any phase relationship with each other in BCLK period
increments.
6.0 PORT SELECTION
On the TP3070 only, an additional capability is available; 2
Transmit serial PCM ports, DX0 and DX1, and 2 Receive se-
rial PCM ports, DR0 and DR1, are provided to enable
two-way space switching to be implemented. Port selections
for transmit and receive are made within the appropriate
time-slot assignment instruction using the “PS” bit in the sec-
ond byte. The PS bit selects either Port 0 or Port 1. Both
ports cannot be active at the same time.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6. The last 6 bits of the second byte indi-
cate the selected time-slot from 0–63 using straight binary
notation. When writing a timeslot and port assignment regis-
ter, if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign-
ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
register contents should not be performed during the talking
On the TP3071, only ports DX0 and DR0 are available, there-
fore the “PS” bit MUST always be set to 0 for these devices.
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
7.0 TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Table 1
and Table 7. This corresponds to a range of 0 dBm0 levels at
VFXI between 1.619 Vrms and 0.087 Vrms (equivalent to
+6.4 dBm to −19.0 dBm in 600Ω).
period of
a connection to prevent waveform distortion
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
caused by loss of a sample which will occur with each regis-
ter write. The “EN” bit allows the PCM inputs, DR0/1, or out-
puts, DX0/1, as appropriate, to be enabled or disabled.
200 x log10 (V/0.08595)
7
www.national.com
ator. Either of the filter sections can be bypassed if only one
is required to achieve good cancellation. A selectable 180
degree inverting stage is included to compensate for inter-
face circuits which also invert the transmit input relative to
the receive output signal. The 2nd order section is intended
mainly to balance low frequency signals across a trans-
former SLIC, and the first order section to balance midrange
to higher audio frequency signals.
Programmable Functions (Continued)
and convert to the binary equivalent. Some examples are
given in Table 7 and a complete tabulation is given in Appen-
dix I of AN-614.
It should be noted that the Transmit (idle channel) Noise and
Transmit Signal to Total Distortion are both specified with
transmit gain set to 0 dB (Gain Register set to all ones). At
high transmit gains there will be some degradation in noise
performance for these parameters. See Application Note
AN-614 for more information on this subject.
As a 2nd order section, Hybal1 has a pair of low frequency
zeroes and a pair of complex conjugate poles. When config-
uring Hybal1, matching the phase of the hybrid at low to
mid-band frequencies is most critical. Once the echo path is
correctly balanced in phase, the magnitude of the cancella-
tion signal can be corrected by the programmable attenua-
tor.
TABLE 7. Byte 2 of Transmit Gain Instruction
Bit Number
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
—
0 dBm0 Test Level (Vrms)
The 2nd order mode of Hybal1 is most suitable for balancing
interfaces with transformers having high inductance of 1.5
Henries or more. An alternative configuration for smaller
transformers is available by converting Hybal1 to a simple
first-order section with a single real low-frequency pole and
zero. In this mode, the pole/zero frequency may be pro-
grammed.
at VFXI
No Output (Note 8)
0.087
0.088
—
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
1.600
1.619
Many line interfaces can be adequately balanced by use of
the Hybal1 section only, in which case the Hybal2 filter
should be de-selected to bypass it.
Note 8: Analog signal path is cut off, but D remains active and will output
X
Hybal2, the higher frequency first-order section, is provided
for balancing an electronic SLIC, and is also helpful with a
transformer SLIC in providing additional phase correction for
mid and high-band frequencies, typically 1 kHz to 3.4 kHz.
Such a correction is particularly useful if the test balance im-
pedance includes a capacitor of 100 nF or less, such as the
loaded and non-loaded loop test networks in the United
States. Independent placement of the pole and zero location
is provided.
codes representing idle noise.
8.0 RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB steps by writ-
ing to the Receive Gain Register as defined in Table 1 and
Table 8. Note the following restrictions on output drive capa-
bility:
a) 0 dBm0 levels ≤ 1.96 Vrms at VFRO may be driven into
a load of ≥ 15 kΩ to GND; receive gain set to 0 dB (Gain
Register set to all ones)
Figure 2 shows a simplified diagram of the local echo path
for a typical application with a transformer interface. The
magnitude and phase of the local echo signal, measured at
VFXI, are a function of the termination impedance ZT, the line
transformer and the impedance of the 2W loop, ZL. If the im-
pedance reflected back into the transformer primary is ex-
pressed as ZL' then the echo path transfer function from
VFRO to VFXI is:
b) 0 dBm0 levels ≤ 1.85 Vrms at VFRO may be driven into
a load of ≥ 600Ω to GND; receive gain set to −0.5 dB
c) 0 dBm0 levels ≤ 1.71 Vrms at VFRO may be driven into
a load of ≥ 300Ω to GND; receive gain set to −1.2 dB
To calculate the binary code for byte 2 of this instruction for
any desired output 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
=
H(w) ZL'/(ZT + ZL')
(1)
200 x log10 (V/0.1043)
9.1 PROGRAMMING THE FILTER
and convert to the binary equivalent. Some examples are
given in Table 8 and a complete tabulation is given in Appen-
dix I of AN-614.
On initial power-up, the Hybrid Balance filter is disabled. Be-
fore the hybrid balance filter can be programmed it is neces-
sary to design the transformer and termination impedance in
order to meet system 2W input return loss specifications,
which are normally measured against a fixed test impedance
(600 or 900Ω in most countries). Only then can the echo
path be modeled and the hybrid balance filter programmed.
Hybrid balancing is also measured against a fixed test im-
pedance, specified by each national Telecom administration
to provide adequate control of talker and listener echo over
the majority of their network connections. This test imped-
ance is ZL in Figure 2. The echo signal and the degree of
transhybrid loss obtained by the programmable filter must be
measured from the PCM digital input, DR0, to the PCM digi-
tal output, DX0, either by digital test signal analysis or by
conversion back to analog by a PCM CODEC/Filter.
TABLE 8. Byte 2 of Receive Gain Instruction
Bit Number
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
—
0 dBm0 Test Level (Vrms)
at VFRO
No Output (Low Z to GND)
0.105
0.107
—
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
1.941
1.964
9.0 HYBRID BALANCE FILTER
The Hybrid Balance Filter on COMBO II is a programmable
filter consisting of a second-order section, Hybal1, followed
by a first-order section, Hybal2, and a programmable attenu-
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8
Programmable Functions (Continued)
DS008635-5
FIGURE 2. Simplified Diagram of Hybrid Balance Circuit
Three registers must be programmed in COMBO II to fully
configure the Hybrid Balance Filter as follows:
POWER SUPPLIES
While the pins of the TP3070 COMBO II devices are well
protected against electrical misuse, it is recommended that
the standard CMOS practice of applying GND to the device
before any other connections are made should always be
followed. In applications where the printed circuit card may
be plugged into a hot socket with power and clocks already
present, extra long pins on the connector should be used for
ground and VBB. In addition, a Schottky diode should be con-
nected between VBB and ground.
Register 1: select/de-select Hybrid Balance Filter;
invert/non-invert cancellation signal;
select/de-select Hybal2 filter section;
attenuator setting.
Register 2: select/de-select Hybal1 filter;
set Hybal1 to 2nd order or 1st order;
pole and zero frequency selection.
To minimize noise sources, all ground connections to each
device should meet at a common point as close as possible
to the device GND pin in order to prevent the interaction of
ground return currents flowing through a common bus im-
pedance. Power supply decoupling capacitors of 0.1 µF
should be connected from this common device ground point
to VCC and VBB as close to the device pins as possible. VCC
and VBB should also be decoupled with Low Effective Series
Resistance Capacitors of at least 10 µF located near the
card edge connector.
Register 3: program pole frequency in Hybal2 filter;
program zero frequency in Hybal2 filter.
Standard filter design techniques may be used to model the
echo path (see Equation (1)) and design a matching hybrid
balance filter configuration. Alternatively, the frequency re-
sponse of the echo path can be measured and the hybrid
balance filter designed to replicate it.
A Hybrid Balance filter design guide and software optimiza-
tion program are available under license from National Semi-
conductor Corporation; order TP3077SW.
Further guidelines on PCB layout techniques are provided in
™
Application Note AN-614, “ COMBO II Programmable PCM
CODEC/Filter Family Application Guide”.
Applications Information
Figure 3 shows a typical application of the TP3071 together
with a typical monolithic SLIC. Four of the IL latches are con-
figured as outputs to control the relay drivers on the SLIC,
while IL4 is an input for the Supervision signal.
9
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Applications Information (Continued)
DS008635-7
FIGURE 3. Typical Application with Monolithic SLIC
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10
Absolute Maximum Ratings (Note 9)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
VBB to GND
−65˚C to + 150˚C
−7V
±
Current at VFR0
100 mA
±
Current at any Digital Output
Lead Temperature
50 mA
300˚C
VCC to GND
7V
(Soldering, 10 sec.)
Voltage at VFXI
VCC + 0.5V to VBB − 0.5V
VCC + 0.5V to GND − 0.5V
Voltage at any Digital Input
Electrical Characteristics
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
=
=
=
specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol Parameter
DIGITAL INTERFACES
Conditions
Min
2.0
2.4
Typ
Max Units
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
All Digital Inputs (DC Meas.) (Note 10)
All Digital Inputs (DC Meas.) (Note 10)
0.7
0.4
V
V
V
VIH
VOL
=
DX0, DX1, TSX0, TSX1 and CO, IL 3.2 mA,
=
All Other Digital Outputs, IL 1 mA
=
VOH
Output High Voltage
DX0, DX1 and CO, IL −3.2 mA,
V
=
All Other Digital Outputs (except TSX), IL −1 mA
=
All Digital Outputs, IL −100 µA
VCC − 0.5
−10
V
<
<
IIL
Input Low Current
Input High Current
Any Digital Input, GND VIN VIL
10
10
µA
µA
µA
<
<
IIH
Any Digital Input except MR, VIH VIN VCC
−10
MR Only
−10
100
IOZ
Output Current in
High Impedance
State (TRI-STATE)
DX0, DX1, TSX0, TSX1, CO and CI/O (as an Output)
IL5–IL0 When Selected as Inputs
−10
10
30
µA
µA
<
<
GND VOUT VCC
−40˚C to +85˚C (TP3070-X)
−30
ANALOG INTERFACES
<
<
<
IVFXI
Input Current, VFXI
−3.3V VFXI 3.3V
−10.0
390
10.0
µA
kΩ
<
RVFXI
VOSX
Input Resistance
Input Offset Voltage
Applied at VFXI
−3.3V VFXI 3.3V
620
=
Transmit Gain 0 dB
200
10
mV
mV
=
Transmit Gain 25.4 dB
=
RLVFRO Load Resistance
Receive Gain 0 dB
15k
600
300
=
Receive Gain −0.5 dB
Ω
pF
Ω
=
Receive Gain −1.2 dB
CLVFRO Load Capacitance
ROVFRO Output Resistance
RLVFRO ≥ 300Ω
200
3.0
CLVFRO from VFRO to GND
Steady Zero PCM Code Applied to
DR0 or DR1
1.0
±
VOSR
Output Offset
Alternating Zero PCM Code Applied to
−200
200
mV
Voltage at VFRO
DR0 or DR1, Maximum Receive Gain
POWER DISSIPATION
=
=
I
CC0
Power Down Current
CCLK, CI/O, CI, CO, 0.4V, CS 2.4V
Interface Latches Set as Outputs with No Load,
All Other Inputs Active, Power Amp Disabled
As Above
0.1
0.6
mA
I
I
BB0
Power Down Current
Power Up Current
−0.1
−0.3
mA
mA
−40˚C to +85˚C (TP3070-X)
−0.4
=
=
CC1
CCLK, CI/O, CI, CO 0.4V, CS 2.4V
No Load on Power Amp
8.0
11.0
mA
mA
Interface Latches Set as Outputs with No Load
−40˚C to +85˚C (TP3070-X)
13.0
11
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Electrical Characteristics (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
=
=
=
specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol Parameter
POWER DISSIPATION
Conditions
Min
Typ
Max Units
I
I
I
BB1
CC2
BB2
Power Up Current
As Above
−8.0 −11.0
mA
mA
mA
mA
mA
mA
−40˚C to +85˚C (TP3070-X)
Power Amp Enabled
−13.0
Power Down Current
Power Down Current
2.0
3.0
4.0
−40˚C to +85˚C (TP3070-X)
Power Amp Enabled
−2.0
−3.0
−4.0
−40˚C to +85˚C (TP3070-X)
Note 9: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 10: See definitions and timing conventions section.
Timing Specifications
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%; VBB −5V 5%; TA 0˚C to
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
=
=
=
specified at VCC +5V, VBB −5V, TA 25˚C.
=
=
All timing parameters are measured at VOH 2.0V and VOL 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MASTER CLOCK TIMING
fMCLK
Frequency of MCLK
Selection of Frequency is
512
kHz
kHz
kHz
kHz
kHz
ns
Programmable (See Table 5)
1536
1544
2048
4096
tWMH
tWML
tRM
Period of MCLK High
Period of MCLK Low
Rise Time of MCLK
Fall Time of MCLK
Measured from VIH to VIH (Note 11)
Measured from VIL to VIL (Note 11)
Measured from VIL to VIH
Measured from VIH to VIL
TP3070 Only
80
80
ns
30
30
ns
tFM
ns
tHBM
HOLD Time, BCLK LOW
to MCLK HIGH
50
1
ns
tWFL
Period of FSX or FSR Low
Measured from VIL to VIL
MCLK Period
kHz
PCM INTERFACE TIMING
fBCLK
Frequency of BCLK
May Vary from 64 kHz to 4096 kHz
in 8 kHz Increments
64
4096
tWBH
tWBL
tRB
Period of BCLK High
Period of BCLK Low
Rise Time of BCLK
Fall Time of BCLK
Hold Time, BCLK Low
to FSX/R High or Low
Setup Time, FSX/R
High to BCLK Low
Delay Time, BCLK High
to Data Valid
Measured from VIH to VIH
Measured from VIL to VIL
Measured from VIL to VIH
Measured from VIH to VIL
80
80
ns
ns
ns
ns
ns
30
30
tFB
tHBF
30
30
tSFB
ns
=
tDBD
Load 100 pF Plus 2 LSTTL Loads
80
ns
ns
−40˚C to +85˚C (TP3070-X)
90
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12
Timing Specifications (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%; VBB −5V 5%; TA 0˚C to
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
=
=
=
specified at VCC +5V, VBB −5V, TA 25˚C.
=
=
All timing parameters are measured at VOH 2.0V and VOL 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PCM INTERFACE TIMING
tDBZ
Delay Time, BCLK Low to DX0/1 DX0/1 Disabled is measured at VOL
or VOH according to Figure 4 or
Figure 5
Disabled if FSX Low, FSX Low to
DX0/1 disabled if 8th BCLK
Low, or BCLK High to DX0/1
Disabled if FSX High
15
80
ns
−40˚C to +85˚C (TP3070-X)
15
100
60
ns
ns
=
Load 100 pF Plus 2 LSTTL Loads
tDBT
tZBT
tDFD
Delay Time, BCLK High to TSX
Low if FSX High, or FSX High to
TSX Low if BCLK High (Non
Delayed Mode); BCLK High to
TSX Low (Delayed Data Mode)
TRI-STATE Time, BCLK Low to
TSX High if FSX Low, FSX Low
to TSX High if 8th BCLK Low, or
BCLK High to TSX High if FSX
High
15
60
ns
=
Delay Time, FSX/R
High to Data Valid
Load 100 pF Plus 2 LSTTL Loads,
Applies if FSX/R Rises Later than
BCLK Rising Edge in Non-Delayed
Data Mode Only
80
ns
−40˚C to +85˚C (TP3070-X)
90
ns
ns
tSDB
Setup Time, DR0/1
Valid to BCLK Low
Hold Time, BCLK
Low to DR0/1 Invalid
30
tHBD
15
ns
ns
−40˚C to +85˚C (TP3070-X)
15
SERIAL CONTROL PORT TIMING
fCCLK
tWCH
tWCL
tRC
Frequency of CCLK
Period of CCLK High
Period of CCLK Low
Rise Time of CCLK
Fall Time of CCLK
Hold Time, CCLK Low
to CS Low
2048
kHz
ns
Measured from VIH to VIH
Measured from VIL to VIL
Measured from VIL to VIH
Measured from VIH to VIL
CCLK1
160
160
ns
50
50
ns
tFC
ns
tHCS
10
100
60
ns
tHSC
tSSC
tSSCO
tSDC
tHCD
tDCD
Hold Time, CCLK
CCLK 8
ns
ns
ns
ns
ns
Low to CS High
Setup Time, CS
Transition to CCLK Low
Setup Time, CS
50
Transition to CCLK High
Setup Time, CI (CI/O)
Data In to CCLK Low
Hold Time, CCLK
50
50
Low to CI/O Invalid
Delay Time, CCLK High
to CI/O Data Out Valid
=
Load 100 pF plus 2 LSTTL Loads
80
ns
ns
−40˚C to +85˚C (TP3070-X)
100
13
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Timing Specifications (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%; VBB −5V 5%; TA 0˚C to
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
=
=
=
specified at VCC +5V, VBB −5V, TA 25˚C.
=
=
All timing parameters are measured at VOH 2.0V and VOL 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
80
Units
SERIAL CONTROL PORT TIMING
tDSD
Delay Time, CS Low
to CO (CI/O) Valid
Applies Only if Separate
CS used for Byte 2
ns
−40˚C to +85˚C (TP3070-X)
100
80
ns
ns
tDDZ
Delay Time, CS or 9th CCLK
High to CO (CI/O) High
Impedance
Applies to Earlier of CS High or 9th
CCLK High
15
INTERFACE LATCH TIMING
tSLC
tHCL
tDCL
Setup Time, IL to
Interface Latch Inputs Only
100
ns
ns
ns
CCLK 8 of Byte 1
Hold Time, IL Valid from
8th CCLK Low (Byte 1)
Delay Time CCLK 8 of
Byte 2 to IL
50
Interface Latch Outputs Only
200
=
CL 50 pF
MASTER RESET PIN
tWMR
Duration of
1
µs
Master Reset High
±
Note 11: Applies only to MCLK Frequencies ≥ 1.536 MHz. At 512 kHz a 50:50 2% Duty Cycle must be used.
Timing Diagrams
DS008635-8
FIGURE 4. Non Delayed Data Timing Mode
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14
Timing Diagrams (Continued)
DS008635-9
FIGURE 5. Delayed Data Timing Mode
(Time Slot Zero Only)
15
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Timing Diagrams (Continued)
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16
Transmission Characteristics
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
=
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. f 1015.625 Hz, VFXI
=
0 dBm0, DR0 or DR1 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB
gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de-
=
=
=
sign and characterization. All signals referenced to GND. Typicals specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
The Maximum 0 dBm0 Levels are:
VFXI
1.619
1.964
Vrms
Vrms
VFRO (15 kΩ Load)
The Minimum 0 dBm0 Levels are:
VFXI
87.0
mVrms
mVrms
VFRO (Any Load ≥ 300Ω)
105.0
Overload Levels are 3.17 dBm0 (µLaw)
and 3.14 dBm0 (A-Law)
GXA
Transmit Gain
Transmit Gain Programmed for Maximum
0 dBm0 Test Level. (All 1’s in gain register)
Measure Deviation of Digital Code from
Ideal 0 dBm0 PCM Code at DX0/1.
Absolute Accuracy
=
TA 25˚C
−0.15
0.15
dB
=
=
=
GXAG
Transmit Gain
Variation with
TA 25˚C, VCC 5V, VBB 5V
Programmed Gain from 0 dB to 19 dB
(0 dBm0 Levels of 1.619 Vrms to
0.182 Vrms)
Programmed Gain
−0.1
−0.3
0.1
0.3
dB
dB
Programmed Gain from 19.1 dB to 25.4 dB
(0 dBm0 Levels of 0.180 Vrms to
0.087 Vrms)
±
Note: 0.1 dB min/max is available as a selected
part.
GXAF
Transmit Gain
Variation with
Frequency
Relative to 1015.625 Hz, (Note 15)
<
<
Minimum Gain GX Maximum Gain
=
=
=
=
=
f
f
f
f
f
60 Hz
−26
−0.1
0.15
0.0
dB
dB
dB
dB
dB
dB
200 Hz
−1.8
−0.15
−0.7
300 Hz to 3000 Hz
3400 Hz
4000 Hz
−14
−32
f ≥ 4600 Hz. Measure Response
at Alias Frequency from 0 kHz to 4 kHz.
=
=
GX 0 dB, VFXI 1.619 Vrms
Relative to 1015.625 Hz
=
=
=
=
=
=
=
=
f
f
f
f
f
f
f
f
62.5 Hz
−24.9
−0.1
0.15
0.15
0.15
0.15
0.0
dB
dB
dB
dB
dB
dB
dB
dB
203.125 Hz
343.75 Hz
−1.7
−0.15
−0.15
−0.15
−0.15
−0.74
515.625 Hz
2140.625 Hz
3156.25 Hz
3406.250 Hz
3984.375 Hz
−13.5
Relative to 1062.5 Hz (Note 15)
=
=
=
f
f
f
5250 Hz, Measure 2750 Hz
11750 Hz, Measure 3750 Hz
49750 Hz, Measure 1750 Hz
−32
−32
−32
dB
dB
dB
17
www.national.com
Transmission Characteristics (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
=
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. f 1015.625 Hz, VFXI
=
0 dBm0, DR0 or DR1 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB
gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de-
=
=
=
sign and characterization. All signals referenced to GND. Typicals specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
=
Measured Relative to GXA, VCC 5V,
GXAT
Transmit Gain
Variation with
Temperature
=
VBB −5V,
−0.1
0.1
dB
dB
<
<
Minimum gain GX Maximum Gain
−40˚C to +85˚C (TP3070-X)
Sinusoidal Test Method.
−0.15
0.15
GXAL
Transmit Gain
Variation with Signal
Level
=
Reference Level 0 dBm0.
=
VFXI −40 dBm0 to +3 dBm0
−0.2
−0.4
−1.2
0.2
0.4
1.2
dB
dB
dB
=
VFXI −50 dBm0 to −40 dBm0
=
VFXI −55 dBm0 to −50 dBm0
GRA
Receive Gain
Receive Gain Programmed for Maximum
0 dBm0 Test Level (All 1’s in
Absolute Accuracy
Gain Register). Apply 0 dBm0 PCM Code
to DR0 or DR1. Measure VFRO.
=
TA 25˚C
−0.15
0.15
dB
=
=
=
GRAG
Receive Gain
TA 25˚C, VCC 5V, VBB −5V
Programmed Gain from 0 dB to 19 dB
(0 dBm0 Levels of 1.964 Vrms to
0.220 Vrms)
Variation with
Programmed Gain
−0.1
−0.3
0.1
0.3
dB
dB
Programmed Gain from 19.1 dB to 25.4 dB
(0 dBm0 Levels of 0.218 Vrms to
0.105 Vrms)
±
Note: 0.1 dB min/max is available as a selected
part.
GRAT
Receive Gain
Measured Relative to GRA.
=
=
Variation with Temperature
VCC 5V, VBB −5V.
−0.1
0.1
dB
dB
<
<
Minimum Gain GR Maximum Gain
−40˚C to +85˚C (TP3070-X)
−0.15
0.15
GRAF
Receive Gain
Relative to 1015.625 Hz, (Note 15)
=
DR0 or DR1 0 dBm0 code.
Variation with Frequency
<
<
Minimum Gain GR Maximum Gain
=
=
=
=
f
f
f
f
200 Hz
−0.25
−0.15
−0.7
0.15
0.15
0.0
dB
dB
dB
dB
300 Hz to 3000 Hz
3400 Hz
4000 Hz
−14
=
=
GR 0 dB, DR0 0 dBm0 Code,
=
GX 0 dB (Note 15)
=
=
=
=
=
=
f
f
f
f
f
f
296.875 Hz
1875.00 Hz
2906.25 Hz
2984.375 Hz
3406.250 Hz
3984.375 Hz
−0.15
−0.15
−0.15
−0.15
−0.74
0.15
0.15
0.15
0.15
0.0
dB
dB
dB
dB
dB
dB
−13.5
www.national.com
18
Transmission Characteristics (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
=
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. f 1015.625 Hz, VFXI
=
0 dBm0, DR0 or DR1 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB
gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de-
=
=
=
sign and characterization. All signals referenced to GND. Typicals specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
GRAL
Receive Gain
Variation with Signal
Level
Sinusoidal Test Method.
=
Reference Level 0 dBm0.
=
DR0 −40 dBm0 to +3 dBm0
−0.2
−0.4
−1.2
0.2
0.4
1.2
dB
dB
dB
=
DR0 −50 dBm0 to −40 dBm0
=
DR0 −55 dBm0 to − 50 dBm0
=
DR0 3.1 dBm0
=
=
RL 600Ω, GR −0.5 dB
−0.2
0.2
dB
dB
=
=
RL 300Ω, GR −1.2 dB
−0.2
0.2
ENVELOPE DELAY DISTORTION WITH FREQUENCY
=
=
=
=
=
=
=
=
=
=
=
=
=
=
DXA
DXR
Tx Delay, Absolute
f
f
f
f
f
f
f
f
f
f
f
f
f
f
1600 Hz
315
220
145
75
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Tx Delay, Relative to DXA
500–600 Hz
600–800 Hz
800–1000 Hz
1000–1600 Hz
1600–2600 Hz
2600–2800 Hz
2800–3000 Hz
1600 Hz
40
75
105
155
200
DRA
DRR
Rx Delay, Absolute
Rx Delay, Relative to DRA
500–1000 Hz
1000–1600 Hz
1600–2600 Hz
2600–2800 Hz
2800–3000 Hz
−40
−30
90
125
175
NOISE
NXC
Transmit Noise, C Message
Weighted, µ-law Selected
Transmit Noise, P Message
Weighted, A-law Selected
Receive Noise, C Message
Weighted, µ-law Selected
Receive Noise, P Message
Weighted, A-law Selected
Noise, Single Frequency
(Note 12)
12
−74
8
15
−67
11
dBrnC0
dBm0p
dBrnC0
dBm0p
dBm0
All ‘1’s in Gain Register
(Note 12)
NXP
NRC
NRP
NRS
All ‘1’s in Gain Register
PCM Code is Alternating Positive
and Negative Zero
PCM Code Equals Positive Zero
−82
−79
−53
=
f
0 kHz to 100 kHz, Loop Around
=
Measurement, VFXI 0 Vrms
=
VCC 5.0 VDC + 100 mVrms
PPSRX Positive Power Supply
Rejection, Transmit
=
=
f
f
0 kHz–4 kHz (Note 13)
4 kHz–50 kHz
36
dBC
dBC
30
=
VBB −5.0 VDC + 100 mVrms
NPSRX Negative Power Supply
Rejection, Transmit
=
=
f
f
0 kHz–4 kHz (Note 13)
4 kHz–50 kHz
36
dBC
dBC
30
19
www.national.com
Transmission Characteristics (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
=
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. f 1015.625 Hz, VFXI
=
0 dBm0, DR0 or DR1 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB
gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de-
=
=
=
sign and characterization. All signals referenced to GND. Typicals specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol
NOISE
Parameter
Conditions
Min
Typ
Max
Units
PPSRR Positive Power Supply
Rejection, Receive
PCM Code Equals Positive Zero
=
VCC 5.0 VDC + 100 mVrms
Measure VFRO
=
=
=
f
f
f
0 Hz–4000 Hz
4 kHz–25 kHz
25 kHz–50 kHz
36
40
36
dBC
dB
dB
NPSRR Negative Power Supply
Rejection, Receive
PCM Code Equals Positive Zero
=
VBB −5.0 VDC + 100 mVrms
Measure VFRO
=
=
=
f
f
f
0 Hz–4000 Hz
4 kHz–25kHz
25 kHz–50 kHz
36
40
36
dBC
dB
dB
SOS
Spurious Out-of-Band
Signals at the Channel
Output
0 dBm0, 300 Hz to 3400 Hz Input PCM
Code Applied at DR0 (or DR1)
4600 Hz–7600 Hz
−30
−40
−30
dB
dB
dB
7600 Hz–8400 Hz
8400 Hz–50,000 Hz
DISTORTION
STDX
STDR
Signal to Total Distortion
Sinusoidal Test Method
=
Transmit or Receive
Level 3.0 dBm0
33
36
30
25
dBC
dBC
dBC
dBC
=
=
=
Half-Channel, µ-law Selected
0 dBm0 to − 30 dBm0
−40 dBm0
−45 dBm0
STDRL
Signal to Total Distortion
Receive with
Sinusoidal Test Method
=
Level +3.1 dBm0
=
=
Resistive Load
RL 600Ω, GR −0.5 dB
33
dBC
dBC
dB
=
=
RL 300Ω, GR −1.2 dB
33
SFDX
SFDR
IMD
Single Frequency
−46
−46
Distortion, Transmit
Single Frequency
dB
dB
Distortion, Receive
Intermodulation Distortion
Transmit or Receive
Two Frequencies in the Range
300 Hz–3400 Hz
−41
www.national.com
20
Transmission Characteristics (Continued)
=
=
=
±
±
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC +5V 5%, VBB −5V 5%; TA 0˚C to
=
=
=
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA 25˚C. f 1015.625 Hz, VFXI
=
0 dBm0, DR0 or DR1 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB
gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de-
=
=
=
sign and characterization. All signals referenced to GND. Typicals specified at VCC +5V, VBB −5V, TA 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CROSSTALK
=
300 Hz–3400 Hz
CTX-R
Transmit to Receive
Crosstalk, 0 dBm0 Transmit
Level
f
−90
−75
dB
=
DR Idle Code
=
CTR-X
Receive to Transmit
Crosstalk, 0 dBm0 Receive
Level
f
300 Hz–3400 Hz
−90
−70
dB
(Note 13)
Note 12: Measured by grounded input at VF I.
X
Note 13: PPSR , NPSR , and CT
R–X
are measured with a −50 dBm0 activation signal applied to VF I.
X
X
X
Note 14: A signal is Valid if it is above V or below V and Invalid if it is between V and V . For the purposes of this specification the following conditions apply:
IH
=
IL
=
IL
<
10 ns.
IH
<
10 ns, t
F
a) All input signals are defined as: V
IL
0.4V, V
IH
2.7V, t
R
b) t is measured from V to V . t is measured from V to V
.
R
IL IH IH IL
F
c) Delay Times are measured from the input signal Valid to the output signal Valid.
d) Setup Times are measured from the data input Valid to the clock input Invalid.
e) Hold Times are measured from the clock signal Valid to the data input Invalid.
f) Pulse widths are measured from V to V or from V to V
.
IH
IL
IL
IH
Note 15: A multi-tone test technique is used.
21
www.national.com
Definitions and Timing Conventions
DEFINITIONS
pulse widths are measured from VIH to
VIH
Pulse Width Low The low pulse width is designated as
tWzzL where zz represents the mne-
.
VIH
VIH is the D.C. input level above which
an input level is guaranteed to appear as
a logical one. This parameter is to be
,
measured by performing
a
functional
monic of the input or output signal whose
pulse width is being specified. Low pulse
test at reduced clock speeds and nomi-
nal timing, (i.e., not minimum setup and
hold times or output strobes), with the
high level of all driving signals set to VIH
and maximum supply voltages applied
to the device.
widths are measured from VIL to VIL
.
Setup Time
Hold Time
Delay Time
Setup times are designated as tSwwxx
,
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or strobe
input represented by mnemonic xx.
Setup times are measured from the ww
Valid to xx Invalid.
VIL
VIL is the D.C. input level below which
an input level is guaranteed to appear as
a logical zero to the device. This param-
eter is measured in the same manner as
VIH but with all driving signal low levels
set to VIL and minimum supply voltages
applied to the device.
Hold times are designated as THwwxx
,
where ww represents the mnemonic of
the input signal whose hold time is being
specified relative to a clock or strobe in-
put represented by the mnemonic xx.
Hold times are measured from xx Valid
to ww Invalid.
VOH
VOH is the minimum D.C. output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
Delay times are designated as
VOL
VOL is the maximum D.C. output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
TDxxyy[ IHIL], where xx represents the
mnemonic of the input reference signal
and yy represents the mnemonic of the
output signal whose timing is being
specified relative to xx. The mnemonic
may optionally be terminated by an H or
L to specify the high going or low going
transition of the output signal. Maximum
delay times are measured from xx Valid
to yy Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the load
conditions specified in the Conditions
column of the Timing Specifications sec-
tion of this datasheet.
Threshold Region The threshold region is the range of in-
put voltages between VIL and VIH
.
Valid Signal
A signal is Valid if it is in one of the valid
logic states. (i.e., above VIH or below
V
IL). In timing specifications, a signal is
deemed valid at the instant it enters a
valid state.
Invalid signal
A signal is invalid if it is not in a valid
logic state, i.e., when it is in the thresh-
old region between VIL and VIH. In timing
specifications, a signal is deemed In-
valid at the instant it enters the threshold
region.
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply.
Input Signals
All input signals may be characterized
=
=
<
<
as: VL 0.4V, VH 2.4V, tR 10 ns, tF
10 ns.
Period
The period of the clock signal is desig-
nated as tPxx where represents the
xx
mnemonic of the clock signal being
specified.
Rise Time
Fall Time
Rise times are designated as tRyy, where
yy represents a mnemonic of the signal
whose rise time is being specified. tRyy is
measured from VIL to VIH
.
Fall times are designated as tFyy, where
yy represents a mnemonic of the signal
whose fall time is being specified. tFyy is
measured from VIH to VIL
.
Pulse Width High The high pulse width width is designated
as tWzzH, where zz represents the mne-
monic of the input or output signal whose
pulse width is being specified. High
www.national.com
22
23
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number TP3071J
NS Package Number J20A
Ceramic Dual-In-Line Package (J)
Order Number TP3070J
NS Package Number J28A
www.national.com
24
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3071N
NS Package Number N20A
25
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number TP3070V or TP3070V-X
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
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Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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