GE28F320W30TD70 [NUMONYX]
Flash, 2MX16, 70ns, PBGA56, 0.75 MM PITCH, VFBGA-56;
| 型号： | GE28F320W30TD70 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 2MX16, 70ns, PBGA56, 0.75 MM PITCH, VFBGA-56 内存集成电路 闪存 |
| 文件： | 总104页 (文件大小：1443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Wireless Flash Memory (W30)
28F640W30, 28F320W30, 28F128W30
Datasheet
Product Features
■ High Performance Read-While-Write/Erase
— Burst Frequency at 40 MHz
— 70 ns Initial Access Speed
■ Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Top or Bottom Parameter Blocks
■ Flash Security
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Speed
— Burst-Mode and Page-Mode in All Blocks
and across All Partition Boundaries
— Burst Suspend Feature
— 128-bit Protection Register: 64 Unique
Device Identifier Bits; 64 User OTP
Protection Register Bits
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
■ Flash Power
— Absolute Write Protection with V at
PP
Ground
— V = 1.70 V – 1.90 V
— Program and Erase Lockout during Power
CC
— V
= 2.20 V – 3.30 V
Transitions
CCQ
— Standby Current (130 nm) = 8 µA (typ.)
— Read Current = 7 mA
— Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
■ Density and Packaging
(4 word burst, typical)
■ Flash Software
— 130 nm: 32Mb, 64Mb, and 128Mb in VF
BGA Package; 64Mb, 128Mb in QUAD+
Package
— 180 nm: 32Mb and 128Mb Densities in VF
BGA Package; 64Mb Density in µBGA*
Package
— 5 µs/9 µs (typ.) Program/Erase Suspend
Latency Time
— Intel® Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
■ Quality and Reliability
— Operating Temperature:
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
–40 °C to +85 °C
— 16-bit Data Bus
— 100K Minimum Erase Cycles
— 130 nm ETOX™ VIII Process
— 180 nm ETOX™ VII Process
The Intel® Wireless Flash Memory (W30) device combines state-of-the-art Intel® Flash technology to
provide a versatile memory solution for high performance, low power, board constraint memory
applications. The W30 flash memory device offers a multi-partition, dual-operation flash architecture
that enables the flash device to read from one partition while programming or erasing in another partition.
This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data
throughput rates compared to single partition devices. Two processors can interleave code execution,
because program and erase operations can now occur as background processes.
The W30 flash memory device incorporates an Enhanced Factory Programming (EFP) mode to improve
12 V factory programming performance. This feature helps eliminate manufacturing bottlenecks associated
with programming high-density flash memory devices. The EFP program time is 3.5 µs per word,
compared to the standard factory program time of 8.0 µs per word, so EFP mode saves significant factory
programming time for improved factory efficiency.
The W30 flash memory device also includes block lock-down and programmable WAIT signal polarity,
and is supported by an array of software tools.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
Order Number: 290702, Revision: 011
June 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Wireless Flash Memory (W30) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, ETOX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.All rights reserved.
June 2005
2
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Contents
1.0 Introduction ...............................................................................................................................8
1.1
1.2
1.3
Document Purpose ...............................................................................................................8
Nomenclature .......................................................................................................................8
Conventions..........................................................................................................................9
2.0 Functional Overview ............................................................................................................10
2.1
2.2
Overview.............................................................................................................................10
Memory Map and Partitioning.............................................................................................11
3.0 Package Information............................................................................................................14
3.1
3.2
W30 Flash Memory Device – 130 nm Lithography.............................................................14
W30 Flash Memory Device – 180 nm Lithography.............................................................16
4.0 Ballout and Signal Descriptions......................................................................................19
4.1
4.2
Signal Ballout......................................................................................................................19
Signal Descriptions .............................................................................................................21
5.0 Maximum Ratings and Operating Conditions ...........................................................25
5.1
5.2
Absolute Maximum Ratings................................................................................................25
Operating Conditions..........................................................................................................26
6.0 Electrical Specifications.....................................................................................................27
6.1
6.2
DC Current Characteristics.................................................................................................27
DC Voltage Characteristics.................................................................................................28
7.0 AC Characteristics................................................................................................................29
7.1
7.2
7.3
7.4
Read Operations - 130 nm Lithography..............................................................................29
Read Operations - 180 nm Lithography..............................................................................30
AC Write Characteristics.....................................................................................................40
Erase and Program Times..................................................................................................44
8.0 Power and Reset Specifications .....................................................................................45
8.1
8.2
8.3
8.4
Active Power.......................................................................................................................45
Automatic Power Savings (APS) ........................................................................................45
Standby Power ...................................................................................................................45
Power-Up/Down Characteristics.........................................................................................46
8.4.1 System Reset and RST# .......................................................................................46
8.4.2 VCC, VPP, and RST# Transitions .........................................................................46
Power Supply Decoupling...................................................................................................46
Reset Specifications ...........................................................................................................47
AC I/O Test Conditions.......................................................................................................48
Flash Device Capacitance ..................................................................................................49
8.5
8.6
8.7
8.8
9.0 Flash Device Operations ....................................................................................................50
9.1
Bus Operations...................................................................................................................50
9.1.1 Read ......................................................................................................................50
9.1.2 Burst Suspend .......................................................................................................51
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
3
28F640W30, 28F320W30, 28F128W30
9.1.3 Standby..................................................................................................................51
9.1.4 Reset .....................................................................................................................52
9.1.5 Write ......................................................................................................................52
Flash Device Commands....................................................................................................52
Command Sequencing.......................................................................................................56
9.2
9.3
10.0 Read Operations....................................................................................................................57
10.1 Read Array..........................................................................................................................57
10.2 Read Device ID...................................................................................................................57
10.3 Read Query (CFI) ...............................................................................................................58
10.4 Read Status Register..........................................................................................................58
10.5 Clear Status Register..........................................................................................................60
11.0 Program Operations.............................................................................................................61
11.1 Word Program ....................................................................................................................61
11.2 Factory Programming.........................................................................................................63
11.3 Enhanced Factory Program (EFP) .....................................................................................63
11.3.1 EFP Requirements and Considerations ................................................................64
11.3.2 Setup .....................................................................................................................64
11.3.3 Program.................................................................................................................64
11.3.4 Verify......................................................................................................................65
11.3.5 Exit.........................................................................................................................65
12.0 Program and Erase Operations.......................................................................................67
12.1 Program/Erase Suspend and Resume...............................................................................67
12.2 Block Erase.........................................................................................................................70
12.3 Read-While-Write and Read-While-Erase..........................................................................72
13.0 Security Modes.......................................................................................................................73
13.1 Block Lock Operations........................................................................................................73
13.1.1 Lock.......................................................................................................................74
13.1.2 Unlock....................................................................................................................74
13.1.3 Lock-Down.............................................................................................................75
13.1.4 Block Lock Status..................................................................................................75
13.1.5 Lock During Erase Suspend..................................................................................76
13.1.6 Status Register Error Checking .............................................................................76
13.1.7 WP# Lock-Down Control .......................................................................................76
13.2 Protection Register.............................................................................................................77
13.2.1 Reading the Protection Register............................................................................78
13.2.2 Programing the Protection Register.......................................................................78
13.2.3 Locking the Protection Register.............................................................................78
13.3 VPP Protection ...................................................................................................................80
14.0 Set Read Configuration Register....................................................................................81
14.1 Read Mode (RCR[15])........................................................................................................ 83
14.2 First Access Latency Count (RCR[13:11])..........................................................................83
14.2.1 Latency Count Settings..........................................................................................84
14.3 WAIT Signal Polarity (RCR[10])..........................................................................................85
14.4 WAIT Signal Function.........................................................................................................85
14.5 Data Hold (RCR[9]).............................................................................................................86
14.6 WAIT Delay (RCR[8]) .........................................................................................................87
June 2005
4
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
14.7 Burst Sequence (RCR[7])...................................................................................................87
14.8 Clock Edge (RCR[6]) ..........................................................................................................88
14.9 Burst Wrap (RCR[3])...........................................................................................................89
14.10 Burst Length (RCR[2:0]) .....................................................................................................89
Appendix A Write State Machine...........................................................................................90
Appendix B Common Flash Interface..................................................................................93
Appendix C Ordering Information.......................................................................................103
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
5
28F640W30, 28F320W30, 28F128W30
Revision History
Date of
Version
Revision
Description
09/19/00
-001
Initial release
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2, Signal Descriptions (DQ15–0, ADV#, WAIT, S-UB#, S-LB#, VCCQ
Revised Section 3.1, Bus Operations
)
Revised Table 5, Command Bus Definitions, Notes 1 and 2
Revised Section 4.2.2, First Latency Count (LC2–0); revised Figure 6, Data Output
with LC Setting at Code 3; added Figure 7, First Access Latency Configuration
Revised Section 4.2.3, WAIT Signal Polarity (WT)
Added Section 4.2.4, WAIT Signal Function
Revised Section 4.2.5, Data Output Configuration (DOC)
Added Figure 8, Data Output Configuration with WAIT Signal Delay
Revised Table 13, Status Register DWS and PWS Description
Revised entire Section 5.0, Program and Erase Voltages
Revised entire Section 5.3, Enhanced Factory Programming (EFP)
Revised entire Section 8.0, Flash Security Modes
03/14/01
-002
Revised entire Section 9.0, Flash Protection Register; added Table 15,
Simultaneous Operations Allowed with the Protection Register
Revised Section 10.1, Power-Up/Down Characteristics
Revised Section 11.3, DC Characteristics. Changed ICCS, CCWS, ICCES Specs from
I
18 µA to 21µA; changed ICCR Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation
Waveform
Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23, Write Waveform
Revised Section 12.4, Reset Operations
Clarified Section 13.2, SRAM Write Operation, Note 2
Revised Section 14.0, Ordering Information
Minor text edits
Deleted SRAM Section
Added 128M DC and AC Specifications
Added Burst Suspend
04/05/02
-003
Added Read While Write Transition Waveforms
Various text edits
Revised Device ID
Revised Write Speed Bin
Various text edits
04/24/02
10/20/02
-004
-005
Added Latency Count Tables
Updated Packing Ball-Out and Dimension
Various text edits
Minor text clarifications
June 2005
6
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Date of
Revision
Version
Description
Revised Table 20, DC Current Characteristics, ICCS
Revised Table 20, DC Current Characteristics, ICCAPS
Removed Intel Burst order
01/14/03
-006
Minor text edits
Updated Package Drawing and Dimensions
Revised Table 22, Read Operations, tAPA
03/22/03
11/17/03
-007
-008
Added note to table 15, Configuration Register Descriptions
Added note to section 3.1.1, Read
Updated Block Lock Operations (Sect. 7.1 and Fig. 11)
Updated improved AC timings
Added QUAD+ package option, and Appendix D
Minor text edits including new product-naming conventions
Corrected Absolute Maximum Rating for VCCQ (Sect. 10.1, Table 18)
Minor text edits
05/06/04
05/17/04
-009
-010
Restructured the datasheet according to new layout.
Timing Diagram Nomenclature Synergy with other product families
Added Ordering information
06/2005
-011
Minor Text Edits
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
7
28F640W30, 28F320W30, 28F128W30
1.0
Introduction
1.1
Document Purpose
This datasheet contains information about the Intel® Wireless Flash Memory (W30) device family.
Throughout this document, this device family is referred to as the W30 flash memory device.
• This chapter provides a flash memory overview.
• Chapter 2.0 through Chapter 8.0 describe the memory functionality.
• Chapter 6.0 describes the electrical specifications for extended temperature product offerings.
• Appendix A describes the Write State Machine (WSM),
• Appendix B describes the Intel® Common Flash Interface (CFI) as it applies to the W30 flash
memory device.
• Appendix C provides ordering information for the Intel® Wireless Flash Memory (W30)
device family.
1.2
Nomenclature
Acronyms that describe product features or usage are defined here:
• APS - Automatic Power Savings
• BBA - Block Base Address
• CFI - Common Flash Interface
• CUI - Command User Interface
• DU - Do not Use
• EFP - Enhanced Factory Programming
• FDI - Flash Data Integrator
• NC - No Connect
• OTP - One-Time Programmable
• PBA - Partition Base Address
• RCR - Read Configuration Register
• RWE - Read-While-Erase
• RWW - Read-While-Write
• SCSP - Stacked Chip Scale Package
• SRD - Status Register Data
• VF BGA - Very-thin, Fine-pitch, Ball Grid Array
• WSM - Write State Machine
June 2005
8
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
1.3
Conventions
The following abbreviated terms and phrases are used throughout this document:
• 1.8 V refers to the V operating voltage range of 1.7 V – 1.9 V (except where noted).
CC
• 3.0 V refers to the V
operating voltage range of 2.2 V - 3.3 V.
CCQ
• V = 12 V refers to 12 V ± 5%.
PP
• When referring to registers, the term set means the bit is a logical 1, and cleared means the bit
is a logical 0.
• The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package. (Ball is the term used for BGA).
• A word is 2 bytes, or 16 bits.
• Signal names are in all CAPS (for example, WAIT).
• Voltage applied to the signal is subscripted (for example, V ).
PP
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
• A block is a group of bits (or words) that erase simultaneously with one block erase
instruction.
• A main block contains 32 Kwords.
• A parameter block contains 4 Kwords.
• The Block Base Address (BBA) is the first address of a block.
• A partition is a group of blocks that share erase and program circuitry and a common status
register.
• The Partition Base Address (PBA) is the first address of a partition. For example, on a
32-Mbit top-parameter flash device, partition number 5 has a PBA of 0x140000.
• The top partition is located at the highest physical flash device address. This partition can be
a main partition or a parameter partition.
• The bottom partition is located at the lowest physical flash device address. This partition can
be a main partition or a parameter partition.
• A main partition contains only main blocks.
• A parameter partition contains a mixture of main blocks and parameter blocks.
• A top parameter device (TPD) has the parameter partition at the top of the memory map with
the parameter blocks at the top of that partition. This flash device type was formerly referred to
as a top-boot flash device.
• A bottom parameter device (BPD) has the parameter partition at the bottom of the memory
map with the parameter blocks at the bottom of that partition. This flash device type was
formerly referred to as a bottom-boot block flash device.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
9
28F640W30, 28F320W30, 28F128W30
2.0
Functional Overview
This section provides an overview of the W30 flash memory device features and architecture.
2.1
Overview
The W30 flash memory device provides Read-While-Write (RWW) and Read-White-Erase (RWE)
capability. This capability provides high-performance synchronous and asynchronous reads in
package-compatible densities using a 16-bit data bus. Individually-erasable memory blocks are
optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the
parameter partition at either the top or bottom of the memory map. The rest of the memory array is
grouped into 32-Kword main blocks.
The memory architecture for the W30 flash memory device consists of multiple 4-Mbit partitions,
the exact number depending on the flash device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read operations. Burst
reads can traverse partition boundaries, but user application code is responsible for ensuring that
burst reads do not extend into a partition that is actively programming or erasing. Although each
partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or
erase in one partition while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of the W30 flash
memory device. An erase can be suspended to perform a program or read operation within any
block, except a block that is erase-suspended. A program operation nested within a suspended
erase can subsequently be suspended to read yet another memory location.
After power-up or reset, the W30 flash memory device defaults to asynchronous read
configuration. Writing to the flash memory device Read Configuration Register (RCR) enables
synchronous burst-mode read operation. In synchronous mode, the CLK input increments an
internal burst address generator. CLK also synchronizes the flash memory device with the host
CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A
programmable WAIT output signals to the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the W30 flash memory device incorporates
Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power
designs. The EFP feature provides fast program performance, which can increase the
manufacturing throughput of a factory.
The W30 flash memory device supports read operations at 1.8 V and erase and program operations
at 1.8 V or 12 V. With the 1.8-V option, VCC and VPP can be tied together for an ultra-low-power
design. In addition to voltage flexibility, the dedicated VPP input provides extensive data
protection when V < V
.
PP
PPLK
A 128-bit protection register can implement new security techniques and data protection schemes:
• A combination of factory-programmed and user-OTP data cells provide unique flash device
identification, help implement fraud or cloning prevention schemes, or help protect content.
• Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data.
• An additional block lock-down capability provides hardware protection where software
commands alone cannot change the block protection status.
June 2005
10
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
The flash device Command User Interface (CUI) links the system processor to the internal flash
memory operation. A valid command sequence written to the CUI initiates the flash device Write
State Machine (WSM) operation, which automatically executes the algorithms, timings, and
verifications necessary to manage flash memory program and erase. An internal status register
provides ready/busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption.
• The flash device automatically enters APS mode following read cycle completion.
• Standby mode begins when the system deselects the flash memory by de-asserting CE#.
• Driving RST# low produces power savings similar to standby mode. It also resets the part to
read-array mode (important for system-level reset), clears internal status registers, and
provides an additional level of flash device write protection.
2.2
Memory Map and Partitioning
The W30 flash memory device is divided into 4-Mbit physical partitions. This partitioning allows
simultaneous RWW or RWE operations, and enables users to segment code and data areas on
4-Mbit boundaries. The flash memory array is asymmetrically blocked, which enables system code
and data integration within a single flash device. Each block can be erased independently in block
erase mode. Simultaneous program and erase operations are not allowed; only one partition at a
time can be actively programming or erasing. See Table 1, “Bottom Parameter Memory Map” on
page 12 and Table 2, “Top Parameter Memory Map” on page 13.
• The 32-Mbit flash device has eight partitions.
• The 64-Mbit flash device has 16 partitions.
• The 128-Mbit flash device has 32 partitions.
Each flash device density contains one parameter partition and several main partitions. The 4-Mbit
parameter partition contains eight 4-Kword parameter blocks and seven 32-Kword main blocks.
Each 4-Mbit main partition contains eight 32-Kword blocks.
The bulk of the flash memory array is divided into main blocks that can store code or data, and
parameter blocks that allow storage of frequently updated small parameters that are normally
stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs
can be emulated.
.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
11
28F640W30, 28F320W30, 28F128W30
Table 1.
Bottom Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
32
32
32
32
32
32
32
32
32
32
32
262
7F8000-7FFFFF
135
134
71
400000-407FFF
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
134
71
70
39
38
31
30
23
22
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
70
39
38
31
30
23
22
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
70
39
38
31
30
23
22
32
32
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
32
4
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
4
0
000000-000FFF
0
000000-000FFF
0
000000-000FFF
June 2005
12
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 2.
Top Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
4
70
1FF000-1FFFFF
134
3FF000-3FFFFF
262
7FF000-7FFFFF
4
63
62
1F8000-1F8FFF
1F0000-1F7FFF
127
126
3F8000-3F8FFF
3F0000-3F7FFF
255
254
7F8000-7F8FFF
7F0000-7F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
56
55
48
47
40
39
32
31
0
1C0000-1C7FFF
1B8000-1BFFFF
18000-187FFF
178000-17FFFF
140000-147FFF
138000-13FFFF
100000-107FFF
0F8000-0FFFFF
000000-007FFF
120
119
112
111
104
103
96
3C0000-3C7FFF
3B8000-3BFFFF
380000-387FFF
378000-37FFFF
340000-347FFF
338000-33FFFF
300000-307FFF
2F8000-2FFFFF
200000-207FFF
1F8000-1FFFFF
000000-007FFF
248
247
240
239
232
231
224
223
192
191
128
127
0
7C0000-7C7FFF
7B8000-7BFFFF
780000-787FFF
778000-77FFFF
740000-747FFF
738000-73FFFF
700000-707FFF
6F8000-6FFFFF
600000-607FFF
5F8000-5FFFFF
400000-407FFF
3F8000-3FFFFF
000000-007FFF
95
64
63
0
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
13
28F640W30, 28F320W30, 28F128W30
3.0
Package Information
3.1
W30 Flash Memory Device – 130 nm Lithography
Figure 1.
32 Mb, 64 Mb, and 128 Mb VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
S2
8
7
6
5
4
3
2
1
A
A
B
B
C
D
E
F
C
D
E
F
E
e
G
G
b
Top View - Bump Side Down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Table 3. 2 Mb, 64 Mb, and 128 Mb VF BGA Package Specifications
Millimeters
Inches
Nom
Dimension
Symbol
Min
Nom
Max
Min
Max
Package Height
Ball Height
A
A1
A2
b
-
-
1.000
-
-
0.0394
0.150
-
-
-
-
0.0059
-
-
-
-
Package Body Thickness
0.665
0.375
7.700
0.0262
Ball (Lead) Width
0.325
7.600
0.425 0.0128 0.0148 0.0167
7.800 0.2992 0.3031 0.3071
Package Body Width (32 Mb, 64 Mb)
Package Body Width (128 Mb)
Package Body Length (32 Mb, 64 Mb, 128 Mb)
Pitch
D
D
10.900 11.000 11.100 0.4291 0.4331 0.4370
E
8.900
9.000
0.750
56
9.100 0.3504 0.3543 0.3583
[e]
N
-
-
-
-
-
-
0.0295
-
Ball (Lead) Count
-
-
56
-
-
Seating Plane Coplanarity
Y
-
0.100
0.0039
Corner to Ball A1 Distance Along D (32 Mb, 64 Mb)
Corner to Ball A1 Distance Along D (128 Mb)
S1
S1
1.125
1.225
1.325 0.0443 0.0482 0.0522
2.775 2.2875 2.975 0.1093 0.1132 0.1171
2.150 2.250 2.350 0.0846 0.0886 0.0925
Corner to Ball A1 Distance Along E (32 Mb, 64 Mb,128
Mb)
S2
June 2005
14
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 2.
32Mb, 64Mb and 128Mb QUAD+ Package Drawing
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
D
e
G
G
H
H
J
J
K
K
L
L
M
M
b
E
Bottom View - Ball Up
A
Top View - Ball Down
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Symbol
A
A1
A2
b
D
E
e
N
Min
Max Notes
1.200
Min
Max
0.0472
0.200
0.0079
0.860
0.375
10.000
8.000
0.800
88
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.325
9.900
7.900
0.425
10.100
8.100
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
Y
S1
S2
0.100
1.300
0.700
0.0039
0.0512
0.0276
1.100
0.500
1.200
0.600
0.0433
0.0197
0.0472
0.0236
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
15
28F640W30, 28F320W30, 28F128W30
3.2
W30 Flash Memory Device – 180 nm Lithography
Figure 3.
64Mb µBGA* CSP Package Drawing and Dimensions
Pin # 1
Indicator
Pin # 1
Corner
s
D
1
s
2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
A
B
C
D
E
F
C
D
E
E
F
G
G
e
b
Top View - Silicon backside
Com plete Ink M ark Not
Bottom View - Bum p side Up
A1
A2
A
Seati
Y
Plan
Side
Millimeters
Inches
Symbol
A
Min
Nom
Max
Notes
Min
Nom
Max
Package Height
0.850
0.150
0.612
0.300
7.600
8.900
1.000
0.0335
0.0059
0.0241
0.0118
0.2992
0.3503
0.0394
Ball Height
A1
A2
b
Package Body Thickness
Ball (Lead) Width
0.712
0.350
7.700
9.000
0.750
56
0.812
0.400
7.800
9.100
0.0280
0.0138
0.3031
0.3543
0.0295
56
0.0320
0.0157
0.3071
0.3583
Package Body Width
Package Body Length
Pitch
D
E
[e]
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Y
0.100
1.325
2.350
0.0039
0.0522
0.0925
S1
S2
1.125
2.150
1.225
2.250
0.0443
0.0846
0.0482
0.0886
June 2005
16
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 4.
32Mb VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
A
B
C
E
D
E
F
D
E
F
e
G
G
b
Top View - Bump Side Down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Figure 5.
128Mb VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
S1
D
S2
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
H
J
G
H
J
b
Top View - Bump Side
Down
Bottom View - Ball Side
Up
A1
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
17
28F640W30, 28F320W30, 28F128W30
Table 4.
32Mb and 128Mb VF BGA Package Dimensions
Millimeters
Nom
Inches
Nom
Dimension
Symbol
Min
Max
Min
Max
Package Height
Ball Height
A
A1
A2
b
0.850
0.150
0.615
0.325
7.600
8.900
-
1.000
-
0.0335
0.0059
-
-
0.0394
-
-
Package Body Thickness
0.665
0.375
7.700
9.000
0.715
0.425
7.800
9.100
0.0242 0.0262 0.0281
0.0128 0.0148 0.0167
0.2992 0.3031 0.3071
0.3503 0.3543 0.3583
Ball (Lead) Width
Package Body Width 32Mb
Package Body Length32Mb
Package Body Width 128Mb
Package Body Length 128Mb
Pitch
D
E
D
12.400 12.500 12.600 0.4882 0.4921 0.4961
11.900 12.000 12.100 0.4685 0.4724 0.4764
E
[e]
N
-
-
0.750
56
-
-
-
-
-
0.0295
-
Ball (Lead) Count 32Mb
-
56
60
-
-
Ball (Lead) Count 128Mb
N
-
60
-
-
Seating Plane Coplanarity
Y
-
-
0.100
1.325
2.350
2.975
0.0039
Corner to Ball A1 Distance Along D 32Mb
Corner to Ball A1 Distance Along E 32Mb
Corner to Ball A1 Distance Along D 128Mb
Corner to Ball A1 Distance Along E 128Mb
S1
S2
S1
S2
1.125
2.150
2.775
2.900
1.225
2.250
2.875
3.000
0.0443 0.0482 0.0522
0.0846 0.0886 0.0925
0.1093 0.1132
0.1171
3.1000 0.1142
0.1181 0.1220
June 2005
18
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
4.0
Ballout and Signal Descriptions
4.1
Signal Ballout
The W30 flash memory device is available in the 56-ball VF BGA and µBGA Chip Scale Package
with 0.75 mm ball pitch, or the QUAD+ SCSP package. Figure 6 shows the VF BGA and µBGA
package ballout. Figure 7 shows the QUAD+ package ballout.
Figure 6.
56-Ball VF BGA/ µBGA Ballout
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
A
B
C
D
E
F
A11
A8
A9
VSS
A20
A21
VCC
CLK
VPP
A18
A17
A19
A6
A5
A7
A4
A3
A2
A4
A6
A5
A7
A18
A17
A19
VPP
VCC
CLK
VSS
A20
A21
A8
A9
A11
A12
A13
B
A12
A3
A2
RST#
WE#
RST#
WE#
C
A13
A10
A10
ADV#
ADV#
D
A15
A14 WAIT
DQ15 DQ6
A16
DQ12
DQ2
WP#
DQ1
A22
CE#
A1
A0
A1
A0
A22
CE#
WP#
DQ1
DQ12
DQ2
A16
WAIT A14
DQ6 DQ15
A15
E
VCCQ
DQ4
DQ4
VCCQ
F
VSS
DQ14 DQ13
VSSQ DQ5
DQ11 DQ10
DQ9
DQ0
OE#
OE#
DQ0
DQ9
DQ10 DQ11
DQ13 DQ14
DQ5 VSSQ
VSS
DQ7
G
G
DQ7
VCC
DQ3
VCCQ DQ8
VSSQ
VSSQ
DQ8 VCCQ
DQ3
VCC
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
Notes:
1.
On lower density flash memory devices, the upper address balls can be treated as NC. (that is, on 32-Mbit density, A22
and A21 are NC).
2.
See Appendix C, “Ordering Information” on page 103 for mechanical specifications for the package.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
19
28F640W30, 28F320W30, 28F128W30
Figure 7.
88-Ball (80 Active Balls) QUAD+ Ballout
1
2
3
4
5
6
7
8
DU
DU
DU
DU
A
B
C
D
E
F
A4
A5
A18
R-LB#
A17
A7
A19
A23
A24
A25
VSS
VSS
F1-VCC F2-VCC
A21
A22
A9
A11
A12
A13
A15
A16
S-CS2
CLK
F-VPP,
F-VPEN
A3
R-WE# P1-CS#
A2
F-WP# ADV#
A20
A8
A10
A14
A1
A6
R-UB# F-RST# F-WE#
G
A0
D8
D2
D10
D5
D13
WAIT F2-CE#
H
J
R-OE#
D0
D1
D9
D3
D12
D4
D14
D6
D7
F2-OE#
VCCQ
S-CS1# F1-OE#
D11
D15
K
L
P-Mode,
P-CRE
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ
VSS
DU
VSS
DU
VCCQ F1-VCC VSS
VSS
VSS
DU
VSS
DU
M
Top View - Ball Side Down
Legend:
SRAM/PSRAM specific
Flash specific
Global
Notes:
1.
On lower density flash memory devices, the upper address balls can be treated as NC (that is, on 64-Mb
density, A[25:23]are NC)
2.
See Appendix C, “Ordering Information” on page 103 for mechanical specifications for the package.
June 2005
20
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
4.2
Signal Descriptions
• Table 5 describes the signals for the 56-ball VF BGA and µBGA Chip Scale Package.
• Table 6 describes the signals for the QUAD+ package ballout.
Table 5.
Signal Descriptions - µBGA Package & VF BGA Package (Sheet 1 of 2)
Symbol
A[22:0]
Type
Name and Function
Input
ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
DATA INPUTS/OUTPUTS:
•
•
Inputs data and commands during write cycles.
Outputs data during reads.
Input/
Output
D[15:0]
Data pins are High-Z when the flash device or its outputs are deselected. Data is internally latched
during writes.
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on the rising edge of ADV#, or the next valid CLK edge with
ADV# low, whichever occurs first.
ADV#
CE#
Input
Input
Input
Input
Input
CHIP ENABLE:
•
•
Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the flash device, places it in standby mode, and tri-states all outputs.
CLOCK: CLK synchronizes the flash device to the system bus frequency during synchronous reads
and increments an internal address generator. During synchronous read operations, addresses are
latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
CLK
OUTPUT ENABLE:
OE#
•
•
When asserted, OE# enables the flash device output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides
data protection during power transitions. De-asserting RST# enables normal operation and places the
flash device in asynchronous read-array mode.
RST#
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be
WAIT
WE#
WP#
Output asserted-high or asserted-low, based on bit 10 of the Read Configuration Register. WAIT is tri-stated if
CE# is deasserted. WAIT is not gated by OE#.
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
Input
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
Input
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 73 for details on block locking.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Flash
memory contents cannot be altered when VPP < VPPLK. Do not attempt block erase and program
operations at invalid VPP voltages.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash device modification. VPP can be 0 V during read operations.
Power/
Input
VPP
VCC
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V might reduce block cycling capability.
FLASH DEVICE POWER SUPPLY: Writes are inhibited at VCC < VLKO. Do not attempt flash device
operations at invalid VCC voltages.
Power
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ.
GROUND: Pins for all internal flash device circuitry must be connected to system ground.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
21
28F640W30, 28F320W30, 28F128W30
Table 5.
Signal Descriptions - µBGA Package & VF BGA Package (Sheet 2 of 2)
Symbol
Type
Name and Function
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal can be tied
directly to VSS.
VSSQ
Power
DO NOT USE: Do not use this pin. Do not connect this pin to any power supplies, signals, or other
pins; this pin must be floated.
DU
NC
—
—
NO CONNECT: No internal connection; can be driven or floated.
Table 6.
Signal Descriptions - QUAD+ Package (Sheet 1 of 3)
Symbol
Type
Description
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 128-Mbit Die : AMAX = A22
• 64-Mbit Die : AMAX = A21
• 32-Mbit Die : AMAX = A20
A[MAX:MIN]
Input
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future flash device densities.
DATA INPUTS/OUTPUTS:
•
•
Inputs data and commands during write cycles.
Outputs data during read cycles.
Input/
Output
DQ[15:0]
Data signals float when the flash device or its outputs are deselected. Data are internally latched
during writes on the flash device.
FLASH CHIP ENABLE: Low-true input.
F[3:1]-CE# low selects the associated flash memory die.
•
When asserted, flash memory internal control logic, input buffers, decoders, and sense amplifiers
are active.
•
When deasserted, the associated flash die is deselected, power is reduced to standby levels, and
data and WAIT outputs are placed in high-Z state.
F[3:1]-CE#
Input
•
•
•
F1-CE# selects or deselects flash die #1.
F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die.
F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two
flash dies.
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).
•
When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input
buffers, decoders, and sense amplifiers are active.
S-CS1#
S-CS2
Input
•
When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its
power is reduced to standby levels.
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked
combinations without SRAM die.
PSRAM CHIP SELECT: Low-true input.
•
When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are
active.
•
•
When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
P[2:1]-CS#
Input
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die.
This ball is an RFU on stacked combinations without PSRAM.
•
P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM
dies. This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM.
June 2005
22
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 6.
Signal Descriptions - QUAD+ Package (Sheet 2 of 3)
Symbol
Type
Description
FLASH OUTPUT ENABLE: Low-true input.
•
•
Fx-OE# low enables the output buffers on the selected flash memory device.
F[2:1]-OE# high disables the output buffers on the selected flash memory device, placing them in
High-Z.
F[2:1]-OE#
Input
•
•
F1-OE# controls the outputs of flash die #1.
F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked
combinations with two or three flash die, and is RFU on stacked combinations with only one flash
die.
RAM OUTPUT ENABLE: Low-true input.
•
•
R-OE# low enables the output buffers on the selected RAM.
R-OE#
Input
R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z.
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
FLASH WRITE ENABLE: Low-true input.
F-WE#
R-WE#
Input
Input
F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of
F-WE#.
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and
increments the internal address generator.
•
•
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
CLK
Input
During asynchronous mode read operations, addresses are latched on the rising edge ADV#, or
are continuously flow-through when ADV# is kept asserted.
WAIT: Output signal.
Indicates invalid data during synchronous array or non-array flash memory reads. Read Configuration
Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
WAIT
Output
•
In synchronous array or non-array flash memory read modes, WAIT indicates invalid data when
asserted and valid data when deasserted.
•
In asynchronous flash memory page read, and all flash memory write modes, WAIT is asserted.
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash die.
•
F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked
using software commands.
F-WP#
ADV#
Input
Input
•
F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked
using software commands.
ADDRESS VALID: Low-true input.
•
During synchronous flash memory read operations, addresses are latched on the rising edge of
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
•
During asynchronous flash memory read operations, addresses are latched on the rising edge of
ADV#, or are continuously flow-through when ADV# is kept asserted.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
23
28F640W30, 28F320W30, 28F128W30
Table 6.
Signal Descriptions - QUAD+ Package (Sheet 3 of 3)
Symbol
Type
Description
RAM UPPER / LOWER BYTE ENABLES: Low-true input.
During RAM read and write cycles:
R-UB#
R-LB#
•
•
R-UB# low enables the RAM high order bytes on D[15:8].
R-LB# low enables the RAM low-order bytes on D[7:0].
Input
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die, and are RFU on
flash-only stacked combinations.
FLASH RESET: Low-true input.
•
•
F-RST# low initializes flash device internal circuitry and disables flash device operations.
F-RST# high enables flash device operation.
F-RST#
Input
Input
Exit from reset places the flash device in asynchronous read array mode.
P-Mode (PSRAM Mode): Low-true input.
P-Mode programs the Configuration Register, and enters/exits the Low Power Mode of the PSRAM
die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-Mode,
P-CRE
•
•
•
P-CRE (PSRAM Configuration Register Enable): High-true input.
P-CRE is high, write operations load the Refresh Control Register or Bus Control Register.
P-CRE applies only on combinations with synchronous PSRAM die.
P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash memory
device program/erase operations.
F-VPP,
Power
Power
Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Do not
attempt erase / program operations at invalid F-VPP (F-VPEN) voltages.
F-VPEN
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.
FLASH LOGIC POWER:
•
•
F1-VCC supplies power to the core logic of flash die #1.
F2-VCC supplies power to the core logic of flash die #2 and flash die #3.
F[2:1]-VCC
Write operations are inhibited when F-VCC < VLKO. Do not attempt flash device operations at invalid
F-VCC voltages.
F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked
combinations with only one flash die.
SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC
P-VCC
Power
Power
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations
without SRAM die.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations
without PSRAM die.
VCCQ
VSS
Power
Power
FLASH DEVICE I/O POWER: Supply power for the flash device input and output buffers.
FLASH DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserved for future flash device functionality/ enhancements. Contact
Intel regarding the use of balls designated RFU.
RFU
DU
—
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
June 2005
24
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the flash device beyond the Absolute Maximum Ratings in Table 7 might cause
permanent damage. These are stress ratings only.
Notice: This datasheet contains information on products in the design phase of development. The information
here is subject to change without notice. Do not finalize a design with this information.
Table 7.
Absolute Maximum Ratings
Parameter
Maximum Rating
–40 °C to +85 °C
Note
Temperature under Bias
Storage Temperature
–65 °C to +125 °C
–0.5 V to +3.8 V
–0.2 V to +14 V
–0.2 V to +2.45 V
–0.2 V to +3.8 V
100 mA
Voltage on Any Pin (except VCC, VCCQ, VPP
)
VPP Voltage
1,2,3
VCC Voltage
1
1
4
VCCQ Voltage
Output Short Circuit Current
Notes:
1.
All specified voltages are relative to VSS. Minimum DC voltage is –0.5 V on input/output
pins and –0.2 V on VCC and VPP pins. During transitions, this level might undershoot to
–2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which,
during transitions, might overshoot to VCC +2.0 V for periods < 20 ns.
2.
3.
Maximum DC voltage on VPP might overshoot to +14.0 V for periods < 20 ns.
V
PP program voltage is normally VPPL. VPP can be 12 V ± 0.6 V for 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks during program/erase.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
25
28F640W30, 28F320W30, 28F128W30
5.2
Operating Conditions
Do not operate the W30 flash memory device beyond the Operating Conditions in Table 8.
Extended exposure beyond these Operating Conditions might affect flash device reliability.
Table 8.
Extended Temperature Operation
Symbol
Parameter1
Min
Nom
Max
Unit
Notes
TA
Operating Temperature
–40
1.7
2.2
0.90
11.4
-
25
1.8
3.0
1.80
12.0
-
85
1.90
3.3
°C
-
VCC
VCCQ
VPPL
VPPH
tPPH
VCC Supply Voltage
3
3
2
2
2
I/O Supply Voltage
V
VPP Voltage Supply (Logic Level)
Factory Programming VPP
1.95
12.6
80
Maximum VPP Hours
VPP = 12 V
VPP < VCC
Hours
Main and Parameter
Blocks
100,000
-
-
2
Block
Erase
Cycles
Cycles
Main Blocks
V
PP = 12 V
-
-
-
-
1000
2500
2
2
Parameter Blocks
VPP = 12 V
Notes:
1.
See Section 6.1, “DC Current Characteristics” on page 27 and Section 6.2, “DC Voltage
Characteristics” on page 28 for specific voltage-range specifications.
VPP is normally VPPL. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main
blocks for extended temperatures and 2500 cycles on parameter blocks at extended
temperature.
2.
3.
4.
Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V.
See the tables in Section 6.0, “Electrical Specifications” on page 27 and in Section 7.0, “AC
Characteristics” on page 29 for operating characteristics
June 2005
26
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
6.0
Electrical Specifications
6.1
DC Current Characteristics
Table 9.
Sym
DC Current Characteristics (Sheet 1 of 2)
VCCQ= 3.0 V
Parameter (1)
Note 32/64 Mbit
128 Mbit
Unit
Test Conditions
Typ Max Typ Max
VCC = VCCMax
ILI
Input Load
9
-
-
±2
-
-
±2
µA
µA
V
CCQ = VCCQMax
VIN = VCCQ or GND
V
V
CC = VCCMax
CCQ = VCCQMax
Output
Leakage
ILO
DQ[15:0]
±10
±10
VIN = VCCQ or GND
180nm
ICCS
V
V
CC = VCCMax
CCQ = VCCQMax
6
8
6
21
50
21
6
8
6
30
70
30
VCC Standby
10
µA
CE# = VCCQ
RST# =VCCQ
130 nm
ICCS
180nm
ICCAPS
VCC = VCCMax
V
CCQ = VCCQMax
APS
11
2
µA CE# = VSSQ
RST# =VCCQ
130nm
ICCAPS
8
4
50
7
8
4
70
10
All other inputs =VCCQ or VSSQ
Asynchronous
Page Mode
f=13 MHz
mA 4 Word Read
V
CC = VCCMax
7
9
15
16
19
7
9
15
16
19
mA Burst length = 4
mA Burst length = 8
mA Burst length =16
Average
VCC
Read
CE# = VIL
OE# = VIH
Inputs = VIH or VIL
ICCR
Synchronous
CLK = 40 MHz
2
11
11
Burst length =
mA
12
22
12
22
Continuous
VPP = VPPL, Program in Progress
VPP = VPPH, Program in Progress
VPP = VPPL, Block Erase in Progress
PP = VPPH, Block Erase in Progress
18
8
40
15
40
15
21
21
18
8
40
15
40
15
30
30
mA
mA
mA
mA
µA
ICCW
VCC Program
3,4,5
3,4,5
18
8
18
8
ICCE
VCC Block Erase
V
CE# = VCC, Program Suspended
CE# = VCC, Erase Suspended
ICCWS
ICCES
VCC Program Suspend
VCC Erase Suspend
6
6
6
6
6
6
µA
V
PP Standby
IPPS
VPP Program Suspend
VPP Erase Suspend
3
-
0.2
2
5
0.2
2
5
µA VPP < VCC
(IPPWS,
IPPES
)
VPP < VCC
IPPR
VPP Read
15
15
µA
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
27
28F640W30, 28F320W30, 28F128W30
Table 9.
DC Current Characteristics (Sheet 2 of 2)
VCCQ= 3.0 V
Note 32/64 Mbit 128 Mbit
Sym
Parameter (1)
Unit
Test Conditions
Typ Max Typ Max
0.05 0.10 0.05 0.10
V
PP = VPPL, Program in Progress
IPPW
VPP Program
4
4
mA
mA
8
22
0.05 0.10 0.05 0.10
22 22
16
37
VPP = VPPH, Program in Progress
PP = VPPL, Erase in Progress
VPP = VPPH, Erase in Progress
V
IPPE
VPP Erase
8
8
Notes:
1.
2.
All currents are RMS unless noted. Typical values at typical VCC, TA = +25°C.
Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ
specification for details.
3.
4.
5.
6.
Sampled, not 100% tested.
V
V
CC read + program current is the sum of VCC read and VCC program currents.
CC read + erase current is the sum of VCC read and VCC erase currents.
I
I
CCES is specified with the flash device deselected. If the flash device is read while in erase suspend, the current is
CCES plus ICCR
.
7.
8.
9.
10.
VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
IL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
If VIN>VCC the input load current increases to 10 µA max.
ICCS is the average current measured over any 5ms time interval 5 µs after a CE# de-assertion.
V
11.
Refer to section Section 8.2, “Automatic Power Savings (APS)” on page 45 for ICCAPS measurement details.
6.2
DC Voltage Characteristics
Table 10.
DC Voltage Characteristics
VCCQ= 3.0 V
32/64 Mbit 128 Mbit
Min Max
Sym
Parameter (1)
Note
Unit
Test Conditions
Min
Max
VIL
Input Low
Input High
Output Low
8
-
0
0.4
0
0.4
V
V
VCCQ
– 0.4
VCCQ
– 0.4
VIH
VCCQ
VCCQ
VOL
VCC = VCCMin
-
-
-
0.1
-
-
0.1
V
V
VCCQ = VCCQMin
IOL = 100 µA
VOH
Output High
VCC = VCCMin
VCCQ
– 0.1
VCCQ
– 0.1
-
VCCQ = VCCQMin
IOH = –100 µA
VPPLK
VLKO
VPP Lock-Out
VCC Lock
7
-
-
0.4
-
0.4
V
V
V
1.0
0.9
-
-
1.0
0.9
-
-
VILKOQ VCCQ Lock
-
Note: For all numbered note references in this table, refer to the notes in Table 9, “DC Current
Characteristics” on page 27.
June 2005
28
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
7.0
AC Characteristics
7.1
Read Operations - 130 nm Lithography
Table 11.
Read Operations - 130 nm Lithography (Sheet 1 of 2)
32-Mbit
64-Mbit
128-Mbit
-70
#
Sym
Parameter 1
Units Notes
-70
-85
Min Max Min Max Min Max
Asynchronous Specifications
R1
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read Cycle Time
70
-
-
70
70
30
150
-
85
-
-
85
85
30
150
-
70
-
-
70
70
30
150
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
R2
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
RST# High to Output Valid
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
OE# High to Output High-Z
CE# (OE#) High to Output Low-Z
CE# Pulse Width High
R3
-
-
-
6
R4
-
-
-
3
R5
-
-
-
-
R6
0
0
-
0
0
-
0
0
-
4
R7
-
-
-
3,4
4
R8
20
14
-
20
14
-
20
14
-
R9
-
-
-
3,4
3,4
5
R10
R11
R12
R13
0
20
-
0
20
-
0
20
-
tEHEL
tELTV
tEHTZ
-
-
-
CE# Low to WAIT Valid
CE# High to WAIT High-Z
20
25
22
25
22
25
5
-
-
-
4,5
Latching Specifications
R101 tAVVH
R102 tELVH
R103 tVLQV
R104 tVLVH
R105 tVHVL
R106 tVHAX
R108 tAPA
Address Setup to ADV# High
10
10
-
-
-
10
10
-
-
12
12
-
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
CE# Low to ADV# High
ADV# Low to Output Valid
ADV# Pulse Width Low
70
-
85
-
70
-
6
-
10
10
9
10
10
9
12
12
9
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
-
-
-
-
-
-
-
2
-
-
25
-
25
-
25
Clock Specifications
R200 fCLK
R201 tCLK
R202 tCH/L
R203 tCHCL
CLK Frequency
-
25
9.5
-
40
-
-
30
9.5
-
33
-
-
25
9.5
-
40
-
MHz
ns
-
-
-
-
CLK Period
CLK High or Low Time
CLK Fall or Rise Time
-
-
-
ns
3
5
5
ns
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
29
28F640W30, 28F320W30, 28F128W30
Table 11.
Read Operations - 130 nm Lithography (Sheet 2 of 2)
32-Mbit
64-Mbit
128-Mbit
-70
#
Sym
Parameter 1
Units Notes
-70
-85
Min Max Min Max Min Max
Synchronous Specifications
R301 tAVCH
R302 tVLCH
R303 tELCH
R304 tCHQV
R305 tCHQX
R306 tCHAX
R307 tCHTV
Notes:
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Valid
9
10
9
-
-
9
10
9
-
-
10
10
9
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
20
-
-
22
-
-
20
-
-
Output Hold from CLK
Address Hold from CLK
CLK to WAIT Valid
5
5
5
-
10
-
-
10
-
-
10
-
-
2
-
20
22
22
1.
See Figure 22, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum
allowable input slew rate.
2.
Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is
satisfied first.
3.
4.
5.
6.
OE# can be delayed by up to tELQV – tGLQV after the falling edge of CE# without impact to tELQV.
Sampled, not 100% tested.
Applies only to subsequent synchronous reads.
During the initial access of a synchronous burst read, data from the first word might begin to be driven onto the
data bus as early as the first clock edge after tAVQV
.
7.2
Read Operations - 180 nm Lithography
Table 12.
Read Operations - 180 nm Lithography (Sheet 1 of 2)
32-Mbit
64-Mbit
128-Mbit
-90
#
Sym
Parameter 1
Units Notes
-70
-85
Min Max Min Max Min Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV
Read Cycle Time
70
-
-
70
70
30
150
-
85
-
-
85
85
30
150
-
90
-
-
90
90
30
150
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
RST# High to Output Valid
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
OE# High to Output High-Z
-
-
-
6
-
-
-
3
-
-
-
-
0
0
-
0
0
-
0
0
-
4
-
-
-
3,4
4
20
14
20
14
20
14
-
-
3,4
June 2005
30
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 12.
Read Operations - 180 nm Lithography (Sheet 2 of 2)
32-Mbit
64-Mbit
128-Mbit
-90
#
Sym
Parameter 1
Units Notes
-70
-85
Min Max Min Max Min Max
R10
R11
R12
R13
tOH
CE# (OE#) High to Output Low-Z
CE# Pulse Width High
0
20
-
-
0
20
-
-
0
20
-
-
ns
ns
ns
ns
3,4
5
tEHEL
tELTV
tEHTZ
-
-
-
CE# Low to WAIT Valid
20
25
22
25
22
25
5
CE# High to WAIT High-Z
-
-
-
4,5
Latching Specifications
R101 tAVVH
R102 tELVH
R103 tVLQV
R104 tVLVH
R105 tVHVL
R106 tVHAX
R108 tAPA
Address Setup to ADV# High
10
10
-
-
-
10
10
-
-
-
12
12
-
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
CE# Low to ADV# High
ADV# Low to Output Valid
ADV# Pulse Width Low
70
-
85
-
90
-
6
-
10
10
9
10
10
9
12
12
9
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
-
-
-
-
-
-
-
2
-
-
25
-
25
-
30
Clock Specifications
R200 fCLK
R201 tCLK
R202 tCH/L
R203 tCHCL
CLK Frequency
-
25
9.5
-
40
-
-
33
-
-
30
9.5
-
33
-
MHz
ns
-
-
-
-
CLK Period
30
9.5
CLK High or Low Time
CLK Fall or Rise Time
-
-
-
ns
3
5
5
ns
Synchronous Specifications
R301 tAVCH
R302 tVLCH
R303 tELCH
R304 tCHQV
R305 tCHQX
R306 tCHAX
R307 tCHTV
Notes:
Address Valid Setup to CLK
9
10
9
-
-
9
10
9
-
-
10
10
9
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Valid
-
-
-
-
-
20
-
-
22
-
22
-
-
Output Hold from CLK
Address Hold from CLK
CLK to WAIT Valid
5
5
5
-
10
-
-
10
-
-
10
-
-
2
-
20
22
22
1.
See Figure 22, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum
allowable input slew rate.
2.
Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is
satisfied first.
3.
4.
5.
6.
OE# can be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV.
Sampled, not 100% tested.
Applies only to subsequent synchronous reads.
During the initial access of a synchronous burst read, data from the first word might begin to be driven onto the
data bus as early as the first clock edge after tAVQV
.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
31
28F640W30, 28F320W30, 28F128W30
Figure 8.
Asynchronous Read Operation Waveform
R1
VIH
VIL
Valid
Address
Address [A]
CE# [E]
R2
R3
VIH
VIL
R8
R9
VIH
VIL
R4
OE# [G]
R7
VIH
VIL
WE# [W]
WAIT [T]
VOH
VOL
High Z
High Z
Note 1
VOH
VOL
High Z
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Notes: .
1.
WAIT shown asserted (RCR[10]=0)
2.
ADV# assumed to be driven to VIL in this waveform
June 2005
32
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 9.
Latched Asynchronous Read Operation Waveform
R1
VIH
VIL
Valid
Address
Valid
Address
A[MAX:2] [A]
A[1:0] [A]
VIH
VIL
Valid
Address
Valid
Address
R2
R101
R104
R102
R105
VIH
R106
R103
ADV# [V]
CE# [E]
VIL
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
Data [Q]
RST# [P]
R7
VIH
VIL
VOH
VOL
High Z
Valid
Output
R5
R10
VIH
VIL
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
33
28F640W30, 28F320W30, 28F128W30
Figure 10.
Page-Mode Read Operation Waveform
R1
VIH
VIL
Valid
Address
A[MAX:2] [A]
A[1:0] [A]
R2
VIH
VIL
Valid
Valid
Valid
Valid
Address
Address
Address
Address
R101
R105
VIH
R106
R103
ADV# [V]
CE# [E]
OE# [G]
VIL
R104
R102
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
R7
VIH
WE# [W]
WAIT [T]
VIL
VOH
High Z
High Z
R108
Note 1
VOL
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Note:
1.
WAIT shown asserted (RCR[10] = 0).
June 2005
34
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 11.
Single Synchronous Read-Array Operation Waveform
R13
R12
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock
cycles during the initial access.
2.
3.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before,
valid data.
In this waveform, an x-word burst is initiated to the main array and it is terminated by a CE# de-assertion
after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted
(low) WAIT signal would have remained asserted (low) as long as CE# is asserted (low).
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
35
28F640W30, 28F320W30, 28F128W30
Figure 12.
Synchronous 4-Word Burst Read Operation Waveform
R11
R13
R12
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock
cycles during the initial access.
2.
WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle
before, valid data.
June 2005
36
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 13.
WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform
R12
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock
cycles during the initial access.
2.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before,
valid data. (This example assumes a wait delay of two clocks.)
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
37
28F640W30, 28F320W30, 28F128W30
Figure 14.
WAIT Signal in Synchronous Non-Read Array Operation Waveform
R13
R12
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock
cycles during the initial access.
2.
WAIT shown asserted (RCR[10]=0).
June 2005
38
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 15.
Burst Suspend
R304
R305
R305
R305
CLK
R1
R2
Address [A]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
R3
R8
R9
R4
R9
R4
R13
R12
WAIT [T]
WE# [W]
R7
R6
R304
Q1
R304
Q2
DATA [D/Q]
Q0
Q1
Note:
1.
During Burst Suspend, the Clock signal can be held high or low.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
39
28F640W30, 28F320W30, 28F128W30
7.3
AC Write Characteristics
Table 13.
AC Write Characteristics
32-Mbit
64-Mbit
128-Mbit
#
Sym
Parameter 1,2
Notes
Unit
-70
-85 / -90
Min
Max
Min
Max
W1
W2
t
PHWL (tPHEL
)
RST# High Recovery to WE# (CE#) Low
CE# (WE#) Setup to WE# (CE#) Low
WE# (CE#) Write Pulse Width Low
Data Setup to WE# (CE#) High
Address Setup to WE# (CE#) High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
3
4
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL (tWLEL
tWLWH (tELEH
tDVWH (tDVEH
tAVWH (tAVEH
tWHEH (tEHWH
)
W3
)
45
45
45
0
60
60
60
0
W4
)
W5
)
W6
)
W7
tWHDX (tEHDX
tWHAX (tEHAX
tWHWL (tEHEL
tVPWH (tVPEH
tQVVL
)
0
0
W8
)
0
0
W9
)
)
5,6,7
3
25
200
0
25
200
0
W10
W11
W12
W13
W14
VPP Setup to WE# (CE#) High
VPP Hold from Valid SRD
3,8
3,8
3
tQVBL
WP# Hold from Valid SRD
0
0
tBHWH (tBHEH
tWHGL (tEHGL
)
WP# Setup to WE# (CE#) High
Write Recovery before Read
200
0
200
0
)
-
tAVQV
+ 40
tAVQV
+ 50
W16
tWHQV
WE# High to Valid Data
3,6,10
-
-
ns
W18
W19
tWHAV
tWHCV
tWHVH
WE# High to Address Valid
WE# High to CLK Valid
WE# High to ADV# High
3,9,10
3,10
0
-
-
-
0
-
-
-
ns
ns
ns
20
20
20
20
W20
3,10
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as during write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL
.
5.
6.
.
System designers must take this into account, and can insert a software No-Op instruction to delay the first read after
issuing a command.
7.
For commands other than resume commands.
8.
9.
10.
V
PP must be held at VPPL or VPPH until block erase or program success is determined.
Applicable during asynchronous reads following a write.
WHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH
t
both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs
first).
June 2005
40
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 16.
Write Operations Waveform
VIH
CLK [C]
VIL
W19
Note 1
Note 2
W5
Note 3
Note 4
W18
Note 5
VIH
VIL
Valid
Address
Valid
Address
Valid
Address
Address [A]
R101
R105
VIH
R106
W8
ADV# [V]
VIL
R104
W2
W20
VIH
VIL
Note 6
CE# (WE#) [E(W)]
OE# [G]
W6
VIH
VIL
W3
W14
W9
VIH
VIL
Note 6
WE# (CE#) [W(E)]
Data [Q]
W1
W7
W16
VIH
VIL
Valid
SRD
Data In
Data In
W4
VIH
VIL
RST# [P]
W12
W11
W13
W10
VIH
VIL
WP# [B]
VPPH
VPPLK
VIL
VPP [V]
Notes:
1.
2.
3.
4.
5.
6.
7.
V
CC power-up and standby.
Write Program or Erase Setup command.
Write valid address and data (for program) or Erase Confirm command.
Automated program/erase delay.
Read status register data (SRD) to determine program/erase operation completion.
OE# and CE# must be asserted and WE# must be deasserted for read operations.
CLK is ignored (but can be kept active/toggling).
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
41
28F640W30, 28F320W30, 28F128W30
Figure 17.
Asynchronous Read to Write Operation Waveform
R1
R2
W5
W8
Address [A]
CE# [E}
R3
R8
R4
R9
OE# [G]
W3
W2
W6
WE# [W]
R7
R6
W7
R10
W4
Data [D/Q]
RST# [P]
Q
D
R5
Figure 18.
Asynchronous Write to Read Operation
W5
W8
R1
Address [A]
W2
W6
R10
CE# [E}
W3
W18
WE# [W]
W14
OE# [G]
R4
R2
R3
W7
R9
W4
R8
Data [D/Q]
RST# [P]
D
Q
W1
June 2005
42
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 19.
Synchronous Read to Write Operation
Latency Count
R301
R302
R306
CLK[C]
R2
W5
R101
W18
Address [A]
R105
R106
R102
R104
W20
ADV# [V]
R303
R3
R11
W6
CE# [E]
R4
R8
OE# [G]
W15
W19
W9
W3
W2
W8
WE#
R12
R307
R304
WAIT [T]
R13
R7
R305
W7
Data [D/Q]
Q
D
D
Figure 20.
Synchronous Write To Read Operation
Latency Count
R2
R302
R301
CLK
W5
W8
R306
Address [A]
ADV#
W20
R106
R104
W6
R303
W2
R11
CE# [E}
W18
W19
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R12
R307
W7
R304
R304
R305
W4
R3
Data [D/Q]
RST# [P]
D
Q
Q
W1
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
43
28F640W30, 28F320W30, 28F128W30
7.4
Erase and Program Times
Table 14.
Erase and Program Times
VPPL
VPPH
Operation
Symbol
Parameter
Description1
Notes
Unit
Typ
Max
Typ
Max
Erasing and Suspending
W500
Erase Time
tERS/PB
tERS/MB
tSUSP/P
tSUSP/E
4-Kword Parameter Block
32-Kword Main Block
Program Suspend
2,3
2,3
2
0.3
0.7
5
2.5
4
0.25
0.4
5
2.5
4
s
W501
s
W600
10
20
10
20
µs
µs
Suspend
Latency
W601
Erase Suspend
2
5
5
Programming
W200
tPROG/W
tPROG/PB
tPROG/MB
Single Word
2
12
0.05
0.4
150
.23
1.8
8
130
0.07
0.6
µs
s
Program
Time
W201
4-Kword Parameter Block
32-Kword Main Block
2,3
2,3
0.03
0.24
W202
s
Enhanced Factory Programming5
W400
W401
W402
W403
W404
W405
tEFP/W
Single Word
4
2,3
2,3
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.5
15
16
-
µs
ms
ms
µs
Program
tEFP/PB
tEFP/MB
tEFP/SETUP
tEFP/TRAN
tEFP/VERIFY
4-Kword Parameter Block
32-Kword Main Block
EFP Setup
120
-
-
5
Operation
Latency
Program to Verify Transition
Verify
-
2.7
1.7
5.6
130
µs
-
µs
Notes:
1.
Unless noted otherwise, all parameters are measured at TA = +25 °C and nominal voltages, and are sampled, not 100%
tested.
2.
3.
4.
Excludes external system-level overhead.
Exact results might vary based on system overhead.
W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming
within a new word-line.
5.
Some EFP performance degradation might occur if block cycling exceeds 10.
June 2005
44
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
8.0
Power and Reset Specifications
Intel® Wireless Flash Memory (W30) devices have a layered approach to power savings that can
significantly reduce overall system power consumption.
• The APS feature reduces power consumption when the flash device is selected but idle.
• If CE# is deasserted, the memory enters its standby mode, where current consumption is even
lower.
• Asserting RST# provides current savings similar to standby mode.
The combination of these features can minimize memory power consumption, and therefore,
overall system power consumption.
8.1
8.2
Active Power
With CE# at V and RST# at V , the flash device is in the active mode. Refer to Section 6.1, “DC
IL
IH
Current Characteristics” on page 27, for I values. When the flash device is in active state, it
consumes the most power from the system. Minimizing flash device active current therefore
reduces system power consumption, especially in battery-powered applications.
CC
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low power operation during a read active state. I
is
CCAPS
the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During
APS, average current is measured over the same time interval 5 µs after the following events:
• There is no internal read, program or erase activity.
• CE# is asserted.
• The address lines are quiescent, and at V or V .
IL
IH
OE# can be driven during APS.
8.3
Standby Power
When CE# is deasserted, the flash device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the
level placed on OE#. Standby current, I , is the average current measured over any 5 ms time
CCS
interval, 5 µs after CE# is deasserted. During standby, average current is measured over the same
time interval 5 µs after CE# is deasserted.
When the flash device is deselected (while CE# is deasserted) during a program or erase operation,
it continues to consume active power until the program or erase operation completes.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
45
28F640W30, 28F320W30, 28F128W30
8.4
Power-Up/Down Characteristics
The flash device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required if V and V are connected together; so it
CC
PP
does not matter whether V or V powers-up first. If V is not connected to the system supply,
PP
CC
PP
then V must attain V
before applying V
and V . Do not drive flash device inputs
CC
CCMIN
CCQ PP
before supply voltage = V
Power supply transitions can occur only when RST# is low.
CCQMIN.
8.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase flash devices,
because the system expects to read from the flash memory when it comes out of reset. If a CPU
reset occurs without a flash memory reset, the CPU is not properly initialized, because the flash
memory might be providing status information instead of array data.
Note:
To allow proper CPU/flash device initialization at system reset, connect RST# to the system CPU
RESET# signal.
System designers must guard against spurious writes when VCC voltages are above V
.
LKO
Because both WE# and CE# must be low for a command write, driving either signal to V inhibits
IH
writes to the flash device. The CUI architecture provides additional protection, because memory
contents can be altered only after successful completion of the two-step command sequences.
The flash device is also disabled until RST# is brought to V , regardless of its control input states.
IH
By holding the flash device in reset (RST# connected to system PowerGood) during power-up/
down, invalid bus conditions during power-up can be masked, providing yet another level of
memory protection.
8.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software, and is not altered by VPP or CE#
transitions or WSM actions. Read-array mode is the power-up default state after the flash device
exits from reset mode or after VCC transitions above V
(Lockout voltage).
LKO
After completing program or block erase operations (even after VPP transitions below V
), the
PPLK
Read Array command must reset the CUI to read-array mode if flash memory array access is
desired.
8.5
Power Supply Decoupling
When the flash device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise.
To minimize the effect of this transient noise, device decoupling capacitors are required. Transient
current magnitudes depend on the flash device output capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection suppresses these transient voltage peaks.
Note:
Each flash device must have a 0.1 µF ceramic capacitor connected between each power (VCC,
VCCQ, VPP) and ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance
,
capacitors must be as close as possible to the package signals.
June 2005
46
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
8.6
Reset Specifications
Table 15.
Reset Specifications
#
Symbol
Parameter1
Notes
Min
Max
Unit
P1
tPLPH
RST# Low to Reset during Read
RST# Low to Reset during Block Erase
RST# Low to Reset during Program
VCC Power Valid to Reset
1, 2, 3, 4
1, 3, 4, 5
1, 3, 4, 5
1,3,4,5,6
100
-
ns
µs
µs
µs
-
-
20
10
-
P2
tPLRH
tVCCPH
P3
60
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all product versions (packages and speeds).
The flash device might reset if tPLPH< tPLPHMin, but this is not guaranteed.
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
If RST# is tied to VCC, the flash device is not ready until tVCCPH occurs after when VCC > VCCMin.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC
VCCMin.
>
Figure 21.
Reset Operations Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
47
28F640W30, 28F320W30, 28F128W30
8.7
AC I/O Test Conditions
Figure 22.
AC Input/Output Reference Waveform
VCCQ
Test Points
Input
VCCQ/2
VCCQ/2
Output
0V
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst case speed conditions are when VCC = VCCMin.
Figure 23.
Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 16 for component values.
Table 16.
Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration
CCQMin Standard Test
CL (pF)
R1 (kΩ)
R1 (kΩ)
V
30
25
25
Note: CL includes jig capacitance.
Figure 24.
Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
June 2005
48
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
8.8
Flash Device Capacitance
T = +25 °C, f = 1 MHz
A
Symbol
CIN
Parameter§
Typ
Max
Unit
Condition
Input Capacitance
Output Capacitance
CE# Input Capacitance
6
8
8
pF
pF
pF
VIN = 0.0 V
VOUT = 0.0 V
VIN = 0.0 V
COUT
CCE
12
12
10
§Sampled, not 100% tested.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
49
28F640W30, 28F320W30, 28F128W30
9.0
Flash Device Operations
This chapter provides an overview of flash device operations. The W30 flash memory device
family includes an on-chip Write State Machine (WSM) to manage block erase and program
algorithms. The WSM Command User Interface (CUI) allows minimal processor overhead with
RAM-like interface timings.
9.1
Bus Operations
Table 17.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
Burst Suspend
VIH
VIH
VIH
VIH
VIH
VIH
VIL
X
L
L
L
L
L
L
L
H
X
L
L
H
H
H
L
Asserted
Driven
Output
Output
Output
Input
-
1
Read
Write
Running
Halted
X
L
H
H
H
X
X
Active
-
X
X
X
X
Asserted
Asserted
High-Z
2
Output Disable
Standby
X
X
X
H
X
X
High-Z
High-Z
High-Z
3
3
Reset
High-Z
3,4
Notes:
1.
2.
3.
4.
WAIT is valid only during synchronous array-read operations.
Refer to the Table 19, “Bus Cycle Definitions” on page 55 for valid DQ[15:0] during a write operation.
X = Don’t Care (H or L).
RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
9.1.1
Read
The W30 flash memory device has several read configurations:
• Asynchronous page mode read.
• Synchronous burst mode read — outputs four, eight, sixteen, or continuous words, from main
blocks and parameter blocks.
Several read modes are available in each partition:
• Read-array mode: read accesses return flash memory array data from the addressed
locations.
• Read identifier mode: reads return manufacturer and device identifier data, block lock status,
and protection register data. Identifier information can be accessed starting at a 4-Mbit
partition base addresses; the flash memory array is not accessible in read identifier mode.
• Read query mode: reads return the flash device CFI data. CFI information can be accessed
starting at a 4-Mbit partition base addresses; the flash memory array is not accessible in read
query mode.
• Read status register mode: reads return status register data from the addressed partition. The
array data for that partition is not accessible. A system processor can check the status register
to determine the state of an addressed partition, or to monitor program and erase progress.
June 2005
50
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
All partitions support the synchronous burst mode that internally sequences addresses with respect
to the input CLK to select and supply data to the outputs.
Identifier codes, query data, and status register read operations execute as single-synchronous or
asynchronous read cycles. WAIT is asserted during these reads.
Access to the modes listed above is independent of V . An appropriate CUI command places the
PP
flash device in a read mode. At initial power-up or after reset, the flash device defaults to
asynchronous read-array mode.
Asserting CE# enables flash device read operations. The flash device internally decodes upper
address inputs to determine which partition is accessed.
• Asserting ADV# opens the internal address latches.
• Asserting OE# activates the outputs, and gates the selected data onto the I/O bus.
• In asynchronous mode, the address is latched when ADV# is deasserted (when the flash device
is configured to use ADV#).
• In synchronous mode, the address is latched by either the rising edge of ADV# or the rising (or
falling) CLK edge while ADV# remains asserted, whichever occurs first.
WE# and RST# must be deasserted during read operations.
Note:
If only asynchronous reads are to be performed in your system, CLK must be tied to a valid V
level, the WAIT signal can be floated, and ADV# must be tied to ground.
IH
9.1.2
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation
if the system needs to use the flash device address and data bus for other purposes. Burst accesses
can be suspended during the initial latency (before data is received) or after the flash device has
output data. When a burst access is suspended, internal array sensing continues and any previously
latched internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at V or V . To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent
IH
IL
CLK edges resume the burst sequence where it left off.
Within the flash device, CE# gates the WAIT signal. Therefore, during Burst Suspend, WAIT
remains asserted and does not revert to a high-impedance state when OE# is deasserted. This WAIT
state can cause contention with another flash device attempting to control the system READY
signal during a Burst Suspend. System using the Burst Suspend feature must not connect the flash
device WAIT signal directly to the system READY signal.
Refer to Figure 15, “Burst Suspend” on page 39.
9.1.3
Standby
De-asserting CE# deselects the flash device and places it in standby mode, substantially reducing
flash device power consumption. In standby mode, outputs are placed in a high-impedance state
independent of OE#. If deselected during a program or erase algorithm, the flash device consumes
active power until the program or erase operation completes.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
51
28F640W30, 28F320W30, 28F128W30
9.1.4
Reset
The flash device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is
turned off and outputs are placed in a high-impedance state.
After returning from reset, a time t
is required until outputs are valid, and a delay (t
) is
PHQV
PHWV
required before a write sequence can be initiated. After this wake-up interval, normal operation is
restored. The flash device defaults to read-array mode, the status register is set to 80h, and the Read
Configuration Register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See Figure 21, “Reset Operations Waveforms”
on page 47 for detailed information regarding reset timings.
As on any automated device, RST# must be asserted during system reset. When the system comes
out of reset, the processor expects to read from the flash memory array. Automated flash memory
devices provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, the CPU might not be properly initialized, because the flash
memory device might be providing status information instead of array data. 1.8 Volt Intel Flash
memory devices allow proper CPU initialization following a system reset through the use of the
RST# input. In this application, RST# is controlled by the same CPU reset signal, RESET#.
9.1.5
Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash memory control
commands are written to the CUI using standard microprocessor write timings. Proper use of the
ADV# input is needed for proper latching of the addresses. Refer to Section 7.3, “AC Write
Characteristics” on page 40 for details. The address and data are latched on the rising edge of WE#.
Write operations are asynchronous; CLK is ignored (but can be kept active/toggling).
The CUI does not occupy an addressable memory location within any partition. The system
processor must access it at the correct address range, depending on the kind of command executed.
Programming or erasing can occur in only one partition at a time. Other partitions must be in one of
the read modes or erase suspend mode.
Table 18, “Command Codes and Descriptions” on page 53 shows the available commands.
Appendix A, “Write State Machine” on page 90 provides information about moving between
different operating modes using CUI commands.
9.2
Flash Device Commands
The flash device on-chip WSM manages erase and program algorithms. This local CPU (WSM)
controls the flash device in-system read, program, and erase operations. Bus cycles to or from the
flash memory device conform to standard microprocessor bus cycles. The RST#, CE#, OE#, WE#,
and ADV# control signals dictate data flow into and out of the flash device. WAIT informs the
CPU of valid data during burst reads. Table 17, “Bus Operations Summary” on page 50
summarizes bus operations.
To select flash device operations, write specific commands into the flash device CUI. Table 18,
“Command Codes and Descriptions” on page 53 lists all possible command codes and
descriptions. Table 19, “Bus Cycle Definitions” on page 55 lists command definitions. Because
commands are partition-specific, you must issue write commands within the target address range.
June 2005
52
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 18.
Command Codes and Descriptions (Sheet 1 of 2)
Flash Device
Command
Operation
Code
Description
FFh
70h
Read Array
Places the selected partition in read-array mode.
Read Status
Register
Places the selected partition in status register read mode. The partition enters this
mode after a Program or Erase command is issued to it.
Places the selected partition in read identifier mode. Flash device reads from
Read Identifier partition addresses output the manufacturer/device codes, configuration register
data, block lock status, or protection register data on D[15:0].
90h
98h
Read
Places the addressed partition in read query mode. Flash device reads from the
Read Query
partition addresses output the CFI information on D[7:0].
The WSM can set the block lock (SR[1]), VPP (SR[3]), program (SR[4]), and
Clear Status
Register
erase (SR[5]) status bits of the status register, but WSM cannot clear these bits.
SR[5:3,1] can be cleared only by a flash device reset or through the Clear Status
Register command.
50h
40h
•
The first cycle of this preferred program command prepares the CUI for a
program operation.
Word Program
Setup
•
The second cycle latches the address and data, and executes the WSM
program algorithm at this location.
Status register updates occur when CE# or OE# is toggled. After programming,
use a Read Array command to read the array data.
Alternate
Setup
10h
30h
Equivalent to a Program Setup command (40h).
Program
This program command activates EFP mode.
•
•
The first write cycle sets up the command.
EFP Setup
If the second cycle is an EFP Confirm command (D0h), subsequent writes
provide program data.
All other commands are ignored after EFP mode begins.
If the first command was EFP Setup (30h), the CUI latches the address and data,
and prepares the flash device for EFP mode.
D0h
20h
EFP Confirm
Erase Setup
This command prepares the CUI for Block Erase. The flash device erases the
block that the Erase Confirm command addresses. If the next command is not
Erase Confirm, the CUI sets status register bits SR[5:4] to indicate a command
sequence error, and places the partition in the read status register mode.
Erase
If the first command was Erase Setup (20h), the CUI latches the address and
data, and erases the block indicated by the erase confirm cycle address. During
D0h
Erase Confirm program or erase, the partition responds only to Read Status Register, Program
Suspend, and Erase Suspend commands. CE# or OE# toggle updates the status
register data.
This command, issued at any flash device address, suspends the currently
executing program or erase operation. Status register data indicates that the
operation was successfully suspended if SR[2] (program suspend) or SR[6]
(erase suspend) and SR[7] are set. The WSM remains in the suspended state
Program
Suspend or
Erase
Suspend
B0h
D0h
Suspend
regardless of the control signal states (except RST#).
Suspend
Resume
This command, issued at any flash device address, resumes the suspended
program or erase operation.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
53
28F640W30, 28F320W30, 28F128W30
Table 18.
Command Codes and Descriptions (Sheet 2 of 2)
Flash Device
Command
Operation
Code
Description
This command prepares the CUI lock configuration. If the next command is not
Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate a
command sequence error.
60h
01h
D0h
2Fh
Lock Setup
Lock Block
Unlock Block
Lock-Down
If the previous command was Lock Setup (60h), the CUI locks the addressed
block.
Block Locking
If the previous command was Lock Setup (60h), the CUI latches the address and
unlocks the addressed block. If previously locked-down, the operation has no
effect.
If the previous command was Lock Setup (60h), the CUI latches the address and
locks-down the addressed block.
This command prepares the CUI for a protection register program operation. The
second cycle latches address and data, and starts the WSM protection register
program or lock algorithm. Toggling CE# or OE# updates the flash device status
register data. To read array data after programming, issue a Read Array
command.
Protection
Program
Setup
Protection
C0h
This command prepares the CUI for flash device configuration. If Set
Configuration Register is not the next command, the CUI sets SR[5:4] to indicate
a command sequence error.
Configuration
Setup
60h
03h
Configuration
Set
Configuration
Register
If the previous command was Configuration Setup (60h), the CUI latches the
address and writes the data from A[15:0] into the configuration register.
Subsequent read operations access the array data.
Note: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.
June 2005
54
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 19.
Bus Cycle Definitions
First Bus Cycle
Second Bus Cycle
Bus
Operation
Command
Cycles
Oper
Addr1
Data2,3
Oper
Addr1
Data2,3
Read
Address
Array
Data
Read Array/Reset
> 1
Write
PnA
FFh
Read
Read Identifier
> 2
> 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
PnA
PnA
PnA
XX
90h
98h
Read
Read
Read
PBA+IA
PBA+QA
PnA
IC
Read
Read Query
QD
Read Status Register
Clear Status Register
Block Erase
70h
SRD
1
50h
2
BA
20h
Write
Write
Write
BA
WA
WA
D0h
WD
D0h
Word Program
2
WA
WA
XX
40h/10h
30h
Program
and
Erase
EFP
>2
1
Program/Erase Suspend
Program/Erase Resume
Lock Block
B0h
D0h
60h
1
XX
2
BA
Write
Write
Write
Write
Write
BA
BA
BA
PA
01h
D0h
Lock
Unlock Block
2
BA
60h
Lock-Down Block
Protection Program
Lock Protection Program
2
BA
60h
2Fh
2
PA
C0h
C0h
PD
Protection
2
LPA
LPA
FFFDh
Set Configuration
Register
Configuration
2
Write
CD
60h
Write
CD
03h
Notes:
1.
First-cycle command addresses must be the same as the target address of the operation. Examples:
—The first-cycle address for the Read Identifier command must be the same as the Identification code address (IA).
—The first-cycle address for the Word Program command must be the same as the word address (WA) to be
programmed.
—The first-cycle address for the Erase/Program Suspend command must be the same as the address within the block
to be suspended.
XX
IA
BA
= Any valid address within the flash device.
= Identification code address.
= Block Address. Any address within a specific block.
LPA = The Lock Protection Address is obtained from the CFI (through the Read Query command). The W30 flash
memory device family LPA is at 0080h.
PA
= User programmable 4-word protection address.
PnA = Any address within a specific partition.
PBA = Partition Base Address. The first address of a particular partition.
QA
WA
= Query code address.
= Word address of memory location to be written.
2.
3.
SRD = Status register data.
WD
IC
PD
QD
CD
= Data to be written at location WA.
= Identifier code data.
= User programmable 4-word protection data.
= Query code data on D[7:0].
= Configuration register code data presented on flash device addresses A[15:0]. A[MAX:16] address bits can
select any partition. See Table 27, “Read Configuration Register Definitions” on page 81 for configuration
register bits descriptions.
Do not use commands other than those shown above. Other commands are reserved by Intel for future flash device
implementations.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
55
28F640W30, 28F320W30, 28F128W30
9.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation can occur between the
two write cycles. The setup phase of a 2-cycle write sequence places the addressed partition into
read-status mode, so if the same partition is read before the second confirm write cycle is issued,
status register data is returned. Reads from other partitions, however, can return actual array data, if
the addressed partition is already in read-array mode. Figure 25 and Figure 26 illustrate these two
conditions.
Figure 25.
Normal Write and Read Cycles
Address [A]
WE# [W]
OE# [G]
Partition A
Partition A
Partition A
Data [Q]
20h
Block Erase Setup
D0h
Block Erase Conf irm
FFh
Read Array
Figure 26.
Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A]
WE# [W]
OE# [G]
Partition B
Partition A
Partition B
Partition A
Data [Q]
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Confirm
By contrast, a write bus cycle must not interrupt a 2-cycle write sequence. Such an interruption
causes a command sequence error to appear in the status register. Figure 27 illustrates a command
sequence error.
Figure 27.
Improper Command Sequencing
Address [A]
WE# [W]
Partition X
Partition Y
Partition X
Partition X
OE# [G]
Data [D/Q]
20h
FFh
D0h
SR Data
June 2005
56
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
10.0
Read Operations
10.1
Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read
data from the flash memory array. Upon initial flash device power-up, or after reset (RST#
transitions from V to V ), all partitions default to asynchronous read-array mode.
IL
IH
To read array data from the flash device:
1. Write the Read Array command (FFh) to the CUI and specify the desired word address.
1. Read from that address.
Note:
If a partition is already in read-array mode, you do not need to issue the Read Array command to
read from that partition.
If the Read Array command is written to a partition that is erasing or programming, the flash device
presents invalid data on the bus until the program or erase operation completes.
After the program or erase finishes in that partition, valid array data can then be read. If an Erase
Suspend or Program Suspend command suspends the WSM, a subsequent Read Array command
places the addressed partition in read-array mode.
The Read Array command functions independently of V .
PP
10.2
Read Device ID
The read identifier mode outputs the manufacturer/device identifier, block lock status, protection
register codes, and configuration register data. The identifier information is contained within a
separate memory space on the flash device, and can be accessed along the 4-Mbit partition address
range supplied by the Read Identifier command (90h) address. Reads from addresses in Table 20
retrieve ID information. Issuing a Read Identifier command to a partition that is programming or
erasing places the outputs of that partition in read ID mode while the partition continues to program
or erase in the background.
Table 20.
Flash Device Identification Codes (Sheet 1 of 2)
Address1
Item
Data
Description
Base
Offset
Manufacturer ID
Partition
00h
0089h
8852h
8853h
8854h
8855h
8856h
8857h
Intel
32-Mbit TPD
32-Mbit BPD
64-Mbit TPD
64-Mbit BPD
128-Mbit TPD
128-Mbit BPD
Device ID
Partition
01h
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
57
28F640W30, 28F320W30, 28F128W30
Table 20.
Flash Device Identification Codes (Sheet 2 of 2)
Address1
Item
Data
Description
Base
Offset
D0 = 0
D0 = 1
Block is unlocked
Block Lock Status(2)
Block
Block
02h
Block is locked
D1 = 0
Block is not locked-down
Block is locked down
Block Lock-Down Status(2)
02h
D1 = 1
Configuration Register
Partition
Partition
05h
80h
Register Data
Lock Data
Protection Register Lock Status
Multiple reads required to read
Register Data the entire 128-bit Protection
Register.
Protection Register
Partition
81h - 88h
Notes:
1.
The address is constructed from a base address plus an offset. For example, to read the Block Lock
Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h),
which in this example is 0F8002h. Then examine bit 0 of the data to determine whether the block is
locked.
2.
See Section 13.1.4, “Block Lock Status” on page 75 for valid lock status.
10.3
Read Query (CFI)
The W30 flash memory device contains a separate CFI query database that acts as an on-chip
datasheet. To access the CFI information within the W30 flash memory device, issue the Read
Query command and supply a specific address.
The address is constructed from the base address of a partition plus a particular offset
corresponding to the desired CFI field.
Appendix B, “Common Flash Interface” on page 93 shows accessible CFI fields and their address
offsets. Issuing the Read Query command to a partition that is programming or erasing puts that
partition in read query mode while the partition continues to program or erase in the background.
10.4
Read Status Register
The flash device status register displays program and erase operation status. The status of a
partition can be read after writing the Read Status Register command to any location within the
address range of that partition. Read-status mode is the default read mode following a Program,
Erase, or Lock Block command sequence. Subsequent single reads from that partition return the
partition status until another valid command is written.
The read-status mode supports single synchronous and single asynchronous reads only; it does not
support burst reads.
The first falling edge of OE# or CE# latches and updates Status Register data. The operation does
not affect the modes of other partitions. Because the Status Register is 8 bits wide, only DQ [7:0]
contain valid status register data; DQ [15:8] contain zeros. See Table 21, “Status Register
Definitions” on page 59 and Table 22, “Status Register Descriptions” on page 59.
June 2005
58
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but
SR[7], the Device WSM Status (DWS) bit, pertains to the entire flash memory device. SR[7]
provides the program and erase status of the entire flash device. By contrast, the Partition WSM
Status (PWS) bit, SR[0], provides program and erase status of the addressed partition only. Status
register bits SR[6:1] present information about partition-specific program, erase, suspend, V , and
PP
block-lock states. Table 23, “Status Register Device WSM and Partition Write Status Description”
on page 60 describes the DWS (SR[7]) and PWS (SR[0]) combinations.
Table 21.
Status Register Definitions
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
DPS
1
PWS
0
Table 22.
Status Register Descriptions
Bit
Name
State
Description
•
•
SR[7] indicates erase or program completion in
the flash device.
DWS
0 = Device WSM is Busy
1 = Device WSM is Ready
7
SR[6:1] are invalid while SR[7] = 0.
Device WSM Status
See Table 23 for valid SR[7] and SR[0] combinations.
After issuing an Erase Suspend command, the WSM
halts and sets SR[7] and SR[6]. SR[6] remains set until
the flash device receives an Erase Resume command.
ESS
0 = Erase in progress/completed
6
Erase Suspend Status 1 = Erase suspended
•
•
SR[5] is set if an attempted erase failed.
ES
0 = Erase successful
1 = Erase error
5
4
A Command Sequence Error is indicated when
SR[7,5:4] are set.
Erase Status
PS
0 = Program successful
1 = Program error
SR[4] is set if the WSM failed to program a word.
Program Status
The WSM indicates the VPP level after program or
erase completes.
VPPS
0 = VPP OK
3
VPP Status
1 = VPP low detect, operation aborted
SR[3] does not provide continuous VPP feedback and
is not guaranteed when VPP≠VPPL/VPPH
PSS
After receiving a Program Suspend command, the
WSM halts execution and sets SR[7] and SR[2]. These
bits remain set until a Resume command is received.
0 = Program in progress/completed
1 = Program suspended
2
1
Program Suspend
Status
0 = Unlocked
If an erase or program operation is attempted to a
locked block (if WP# = VIL), the WSM sets SR[1] and
aborts the operation.
DPS
1 = Aborted erase/program attempt on
a locked block
Device Protect Status
The addressed partition is erasing or programming. In
EFP mode, SR[0] indicates that a data-stream word
has finished programming or verifying, depending on
the particular EFP phase.
0 = This partition is busy, but only if
SR[7]=0
PWS
0
Partition Write Status 1 = Another partition is busy, but only if
SR[7]=0
See Table 23 for valid SR[7] and SR[0] combinations.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
59
28F640W30, 28F320W30, 28F128W30
Table 23.
Status Register Device WSM and Partition Write Status Description
DWS
(SR[7])
PWS
(SR[0])
Description
The addressed partition is performing a program/erase operation.
0
0
0
1
EFP: the flash device has finished programming or verifying data, or is ready for data.
A partition other than the one currently addressed is performing a program/erase operation.
EFP: the flash device is either programming or verifying data.
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])
indicate whether other partitions are suspended.
1
1
0
1
EFP: the flash device has exited EFP mode.
Does not occur in standard program or erase modes.
EFP: this combination does not occur.
10.5
Clear Status Register
The Clear Status Register command clears the status register and leaves all partition output states
unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits
SR[5,4,3,1] indicate various error conditions, they can be cleared only by the Clear Status Register
command. By allowing system software to reset these bits, several operations (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) can be
performed before reading the status register to determine whether an error occurred.
If an error is detected, the Status Register must be cleared before beginning another command or
sequence. Flash device reset (RST# = V ) also clears the status register. This command functions
IL
independently of V .
PP
June 2005
60
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
11.0
Program Operations
11.1
Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed
events to program a word at the desired address, and to verify that the bits are sufficiently
programmed. Programming the flash memory array changes specifically addressed bits to 0; 1 bits
do not change the memory cell contents.
Programming can occur in only one partition at a time. All other partitions must be in either a read
mode or erase suspend mode. Only one partition can be in erase suspend mode at a time.
To examine the status register can be examined for program progress, read any address within the
partition that is busy programming. However, while most status register bits are partition-specific,
the Device WSM Status bit, SR[7], is device-specific. That is, if the status register is read from any
other partition, SR[7] indicates the program status of the entire flash memory device. This status bit
permits the system CPU to monitor the program progress while reading the status of other
partitions.
CE# or OE# toggle (during polling) updates the status register. Several commands can be issued to
a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and Read
Query. The Read Array command can also be issued, but the read data is indeterminate.
After programming completes, three status register bits can signify various possible error
conditions:
• SR[4] indicates a program failure if set.
• If SR[3] is set, the WSM could not execute the Word Program command, because V was
PP
outside the acceptable limits.
• If SR[1] is set, the program was aborted, because the WSM attempted to program a locked
block.
After the status register data is examined, clear it using the Clear Status Register command before
issuing a new command. The partition remains in status register mode until another command is
written to that partition. Any command can be issued after the status register indicates program
completion.
If CE# is deasserted while the flash device is programming, the flash devices do not enter standby
mode until the program operation completes.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
61
28F640W30, 28F320W30, 28F128W30
Figure 28.
Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = 40h
Write
Write
Read
Setup
Data
Addr = Location to program (WA)
Write 40h,
Word Address
Data = Data to program (WD)
Addr = Location to program (WA)
Write Data
Word Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Program
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Yes
Suspend
Program
0
SR[7] =
1
Repeat for subsequent programming operations.
Full status register check can be done after each program or
after a sequence of program operations.
Full Program
Status Check
(if desired)
Program
Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
VPP Range
Error
1
1
1
SR[3] =
0
Check SR[4]
1 = Data program error
Check SR[1]
Program
Error
SR[4] =
0
Standby
1 = Attempted program to locked block
Program aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts
Device
Protect Error
SR[1] =
0
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
June 2005
62
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
11.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When V is at V , program and erase currents are drawn through
PP
PPL
VCC. If VPP is driven by a logic signal, V
must remain above the V Min value to perform
PPL
PPL
in-system flash memory modifications. When VPP is connected to a 12 V power supply, the flash
device draws program and erase current directly from VPP, which eliminates the need for an
external switching transistor to control the V voltage.
PP
Figure 37, “Examples of VPP Power Supply Configurations” on page 80 shows examples of flash
device power supply usage in various configurations.
The 12-V V mode enhances programming performance during the short time period typically
PP
found in manufacturing processes. However, this mode is not intended for extended use.12 V can
be applied to V during program and erase operations as specified in Section 5.2, “Operating
PP
Conditions” on page 26. VPP can be connected to 12 V for a total of t
hours maximum.
PPH
Stressing the flash device beyond these limits might cause permanent damage.
11.3
Enhanced Factory Program (EFP)
EFP substantially improves flash device programming performance through a number of
enhancements to the conventional 12-Volt word program algorithm. The more efficient WSM
algorithm in EFP eliminates the traditional overhead delays of the conventional word program
mode in both the host programming system and the flash device. Changes to the conventional word
programming flowchart and internal WSM routine were developed because of today's beat-rate-
sensitive manufacturing environments; a balance between programming speed and cycling
performance was attained.
The host programmer writes data to the flash device and checks the Status Register to determine
when the data has completed programming. This modification cuts write bus cycles approximately
in half.
• Following each internal program pulse, the WSM increments the flash device address to the
next physical location.
• Programming equipment can then sequentially stream program data throughout an entire block
without having to setup and present each new address.
In combination, these enhancements reduce much of the host programmer overhead, enabling more
of a data streaming approach to flash device programming.
EFP further speeds up programming by performing internal code verification. With this feature,
PROM programmers can rely on the flash device to verify that it has been programmed properly.
From the flash device side, EFP streamlines internal overhead by eliminating the delays previously
associated with switching voltages between programming and verify levels at each memory-word
location.
EFP consists of four phases: setup, program, verify, and exit. Refer to Figure 29, “Enhanced
Factory Program Flowchart” on page 66 for a detailed graphical representation of how to
implement EFP.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
63
28F640W30, 28F320W30, 28F128W30
11.3.1
EFP Requirements and Considerations
Table 24.
EFP Requirements and Considerations
EFP Requirements
EFP Considerations
Ambient temperature: TA = 25 °C ±5 °C Block cycling below 100 erase cycles 1
VCC within specified operating range
VPP within specified VPPH range
Target block unlocked
RWW not supported2
EFP programs one block at a time
EFP cannot be suspended
1.
Recommended for optimum performance. Some degradation in
performance might occur if this limit is exceeded, but the internal
algorithm will continue to work properly.
2.
Code or data cannot be read from another partition during EFP.
11.3.2
Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions
from a 1 to a 0, indicating that the WSM is busy with EFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM time to perform all of its setups and checks (V
PP
level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1]
are set, and the EFP operation terminates.
Note:
After the EFP Setup and Confirm command sequence, reads from the flash device automatically
output status register data. Do not issue the Read Status Register command, because this command
is interpreted as data to program at WA .
0
11.3.3
Program
After setup completion, the host programming system must check SR[0] to determine the
data-stream ready status (SR[0]=0). Each subsequent write after this check is a program-data write
to the flash memory array. Each cell within the memory word to be programmed to 0 receives one
WSM pulse; additional pulses, if required, occur in the verify phase.
SR[0]=1 indicates that the WSM is busy applying the program pulse.
The host programmer must poll the flash device status register for the program done state after
each data-stream write.
SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location have
received their single WSM program pulse, and that the flash device is ready for the next word.
Although the host can check full status for errors at any time, this check is necessary only on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside of the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
June 2005
64
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
The address can either remain constant or increment. The flash device compares the incoming
address to the address stored from the setup phase (WA ).
0
• If the addresses match, the WSM programs the new data word at the next sequential memory
location.
• If the addresses differ, the WSM jumps to the new address location.
The program phase concludes when the host programming system writes to a different block
address. The data supplied must be FFFFh. Upon program phase completion, the flash device
enters the EFP verify phase.
11.3.4
Verify
A high percentage of the flash memory bits program on the first WSM pulse. However, EFP
internal verification identifies cells that do not completely program on their first attempt, and
applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of programming
incoming data, the WSM compares the verify-stream data to the data that was previously
programmed into the block.
• If the data compares correctly, the host programmer proceeds to the next word.
• If the data does not match, the host waits while the WSM applies one or more additional
pulses.
The host programmer must reset its initial verify-word address to the same starting location
supplied during the program phase. It then reissues each data word in the same order as during the
program phase. Like programming, the host can write each subsequent data word to WA or it can
0
increment through the block addresses.
The verification phase concludes when the interfacing programmer writes to a different block
address. The data supplied must be FFFFh. Upon completion of the verify phase, the flash device
enters the EFP exit phase.
11.3.5
Exit
SR[7]=1 indicates that the flash device has returned to normal operating conditions. Perform a full
status check at this time, to verify that the entire block programmed successfully. After EFP exit,
any valid CUI command can be issued.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
65
28F640W30, 28F320W30, 28F128W30
Figure 29.
Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE
EFP Setup
EFP Program
EFP Verify
EFP Exit
Read
Status Register
Read
Status Register
Read
Status Register
Start
VPP = 12V
Unlock Block
SR[0]=1=N
SR[0]=1=N
SR[7]=0=N
Data Stream
Ready?
Verify Stream
Ready?
EFP
Exited?
SR[0] =0=Y
SR[0] =0=Y
SR[7]=1=Y
Write 30h
Address = WA 0
Write Data
Address = WA 0
Write Data
Address = WA 0
Full Status Check
Procedure
Write D0h
Address = WA 0
Read
Status Register
Read
Status Register
Operation
Complete
EFP setup time
Program
Done?
Verify
Done?
Read
Status Register
SR[0]=0=Y
SR[0]=0=Y
N
N
Last
Data?
Last
Data?
EFP Setup
Done?
Y
Y
SR[7]=1=N
Check VPP & Lock
errors (SR[3,1])
Write FFFFh
Write FFFFh
Address ≠ BBA
Address
≠
BBA
Exit
EFP Setup
EFP Program
EFP Verify
Bus
State
Bus
State
Bus
State
Comments
Comments
Comments
Read
Status Register
Check SR[0]
Read
Status Register
Verify Check SR[0]
Unlock VPP = 12V
Block Unlock block
Write
Data
Standby Stream 0 = Ready for data
Ready? 1 = Not ready for data
Standby Stream 0 = Ready for verify
Ready? 1 = Not ready for verify
EFP
Data = 30h
Write
Write
Setup Address = WA 0
EFP Data = D0h
Confirm Address = WA 0
Write
Data = Data to program
Address = WA 0
Write
Data = Word to verify
Address = WA 0
(note 1)
(note 2)
Read
Status Register
Read
Status Register
Standby
Read
EFP setup time
Check SR[0]
0 = Program done
1 = Program not done
Check SR[0]
0 = Verify done
1 = Verify not done
Program
Done?
Standby
(note 3) Done?
Verify
Status Register
Standby
EFP
Check SR[7]
Standby
Setup 0 = EFP ready
Done? 1 = EFP not ready
Last
Device automatically
Last
Device automatically
Standby
Standby
Data? increments address.
Data? increments address.
If SR[7] = 1:
Error
Exit Data = FFFFh
Write Program Address not within same
Phase BBA
Exit Data = FFFFh
Verify Address not within same
Phase BBA
Check SR[3,1]
Standby Condition
Check
Write
SR[3] = 1 = V PP error
SR[1] = 1 = locked block
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur , the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal to
Read
Status Register
Check SR[7]
EFP
Standby
0 = Exit not finished
Exited?
1 = Exit completed
Repeat for subsequent operations.
WA
After EFP exit, a Full Status Check can
determine if any program error occurred.
terminates the EFP verify phase, and instructs the device to exit EFP
.
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
See the Full Status Check procedure in the
Word Program flowchart.
June 2005
66
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
12.0
Program and Erase Operations
12.1
Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase
operation. The command can be issued at any flash device address. The partition corresponding to
the address of the command remains in its previous state. A suspend command allows data to be
accessed from memory locations other than the location being programmed or the block being
erased.
• A program operation can be suspended only to perform a read operation.
• An erase operation can be suspended to perform either a program or a read operation within
any block, except the block that is erase suspended.
• A program command nested within a suspended erase can subsequently be suspended to read
yet another location.
Once a program or erase process starts, the Suspend command requests that the WSM suspends the
program or erase sequence at predetermined points in the algorithm. The partition that is actually
suspended continues to output status register data after the Suspend command is written. An
operation is suspended when status bits SR[7] and SR[6] and/or SR[2] are set.
To read data from blocks within the partition (other than an erase-suspended block), write a Read
Array command. Block erase cannot resume until the program operations initiated during erase
suspend are complete.
• Read Array, Read Status Register, Read Identifier (ID), Read Query, and Program Resume are
valid commands during Program or Erase Suspend.
• Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block,
Unlock Block, and Lock-Down Block are valid commands during erase suspend.
To read data from a block in a partition that is not programming or erasing, the operation does not
need to be suspended.
• If the other partition is already in read array, ID, or Query mode, issuing a valid address returns
corresponding data.
• If the other partition is not in a read mode, one of the read commands must be issued to the
partition before data can be read.
During a suspend, CE# = V places the flash device in standby state, which reduces active current.
IH
V
must remain at its program level and WP# must remain unchanged while in suspend mode.
PP
A resume command instructs the WSM to continue programming or erasing, and clears status
register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition.
When read at the partition that is programming or erasing, the flash device outputs data
corresponding to the last mode for that partition. If the status register error bits are set, the status
register can be cleared before issuing the next instruction. RST# must remain at V . See Figure
IH
30, “Program Suspend / Resume Flowchart” on page 68, and Figure 31, “Erase Suspend / Resume
Flowchart” on page 69.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
67
28F640W30, 28F320W30, 28F128W30
If a suspended partition was placed in Read Array, Read Status Register, Read Identifier (ID), or
Read Query during the suspend, the flash device remains in that mode, and outputs data
corresponding to that mode after the program or erase operation resumes.
After resuming a suspended operation, issue the read command appropriate to the read operation.
To read status after resuming a suspended operation, issue a Read Status Register command (70h)
to return the suspended partition to status mode.
Figure 30.
Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Start
Command
Comments
Operation
Data = B0h
Addr = Any address within programming
partition
Program
Suspend
Write
Write B0h
Any Address
Read
Data = 70h
Write
Read
Status Addr = Any address in same partition
Write 70h
Same Partition
Read SRD
Toggle CE# or OE# to update SRD
Addr = Any address in same partition
Read Status
Register
Check SR[7]
Standby
Standby
1 = WSM ready
0 = WSM busy
0
0
SR[7] =
1
Check SR[2]
1 = Program suspended
0 = Program completed
Program
Completed
SR[2] =
1
Data = FFh
Addr = Any device address (except word
being programmed)
Read
Array
Write
Read
Write
Write FFh
Susp Partition
Read array data from block other than
the one being programmed
Read Array
Data
Program Data = D0h
Resume Addr = any device address
If the suspended partition was placed in Read Array mode:
Done
No
Reading
Return partition to status mode:
Read
Write
Data = 70h
Yes
Status
Addr = address within same partition
Write D0h
Write FFh
Any Address
Pgm'd Partition
Program
Resumed
Read Array
Data
Write 70h
Same Partition
June 2005
68
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 31.
Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Erase Data = B0h
Suspend Addr = Any address
Write
Write
Write B0h
Any Address
Read Data = 70h
Status Addr = Any address in same partition
Write 70h
Same Partition
Read SRD
Read
Toggle CE# or OE# to update SRD
Addr = Any address in same partition
Read Status
Register
Check SR[7]
Standby
1 = WSM ready
0 = WSM busy
0
0
SR[7] =
1
Check SR[6]
1 = Erase suspended
0 = Erase completed
Standby
Write
Erase
Completed
SR[6] =
1
Data = FFh or 40h
Read Array
Addr = Any device address (except
or Program
block being erased)
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
Read Array
Data
Program
Loop
Erase Data = D0h
Resume Addr = Any address
No
Write
If the suspended partition was placed in
Read Array mode or a Program Loop:
Done?
Yes
Return partition to status mode:
Data = 70h
Status
Read
Write
Write D0h
Any Address
Write FFh
Erased Partition
Addr = Address within same partition
Read Array
Data
Erase Resumed
Write 70h
Same Partition
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
69
28F640W30, 28F320W30, 28F128W30
12.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm
(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode
at a time; other partitions must be in a read mode. The Erase Confirm command internally latches
the address of the block to erase. Erase forces all bits within the block to 1.
SR[7] is cleared while the erase executes.
After writing the Erase Confirm command, the selected partition is placed in read status register
mode. Reads performed to that partition return the current status data. The address given during the
Erase Confirm command does not need to be the same address used in the Erase Setup command.
For example, if the Erase Confirm command is given to partition B, then the selected block in
partition B is erased, even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, to
execute properly, an Erase Setup command must be immediately followed by the Erase Confirm
command. If a different command is issued between the setup and confirm commands, the
following occurs:
• The partition is placed in read-status mode.
• The status register signals a command sequence error.
• All subsequent erase commands to that partition are ignored until the status register is cleared.
To detect block erase completion, the CPU analyzes SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent status register reads.
June 2005
70
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 32.
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Write
Write
Read
Write 20h
Block Address
Erase
Data = D0h
Confirm Addr = Block to be erased (BA)
Write D0h and
Block Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Erase
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
Standby
VPP Range
Error
1
1
1
1
SR[3] =
0
Check SR[5:4]
Both 1 = Command sequence error
Command
Sequence Error
Check SR[5]
1 = Block erase error
SR[5:4] =
0
Check SR[1]
Standby
1 = Attempted erase of locked block
Erase aborted
Block Erase
Error
SR[5] =
0
SR[3,1] must be cleared before the WSM will allow further
erase attempts.
Erase of
Locked Block
Aborted
SR[1] =
0
Only the Clear Status Register command clears SR[5:3,1].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
71
28F640W30, 28F320W30, 28F128W30
12.3
Read-While-Write and Read-While-Erase
The Intel® Wireless Flash Memory (W30) supports flexible multi-partition dual-operation
architecture. By dividing the flash memory into many separate partitions, the flash device can read
from one partition while programing (Read-While-Write) or erasing (Read-While-Eras) in another
partition. Both of these features greatly enhance data storage performance.
The W30 flash memory device does not support simultaneous program and erase operations.
Attempting to perform operations such as these results in a command sequence error. Only one
partition can be programming or erasing while another partition is reading. However, one partition
can be in erase suspend mode while a second partition is performing a program operation, and yet
another partition is executing a read command. Table 18, “Command Codes and Descriptions” on
page 53 describes the command codes available for all functions.
June 2005
72
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
13.0
Security Modes
The W30 flash memory device offers both hardware and software security features to protect the
flash memory data.
• To use the software security feature, execute the Lock Block command.
• To use the hardware security feature, execute the Lock-Down Block command and assert the
WP# signal.
Refer to Figure 33, “Block Locking State Diagram” on page 74 for a state diagram of the flash
device security features. Also see Figure 34, “Locking Operations Flowchart” on page 77.
13.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection:
• Software-only control of block locking (useful for frequently changed data blocks).
• Hardware interaction before locking can be changed (protects infrequently changed code
blocks).
The following sections discuss the locking system operation. The term state [abc] specifies locking
states, such as state [001]. In this syntax:
• a = WP# value.
• b = block lock-down status bit D1.
• c = Block Lock status register bit D0.
Figure 33, “Block Locking State Diagram” on page 74 defines possible locking states.
The following summarizes the locking functionality.
• All blocks power-up in a locked state.
• Unlock commands can unlock these blocks, and lock commands can lock them again.
• The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP# is
deasserted.
— When WP# is asserted, previously locked-down blocks return to lock-down.
— The lock-down status bit clears only when the flash device is reset or powered-down.
Block lock registers are not affected by the V level. These registers can be modified and read
PP
even if V < V
.
PP
PPLK
The locking status of each block can be set to locked, unlocked, and lock-down, as described in the
following sections. See Figure 34, “Locking Operations Flowchart” on page 77.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
73
28F640W30, 28F320W30, 28F128W30
Figure 33.
Block Locking State Diagram
Locked-
Down
Hardware
Locked
4,5
5
Power-Up/Reset
Locked
[011]
[X01]
[011]
WP# Hardware Control
Software
Locked
Unlocked
Unlocked
[X00]
[111]
[110 ]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
Notes:
1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status.
- D1 = 0, Lock-down has not been issued to this block .
- D1 = 1, Lock-down has been issued to this block .
3. D0 indicates block lock status.
- D0 = 0, block is unlocked.
- D0 = 1, block is locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked -Down states.
B5070
13.1.1
13.1.2
Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully
protected from alteration. Attempted program or erase operations to a locked block return an error
in SR[1].
• To lock unlocked blocks, use the Lock Block command sequence.
• To change the status of a locked block to unlocked or lock-down, use the appropriate software
commands.
Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return
to the locked state when the flash device is reset or powered-down.
• To change the status of an unlocked block to the locked or locked-down state, use the
appropriate software commands.
• To unlock a locked block, write the Unlock Block command sequence if the block is not
locked-down.
June 2005
74
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
13.1.3
Lock-Down
Locked-down blocks (state [011]) offer an additional level of write protection beyond the
protection of a regular locked block. If a block is locked-down, the software cannot change the
state of the block if WP# is asserted.
• To lock-down a locked or unlocked block, write the Lock-Down Block command sequence.
• If a block was set to locked-down, then later changed to unlocked, issue the Lock-down
command before asserting WP#, to put that block back in the locked-down state.
• When WP# is deasserted, locked-down blocks change to the locked state, and can then be
unlocked using the Unlock Block command.
13.1.4
Block Lock Status
The lock status of every block can be read in read identifier mode.
To enter this mode, issue the Read Identifier command to the flash device.
Note:
Subsequent reads at BBA + 02h output the lock status of that block. For example, to read the block
lock status of block 10, the address sent to the flash device must be 50002h (for a top-parameter
device).
The lowest two data bits of the read data, DQ1 and DQ0, represent the lock status.
• DQ0 indicates the block lock status. This bit is set using the Lock Block command and cleared
using the Block Unlock command. It is also set when entering the lock-down state.
• DQ1 indicates lock-down status and is set using the Lock-Down command.
The lock-down status bit cannot be cleared by software–only by a flash device reset or
power-down. See Table 25.
Table 25.
Write Protection Truth Table
VPP
WP#
RST#
Write Protection
Device is inaccessible
X
VIL
X
X
X
VIL
VIH
VIH
VIH
Word program and block erase are prohibited
All lock-down blocks are locked
VIL
VIH
X
All lock-down blocks can be unlocked
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
75
28F640W30, 28F320W30, 28F128W30
13.1.5
Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation, using the standard
locking command sequences to unlock, lock, or lock-down a block. This feature is useful when
another block requires immediate updating.
To change block locking during an erase operation:
1. Write the Erase Suspend command.
2. Check SR[6] to determine that the erase operation has suspended.
3. Write the desired lock command sequence to a block.
The lock status changes.
4. After completing lock, unlock, read, or program operations, resume the erase operation with
the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits change immediately. When the erase operation resumes, it completes normally.
Locking operations cannot occur during program suspend. Appendix A, “Write State Machine” on
page 90 shows valid commands during erase suspend.
13.1.6
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into status register results.
Because locking changes require 2-cycle command sequences—for example, 60h followed by 01h
to lock a block—following the Configuration Setup command (60h) with an invalid command
produces a command sequence error (SR[5:4]=11b).
If a Lock Block command error occurs during erase suspend, the flash device sets SR[4] and SR[5]
to 1 even after the erase resumes. When erase is complete, possible errors during the erase cannot
be detected from the status register, because of the previous locking command error. A similar
situation occurs if a program operation error is nested within an erase suspend.
13.1.7
WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# affects only blocks
that previously had the Lock-Down command written to them.
• After the lock-down status bit is set for a block, asserting WP# forces that block into the
lock-down state [011] and prevents it from being unlocked.
• After WP# is deasserted, the state of the block reverts to locked [111]. Software commands
can then unlock the block (for erase or program operations) and subsequently re-lock it.
Only flash device reset or power-down can clear the lock-down status bit and render WP#
ineffective.
June 2005
76
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Figure 34.
Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Operation
Command
Comments
Write 60h
Block Address
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Write
Write
Write 01,D0,2Fh
Block Address
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Write 90h
BBA + 02h
Write
Read ID Data = 90h
(Optional)
Plane
Addr = BBA + 02h
Read Block Lock
Status
Read
(Optional)
Block Lock Block Lock status data
Status Addr = BBA + 02h
Locking
Change?
No
Confirm locking change on DQ[1:0].
(See Block Locking State Transitions Table
for valid combinations.)
Standby
(Optional)
Yes
Read
Array
Data = FFh
Addr = Any address in same partition
Write
Write FFh
Partition Address
Lock Change
Complete
13.2
Protection Register
The W30 flash memory device includes a 128-bit Protection Register. This protection register is
used to increase system security and for identification purposes. The protection register value can
match the flash device to the system CPU or ASIC to prevent flash device substitution.
• The lower 64 bits within the protection register are programmed by Intel with a unique number
in each flash device.
• The upper 64 OTP bits within the protection register are left for the customer to program.
Once programmed, the customer segment can be locked to prevent further programming.
Note:
The individual bits of the user segment of the protection register are OTP, not the register in total.
The user can program each OTP bit individually, one at a time, if desired. However, after the
protection register is locked, the entire user segment is locked and no more user bits can be
programmed.
The protection register shares some of the same internal flash device resources as the parameter
partition. Therefore, RWW is allowed only between the protection register and the main partitions.
Table 26 describes the operations allowed in the protection register, parameter partition, and main
partition during RWW and RWE.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
77
28F640W30, 28F320W30, 28F128W30
Table 26.
Simultaneous Operations Allowed with the Protection Register
Parameter
Partition
Array Data
Protection
Register
Main
Partitions
Description
While programming or erasing in a main partition, the protection register can be
read from any other partition. Reading the parameter partition data is not
allowed if the protection register is being read from addresses within the
parameter partition.
See
Description
Read
Write/Erase
While programming or erasing in a main partition, read operations are allowed
Write/Erase in the parameter partition. Accessing the protection registers from parameter
partition addresses is not allowed.
See
Description
Read
Read
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers is allowed, but
only in a partition that is different from the partition being programmed or
erased, and also different from the parameter partition.
Read
Write
Write/Erase
While programming the protection register, reads are allowed only in the other
main partitions. Access to the parameter partition is not allowed, because
programming of the protection register can occur only in the parameter
No Access
Allowed
Read
partition, so that the parameter partition exists in status mode.
While programming or erasing the parameter partition, reads of the protection
registers are not allowed in any partition. Reads in other main partitions are
supported.
No Access
Allowed
Write/Erase
Read
13.2.1
Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time
from addresses shown in Table 20, “Flash Device Identification Codes” on page 57. The protection
register is read from the Read Identifier command, and can be read in any partition.Writing the
Read Array command returns the flash device to read-array mode.
13.2.2
Programing the Protection Register
Issue the Protection Program command only at the parameter partition followed by the data to be
programmed at the specified location. This command programs the upper 64 bits of the protection
register 16 bits at a time. Table 20, “Flash Device Identification Codes” on page 57 shows
allowable addresses. See also Figure 35, “Protection Register Programming Flowchart” on
page 79. Issuing a Protection Program command outside the address space of the register results in
a status register error (SR[4]=1).
13.2.3
Locking the Protection Register
• PR-LK.0 is programmed to 0 by Intel to protect the unique flash device number.
• PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of the
protection register (See Figure 36, “Protection Register Locking). This bit is set using the
Protection Program command to program a value of FFFDh into PR-LK.
After PR-LK register bits are programmed (locked), the stored values in the protection register
cannot be changed. Protection Program commands written to a locked section result in a status
register error (SR[4]=1, SR[5]=1).
June 2005
78
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
.
Figure 35.
Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMINGPROCEDURE
Bus
Operation
Start
Command
Comments
Protection
Program
Setup
Data = C0h
Addr = Protection address
Write
Write
Read
Write C0h
Addr=Prot addr
Protection Data = Data to program
Program Addr = Protection address
Write Protect.
Register
Address / Data
Read SRD
Toggle CE# or OE# to update SRD
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Standby
No
SR[7] = 1?
Yes
Protection Program operations addresses must be within the
protection register address space. Addresses outside this
space will return an error.
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full status register check can be done after each program or
after a sequence of program operations.
Program
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read SRD
SR[4:3] =
Command
Comments
SR[1] SR[3] SR[4]
Standby
Standby
Standby
0
0
1
0
1
1
VPP Error
1,1
1,0
1,1
VPP Range Error
Protection register
program error
1
0
1
Register locked;
SR[4,1] =
SR[4,1] =
Programming Error
Operation aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts.
Locked-Register
Program Aborted
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
79
28F640W30, 28F320W30, 28F128W30
Figure 36.
Protection Register Locking
0x88
User-Programmable
0x85
0x84
Intel Factory-Programmed
PR Lock Register 0
0x81
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x80
13.3
VPP Protection
The Intel® Wireless Flash Memory (W30) provides in-system program and erase at V . For
PPL
factory programming, the W30 flash memory device also includes a low-cost, backward-
compatible 12 V programming feature.(See “Factory Programming” on page 63.) The EFP feature
can also be used to greatly improve factory program performance, as explained in Section 11.3,
“Enhanced Factory Program (EFP)” on page 63.
In addition to flexible block locking, holding the V programming voltage low can provide
PP
hardware write protection of all flash-device blocks. If V is below V
, program or erase
PP
PPLK
operations result in an error displayed in SR[3]. (See Figure 37.)
Figure 37.
Examples of VPP Power Supply Configurations
System supply
12 V supply
System supply
Prot# (logic signal)
VCC
VPP
VCC
VPP
≤
Ω
10K
•
•
•
•
12 V fast programming
Absolute write protection with VPP VPPLK
Low-voltage programming
Absolute write protection via logic signal
≤
System supply
VCC
System supply
VCC
(Note 1)
VPP
VPP
12 V supply
•
•
Low voltage and 12 V fast programming
Low-voltage programming
Note: If the VCC supply can sink adequate current, you can use an appropriately valued resistor.
June 2005
80
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
14.0
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The read configuration register data is
placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles.
1. The Set Read Configuration Register command is written, along with the configuration data
(on the address bus).
2. A second write confirms the operation and again presents the read configuration register data
on the address bus.
3. The read configuration register data is latched on the rising edge of ADV#, CE#, or WE#
(whichever occurs first).
This command functions independently of the applied V voltage. After executing this command,
PP
the flash device returns to read-array mode.
To examine the contents of the read configuration register, write the Read Identifier command and
then read location 05h. (See Table 27 and Table 28.)
Table 27.
Read Configuration Register Definitions
Data
Output
Config
WAIT
Confi
g
Clock
Confi
g
Read
Mode
First Access Latency
Count
WAIT
Polarity
Burst
Seq
Res’
d
Res’
d
Burst
Wrap
Res’d
Burst Length
RM
15
R
LC2
13
LC1
12
LC0
11
WP
10
DOC
9
WC
8
BS
7
CC
6
R
5
R
4
BW
3
BL2 BL1 BL0
14
2
1
0
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
81
28F640W30, 28F320W30, 28F128W30
Table 28.
Read Configuration Register Descriptions
Bit
Name
Description1
Notes
RM
0 = Synchronous Burst Reads Enabled
15
14
2,6
5
1 = Asynchronous Reads Enabled (Default)
Reserved
Read Mode
R
LC[2:0]
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
13-11
6
First Access Latency
Count
WP
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
10
9
3
6
6
WAIT Signal Polarity
DOC
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
Data Output Configuration
WC
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
8
WAIT Configuration
BS
7
1 = Linear Burst Order (Default)
Burst Sequence
CC
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
6
Clock
Configuration
5
4
R
R
Reserved
Reserved
5
5
BW
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
3
Burst Wrap
001 = 4-Word Burst
010 = 8-Word Burst
BL[2:0]
2-0
4
011 = 16-Word Burst (Available on the 130 nm lithography)
111 = Continuous Burst (Default)
Burst Length
Notes:
1.
2.
Undocumented combinations of bits are reserved by Intel for future implementations.
Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register
and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0].
Data is not ready when WAIT is asserted.
Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.
Set all reserved Read Configuration Register bits to zero.
3.
4.
5.
6.
Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data
hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.
June 2005
82
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
14.1
Read Mode (RCR[15])
All partitions support two high-performance read configurations:
• synchronous burst mode
• asynchronous page mode (default)
RCR[15] sets the read configuration to one of these modes.
Status register, query, and identifier modes support only asynchronous and single-synchronous read
operations.
14.2
First Access Latency Count (RCR[13:11])
The First Access Latency Count (RCR[13:11]) configuration tells the flash device how many
clocks must elapse from ADV# de-assertion (V ) before driving the first data word onto its data
IH
pins. The input clock frequency determines this value. See Table 27, “Read Configuration Register
Definitions” on page 81 for latency values.
Figure 38 shows data output latency from ADV# assertion for different latencies. Refer to Section
14.2.1, “Latency Count Settings” on page 84 for Latency Code Settings.
Figure 38.
First Access Latency Configuration
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
Code 3
Code 4
Code 5
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Note: Other First Access Latency Configuration settings are reserved.
)
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
83
Figure 39.
Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0
1 2 3 4 5 6 7 8 9 A B C D E F
16 Word Boundary
4 Word Boundary
Note: The 16-word boundary is the end of the flash device sense word-line.
14.2.1
Latency Count Settings
Table 29.
Latency Count Settings
tAVQV/tCHQV (90ns/22ns)
Unit
tAVQV/tCHQV (85ns/22ns)
tAVQV/tCHQV (70ns/20ns)
Latency Count
2
3, 4, 5
< 33
2, 3, 4, 5
< 40
2
3, 4, 5
< 33
Settings
Frequency
< 31
< 29
MHz
Figure 40.
Data Output with LC Setting at Code 3
tADD-DELAY
tDATA
2rd
CLK (C)
CE# (E)
0st
1nd
3th
4th
ADV# (V)
AMAX-0 (A)
Valid Address
High Z
Code 3
Valid
Output
Valid
Output
DQ15-0 (D/Q)
R103
28F640W30, 28F320W30, 28F128W30
14.3
14.4
WAIT Signal Polarity (RCR[10])
• If the WT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. A 0 on the
WAIT signal indicates that data is not ready and the data bus contains invalid data.
• Conversely, if RCR[10] is set, then WAIT is asserted high.
In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during
asynchronous page mode reads.
WAIT Signal Function
The WAIT signal indicates data valid when the flash device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT
signal is deasserted only when data is valid on the bus.
• When the flash device is operating in synchronous non-read-array mode, such as read status,
read ID, or read query, WAIT is set to an asserted state, as determined by RCR[10]. See Figure
14, “WAIT Signal in Synchronous Non-Read Array Operation Waveform” on page 38.
• When the flash device is operating in asynchronous page mode or asynchronous single word
read mode, WAIT is set to an asserted state, as determined by RCR[10]. See Figure 10, “Page-
Mode Read Operation Waveform” on page 34, and Figure 8, “Asynchronous Read Operation
Waveform” on page 32.
From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the
flash device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or
Read Status), or if the flash device is operating in asynchronous mode (RCR[15]=1). In these cases,
the system software must ignore (mask) the WAIT signal, because WAIT does not convey any
useful information about the validity of what is appearing on the data bus.
CONDITION
WAIT
CE# = VIH
CE# = VIL
Tri-State
Active
OE#
No-Effect
Active
Synchronous Array Read
Synchronous Non-Array Read
All Asynchronous Read and all Write
Asserted
Asserted
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
85
28F640W30, 28F320W30, 28F128W30
14.5
Data Hold (RCR[9])
The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word remains valid
on the data bus for one or two clock cycles. The minimum data set-up time on the processor, and
the flash memory clock-to-data output delay, determine whether one or two clocks are needed.
• A DOC set at 1-clock data hold corresponds to a 1-clock data cycle.
• A DOC set at 2-clock data hold corresponds to a 2-clock data cycle.
The setting of this configuration bit depends on the system and CPU characteristics. For
clarification, see Figure 41. The following is a method for determining this configuration setting.
To set the flash device at 1-clock data hold for subsequent reads, the following condition must be
satisfied:
t
t
(ns) < One CLK Period (ns)
CHQV (ns) + DATA
As an example, use a clock frequency of 54 MHz and a clock period of 25 ns. Assume the data
output hold time is one clock. Apply this data to the formula above for the subsequent reads:
20 ns + 4 ns ≤ 25 ns
This equation is satisfied, and data output is available and valid at every clock period. If t
is
DATA
long, hold for two cycles. During page-mode reads, the initial access time can be determined using
the formula:
t
t
(ns) + t
(ns)
ADD-DELAY (ns) DATA
AVQV
Subsequent reads in page mode are defined by:
(ns) (minimum time)
t
t
APA (ns) + DATA
Figure 41.
Data Output Configuration with WAIT Signal Delay
CLK [C]
WAIT (CR.8 = 1)
Note 1
Note 1
tCHQV
WAIT (CR.8 = 0)
1 CLK
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [Q]
Data Hold
WAIT (CR.8 = 0)
tCHTL/H
Note 1
Note 1
tCHQV
WAIT (CR.8 = 1)
2 CLK
Valid
Output
Valid
Output
DQ15-0 [Q]
Data Hold
Note: WAIT shown asserted high (RCR[10]=1).
June 2005
86
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
14.6
WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. This bit setting depends on the system and CPU characteristics. The WAIT can
be asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-word, 8-word, 16-word, or
continuous-word burst mode, an output delay might occur when a burst sequence crosses its first
flash device-row boundary (16-word boundary).
• If the burst start address is 4-word boundary aligned, the delay does not occur.
• If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode
read sequence. The WAIT signal informs the system of this delay.
14.7
Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 30, “Sequence and
Burst Length” on page 88). When operating in a linear burst mode, either 4-word, 8-word, or
16-word burst length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the flash
device might incur an output delay when the burst sequence crosses the first 16-word boundary.
(See Figure 39, “Word Boundary” on page 84 for word boundary description.)
Whether this delay occurs depends on the starting address.
• If the starting address is aligned to a 4-word boundary, there is no delay.
• If the starting address is the end of a 4-word boundary, the output delay is one clock cycle less
than the First Access Latency Count; this is the worst-case delay.
The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. The
WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see these
figures:
• Figure 11, “Single Synchronous Read-Array Operation Waveform” on page 35
• Figure 12, “Synchronous 4-Word Burst Read Operation Waveform” on page 36
• Figure 13, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform” on
page 37
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
87
28F640W30, 28F320W30, 28F128W30
Table 30.
Sequence and Burst Length
Burst Addressing Sequence (Decimal)
Start
Addr.
(Dec)
4-Word Burst
CR[2:0]=001b
8-Word Burst
CR[2:0]=010b
16-Word Burst1
CR[2:0]=011b
Continuous Burst
CR[2:0]=111b
Linear
Linear
Linear
Linear
0
1
2
3
4
5
6
7
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
0-1-2...14-15
1-2-3...14-15-0
2-3-4...15-0-1
3-4-5...15-0-1-2
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
4-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
5-6-7...15-0-1...4
6-7-8...15-0-1...5
7-8-9...15-0-1...6
14
15
0
14-15-0-1...13
15-0-1-2-3...14
0-1-2...14-15
1-2-3...15-16
2-3-4...16-17
3-4-5...17-18
14-15-16-17-18-19-20-...
15-16-17-18-19-...
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
1
2
3
4-5-6-7-8-9-10-
11
4
5
6
7
4-5-6...18-19
5-6-7...19-20
6-7-8...20-21
7-8-9...21-22
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
5-6-7-8-9-10-11-
12
6-7-8-9-10-11-
12-13
7-8-9-10-11-12-
13-14
14
15
14-15...28-29
15-16...29-30
14-15-16-17-18-19-20-...
15-16-17-18-19-20-21-...
Note: Available on the 130 nm lithography.
14.8
Clock Edge (RCR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst
CPUs. Clock configuration sets the flash device to start a burst cycle, output data, and assert WAIT
on the rising or falling edge of the clock.
June 2005
88
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
14.9
Burst Wrap (RCR[3])
The burst wrap bit determines whether 4-word, 8-word, or 16-word burst accesses wrap within the
burst-length boundary, or they cross word-length boundaries to perform linear accesses.
No-wrap mode (RCR[3]=1) enables WAIT to hold off the system processor, as it does in the
continuous burst mode, until valid data is available.
In no-wrap mode (RCR[3]=0), the flash device operates similarly to continuous linear burst mode,
but consumes less power during 4-word, 8-word, or 16-word bursts.
For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst
sequences. However, significantly more power might be consumed. The 1-2-3-4 sequence, for
example, consumes power during the initial access, again during the internal pipeline lookup as the
processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the flash device pipelines the next 4-word sequence. RCR[3]=1 while in 4-word burst
mode (no-wrap mode) reduces this excess power consumption.
14.10
Burst Length (RCR[2:0])
The burst length is the number of words the flash device outputs in a synchronous read access.
4-word, 8-word, 16-word, and continuous-word are supported.
In 4-word, 8-word, or 16-word burst configuration, the burst wrap bit (RCR[3]) determines
whether burst accesses wrap within word-length boundaries, or they cross word-length boundaries
to perform a linear access.
After an address is specified, the flash device outputs data until it reaches the end of its burstable
address space. Continuous burst accesses are linear only (burst wrap bit RCR[3] is ignored during
continuous burst) and do not wrap within word-length boundaries (see Table 30, “Sequence and
Burst Length” on page 88).
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
89
28F640W30, 28F320W30, 28F128W30
Appendix A Write State Machine
Table 31 shows the command state transitions, based on incoming commands. Only one partition
can be actively programming or erasing at a time.
Table 31.
Next State Table (Sheet 1 of 2)
Chip Next State after Command Input
Enhanced BE Confirm,
Factory P/E Resume,
Clear
Status
Register(6)
Program/
Erase
Suspend
Read
Array(3)
Program
Setup(4,5)
Erase
Setup(4,5)
Read
Status
Read
ID/Query
Current Chip
State(8)
Pgm
ULB
Confirm(9)
Setup(4)
(FFH)
(10H/40H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
Program
Setup
Erase
Setup
EFP
Setup
Ready
Ready
Ready
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Setup
Busy
Program Busy
Program
Erase
Program Busy
Pgm Susp
Program Busy
Suspend
Setup
Busy
Program Suspend
Ready (Error)
Pgm Busy
Program Suspend
Ready (Error)
Erase Busy
Erase Busy
Erase Susp
Erase Busy
Pgm in
Erase
Susp Setup
Erase
Suspend
Suspend
Erase Suspend
Erase Busy
Erase Suspend
Setup
Busy
Program in Erase Suspend Busy
Pgm Susp in
Erase Susp
Program in
Erase Suspend
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Pgm in Erase
Susp Busy
Suspend
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Suspend (Lock Error)
Ready (Error)
Erase Susp
Setup
EFP Busy
Ready (Error)
Enhanced
Factory
EFP Busy(7)
Verify Busy(7)
EFP Busy
EFP Verify
Program
Output Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
OTP Busy
Status
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
Output
does not
change
Array(3)
Status
Output does not change
Status
ID/Query
June 2005
90
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 31.
Next State Table (Sheet 2 of 2)
Chip Next State after Command Input
Lock,
Unlock,
Lock-down,
CR setup(5)
Lock-
Down
Block
Confirm(9)
Enhanced
Fact Pgm
Exit (blk add
<> WA0)
Lock
Block
Confirm(9)
Illegal
commands or
EFP data(2)
OTP
Setup(5)
Write CR
Confirm(9)
WSM
Operation
Completes
Current Chip
State(8)
(60H)
(C0H)
(01H)
(2FH)
(03H)
Ready
Ready
(XXXXH)
(other codes)
Lock/CR
Setup
OTP
Setup
Ready
N/A
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Ready
N/A
Setup
Busy
Program Busy
Program Busy
Program Suspend
Ready (Error)
Program
Erase
Ready
Suspend
Setup
Busy
N/A
Erase Busy
Erase Busy
Ready
Lock/CR
Setup in
Erase Susp
Suspend
Erase Suspend
N/A
Setup
Busy
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Erase
Suspend
Program in
Erase Suspend
Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)
N/A
Setup
Ready (Error)
EFP Verify
Enhanced
Factory
Program
EFP Busy(7)
Verify Busy(7)
EFP Busy(7)
EFP Verify(7)
EFP Busy
EFP Verify
Ready
Ready
Output Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
Array
Status
Output does
not change
OTP Busy
Ready,
Pgm Busy,
Output does
not change
Pgm Suspend,
Erase Busy,
Status
Output does not change
Array
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
Notes:
1.
The output state shows the type of data that appears at the outputs if the partition address is the same as the command
address.
— A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.
— Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM
state does not depend on the output state of the partition.
— For example, if the partition #1 output state is Read Array and the partition #4 output state is Read Status, every read
from partition #4 (without issuing a new command) outputs the Status register.
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
91
28F640W30, 28F320W30, 28F128W30
2.
3.
Illegal commands are any commands not defined in the command set.
All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in
undetermined data when a partition address is read.
4.
Both cycles of two-cycle commands must be issued to the same partition address. If the two cycles are issued to different
partitions, the address used for the second write cycle determines the active partition. Both partitions output status
information when read.
5.
6.
If the WSM is active, both cycles of a two-cycle command are ignored. This feature differs from previous Intel flash
memory devices.
The Clear Status command clears status register error bits, except when the WSM is running (Pgm Busy, Erase Busy, Pgm
Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase
Suspend).
7.
EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if the Block Address = the address at the EFP
Confirm command. Any other commands are treated as data.
8.
9.
The current state is the state of the WSM, not the state of the partition.
Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then
move to the Ready State.
10.
In Erase suspend mode, the only valid two-cycle commands are Program Word, Lock/Unlock/Lockdown Block, and CR
Write. Both cycles of other two-cycle commands (Program OTP & confirm, EFP Setup & confirm, Erase setup & confirm)
are ignored. In Program suspend or Program suspend in Erase suspend, both cycles of all two-cycle commands are
ignored.
June 2005
92
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Appendix B Common Flash Interface
This appendix defines the data structure or database returned by the Common Flash Interface
(CFI) Query command. System software parses this structure to gain critical information, such as
block size, density, x8/x16, and electrical specifications.
Once this information has been obtained, the software can determine which command sets to use to
enable flash device writes, enable block erases, and otherwise control the flash device. The Query
is part of an overall specification for multiple command set and control interface descriptions,
which is called the Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the flash device CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset
value is the address relative to the maximum bus width that the flash device supports. On the W30
family of flash memory devices, the Query table device starting address is a 10h, which is a word
address for x16 flash devices.
For a word-wide (x16) flash device, the first two Query-structure bytes, ASCII Q and R, appear on
the low byte at word addresses 10h and 11h.
• This CFI-compliant flash device outputs 00h data on upper bytes.
• The flash device outputs ASCII Q in the low byte (DQ ) and 00h in the high byte (DQ ).
0-7
8-15
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the h
suffix has been dropped. In addition, because the upper byte of word-wide flash devices is always
00h, the leading 00 has been dropped from the table notation, and only the lower byte value is
shown. Any x16 flash device outputs can be assumed to have 00h on the upper byte in this mode.
Table 32.
Summary of Query Structure Output as a Function of the Flash Device and Mode
Hex
Offset
Hex
Code Value
ASCII
Device
00010:
00011:
00012:
51
52
59
Q
R
Y
Device Addresses
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
93
28F640W30, 28F320W30, 28F128W30
Table 33. Example of Query Structure Output of x16- and x8 Flash Devices
Word Addressing:
Hex Code
Byte Addressing:
Hex Code
Offset
A —A
Value
Offset
Value
D
—D
A —A
D —D
7 0
X
0
15
0
X
0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
“Q”
“R”
“Y”
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
51
52
Q
R
Y
59
P IDLO
P IDHI
PLO
PrVendor
ID #
P IDLO
P IDLO
P IDHI
...
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
ID #
PHI
...
A IDLO
A IDHI
...
...
B.2
Query Structure Overview
The Query command causes the flash device to display the Common Flash Interface (CFI) Query
structure or database. Table 34 summarizes the structure sub-sections and address locations.
Table 34.
Query Structure
Description(1)
Manufacturer Code
Device Code
Offset
00000h
Sub-Section Name
00001h
(BA+2)h(2)
Block Status register
Block-specific information
00004-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
0001Bh
00027h
CFI query identification string
System interface information
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Intel-specific Extended Query Table
Notes:
1.
2.
3.
Refer to the Section B.1, “Query Structure Output” on page 93 and offset 28h, for the detailed definition
of the offset address as a function of the flash device bus width and mode.
BA = Block Address beginning location (for example, 08000h is the block 1’beginning location when the
block size is 32K-word).
Offset 15 defines P, which points to the Primary Intel-specific Extended Query Table.
June 2005
94
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
B.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully, a given
block is locked, or a given block can be accessed for flash memory program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. Use BSR.1 just after power-up to verify that the VCC supply was not accidentally
removed during an erase operation.
Table 35.
Block Status Register
Offset
Length
Description
Block Lock Status Register
BSR.0 Block lock status
0 = Unlocked
Add.
Value
(BA+2)h(1)
1
BA+2 --00 or --01
BA+2 (bit 0): 0 or 1
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
BA+2 (bit 1): 0 or 1
BA+2 (bit 2–7): 0
BSR 2–7: Reserved for future use
Notes:
1.
BA = Block Address beginning location (for example, 08000h is the block 1 beginning location when the
block size is 32K-word).
B.4
CFI Query Identification String
The Identification String verifies that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command
set(s).
.
Table 36.
CFI Identification
Hex
Code
Offset Length
Description
Add.
Value
10:
11:
12:
--51
--52
--59
Q
R
Y
10h
3
Query-unique ASCII string ”QRY”
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
13:
14:
--03
--00
13h
15h
17h
19h
2
2
2
2
15:
16:
--39
--00
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
17:
18:
--00
--00
Secondary algorithm Extended Query Table address.
0000h means none exists
19:
1A:
--00
--00
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
95
28F640W30, 28F320W30, 28F128W30
Table 37.
System Interface Information
Hex
Offset
Length
Description
CC logic supply minimum program/erase voltage
Add. Code Value
1Bh
1
1
1
1
V
1B:
1C:
1D:
1E:
--17 1.7V
--19 1.9V
--B4 11.4V
--C6 12.6V
--04 16µs
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
1Ch
1Dh
1Eh
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µ-sec
“n” such that typical max. buffer write time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
NA
1s
NA
--04 256µs
--00
--03
--00
NA
8s
NA
June 2005
96
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
B.5
Flash Device Geometry Definition
Table 38.
Flash Device Geometry Definition
Offset
27h
Length
Description
Code
See table below
1
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
27:
28:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
x64
11
2
x32
10
1
x16
9
0
x8
8
28h
2
—
15
—
—
14
—
—
13
—
—
12
—
--01
x16
0
—
—
—
—
29:
2A:
2B:
2C:
--00
--00
--00
2
1
“n” such that maximum number of bytes in write buffer = 2n
2Ah
2Ch
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2Dh
31h
35h
4
4
4
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
32 Mbit
64 Mbit
128 Mbit
–B
Address
–B
–T
–B
–T
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--00
--00
--00
--00
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--07
--00
--20
--00
--7E
--00
--00
--01
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--7E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--07
--00
--20
--00
--FE
--00
--00
--01
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--FE
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
97
28F640W30, 28F320W30, 28F128W30
B.6
Intel-Specific Extended Query Table
Table 39.
Primary Vendor-Specific Extended Query
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
Unique ASCII string “PRI“
39:
3A:
3B:
3C:
3D:
3E:
3F:
40:
41:
--50
--52
--49
--31
--33
--E6
--03
--00
--00
"P"
"R"
"I"
"1"
"3"
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
No
Yes
Yes
Yes
Yes
Yes
bit 9 Simultaneous operations supported
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
(P+9)h
1
2
42:
--01
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bit 0 = 1
Yes
(P+A)h
(P+B)h
43:
44:
--03
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
(P+C)h
(P+D)h
1
1
45:
--18 1.8V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
46:
--C0 12.0V
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
June 2005
98
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 40.
Protection Register Information
Offset(1)
P = 39h
Hex
Code
Length Description (Optional flash device features and commands)
Add.
Value
Number of Protection register fields in JEDEC ID space.
(P+E)h
1
47:
48:
--01
1
00h indicates that 256 protection fields are available
(P+F)h
4
Protection Field 1: Protection Description
--80
--00
--03
--03
80h
(P+10)h
(P+11)h
(P+12)h
This field describes user-available One Time Programmable (OTP) 49:
Protection register bytes.
00h
4A:
8 byte
8 byte
•
Some bytes are pre-programmed with flash device-unique
serial numbers.
4B:
•
Other bytes are user programmable.
Bits 0-15 point to the Protection register Lock byte, the first byte in
the section. The following bytes are factory pre-programmed and
user-programmable.
•
•
•
•
bits 0--7 = Lock/bytes Jedec-plane physical low address
bits 8--15 = Lock/bytes Jedec-plane physical high address
bits 16--23 = n such that 2n = factory pre-programmed bytes
bits 24--31 =n such that 2n = user programmable bytes
Table 41.
Burst Read Information for Non-Multiplexed Flash Device
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Add. Code Value
(P+13)h
1
Page Mode Read capability
4C:
--03 8 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
(P+14)h
(P+15)h
1
1
4D:
4E:
--04
--01
4
4
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
(P+16)h
(P+17)h
(P+18)h
1
1
1
4F:
50:
51:
--02
--03
--07 Cont
8
16
Table 42.
Partition and Erase-Block Region Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features and commands)
Len
(P+19)h (P+19)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
52:
52:
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
99
28F640W30, 28F320W30, 28F128W30
Table 43.
Partition Region 1 Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
Top
Bottom
Top
(P+1A)h (P+1A)h
(P+1B)h (P+1B)h
(Optional flash features and commands)
Number of identical partitions within the partition region
Len
2
53:
54:
55:
53:
54:
55:
(P+1C)h (P+1C)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
1
1
bits 4–7 = number of simultaneous Erase operations
(P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1E)h (P+1E)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1F)h (P+1F)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
56:
57:
58:
56:
57:
58:
1
1
(P+20)h (P+20)h Partition Region 1 Erase Block Type 1 Information
4
59:
5A:
5B:
5C:
5D:
5E:
5F:
59:
5A:
5B:
5C:
5D:
5E:
5F:
(P+21)h (P+21)h
(P+22)h (P+22)h
(P+23)h (P+23)h
(P+24)h (P+24)h
(P+25)h (P+25)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 1 (Erase Block Type 1)
Minimum block erase cycles x 1000
2
1
(P+26)h (P+26)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+27)h (P+27)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
60:
60:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+28)h
(P+29)h
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase block Type 2)
Minimum block erase cycles x 1000
61:
62:
63:
64:
65:
66:
67:
2
1
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+2F)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
68:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
June 2005
100
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Table 44.
Partition Region 2 Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features and commands)
Len
(P+30)h (P+28)h Number of identical partitions within the partition region
(P+31)h (P+29)h
(P+32)h (P+2A)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
2
69:
6A:
6B:
61:
62:
63:
1
1
1
1
(P+33)h (P+2B)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+34)h (P+2C)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+35)h (P+2D)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
6C:
6D:
6E:
64:
65:
66:
(P+36)h (P+2E)h Partition Region 2 Erase Block Type 1 Information
4
6F:
70:
71:
72:
73:
74:
75:
67:
68:
69:
6A:
6B:
6C:
6D:
(P+37)h (P+2F)h
(P+38)h (P+30)h
(P+39)h (P+31)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3A)h (P+32)h Partition 2 (Erase block Type 1)
(P+3B)h (P+33)h Minimum block erase cycles x 1000
(P+3C)h (P+34)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+3D)h (P+35)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
76:
6E:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+36)h Partition Region 2 Erase Block Type 2 Information
6F:
70:
71:
72:
73:
74:
75:
(P+37)h
(P+38)h
(P+39)h
(P+3A)h
(P+3B)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 2 (Erase Block Type 2)
Minimum block erase cycles x 1000
2
1
(P+3C)h Partition 2 (Erase Block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserved for future use
(P+3D)h Partition 2 (Erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
76:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+3E)h (P+3E)h Features Space definitions (Reserved for future use)
(P+3F)h (P+3F)h Reserved for future use
TBD
Resv'd 78:
77:
77:
78:
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
101
28F640W30, 28F320W30, 28F128W30
Table 45.
Partition and Erase-Block Region Information
Address
32 Mbit
64Mbit
128Mbit
–B
–T
–B
–T
–B
–T
52:
53:
54:
55:
56:
57:
58:
59:
5A:
5B:
5C:
5D:
5E:
5F:
60:
61:
62:
63:
64:
65:
66:
67:
68:
69:
6A:
6B:
6C:
6D:
6E:
6F:
70:
71:
72:
73:
74:
75:
76:
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
Notes:
1.
2.
The P variable is a pointer which is defined at CFI offset 15h.
TPD - Top parameter device.
BPD - Bottom parameter device.
3.
4.
Partition: Each partition is 4 Mb in size. It can contain main blocks OR a combination of both main and
parameter blocks.
Partition Region: Symmetrical partitions form a partition region.
— Partition region A. contains all partitions that are made up of main blocks only.
— Partition region B. contains the partition that is made up of the parameter and the main blocks.
June 2005
102
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
28F640W30, 28F320W30, 28F128W30
Appendix C Ordering Information
Figure 42.
VF BGA Ordering Information
G E 2 8 F 6 4 0 W 3 0 T D 7 0
Access Speed(ns)
(70,85)
Package:
GE = VF BGA, Leaded
PH = VF BGA, Pb-Free
Process Identifie:r
D = 0. 13µm
Product Line Designato:r
For all Intel Flash Products
Parameter Location:
T = Top Parameter
B = Bottom Parameter
Device Density:
320 = 32Mbit
640 = 64Mbit
128 = 128Mbit
Product Family:
W30 = Inte®l Wireless Flash
Memory with3 Volt I/O
Figure 43.
SCSP Ordering Information
P F 4 8 F 2 0 0 0 W 0 Z B Q 0
Device Details:
0 = Initial Version
Package:
RD = SCSP, Leaded
PF = SCSP, Pb- Free
Ballout Indicator:
Q = QUAD+
Product Line:
48 F = Flash Only
Parameter Location:
T = Top Parameter
B = Bottom Parameter
Flash Density:
0 = No die
1 = 32 Mbit
2 = 64 Mbit
3 = 128 Mbit
Voltage:
Z = 3 V olt I/ O
Product Family Designato:r
W = Intel ®
Wireless Flash Memory
Datasheet
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
June 2005
103
28F640W30, 28F320W30, 28F128W30
Table 46.
W30 Flash Memory Family: Available Product Ordering Information
I/O
Voltage
(V)
Package
Size (mm)
Ballout
Name
Ballout
Type
Flash Density
Part Number
GE28F320W30BD70
GE28F320W30TD70
GE28F320W30BD85
GE28F320W30TD85
Leaded
9x7.7x1.0 VF BGA
32 Mbit
PH28F320W30BD70
PH28F320W30TD70
Lead Free
Lead Free
Leaded
PF48F1000W0ZBQ0
PF48F1000W0ZTQ0
10x8x1.2
SCSP
GE28F640W30BD70
GE28F640W30TD70
3.0
9x7.7x1.0 VF BGA
PH28F640W30BD70
PH28F640W30TD70
64 Mbit
Lead Free
Lead Free
Leaded
PF48F2000W0ZBQ0
PF48F2000W0ZTQ0
10x8x1.2
9x11x1.0
10x8x1.2
SCSP
VF BGA
SCSP
GE28F128W30BD70
GE28F128W30TD70
128 Mbit
RD48F3000W0ZBQ0
RD48F3000W0ZTQ0
Leaded
June 2005
104
Intel® Wireless Flash Memory (W30)
Order Number: 290702, Revision: 011
Datasheet
相关型号：
©2020 ICPDF网 联系我们和版权申明