GE28F640L30T90 [NUMONYX]
Flash, 4MX16, 90ns, PBGA56, 0.75 MM PITCH, VFBGA-56;
| 型号： | GE28F640L30T90 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 4MX16, 90ns, PBGA56, 0.75 MM PITCH, VFBGA-56 |
| 文件： | 总92页 (文件大小：1208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
1.8 Volt Intel StrataFlash Wireless
Memory with 3.0 Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
■ High performance Read-While-Write/Erase
— 90 ns initial access
■ Software
— 20 µs (Typ) program suspend
— 50MHz with zero wait state, 17 ns clock-to-data
— 20 µs (Typ) erase suspend
output synchronous-burst mode
— Intel® Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Common Flash Interface (CFI) capable
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 10 µs/byte (Typ)
■ Security
• OTP space:
— 64 unique device identifier bits
— 64 user-programmable OTP bits
■ Architecture
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions
— Four 16K-Word parameter blocks: top or
bottom configurations
— 64K-Word main blocks
— Dual-operation: Read-While-Write (RWW) or
■ Quality and Reliability
Read-While-Erase (RWE)
— Expanded temperature: –25° C – +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
■ Density and Packaging
— Status register for partition and device status
■ Power
— 1.7 V - 2.0 V VCC operation
— I/O voltage: 2.2 V - 3.3 V
— Standby current: 30 µA (Typ)
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— 64-, 128- and 256-Mbit density in VF BGA
packages
— 16-bit wide data bus
— Automatic Power Savings (APS) mode
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O product is the latest generation of
Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance asynchronous read mode and synchronous-burst read mode using 1.8 Volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background. 8-Mbit partitions allow system designers to choose the size ofthe code and data segments.
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O device is manufactured using Intel
0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging.
.
Notice: This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design w ith this information.
Order Number: 251903
October 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The 1.8 Volt Intel StrataFlash® Wireless Memory with 3.0 Volt I/O datasheet may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2002, Intel Corporation
* Other names and brands may be claimed as the property of others.
2
28F640L30, 28F128L30, 28F256L30
Contents
1.0
Introduction ..................................................................................................................7
1.1
1.2
1.3
Nomenclature........................................................................................................7
Acronyms ..............................................................................................................7
Conventions ..........................................................................................................8
2.0
Device Description ....................................................................................................9
2.1
2.2
2.3
2.4
Product Overview..................................................................................................9
Ballout Diagrams.................................................................................................10
Signal Descriptions..............................................................................................11
Memory Map .......................................................................................................12
3.0
4.0
Device Operations ...................................................................................................14
3.1
Bus Operations....................................................................................................14
3.1.1 Reads .....................................................................................................14
3.1.2 Writes .....................................................................................................14
3.1.3 Output Disable........................................................................................14
3.1.4 Standby ..................................................................................................15
3.1.5 Reset......................................................................................................15
Device Commands..............................................................................................15
Command Definitions..........................................................................................17
3.2
3.3
ReadOperations .......................................................................................................19
4.1
4.2
Asynchronous Page-Mode Read ........................................................................19
Synchronous Burst-Mode Read ..........................................................................20
4.2.1 Burst Suspend........................................................................................20
Read Configuration Register (RCR)....................................................................21
4.3.1 Read Mode.............................................................................................22
4.3.2 Latency Count ........................................................................................22
4.3.3 WAIT Polarity .........................................................................................23
4.3.3.1 WAIT Signal Function................................................................24
4.3
4.3.4 Data Hold ...............................................................................................24
4.3.5 WAIT Delay ............................................................................................25
4.3.6 Burst Sequence......................................................................................25
4.3.7 Clock Edge.............................................................................................26
4.3.8 Burst Wrap .............................................................................................26
4.3.9 Burst Length...........................................................................................26
5.0
Programming Operations .....................................................................................27
5.1
Word Programming .............................................................................................27
5.1.1 Factory Word Programming ...................................................................28
Buffered Programming ........................................................................................28
Buffered Enhanced Factory Programming..........................................................29
5.3.1 Buffered EFP Requirements and Considerations ..................................29
5.3.2 Buffered EFP Setup Phase ....................................................................30
5.3.3 Buffered EFP Program/Verify Phase......................................................30
5.3.4 Buffered EFP Exit Phase........................................................................31
Program Suspend ...............................................................................................31
5.2
5.3
5.4
3
28F640L30, 28F128L30, 28F256L30
5.5
5.6
Program Resume................................................................................................ 31
Program Protection ............................................................................................. 32
6.0
7.0
Erase Operations ..................................................................................................... 33
6.1
6.2
6.3
6.4
Block Erase......................................................................................................... 33
Erase Suspend.................................................................................................... 33
Erase Resume .................................................................................................... 34
Erase Protection..................................................................................................34
Security Modes ......................................................................................................... 35
7.1
Block Locking ...................................................................................................... 35
7.1.1 Lock Block.............................................................................................. 35
7.1.2 Unlock Block .......................................................................................... 35
7.1.3 Lock-Down Block ................................................................................... 35
7.1.4 Block Lock Status................................................................................... 36
7.1.5 Block Locking During Suspend .............................................................. 36
Protection Registers............................................................................................ 37
7.2.1 Reading the Protection Registers .......................................................... 38
7.2.2 Programming the Protection Registers .................................................. 39
7.2.3 Locking the Protection Registers ........................................................... 39
7.2
8.0
Dual-Operation Considerations ......................................................................... 40
8.1
8.2
Memory Partitioning ............................................................................................ 40
Read-While-Write Command Sequences ........................................................... 40
8.2.1 Simultaneous Operation Details............................................................. 41
8.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and
Waveforms41
8.2.3 Read Operation During Buffered Programming Flowchart..................... 42
Simultaneous Operation Restrictions..................................................................42
8.3
9.0
Special ReadStates ................................................................................................ 43
9.1
Read Status Register .......................................................................................... 43
9.1.1 Clear Status Register .............................................................................44
Read Device Identifier......................................................................................... 44
CFI Query............................................................................................................45
9.2
9.3
10.0
11.0
12.0
Power andReset ...................................................................................................... 46
10.1
10.2
10.3
10.4
Power-Up/Down Characteristics ......................................................................... 46
Power Supply Decoupling ................................................................................... 46
Automatic Power Saving (APS) .......................................................................... 46
Reset Characteristics .......................................................................................... 46
Thermal andDC Characteristics ........................................................................ 48
11.1
11.2
11.3
11.4
Absolute Maximum Ratings ................................................................................ 48
Operating Conditions .......................................................................................... 48
DC Current Characteristics ................................................................................. 49
DC Voltage Characteristics ................................................................................. 50
AC Characteristics................................................................................................... 51
12.1
12.2
AC Read Specifications (VCCQ = 2.2 V – 3.3 V)................................................ 51
AC Write Specifications.......................................................................................56
4
28F640L30, 28F128L30, 28F256L30
12.3
12.4
12.5
12.6
Program and Erase Characteristics ....................................................................60
Reset Specifications............................................................................................60
AC Test Conditions .............................................................................................61
Capacitance ........................................................................................................62
Appendix A Write State Machine (WSM)...........................................................................63
Appendix B Flowcharts............................................................................................................70
Appendix C Common Flash Interface ................................................................................79
Appendix D Mechanical Information...................................................................................89
Appendix E
Appendix F
Additional Information.....................................................................................91
Ordering Information........................................................................................92
5
28F640L30, 28F128L30, 28F256L30
Revision History
Revision
Revision
Date
Description
10/14/02
-001
Initial Release
6
28F640L30, 28F128L30, 28F256L30
1.0
Introduction
This document provides information about the 1.8 Volt Intel StrataFlash® wireless memory with
3-Volt I/O (L30) device. This document describes the L30 flash memory device features, operation,
and specifications.
1.1
Nomenclature
1.8 V: VCC voltage range of1.7 V – 2.0 V (except where noted)
3.0 V Range: VCCQ voltage range of2.2 V – 3.3 V
VPP = 9.0 V: VPP voltage range of8.5 V – 9.5 V
Block: A group ofbits, bytes or words within the flash memory array that erase simultaneously
when the Erase command is issued to the device. The L30 flash memory device has two block
sizes: 16K-Word, and 64K-Word.
Main block: An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Parameter block: An array block that is usually used to store frequently changing data or small
system parameters that traditionally would be stored in EEPROM.
Top parameter device: Previously referred to as a top-boot device, a device with its parameter
partition located at the highest physical address ofits memory map. Parameter blocks within a
parameter partition are located at the highest physical address ofthe parameter partition.
Bottom parameter device: Previously referred to as a bottom-boot device, a device with its
parameter partition located at the lowest physical address ofits memory map. Parameter blocks
within a parameter partition are located at the lowest physical address ofthe parameter partition.
Partition: A group ofblocks that share common program/erase circuitry. Blocks within a partition
also share a common status register. Ifany block within a partition is being programmed or erased,
only status register data (rather than array data) is available when any address within that partition
is read.
Main partition: A partition containing only main blocks.
Parameter partition: A partition containing parameter blocks and main blocks.
1.2
Acronyms
CUI: Command User Interface
MLC: Multi-Level Cell
OTP: One-Time Programmable
PLR: Protection Lock Register
PR: Protection Register
RCR: Read Configuration Register
RFU: Reserved for Future Use
SR: Status Register
WSM: Write State Machine
Datasheet
7
28F640L30, 28F128L30, 28F256L30
1.3
Conventions
VCC: signal or voltage connection
VCC: signal or voltage level
0x: hexadecimal number prefix
0b: binary number prefix
SR[4]: Denotes an individual register bit.
A[15:0]: Denotes a group ofsimilarly named signals, such as address or data bus.
A5: Denotes one element ofa signal group membership, such as an address.
bit: binary unit
byte: eight bits
word: two bytes, or sixteen bits
Kbit: 1024 bits
KByte: 1024 bytes
KWord: 1024 words
Mbit: 1,048,576 bits
MByte: 1,048,576 bytes
MWord: 1,048,576 words
8
Datasheet
28F640L30, 28F128L30, 28F256L30
2.0
Device Description
®
This section provides an overview ofthe features and capabilities ofthe 1.8 Volt Intel StrataFlash
wireless memory with 3-Volt I/O (L30) device.
2.1
Product Overview
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O (L30) device provides read-while-
write and read-while-erase capability with density upgrades through 256-Mbit. This family of
devices provides high performance at low voltage on a 16-bit data bus. Individually erasable
memory blocks are sized for optimum code and data storage.
Each device density contains one parameter partition and several main partitions. The flash
memory array is grouped into multiple 8-Mbit partitions. By dividing the flash memory into
partitions, program or erase operations can take place at the same time as read operations.
Although each partition has write, erase and burst read capabilities, simultaneous operation is
limited to write or erase in one partition while other partitions are in read mode. The L30 flash
memory device allows burst reads that cross partition boundaries. User application code is
responsible for ensuring that burst reads don’t cross into a partition that is programming or erasing.
Upon initial power up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT
signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technology that
enables fast factory program and erase operations. Designed for low-voltage systems, the L30 flash
memory device supports read operations with VCC at 1.8 V, and erase and program operations with
VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the
fastest flash array programming performance with VPP at 9.0 Volt, which increases factory
throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power
design. In addition to voltage flexibility, a dedicated VPP connection provides complete data
protection when VPP is less than VPPLK
.
A Command User Interface (CUI) is the interface between the system processor and all internal
operations ofthe device. An internal Write State Machine (WSM) automatically executes the
algorithms and timings necessary for block erase and program. A Status Register indicates erase or
program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to pause an erase
cycle to read or program data in another block. Program Suspend allows system software to pause
programming to read other locations. Data is programmed in word increments (x16).
The L30 flash memory device offers power savings through Automatic Power Savings (APS)
mode and standby mode. The device automatically enters APS following read-cycle completion.
Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#.
Combined, these features can significantly reduce power consumption.
The L30 flash memory device’s protection register allows unique flash device identification that
can be used to increase system security. Also, the individual Block Lock feature provides zero-
latency block locking and unlocking.
Datasheet
9
28F640L30, 28F128L30, 28F256L30
2.2
Ballout Diagrams
The L30 flash memory device is available in a VF BGA package with 0.75 mm ball-pitch. Figure 1
shows the ballout for the 64-Mbit and 128-Mbit devices in the 56-ball VF BGA package with a 7 x
8 active-ball matrix. Figure 2 shows the device ballout for the 256-Mbit device in the 63-ball VF
BGA package with a 7 x 9 active-ball matrix. Both package densities are ideal for space-
constrained board applications
Figure 1. 7x8 Active-Ball Matrix for 64-, and128-Mbit Densities in VF BGA Packages
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
A11
A12
A8
A9
VSS
A20
VCC
CLK
VPP
A18
A17
A6
A5
A4
A3
A4
A3
A6
A5
A18
A17
VPP
VCC
CLK
VSS
A20
A21
WAIT
D6
A8
A9
A11
A12
RST#
RST#
A13
A15
A10
A14
D15
A21
ADV#
A16
WE#
D12
A19
A7
A2
A1
A2
A1
A7
A19
WE#
D12
ADV#
A16
D4
A10
A14
D15
A13
A15
WP#
WP#
WAIT
D6
A22
CE#
A22
CE#
VCCQ
D4
VCCQ
D2
D1
A0
A0
D1
D2
OE#
OE#
VSS
D7
D14
D13
D5
D11
D10
D3
D9
D0
D8
D0
D8
D9
D10
D3
D11
D13
D5
D14
VSS
D7
G
G
VSSQ
VCC
VCCQ
VSSQ
VSSQ
VCCQ
VCC
VSSQ
VFBGA 7x8
Top View - Ball Side Down
VFBGA 7x8
Bottom View - Ball Side Up
NOTE: On lower-density devices, upper-address balls can be treated as NC. (e.g., for 64-Mbit density, A22 will be NC)
Figure 2. 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package
1
1
13
12
11
10
9
8
7
6
5
4
3
2
2
3
4
5
6
7
8
9
10
11
12
13
A
B
A
B
DU
DU
DU
DU
RFU
RFU
A4
A6
A5
A7
A18
VPP
VCC VSS
CLK A20
A8
A9
A11
A12
DU
DU
DU
DU
DU
DU
DU
DU
A11
A12
A8
A9
VSS VCC
A20 CLK
VPP A18
RST# A17
A6
A5
A4
A3
RFU
RFU
DU
DU
DU
DU
A3
A17 RST#
C
D
E
C
D
E
A10 A21 ADV#
A25
A24
A2
A1
A19 WE# ADV# A21 A10
A13
A15
A13
A15
WE# A19
D12 WP#
A7
A2
A1
A25
A24
A22 WP# D12
A16 WAIT A14
A14 WAIT
A16
D4
A22
D15
D6
A23
RFU
A0
CE#
D0
D1
D9
D2
D4
D6
D15 VCCQ
VCCQ
D2
D1
D9
CE#
D0
A0
A23
F
F
DU
DU
DU
DU
DU
DU
DU
DU
OE#
D10
D11 D13
D14
VSS
DU
DU
DU
DU
DU
DU
DU
DU
VSS D14
D13 D11
D10
OE# RFU
G
G
RFU VSSQ D8 VCCQ D3
Bottom View
VCC D5
VSSQ D7
D7 VSSQ D5 VCC
Ball Side Down-
D3 VCCQ D8 VSSQ RFU
Top View
-
Ball Side Up
NOTE: On lower density devices upper address balls can be treated as RFUs. (A24 is for 512Mb and A25 is for 1Gb densities.) All
ball locations are populated.
10
Datasheet
28F640L30, 28F128L30, 28F256L30
2.3
Signal Descriptions
Table 1 describes the active signals used on the L30 flash memory device.
Table 1. Signal Descriptions
Symbol
Type
In
Name andFunction
A[MAX:0]
ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory,
Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are de-asserted. Data is internally latched during writes.
D[15:0]
In/Out
ADDRESS VALID: Active-lowinput. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
CE#
In
In
CHIP ENABLE: Active-lowinput. CE#-lowselects the device. CE#-high deselects the device, placing it
in standby, with D[15:0] and WAIT in High-Z.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and
increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
CLK
In
OUTPUT ENABLE: Active-lowinput. OE#-lowenables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z.
OE#
In
In
RESET: Active-lowinput. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read array mode.
RST#
WAIT: Wait is driven when CE# is asserted. RCR[10] [WP] determines the WAIT -asserted logic level.
•
In synchronous array read modes, WAIT indicates invalid data when asserted and valid data when
de-asserted.
WAIT
Out
•
In synchronous non-array read modes, asynchronous page mode, and all write modes, WAIT is
asserted.
WRITE ENABLE: Active-lowinput. WE# controls writes to the device. Address and data are latched on
the rising edge of WE#.
WE#
WP#
In
In
WRITE PROTECT: Active-lowinput. WP#-lowenables the lock-down mechanism. Blocks in lock-down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
ERASE/ PROGRAM POWER: Valid V voltages on this ball allowblock erase and program functions.
PP
VPP
Pwr
Flash memory array contents cannot be altered when V ≤ V
. Block erase and program at invalid
PP
PPLK
V
voltages should not be attempted.
PP
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when V ≤ V . Operations at invalid V voltages should not be attempted.
VCC
Pwr
Pwr
CC
LKO
CC
OUTPUT POWER SUPPLY: Output-driver source voltage. This ball can be tied directly to V if
CC
VCCQ
operating within V range.
CC
VSS
Pwr
Pwr
GROUND: Ground reference for device logic voltages. Connect to system ground.
GROUND: Ground reference for device output voltages. Connect to system ground.
VSSQ
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
DU
-
NC
-
-
NO CONNECT: No internal connection; can be driven or floated.
RFU
RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement.
Datasheet
11
28F640L30, 28F128L30, 28F256L30
2.4
Memory Map
The L30 flash memory array is divided into multiple 8-Mbit partitions. Each device density
contains one parameter partition and several main partitions. The 8-Mbit top or bottom parameter
partition contains four 16K-Word blocks and seven 64K-Word blocks. There are multiple 8-Mbit
main partitions. The 8-Mbit main partitions each contains eight 64K-Word blocks.
The device multi-partition architecture is divided as follow:
• The 64-Mbit device contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit
main partitions.
• The 128-Mbit device contains sixteen partitions: one 8-Mbit parameter partition, fifteen 8-
Mbit main partitions.
• The 256-Mbit device contains thirty-two partitions: one 8-Mbit parameter partition, thirty-
one 8-Mbit main partitions.
Table 2. Top Parameter Memory Map
Size (KW) Blk
64-Mbit
Size (KW) Blk
128-Mbit
Blk
256-Mbit
43
16
16
16
16
64
66 3FC000-3FFFFF
16 130 7FC000-7FFFFF 258 FFC000-FFFFFF
16 129 7F8000-7FBFFF 257 FF8000-FFBFFF
16 128 7F4000-7F7FFF 256 FF4000-FF7FFF
16 127 7F0000-7F3FFF 253 FF0000-FF3FFF
64 126 7E0000-7EFFFF 254 FE0000-FEFFFF
65 3F8000-3FBFFF
64 3F4000-3F7FFF
63 3F0000-3F3FFF
62 3E0000-3EFFFF
64
64
56 380000-38FFFF
55 370000-37FFFF
64 120 780000-78FFFF 248 F80000-F8FFFF
64 119 770000-77FFFF 247 F70000-F7FFFF
64
0
000000-00FFFF
64
64
0
000000-00FFFF 128 800000-80FFFF
127 7F0000-7FFFFF
64
0
000000-00FFFF
12
Datasheet
28F640L30, 28F128L30, 28F256L30
Table 3. Bottom Parameter Memory Map
Size (KW)
Size (KW)
Blk
64-Mbit
Blk
128-Mbit
Blk
256-Mbit
64
64
258 FF0000-FFFFFF
131 800000-80FFFF
64 66 3F0000-3FFFFF
64 130 7F0000-7FFFFF 130 7F0000-7FFFFF
64
11 080000-08FFFF
64
11 080000-08FFFF 11 080000-08FFFF
64 10 070000-07FFFF
64 10 070000-07FFFF 10 070000-07FFFF
64
16
16
16
16
4
3
2
1
0
010000-01FFFF
00C000-00FFFF
008000-00BFFF
004000-007FFF
000000-003FFF
64
16
16
16
16
4
3
2
1
0
010000-01FFFF
00C000-00FFFF
008000-00BFFF
004000-007FFF
000000-003FFF
4
3
2
1
0
010000-01FFFF
00C000-00FFFF
008000-00BFFF
004000-007FFF
000000-003FFF
Datasheet
13
28F640L30, 28F128L30, 28F256L30
3.0
Device Operations
This section provides an overview ofdevice operations. The system CPU provides control ofall in-
system read, write, and erase operations ofthe device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
3.1
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes upper
address inputs to determine the accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through
ifADV# is held low. In synchronous mode, the address is latched by the first ofeither the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must
be VIL).
3.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See Section 4.0, “Read Operations” on page 19 for details on the available read modes, and see
Section 9.0, “Special Read States” on page 43 for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low power operation following reads during
active mode. After data is read from the memory array and the address lines are quiescent, APS
automatically places the device into standby. In APS, device current is reduced to ICCAPS (see
Section 11.3, “DC Current Characteristics” on page 49).
3.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted.
All device write operations are asynchronous, with CLK being ignored. During a write operation,
address and data are latched on the rising edge ofWE# or CE#, whichever occurs first. Table 4,
“Command Bus Cycles” on page 16 shows the bus cycle sequence for each of the supported device
commands, while Table 5, “Command Codes and Definitions” on page 17 describes each
command. See Section 12.0, “AC Characteristics” on page 51 for signal-timing details.
Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not
be attempted.
3.1.3
Output Disable
When OE# is deasserted, device outputs D[15:0] are disabled and placed in a high-impedance
(High-Z) state.
14
Datasheet
28F640L30, 28F128L30, 28F256L30
3.1.4
3.1.5
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing
power consumption. In standby, the data outputs are placed in High-Z, independent ofthe level
placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval,
5 µs after CE# is deasserted. During standby, average current is measured over the same time
interval 5 µs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset. When the
system comes out of reset, the system processor attempts to read from the flash memory if it is the
system boot device. Ifa CPU reset occurs with no flash memory reset, improper CPU initialization
may occur because the flash memory may be providing status information rather than array data.
Intel® flash memory devices allow proper CPU initialization following a system reset through the
use ofthe RST# input. RST# should be controlled by the same low-true reset signal that resets the
system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status
Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output
drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
process which takes a minimum amount oftime to complete. When RST# has been deasserted, the
device is reset to asynchronous Read Array state.
Note: IfRST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the initial read
access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can
be initiated. After this wake-up interval passes, normal operation is restored. See Section 12.0, “AC
Characteristics” on page 51 for details about signal-timing.
3.2
Device Commands
Device operations are initiated by writing specific device commands to the Command User
Interface (CUI). See Table 4, “Command Bus Cycles” on page 16.
Several commands are used to modify array data including Word Program and Block Erase
commands. Writing either command to the CUI initiates a sequence ofinternally -timed functions
that culminate in the completion ofthe requested task. However, the operation can be aborted by
either asserting RST# or by issuing an appropriate suspend command.
Datasheet
15
28F640L30, 28F128L30, 28F256L30
Table 4. Command Bus Cycles
First Bus Cycle
SecondBus Cycle
Addr1 Data2
Bus
Cycles
Mode
Command
Oper Addr1 Data2 Oper
Read Array
1
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
PnA
PnA
PnA
PnA
X
0xFF
0x90
0x98
0x70
0x50
Read Device Identifier
CFI Query
Read PBA+IA ID
Read PnA+QA QD
Read
Read Status Register
Clear Status Register
Read PnA
SRD
1
0x40/
0x10
Word Program
2
Write
Write
Write
WA
WA
WA
Write WA
Write WA
Write WA
WD
Program
Buffered Program3
≥ 2
> 2
0xE8
0x80
N - 1
0xD0
Buffered Enhanced Factory Program
(Buffered EFP)4
Erase
Block Erase
2
Write
BA
0x20
Write BA
0xD0
Program/Erase Suspend
Program/Erase Resume
Lock Block
1
1
2
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
X
X
0xB0
0xD0
0x60
0x60
0x60
0xC0
0xC0
Suspend
BA
BA
BA
PRA
LRA
Write BA
Write BA
Write BA
Write PRA
Write LRA
0x01
0xD0
0x2F
PD
Block
Locking/
Unlocking
Unlock Block
Lock-down Block
Program Protection Register
Program Lock Register
Protection
LRD
Configuration Program Read Configuration Register
2
Write
RCD
0x60
Write RCD
0x03
NOTES:
1. First command cycle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register address.
LRA = Lock Register address.
X = Any valid address within the device.
2. ID = Identifier data.
QD = Query data on D[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition.
3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is
followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation.
4. The confirm command (0xD0) is followed by the buffer data.
16
Datasheet
28F640L30, 28F128L30, 28F256L30
3.3
CommandDefinitions
Valid device command codes and descriptions are shown in Table 5.
Table 5. CommandCodes andDefinitions (Sheet 1 of 2)
Mode
Code Device Mode
Description
Places the addressed partition in Read Array mode. Array data is output on D[15:0].
0xFF Read Array
Read Status Places the addressed partition in Read Status Register mode. The partition enters this mode
0x70
0x90
Register
after a program or erase command is issued. Status Register data is output on D[7:0].
Read Device
ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/device codes, Configuration Register data,
Block Lock status, or Protection Register data on D[15:0].
Read
Places the addressed partition in Read Query mode. Subsequent reads from the partition
addresses output Common Flash Interface information on D[7:0].
0x98 Read Query
Clear Status The WSM can only set Status Register error bits. The Clear Status Register command is used
0x50
Register
to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the
next write cycle, the address and data are latched and the WSM executes the programming
Word Program algorithm at the addressed location. During program operations, the partition responds only to
0x40
Setup
Read Status Register and Program Suspend commands. CE# or OE# must be toggled to
update the Status Register. The Read Array command must be issued to read array data after
programming has finished.
AlternateWord
0x10 Program
Setup
Equivalent to the Word Program Setup command, 0x40.
Buffered
Program
This command loads a variable number of bytes up to the buffer size of 32 words onto the
program buffer.
0xE8
Write
Buffered
0xD0 Program
Confirm
The confirm command is Issued after the data streaming for writing into the buffer is done. This
instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer
to the flash memory array.
Buffered
Enhanced
0x80 Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode
(Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that
initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP mode
begins.
Buffered EFP If the previous command was Buffered EFP Setup (0x80), the CUI latches the address and
0xD0
Confirm
data, and prepares the device for Buffered EFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM
performs the erase algorithm on the block addressed by the Erase Confirm command. If the
next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits
SR[4] and SR[5], and places the addressed partition in read status register mode.
If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and
the WSM erases the addressed block. During block-erase operations, the partition responds
only to Read Status Register and Erase Suspend commands. CE# or OE# must be toggled to
update the Status Register.
Block Erase
Setup
0x20
Erase
Block Erase
Confirm
0xD0
This command issued to any device address initiates a suspend of the currently-executing
program or block erase operation. The Status Register indicates successful suspend operation
by setting either SR[2] (program suspended) or SR[6] (erase suspended), along with SR[7]
(ready). The Write State Machine remains in the suspend mode regardless of control signal
states (except for RST# asserted).
Program or
0xB0 Erase
Suspend
Suspend
Suspend
Resume
This command issued to any device address resumes the suspended program or block-erase
operation.
0xD0
Datasheet
17
28F640L30, 28F128L30, 28F256L30
Table 5. CommandCodes andDefinitions (Sheet 2 of 2)
Mode
Code Device Mode
Description
First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the
next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the
CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block is locked.
If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the
addressed block is in a lock-down state, the operation has no effect.
Lock Block
0x60
Setup
Block
Locking/
Unlocking
0x01 Lock Block
0xD0 Unlock Block
Lock-Down
0x2F
If the previous command was Block Lock Setup (0x60), the addressed block is locked down.
Block
Program
Protection
Register
Setup
First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock
Register program operation. The second cycle latches the register address and data, and starts
the programming algorithm. CE# or OE# must be toggled to update the Status Register. The
Read Array command must be issued to read array data after programming has finished.
Protection 0xC0
Read
First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set
Read Configuration Register command (0x03) is not the next command, the CUI sets Status
Register bits SR[4] and SR[5], indicating a command sequence error.
Configuration
Register
Setup
0x60
Configu-
ration
Read
If the previous command was Read Configuration Register Setup (0x60), the CUI latches the
0x03 Configuration address and writes A[15:0] to the Read Configuration Register. Following a Configure Read
Register Configuration Register command, subsequent read operations access array data.
18
Datasheet
28F640L30, 28F128L30, 28F256L30
4.0
ReadOperations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see Section 4.3, “Read Configuration Register (RCR)” on page 21).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the
device (see Section 3.2, “Device Commands” on page 15). See Section 9.0, “Special Read States”
on page 43 for details regarding Read Status, Read ID, and CFI Query modes.
Ifthe Read Array command is written to a partition that is performing a program or erase
operation, invalid data is read until the program or erase operation completes. Subsequent reads
produce array data. Ifa Program Suspend or Erase Suspend command is issued during a program
or erase operation, a subsequent Read Array command puts the addressed partition into Read
Array. The Read Array command functions independent of VPP.
The following sections describe read-mode operations in detail.
4.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array. Asynchronous page-mode reads are permitted in all blocks.
Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 4.3, “Read Configuration Register (RCR)” on page 21).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and
ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is asserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it can be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid VIH level. Array data
is driven onto D[15:0] after an initial access time tAVQV delay. (see Section 12.0, “AC
Characteristics” on page 51).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto D[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word group. Address bits A[1:0] determine which word ofthe 4-word group is output from
the data buffer at any given time.
Datasheet
19
28F640L30, 28F128L30, 28F256L30
4.2
Synchronous Burst-Mode Read
Read Configuration register bits CR[15:0] must be set before synchronous burst operation can be
performed. (See Section 4.3, “Read Configuration Register (RCR)” on page 21 for details).
Synchronous burst mode outputs 4, 8, 16, or a continuous number ofcontiguous words. To perform
a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are
asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then
deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access,
in which case the address is latched on the next valid CLK edge while ADV# is asserted.
The first word is output from the data buffer on the next valid CLK edge after the initial access
latency delay (see Section 4.3.2, “Latency Count” on page 22). Subsequent data is output on valid
CLK edges following a minimum delay. Synchronous burst-mode reads can only step through the
data buffer once, and can only do so in a sequential manner, starting from the address latched at the
beginning ofthe burst cycle (see Section 12.0, “AC Characteristics” on page 51).
During synchronous read operations, WAIT is driven with respect to CE#. WAIT indicates invalid
data when asserted, and valid data when de-asserted with respect to a valid clock edge. See Figure
18, “Burst Suspend Timing” on page 55 for additional details.
The device supports 4-word, 8-word, 16-word, and continuous-word bursts. Synchronous burst-
mode reads can only be performed in a partition that is in Read Array. If an attempt is made to
perform a synchronous burst-mode read from a partition that is not in Read Array (e.g. Read Status
Register, Read Device ID, CFI Query) the flash device still drives data onto the data bus with
respect to the clock, but not in accordance with the settings ofthe RCR. The addressed data is
output on the next valid clock edge following the initial asynchronous access delay, and remains on
the bus for the duration of the access cycle. WAIT is asserted during synchronous non-array read.
4.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred
when system software needs to suspend a burst sequence that is in progress in order to retrieve data
from another device on the same system bus. The system processor can resume the burst sequence
later. Burst suspend provides maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the device has output data. When a burst access is suspended, internal array sensing continues and
any previously latched internal data is retained. A burst sequence can be suspended and resumed
without limit as long as device operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL.
To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK edges resume
the burst sequence.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains active and
does not revert to a high-impedance state when OE# is deasserted. This can cause contention with
another device attempting to control the system’s READY signal during a Burst Suspend. Systems
using the Burst Suspend feature should not connect the device’s WAIT signal directly to the
system’s READY signal. See Figure 18, “Burst Suspend Timing” on page 55.
20
Datasheet
28F640L30, 28F128L30, 28F256L30
4.3
ReadConfiguration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the
synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read
Configuration Register command (see Section 3.2, “Device Commands” on page 15).
RCR contents can be examined using the Read Device Identifier command, and then reading from
<partition base address> + 0x05 (see Section 9.2, “Read Device Identifier” on page 44).
The RCR is shown in Table 6. The following sections describe each RCR bit.
Table 6. ReadConfiguration Register Description
ReadConfiguration Register (RCR)
Data WAIT
Hold Delay
Burst
Wrap
Read
Mode
WAIT
Burst
Seq
CLK
RES
Latency Count
LC[2:0]
RES RES
Burst Length
Polarity
Edge
RM
15
R
WP
10
DH
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Bit
15
Name
Description
Read Mode (RM)
Reserved (R)
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Reserved bits should be cleared (0)
14
13:11 Latency Count (LC[2:0])
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7
(Other bit settings are reserved)
10
9
Wait Polarity (WP)
Data Hold (DH)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8
Wait Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
0 =WAIT de-asserted with valid data
1 =WAIT de-asserted one data cycle before valid data (default)
7
0 =Reserved
1 =Linear (default)
6
0 = Falling edge
1 = Rising edge (default)
5:4
3
Reserved (R)
Reserved bits should be cleared (0)
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
NOTE: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be de-asserted with valid data (WD =
0). WD = 1 is not supported.
Datasheet
21
28F640L30, 28F128L30, 28F256L30
4.3.1
4.3.2
ReadMode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation
for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is
cleared, synchronous burst mode is selected.
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto D[15:0]. The input clock frequency is used to determine this value.
Figure 3 shows the data output latency for the different settings of LC[2:0].
During synchronous burst a Latency Count setting ofCode 5 will cause 1 WAIT state (Code 6 will
cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of
whether a 16-word boundary is crossed. IfCR.[9] (Data Hold) bit is set (data hold oftwo clocks)
this WAIT condition will not occur because enough clocks elapse during each burst cycle to
eliminate subsequent WAIT states.
Refer to Table 7, “LC and Frequency Support for Bin 1 tAVQV/tCHQV (90ns / 17ns)” on page 23
and Table 8, “LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns)” on page 23 for
Latency Code Settings.
Figure 3. First-Access Latency Count
CLK [C]
Address [A]
ADV# [V]
Valid
Address
Code0(Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
22
Datasheet
28F640L30, 28F128L30, 28F256L30
Table 7. LC andFrequency Support for Bin 1 t AVQV/tCHQV (90ns / 17ns)
Latency Count Settings
Frequency Support (MHz)
2
≤ 27
≤ 40
≤ 50
3
4, 5, 6, or 7
Table 8. LC andFrequency Support for Bin 2 t AVQV/tCHQV (110ns / 20ns)
Latency Count Settings
Frequency Support (MHz)
2
≤ 22
≤ 33
≤40
3
4, 5, 6, or 7
See Figure 4, “Example Latency Count Setting using Code 3” on page 23.
Figure 4. Example Latency Count Setting using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:0]
Code 3
High-Z
Data
D[15:0]
R103
4.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, RST#
deasserted).
Datasheet
23
28F640L30, 28F128L30, 28F256L30
4.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT signal
is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an “asserted” state as determined by CR[10].
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to an “asserted” state as determined by CR[10]. See Figure
13, “Asynchronous Single-Word Read (ADV# Latch)” on page 52, and Figure 14, “Asynchronous
Page-Mode Read Timing” on page 53.
From a system perspective, the WAIT signal is in the asserted state (based on CR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or ifthe device is operating in asynchronous mode (CR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity ofwhat is appearing on the data bus.
Table 9. WAIT Summary Table
CONDITION
WAIT
CE# = VIH
CE# = VIL
High-Z
Active
OE# = VIH
OE# = VIL
High-Z
Active
Synchronous Array Reads
Active
Synchronous Non-Array Reads
Asserted
All Asynchronous Reads and all Writes Asserted
NOTE: Active: WAIT is asserted until data becomes valid, then de-asserts
4.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on D[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH is
set, output data is held for two clocks (default). When DH is cleared, output data is held for one
clock (see Figure 5). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
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28F640L30, 28F128L30, 28F256L30
The equation is satisfied and data will be available at every clock period with data hold setting at
one clock.
Ift CHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of2 clock periods must be
used.
Figure 5. Data HoldTiming
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
1 CLK
Data Hold
Valid
Output
Valid
Output
Valid
Output
2 CLK
Data Hold
Valid
Output
Valid
Output
4.3.5
4.3.6
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst
reads. WAIT can be asserted either during or one data cycle before valid data is output on
DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid data (default). When
WD is cleared, WAIT is de-asserted during valid data.
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is
supported. Table 10 shows the synchronous burst sequence for all burst lengths, as well as the
effect of the Burst Wrap (BW) setting.
Table 10. Burst Sequence WordOrdering (Sheet 1 of 2)
Burst Addressing Sequence (DEC)
Start
Addr.
(DEC)
Burst Wrap
(RCR[3])
4-WordBurst
(BL[2:0] = 0b001)
8-WordBurst
16-WordBurst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
(BL[2:0] = 0b010)
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1-2-3-4-5…15-0
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-4
6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-…
7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13…
14
15
0
0
14-15-0-1-2…12-13
15-0-1-2-3…13-14
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
0
1
2
3
4
5
6
1
1
1
1
1
1
1
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
Datasheet
25
28F640L30, 28F128L30, 28F256L30
Table 10. Burst Sequence WordOrdering (Sheet 2 of 2)
7
1
7-8-9-10-11-12-13-14 7-8-9-10-11…21-22
7-8-9-10-11-12-13…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
4.3.7
4.3.8
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock
edge is used at the start ofa burst cycle, to output synchronous data, and to assert/deassert WAIT.
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries. When BW is
set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may occur
when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s
start address is 4-word aligned, then no delay occurs. Ifthe start address is at the end ofa 4-word
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.
This delay can take place only once, and doesn’t occur ifthe burst sequence does not cross a
device-row boundary. WAIT informs the system of this delay when it occurs.
4.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 10, “Burst Sequence Word Ordering” on page 25). When a burst cycle begins, the device
outputs synchronous burst data until it reaches the end ofthe “burstable” address space.
26
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28F640L30, 28F128L30, 28F256L30
5.0
Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (Buffered EFP) (80h,
D0h). See Section 3.0, “Device Operations” on page 14 for details on the various programming
commands issued to the device.
Successful programming requires the addressed block to be unlocked. If the block is locked down,
WP# must be deasserted and the block unlocked before attempting to program the block.
Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and
termination ofthe operation. See Section 7.0, “Security Modes” on page 35 for details on locking
and unlocking blocks.
The following sections describe device programming in detail.
5.1
WordProgramming
Word programming operations are initiated by writing the Word Program Setup command to the
device (see Section 3.0, “Device Operations” on page 14). This is followed by a second write to the
device with the address and data to be programmed. The partition accessed during both write
cycles outputs Status Register data when read. The partition accessed during the second cycle (the
data cycle) ofthe program command sequence is the location where the data is written. See Figure
29, “Word Program Flowchart” on page 70.
Programming can occur in only one partition at a time; all other partitions must be in a read state or
in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values
(nominally 1.8 V).
During programming, the Write State Machine (WSM) executes a sequence ofinternally-timed
events that program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.”
Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 6.0,
“Erase Operations” on page 33).
The Status Register can be examined for programming progress and errors by reading any address
within the partition that is being programmed. The partition remains in the Read Status Register
state until another command is written to that partition. Issuing the Read Status Register command
to another partition address sets that partition to the Read Status Register state, allowing
programming progress to be monitored at that partition’s address.
Status Register bit SR[7] indicates the programming status while the sequence executes.
Commands that can be issued to the programming partition during programming are Program
Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns
unknown data). CE# or OE# must be toggled to update Status Register contents.
When programming has finished, Status Register bit SR[4] (when set) indicates a programming
failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP
was outside ofits acceptable limits. IfSR[1] is set, the word programming operation attempted to
program a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow, when word
programming has completed.
Datasheet
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28F640L30, 28F128L30, 28F256L30
5.1.1
Factory WordProgramming
Factory word programming is similar to word programming in that it uses the same commands and
programming algorithms. However, factory word programming enhances the programming
performance with VPP = VPPH. This can enable faster programming times during OEM
manufacturing processes. Factory word programming is not intended for extended use. See Section
11.2, “Operating Conditions” on page 48 for limitations when VPP = VPPH
.
Note: When VPP = VPPL, the device draws programming current from the VCC supply. IfV PP is driven
by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH
the device draws programming current from the VPP supply. Figure 6, “Example VPP Supply
Connections” on page 32 shows examples ofdevice power supply configurations.
,
5.2
BufferedProgramming
The device features a 32-word buffer to enable optimum programming performance. For Buffered
Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed
into the flash memory array in buffer-size increments. This can improve system programming
performance significantly over non-buffered programming.
When the Buffered Programming Setup command is issued (see Section 3.2, “Device Commands”
on page 15), Status Register information is updated and reflects the availability of the buffer. SR[7]
indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To
retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is
set, the buffer is ready for loading. (see Figure 31, “Buffered Program Flowchart” on page 72).
On the next write, a word count is written to the device at the buffer address. This tells the device
how many data words will be written to the buffer, up to the maximum size of the buffer.
On the next write, a device start address is given along with the first data to be written to the flash
memory array. Subsequent writes provide additional device addresses and data. All data addresses
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning ofa 32-word
boundary (A[4:0] = 0x00). A misaligned starting address doubles the total program time.
After the last data is written to the buffer, the Buffered Programming Confirm command is issued.
The WSM begins to program buffer contents to the flash memory array. If a command other than
the Buffered Programming Confirm command is written to the device, a command sequence error
occurs and Status Register bits SR[7,5,4] are set. Ifan error occurs while writing to the array, the
device stops programming, and Status Register bits SR[7,4] are set, indicating a programming
failure.
Reading from another partition is allowed while data is being programmed into the array from the
write buffer (see Section 8.0, “Dual-Operation Considerations” on page 40).
Additional buffer writes can be initiated by issuing another Buffered Programming Setup
command and repeating the buffered program sequence. Buffered programming may be performed
with VPP = VPPL or VPPH (see Section 11.2, “Operating Conditions” on page 48 for limitations
when operating the device with VPP = VPPH).
When Status Register bits SR[5,4] are set, the device does not accept Buffered Program
commands. If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command sequence error, and
Status Register bits SR[5,4] are set.
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If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are
set. Ifany errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
5.3
BufferedEnhancedFactory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash
programming for today's beat-rate-sensitive manufacturing environments. The enhanced
programming algorithm used in Buffered EFP eliminates traditional programming elements that
drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 32, “Buffered
EFP Flowchart” on page 73). It uses a write buffer to spread MLC program performance across 32
data words. Verification occurs in the same phase as programming to accurately program the flash
memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block ofdata. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each set of 32 data
words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0]
indicates when data from the buffer has been programmed into sequential flash memory array
locations.
Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)
increments internal addressing to automatically select the next 32-word array boundary. This
aspect of Buffered EFP saves host programming equipment the address-bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the device has programmed properly. This eliminates the external post-
program verification and its associated overhead.
5.3.1
BufferedEFP Requirements andConsiderations
Buffered EFP requirements:
• Ambient temperature: TA = 25°C, 5°C
• VCC within specified operating range.
• VPP driven to VPPH
.
• Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.
• The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired.
1
• WA0 must align with the start ofan array bufer boundary
.
Buffered EFP considerations:
• For optimum performance, cycling must be limited below 100 erase cycles per block2.
• Buffered EFP programs one block at a time; all buffer data must fall within a single block3.
• Buffered EFP cannot be suspended.
• Programming to the flash memory array can occur only when the buffer is full4.
Datasheet
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28F640L30, 28F128L30, 28F256L30
• Read operation while performing Buffered EFP is not supported.
NOTES:
1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point
is A[4:0] = 0x00.
2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to
work properly.
3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to
the beginning of the block.
4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
5.3.2
BufferedEFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay
before checking SR[7] is required to allow the WSM enough time to perform all of its setups and
checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP
operation terminates. Ifthe block was found to be locked, SR[1] is also set. SR[3] is set ifthe error
occurred due to an incorrect VPP level.
Note: Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be interpreted as data
to be loaded into the buffer.
5.3.3
BufferedEFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability ofthe write bufer for data streaming. SR[7] cleared indicates
the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the
write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data
programming to the array. For Buffered EFP, the count value for buffer loading is always the
maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential
buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory
array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer
locations must be filled with 0xFFFF.
Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the
current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any
data previously loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm
will be aborted and the program fail (SR[4]) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the flash memory
array; programming continues from where the previous buffer sequence ended. The host
programming system must poll SR[0] to determine when the buffer program sequence completes.
SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set
indicates that the buffer is not available yet for the next fill cycle. The host system may check full
status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit.
The host programming system continues the Buffered EFP algorithm by providing the next group
ofdata words to be written to the bufer. Alternatively, it can terminate this phase by changing the
block address to one outside ofthe current block’s range.
30
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28F640L30, 28F128L30, 28F256L30
The Program/Verify phase concludes when the programmer writes to a different block address;
data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the
Buffered EFP Exit phase.
5.3.4
BufferedEFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check
should be performed on the partition being programmed at this time to ensure the entire block
programmed successfully. When exiting the Buffered EFP algorithm with a block address change,
the read mode ofboth the programmed and the addressed partition will not change. After Bufered
EFP exit, any valid command can be issued to the device.
5.4
Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation.
This allows data to be accessed from memory locations other than the one being programmed. The
Program Suspend command can be issued to any device address; the corresponding partition is not
affected. A program operation can be suspended to perform reads only. Additionally, a program
operation that is running during an erase suspend can be suspended to perform a read operation
(see Figure 30, “Program Suspend/Resume Flowchart” on page 71).
When a programming operation is executing, issuing the Program Suspend command requests the
WSM to suspend the programming algorithm at predetermined points. The partition that is
suspended continues to output Status Register data after the Program Suspend command is issued.
Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified
in Section 12.3, “Program and Erase Characteristics” on page 60.
To read data from blocks within the suspended partition, the Read Array command must be issued
to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, program
RCR, and Program Resume are valid commands during a program suspend.
A program operation does not need to be suspended in order to read data from a block in another
partition that is not programming. Ifthe other partition is already in a Read Array, Read Device
Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other
partition is not in a read mode, one ofthe read commands must be issued to the partition before
data can be read.
During a program suspend, deasserting CE# places the device in standby, reducing active current.
VPP must remain at its programming level, and WP# must remain unchanged while in program
suspend. IfRST# is asserted, the device is reset.
5.5
Program Resume
The Resume command instructs the device to continue programming, and automatically clears
Status Register bits SR[7,2]. This command can be written to any partition. When read at the
partition that’s programming, the device outputs data corresponding to the partition’s last state. If
error bits are set, the Status Register should be cleared before issuing the next instruction. RST#
must remain deasserted (see Figure 30, “Program Suspend/Resume Flowchart” on page 71).
Datasheet
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28F640L30, 28F128L30, 28F256L30
5.6
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is
below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block
lock registers are not affected by the voltage level on VPP; they may still be programmed and read,
even ifV PP is less than VPPLK
.
Figure 6. Example VPP Supply Connections
VCC
VCC
VCC
VPP
VCC
VPP
VPP
PROT#
10
KΩ
Factory Word Programming with VPP = VPPH
LowVoltage Programming Only
Logic Control of Device Protection
Complete Write/Erase Protection when VPP < VPPLK
VCC
VCC
VCC
VCC
VPP
VPP = VPPH
VPP
LowVoltage and Factory Word Programming
LowVoltage Programming Only
Full Device Protection Unavailable
32
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6.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an erase command
sequence is issued, and only one block is erased at a time. When a block is erased, all bits within
that block read as logical ones. The following sections describe block erase operations in detail.
6.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of
the block to be erased (see Section 3.2, “Device Commands” on page 15). Next, the Block Erase
Confirm command is written to the address of the block to be erased. Erasing can occur in only one
partition at a time; all other partitions must be in a read state. Ifthe device is placed in standby
(CE# deasserted) during an erase operation, the device completes the erase operation before
entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 33, “Block
Erase Flowchart” on page 74).
During a block erase, the Write State Machine (WSM) executes a sequence ofinternally-timed
events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones.” Memory array bits that are ones can be changed to zeros only by
programming the block (see Section 5.0, “Programming Operations” on page 27).
The Status Register can be examined for block erase progress and errors by reading any address
within the partition that is being erased. The partition remains in the Read Status Register state
until another command is written to that partition. Issuing the Read Status Register command to
another partition address sets that partition to the Read Status Register state, allowing erase
progress to be monitored at that partition’s address. SR[0] indicates whether the addressed partition
or another partition is erasing. The partition’s Status Register bit SR[7] is set upon erase
completion.
Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase
operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would
indicate that the WSM could not perform the erase operation because VPP was outside ofits
acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block,
causing the operation to abort. CE# or OE# must be toggled to update Status Register contents.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow once the block erase
operation has completed.
6.2
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows
data to be accessed from memory locations other than the one being erased. The Erase Suspend
command can be issued to any device address; the corresponding partition is not affected. A block
erase operation can be suspended to perform a word or write-buffer program operation, or a read
operation within any block except the block that is erase suspended (see Figure 30, “Program
Suspend/Resume Flowchart” on page 71).
Datasheet
33
28F640L30, 28F128L30, 28F256L30
When a block erase operation is executing, issuing the Erase Suspend command requests the WSM
to suspend the erase algorithm at predetermined points. The partition that is suspended continues to
output Status Register data after the Erase Suspend command is issued. Block erase is suspended
when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 12.3, “Program
and Erase Characteristics” on page 60.
To read data from blocks within the suspended partition (other than an erase-suspended block), the
Read Array command must be issued to that partition first. During Erase Suspend, a Program
command can be issued to any block other than the erase-suspended block. Block erase cannot
resume until program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase
Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block
Unlock, and Block Lock-Down are valid commands during Erase Suspend.
To read data from a block in a partition that is not erasing, the erase operation does not need to be
suspended. Ifthe other partition is already in Read Array, Read Device Identifier, or CFI Query,
issuing a valid address returns corresponding data. Ifthe other partition is not in a read state, one of
the read commands must be issued to the partition before data can be read.
During an erase suspend, deasserting CE# places the device in standby, reducing active current.
VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If
RST# is asserted, the device is reset.
6.3
6.4
Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears
status register bits SR[7,6]. This command can be written to any partition. When read at the
partition that’s erasing, the device outputs data corresponding to the partition’s last state. Ifstatus
register error bits are set, the Status Register should be cleared before issuing the next instruction.
RST# must remain deasserted (see Figure 30, “Program Suspend/Resume Flowchart” on page 71).
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is
below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.
34
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28F640L30, 28F128L30, 28F256L30
7.0
Security Modes
The device features security modes used to protect the information stored in the flash memory
array. The following sections describe each security mode in detail.
7.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash memory
array. All blocks power up in a locked state to protect array data from being altered during power
transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be
programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock commands.
Hardware-controlled security can be implemented using the Block Lock-Down command along
with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations
(see Section 5.6, “Program Protection” on page 32 and Section 6.4, “Erase Protection” on page 34).
7.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block
command issued to the desired block’s address (see Section 3.2, “Device Commands” on page 15
and Figure 35, “Block Lock Operations Flowchart” on page 76). Ifthe Set Read Configuration
Register command is issued after the Block Lock Setup command, the device configures the RCR
instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits
may be modified and/or read even if VPP is below VPPLK
.
7.1.2
7.1.3
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 3.2, “Device Commands” on
page 15). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a
locked state when the device is reset or powered down. Ifa block is in a lock-down state, WP#
must be deasserted before it can be unlocked (see Figure 7, “Block Locking State Diagram” on
page 36).
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block command
sequence (see Section 3.2, “Device Commands” on page 15). Blocks in a lock-down state cannot
be programmed or erased; they can only be read. However, unlike locked blocks, their locked state
cannot be changed by software commands alone. A locked-down block can only be unlocked by
issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-
down state, a Lock command must be issued prior to changing WP# to VIL. Locked-down blocks
revert to the locked state upon reset or power up the device (see Figure 7, “Block Locking State
Diagram” on page 36).
Datasheet
35
28F640L30, 28F128L30, 28F256L30
7.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see Section 9.2,
“Read Device Identifier” on page 44). Data bits D[1:0] display the addressed block’s lock status;
D0 is the addressed block’s lock bit, while D1 is the addressed block’s lock-down bit.
Figure 7. Block Locking State Diagram
UNLOCKED
LOCKED
60h/
D0h
60h/01h
[000]
[001]
Power-Up/Reset
Default
60h/
2Fh
WP# = VIL = 0
[011]
Locked-down
60h/
01h
Locked-down is disabled by
WP# = VIH
60h/D0h
[110]
[111]
60h/
2Fh
WP# = VIH = 1
60h/
2Fh
Power-Up/Reset
Default
60h/
D0h
60h/
01h
[100]
[101]
60h/D0h = Unlock Command
60h/01h = Lock Command
60h/2Fh = Lock-Down Command
7.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change block
locking during an erase operation, first issue the Erase Suspend command. Monitor the Status
Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept
another command.
Next, write the desired lock command sequence to a block, which changes the lock state ofthat
block. After completing block lock or unlock operations, resume the erase operation using the
Erase Resume command.
36
Datasheet
28F640L30, 28F128L30, 28F256L30
Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,
or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and
SR[5]. Ifa command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set,
even after the erase operation is resumed. Unless the Status Register is cleared using the Clear
Status Register command before resuming the erase operation, possible erase errors may be
masked by the command sequence error.
Ifa block is locked or locked-down during an erase suspend ofthe same block, the lock status bits
change immediately. However, the erase operation completes when it is resumed. Block lock
operations cannot occur during a program suspend. See Appendix A, “Write State Machine
(WSM)” on page 63, which shows valid commands during an erase suspend.
7.2
Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security
measures and/or device identification. Each Protection Register can be individually locked.
The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-
bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit
segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program
these registers as needed. When programmed, users can then lock the Protection Register(s) to
prevent additional bit programming (see Figure 8, “Protection Register Map” on page 38).
The user-programmable Protection Registers contain one-time programmable (OTP) bits; when
programmed, register bits cannot be erased. Each Protection Register can be accessed multiple
times to program individual bits, as long as the register remains unlocked.
Each Protection Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated Protection Register can only be read; it can no longer be programmed.
Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock
Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be
unlocked
Datasheet
37
28F640L30, 28F128L30, 28F256L30
.
Figure 8. Protection Register Map
0x109
128-bit Protection Register 16
(User-Programmable)
0x102
0x91
128-bit Protection Register 1
(User-Programmable)
0x8A
0x89
Lock Register 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7.2.1
Reading the Protection Registers
The Protection Registers can be read from within any partition’s address space. To read the
Protection Register, first issue the Read Device Identifier command at any partitions’ address to
place that partition in the Read Device Identifier state (see Section 3.2, “Device Commands” on
page 15). Next, perform a read operation at that partition’s base address plus the address offset
corresponding to the register to be read. Table 13, “Device Identifier Information” on page 45
shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16
bits at a time.
Note: Ifa program or erase operation occurs within the device while it is reading a Protection Register,
certain restrictions may apply. See Table 11, “Simultaneous Operation Restrictions” on page 42 for
details.
38
Datasheet
28F640L30, 28F128L30, 28F256L30
7.2.2
Programming the Protection Registers
To program any ofthe Protection Registers, first issue the Program Protection Register command
at the parameter partition’s base address plus the offset to the desired Protection Register (see
Section 3.2, “Device Commands” on page 15). Next, write the desired Protection Register data to
the same Protection Register address (see Figure 8, “Protection Register Map” on page 38).
The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at
a time (see Figure 36, “Protection Register Programming Flowchart” on page 77). Issuing the
Program Protection Register command outside ofthe Protection Register’s address space causes a
program error (SR[4] set). Attempting to program a locked Protection Register causes a program
error (SR[4] set) and a lock error (SR[1] set).
Note: Ifa program or erase operation occurs when programming a Protection Register, certain
restrictions may apply. See Table 11, “Simultaneous Operation Restrictions” on page 42 for details.
7.2.3
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the Lock
Register. To lock a Protection Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register data (see
Section 3.2, “Device Commands” on page 15). The physical addresses ofthe Lock Registers are
0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock
registers (see Table 13, “Device Identifier Information” on page 45).
Bit 0 ofLock Register 0 is already programmed at the factory, locking the lower, pre-programmed
64-bit region of the first 128-bit Protection Register containing the unique identification number of
the device. Bit 1 ofLock Register 0 can be programmed by the user to lock the user-programmable,
64-bit region ofthe first 128-bit Protection Register. The other bits in Lock Register 0 are not used.
Lock Register 1 controls the locking ofthe upper sixteen 128-bit Protection Registers. Each ofthe
16 bits ofLock Register 1 correspond to each ofthe upper sixteen 128-bit Protection Registers.
Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.
Caution: After being locked, the Protection Registers cannot be unlocked.
Datasheet
39
28F640L30, 28F128L30, 28F256L30
8.0
Dual-Operation Considerations
The multi-partition architecture ofthe device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
8.1
Memory Partitioning
The L30 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous
read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at
a time can be in program or erase mode.
The flash device supports read-while-write operations with bus cycle granularity and not command
granularity. In other words, it is not assumed that both bus cycles ofa two cycle command (an erase
command for example) will always occur as back to back bus cycles to the flash device. In
practice, code fetches (reads) may be interspersed between write cycles to the flash device, and
they will likely be directed to a different partition than the one being written. This is especially true
when a processor is executing code from one partition that instructs the processor to program or
erase in another partition.
8.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (Figure 9, and Figure 10). However, a write operation issued between a 2-cycle
commands write sequence causes a command sequence error. (See Figure 11)
When reading from the same partition after issuing a Setup command, Status Register data is
returned, regardless ofthe read mode ofthe partition prior to issuing the Setup command.
.
Figure 9. Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition A
Partition B
OE# [G]
Data [D/Q]
0x20
0xD0
0xFF
40
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 10. Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
OE# [G]
Data [D/Q]
0x20
Valid Array Data
0xD0
Figure 11. Operating Mode with Illegal Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
Partition A
OE# [G]
Data [D/Q]
0x20
0xFF
0xD0
SR[7:0]
8.2.1
8.2.2
Simultaneous Operation Details
The L30 flash memory device supports simultaneous read from one partition while programming
or erasing in any other partition. Certain features like the Protection Registers and Query data have
special requirements with respect to simultaneous operation capability. These will be detailed in
the following sections.
Synchronous andAsynchronous Read-While-Write Characteristics
andWaveforms
W18 - t
WHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a
write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
W19 andW20 - t
andt
WHVH
WHCV
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to
ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a
synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high
to latch a new address must be met.
See Figure 21, “Write to Asynchronous Read Timing” on page 58, Figure 22, “Synchronous Read
to Write Timing” on page 58 and Figure 23, “Write to Synchronous Read Timing” on page 59 for
representation ofthese timings.
Datasheet
41
28F640L30, 28F128L30, 28F256L30
8.2.3
ReadOperation During BufferedProgramming Flowchart
The multi-partition architecture ofthe device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
To perform a read while buffered programming operation, first issue a Buffered Program set up
command in a partition. When a read operation occurs in the same partition after issuing a setup
command, Status Register data will be returned, regardless ofthe read mode ofthe partition prior to
issuing the setup command. Toggle CE# or OE# to update Status Register data.
To read data from a block in other partition and the other partition already in read array mode, a
new block address must be issued. However, ifthe other partition is not already in read array mode,
issuing a read array command will cause the buffered program operation to abort and a command
sequence error would be posted in the Status Register. See Figure 37, “Read While Buffered
Programming Flowchart” on page 78 for more details.
Note: Simultaneous read-while-Buffered EFP is not supported.
8.3
Simultaneous Operation Restrictions
Since the L30 flash memory device supports simultaneous read from one partition while
programming or erasing in another partition, certain features like the Protection Registers and CFI
Query data have special requirements with respect to simultaneous operation capability. (Table 11
provides details on restrictions during simultaneous operations.)
Table 11. Simultaneous Operation Restrictions
Protection Parameter
Other
Register or
CFI data
Partition
Notes
Partitions
Array Data
While programming or erasing in a main partition, the Protection
Register or CFI data may be read from any other partition.
Read
(See Notes)
Read
(See Notes) Write/Erase
Reading the parameter partition array data is not allowed if the
Protection Register or Query data is being read from addresses
within the parameter partition.
While programming or erasing in a main partition, read operations
are allowed in the parameter partition.
Read
Read
Write/Erase
Write/Erase
Accessing the Protection Registers or CFI data from parameter
partition addresses is not allowed when reading array data from the
parameter partition.
While programming or erasing in a main partition, read operations
are allowed in the parameter partition.
Accessing the Protection Registers or CFI data in a partition that is
different from the one being programed/erased, and also different
from the parameter partition is allowed.
While programming the Protection Register, reads are only allowed
in the other main partitions.
No Access
Allowed
Write
Read
Read
Access to array data in the parameter partition is not allowed.
Programming of the Protection Register can only occur in the
parameter partition, which means this partition is in Read Status.
While programming or erasing the parameter partition, reads of the
Protection Registers or CFI data are not allowed in any partition.
No Access
Allowed
Write/Erase
Reads in partitions other than the main partitions are supported.
42
Datasheet
28F640L30, 28F128L30, 28F256L30
9.0
Special ReadStates
The following sections describe non-array read states. Non-array reads can be performed in
asynchronous read or synchronous burst mode. However, a non-array read operation occurs as
asynchronous single-word mode or single synchronous mode. When non-array reads are performed
in page mode or burst mode, only the first data is valid. All subsequent data are undefined.
Each partition can be in one ofits read states independent ofother partitions’ modes. See Figure
12, “Asynchronous Single-Word Read (ADV# Low)” on page 52 and Figure 15, “Synchronous
Single-Word Array-Read Timing” on page 53 for details.
9.1
ReadStatus Register
The status ofany partition is determined by reading the Status Register from the address ofthat
particular partition. To read the Status Register, issue the Read Status Register command within the
desired partition’s address range. Status Register information is available at the partition address to
which the Read Status Register, Word Program, or Block Erase command was issued. Status
Register data is automatically made available following a Word Program, Block Erase, or Block
Lock command sequence. Reads from a partition after any of these command sequences outputs
that partition’s status until another valid command is written to that partition (e.g. Read Array
command).
Status Register data is output on D[7:0], while 0x00 is output on D[15:8]. The falling edge of OE#,
ADV#, or CE# (whichever occurs first) updates and latches the Status Register contents. Status
Register read operations do not affect the read state of the other partitions.
The Device Write Status bit (SR[7]) provides overall status ofthe device. The Partition Status bit
(SR[0]) indicates whether the addressed partition or some other partition is actively programming
or erasing. Status register bits SR[6:1] present status and error information about the program,
erase, suspend, VPP, and block-locked operations.
Table 12. Status Register Description (Sheet 1 of 2)
Default Value = 0x80
Status Register (SR)
Erase
Suspend
Status
Program
Suspend
Status
Block-
Partition
Locked
Status
Device
Write Status
Erase
Status
Program
Status
V
Status
PP
Status
DWS
7
ESS
6
ES
5
PS
4
VPPS
PSS
2
BLS
1
PWS
0
3
Bit
Name
Description
Device Write Status
(DWS)
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
7
6
5
4
3
Erase Suspend Status
(ESS)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
0 = Erase successful.
1 = Erase fail or program sequence error when set with SR[4,7].
Erase Status (ES)
0 = Program successful.
1 = Program fail or program sequence error when set with SR[5,7]
Program Status (PS)
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
V
Status (VPPS)
PP
Datasheet
43
28F640L30, 28F128L30, 28F256L30
Table 12. Status Register Description (Sheet 2 of 2)
Status Register (SR)
Default Value = 0x80
Program Suspend Status 0 = Program suspend not in effect.
2
1
(PSS)
1 = Program suspend in effect.
Block-Locked Status
(BLS)
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
DWS PWS
0
0
1
1
0
1
0
1
= Program or erase operation in addressed partition.
= Program or erase operation in other partition.
= No active program or erase operations.
= Reserved.
Partition Write Status
(PWS)
0
(Non-buffered EFP operation. For Buffered EFP operation, see
Section 5.3, “Buffered Enhanced Factory Programming” on
page 29).
Always clear the Status Register prior to resuming erase operations. Avoids Status Register
ambiguity when issuing commands during Erase Suspend. Ifa command sequence error occurs
during an erase-suspend state, the Status Register contains the command sequence error status
(SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase
operation cannot be detected via the Status Register because it contains the previous error status.
9.1.1
Clear Status Register
The Clear Status Register command clears the status register, leaving all partition read states
unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears
SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared
before starting a command sequence to avoid any ambiguity. A device reset also clears the Status
Register.
9.2
ReadDevice Identifier
The Read Device Identifier command instructs the addressed partition to output manufacturer
code, device identifier code, block-lock status, protection register data, or configuration register
data when that partition’s addresses are read (see Section 3.2, “Device Commands” on page 15 for
details on issuing the Read Device Identifier command). Table 13, “Device Identifier Information”
on page 45 and Table 14, “Device ID codes” on page 45 show the address offsets and data values
for this device.
Issuing a Read Device Identifier command to a partition that is programming or erasing places that
partition in the Read Identifier state while the partition continues to program or erase in the
background.
44
Datasheet
28F640L30, 28F128L30, 28F256L30
Table 13. Device Identifier Information
Item
Address(1,2)
Data
Manufacturer Code
PBA + 0x00
PBA + 0x01
0089h
Device ID Code
ID (see Table 14)
Block Lock Configuration:
• Block Is Unlocked
Lock Bit:
DQ = 0b0
0
• Block Is Locked
BBA + 0x02
DQ = 0b1
0
• Block Is not Locked-Dow n
• Block Is Locked-Dow n
Configuration Register
DQ = 0b0
1
DQ = 0b1
1
PBA + 0x05
PBA + 0x80
Configuration Register Data
PR-LK0
Lock Register 0
64-bit Factory-Programmed Protection Register
64-bit User-Programmable Protection Register
Lock Register 1
PBA + 0x81–0x84 Factory Protection Register Data
PBA + 0x85–0x88 User Protection Register Data
PBA + 0x89
Protection Register Data
128-bit User-Programmable Protection Registers
PBA + 0x8A–0x109 PR-LK1
NOTES:
1. PBA = Partition Base Address.
2. BBA = Block Base Address.
Table 14. Device ID codes
Device Identifier Codes
–T –B
ID Code Type
Device Density
(Top Parameter) (Bottom Parameter)
64 Mbit
128 Mbit
256 Mbit
8811
8812
8813
8814
8815
8816
Device Code
9.3
CFI Query
The CFI Query command instructs the device to output Common Flash Interface (CFI) data when
partition addresses are read. See Section 3.2, “Device Commands” on page 15 for details on
issuing the CFI Query command. Appendix C, “Common Flash Interface” on page 79 shows CFI
information and address offsets within the CFI database.
Issuing the CFI Query command to a partition that is programming or erasing places that partition’s
outputs in the CFI Query state, while the partition continues to program or erase in the background.
The CFI Query command is subject to read restrictions dependent on parameter partition
availability, as described in Table 11.
Datasheet
45
28F640L30, 28F128L30, 28F256L30
10.0
Power andReset
10.1
Power-Up/Down Characteristics
Power supply sequencing is not required ifVCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before
applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
10.2
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power supply current
considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks
produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the device enable
charge-pumps, and internal logic states change at high speed. All ofthese internal activities
produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive
and inductive loading. Two-line control and correct de-coupling capacitor selection suppress
transient voltage peaks.
Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP,
and VCCQ, each power connection should have a 0.1 µF ceramic capacitor connected to a
corresponding ground connection (e.g.VCCQ to VSSQ). High-frequency, inherently low-
inductance capacitors should be placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be
placed between power and ground close to the devices. The bulk capacitor is meant to overcome
voltage droop caused by PCB trace inductance.
10.3
10.4
Automatic Power Saving (APS)
Automatic Power Saving (APS) provides low power operation during a read’s active state. ICCAPS
is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During
APS, average current is measured over the same time interval 5 µs after the following events
happen: (1) there is no internal read, program or erase operations cease; (2) CE# is asserted; (3) the
address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS.
Reset Characteristics
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active-low reset signal used for CPU initialization.
46
Datasheet
28F640L30, 28F128L30, 28F256L30
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level ofmemory protection.
System designers should guard against spurious writes when VCC voltages are above VLKO
.
Because both WE# and CE# must be asserted for a write operation, deasserting either signal
inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because alteration
ofmemory contents can only occur after successful completion ofa two-step command sequence
(see Section 3.2, “Device Commands” on page 15).
Datasheet
47
28F640L30, 28F128L30, 28F256L30
11.0
Thermal andDC Characteristics
11.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
Parameter
Maximum Rating
–25 °C to +85 °C
Notes
Temperature under bias
Storage temperature
–65 °C to +125 °C
–0.5 V to +3.8 V
–0.2 V to +14 V
–0.2 V to +2.45 V
–0.2 V to +3.8 V
100 mA
Voltage on any signal (except VCC, VPP)
VPP voltage
1
1,2,3
1
VCC voltage
VCCQ voltage
1
Output short circuit current
NOTES:
1. Voltages shown are specified with respect to V . Minimum DC voltage is –0.5 V on input/output signals
and
4
SS
–0.2 V on V , V
, and V . During transitions, this level may undershoot to –2.0 V for periods <20 ns.
PP
CC CCQ
Maximum DC voltage on V is V +0.5 V, which, during transitions, may overshoot to V +2.0 V for
periods <20 ns. Maximum DC voltage on input/output signals and V
transitions, may overshoot to V
2. Maximum DC voltage on V may overshoot to +14.0 V for periods <20 ns.
CC
CC
CC
is V
+0.5 V, which, during
CCQ
CCQ
+2.0 V for periods <20 ns.
CCQ
PP
3. Program/erase voltage is typically 1.7 V–2.0 V. 9.0 V can be applied for 80 hours maximum total, to any
blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
11.2
Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Symbol
Parameter
Min
Max
Units
Notes
T
Operating Temperature
VCC Supply Voltage
I/O Supply Voltage
–25
1.7
2.2
0.9
8.5
+85
2.0
3.3
2.0
9.5
80
°C
A
V
CC
V
CCQ
V
V
V
Voltage Supply (Logic Level)
PPL
PPH
PPH
PP
V
Factory word programming V
Maximum VPP Hours
PP
t
V
V
V
V
= V
= V
= V
= V
Hours
PP
PP
PP
PP
PPH
1
Main and Parameter Blocks
100,000
CC
Block
Erase Main Blocks
Cycles
1000
2500
Cycles
PPH
PPH
Parameter Blocks
NOTES:
1. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.50 V – 9.5 V for 1000
cycles on main blocks, and 2500 cycles on parameter blocks.
48
Datasheet
28F640L30, 28F128L30, 28F256L30
11.3
DC Current Characteristics
VCCQ
2.2 V – 3.3 V
Sym
Parameter
Unit
µA
Test Conditions
= V Max
Notes
Typ
Max
V
V
V
CC
CC
I
Input Load Current
2
= V
Max
or GND
LI
CCQ
CCQ
= V
IN
CCQ
1
Output
V
V
V
= V Max
CC CC
I
Leakage D[15:0], WAIT
Current
10
µA
= V
Max
CCQ
LO
CCQ
= V
or GND
IN
CCQ
64 Mbit
128 Mbit 30
20
35
55
V
= V Max
CC CC
V
= V
CCQ
Max
(for I
CCQ
CCQ
I
I
V
Standby,
CE# = V
CCS
CC
µA
RST# = V
RST# = GND (for I
WP# = V
)
CCS
CCD
Power Down
CCQ
CCD
256 Mbit 55
95
)
IH
1,2
64 Mbit
128 Mbit 30
20
35
55
V
= V Max
CC CC
V
= V Max
CCQ
CCQ
SSQ
CCQ
CE# = V
I
APS
µA
CCAPS
RST# = V
256 Mbit 55
95
All inputs are at rail to rail (V
or V
).
SSQ
CCQ
Asynchronous Single-Word
f = 5MHz (1 CLK)
Page-Mode Read
f = 13 MHz (5 CLK)
14
9
16
10
mA
mA 4-Word Read
16
20
23
19
24
27
mA Burst length=4
mA Burst length=8
mA Burst length=16
V
= V MAX
CC
CC
CE# = V
Synchronous Burst Read
f = 40MHz
IL
Average
Read
Current
I
V
OE# = V
IH
1
CCR
CC
Burst length =
30
35
mA
Inputs: V or V
IL
IH
Continuous
18
24
28
21
28
33
mA Burst length=4
mA Burst length=8
mA Burst length=16
Synchronous Burst Read
f = 54MHz
Burst Length =
Continuous
30
36
26
35
51
33
mA
1,3,4,
7
1,3,5,
7
mA
mA
V
= V , program/erase in progress
PPL
PP
PP
V
V
Program Current,
I
I
CC
CCW,
CCE
Erase Current
CC
V
= V
, program/erase in progress
PPH
64 Mbit
20
128 Mbit 30
256 Mbit 55
35
55
95
I
V
V
Program Suspend Current,
Erase Suspend Current
CCWS,
CC
µA CE# = V
; suspend in progress
1,6,3
1,3
CCQ
I
CCES
CC
I
V
V
V
Standby Current,
PPS,
PP
PP
PP
I
Program Suspend Current,
Erase Suspend Current
0.2
5
µA
V
= V , suspend in progress
PPWS,
PP PPL
I
PPES
Datasheet
49
28F640L30, 28F128L30, 28F256L30
VCCQ
2.2 V – 3.3 V
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
I
V
V
Read
2
15
µA
V
V
V
V
V
≤ V
= V
= V
= V
= V
PPR
PP
PP
PP
PP
PP
PP
CC
0.05 0.10
22
0.05 0.10
22
program in progress
program in progress
erase in progress
erase in progress
PPL,
PPH,
PPL,
PPH,
I
Program Current
Erase Current
mA
PPW
PP
8
1,3
I
V
mA
PPE
PP
8
NOTES:
1. All currents are RMS unless noted. Typical values at typical V , T = +25°C.
CC
A
2. I
is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
CCS
3. Sampled, not 100% tested.
4. V read + program current is the sum of V read and V program currents.
CC
CC
CC
5. V read + erase current is the sum of V read and V erase currents.
CC
CC
CC
6. I
7. I
is specified with the device deselected. If device is read while in erase suspend, current is I
plus I
.
CCR
CCES
CCES
, I
measured over typical or max times specified in Section 12.3, “Program and Erase Characteristics” on
CCW CCE
page 60
11.4
DC Voltage Characteristics
VCCQ
2.2 V – 3.3 V
Sym
Parameter
Unit
Test Condition
Notes
Min
Max
V
Input LowVoltage
0
0.4
V
V
1
IL
V
–0.4
CCQ
V
Input High Voltage
Output LowVoltage
V
CCQ
IH
V
V
= V MIN
CC
CC
V
0.1
V
V
= V
MIN
OL
CCQ
CCQ
I
= 100 µA
OL
V
V
= V MIN
CC
CC
CCQ
V
CCQ
V
Output High Voltage
= V
= –100 µA
MIN
OH
CCQ
–0.1
I
OH
V
V
V
V
Lock-Out Voltage
Lock Voltage
0.4
V
V
V
2
PPLK
PP
V
1.0
0.9
LKO
CC
V
Lock Voltage
LKOQ
CCQ
NOTES:
1. V can undershoot to –0.4V and V can overshoot to V +0.4V for durations of 20 ns or less.
CCQ
IL
PP
IH
2. V < V
inhibits erase and program operations. Do not use V
and V
outside their valid ranges.
PPLK
PPL
PPH
50
Datasheet
28F640L30, 28F128L30, 28F256L30
12.0
AC Characteristics
12.1
AC ReadSpecifications (V CCQ = 2.2 V – 3.3 V)
Speed–90
Min
–110
Min
Num
Symbol
Parameter
Units Notes
Max
Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
Read cycle time
90
110
ns
Address to output valid
CE# lowto output valid
90
90
110
110
30
ns
ns
ns
ns
ns
ns
ns
6
OE# lowto output valid
25
1,2
1
RST# high to output valid
CE# lowto output in low-Z
OE# lowto output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
150
150
0
0
0
1,3
0
1,2,3
24
24
24
24
ns
ns
ns
1,3
Output hold from first occurring address, CE#, or OE#
change
R10
tOH
0
0
R11
R12
R13
R16
tEHEL
tELTV
tEHTZ
CE# pulse width high
CE# lowto WAIT valid
CE# high to WAIT high Z
OE# lowto WAIT in low-Z
20
20
1
1
16
20
20
20
ns
ns
ns
1,3
1,3
0
0
t
GLTX
OE# high to WAIT in high-Z
24
24
ns
1,3
R17
t
GHTZ
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
Address setup to ADV# high
CE# lowto ADV# high
10
10
12
12
ns
ns
ns
ns
ADV# lowto output valid
ADV# pulse width low
90
110
1
10
10
9
12
12
10
ADV# pulse width high
Address hold from ADV# high
Page address access
ns
ns
ns
1,4
1
t
25
50
25
40
APA
Clock Specifications
R200
R201
R202
R203
fCLK
tCLK
CLK frequency
CLK period
MHz
ns
20
9
25
9
1,3
tCH/CL
CLK high/lowtime
ns
tFCLK/RCLK CLK fall/rise time
3
3
ns
Synchronous Specifications
R301
R302
R303
tAVCH/L
tVLCH/L
tELCH/L
Address setup to CLK
ADV# lowsetup to CLK
CE# low setup to CLK
9
9
9
9
ns
ns
ns
ns
ns
ns
ns
1
9
9
R304 tCHQV / tCLQV CLK to output valid
17
20
20
22
R305
tCHQX
tCHAX
tCHTV
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
3
1,5
1,4,5
1,5
R306
10
10
R307
NOTES:
1. See Figure 25, “AC Input/Output Reference Waveform” on page 61 for timing measurements and maximum
allowable input slew rate.
2. OE# may be delayed by up to t
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is t
– t
after CE#’s falling edge without impact to t
.
ELQV
GLQV
ELQV
or t
, whichever timing specification is satisfied first.
VHAX
CHAX
5. Applies only to subsequent synchronous reads.
Datasheet
51
28F640L30, 28F128L30, 28F256L30
l
Figure 12. Asynchronous Single-WordRead(ADV# Low)
R1
R2
Address [A]
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
WAIT [T]
R13
R7
R6
R10
Data [D/Q]
RST# [P]
R5
NOTE: WAIT asserted (CR[10]=1) during asynchronous read mode.
Figure 13. Asynchronous Single-WordRead(ADV# Latch)
R1
R2
Address [A]
A[1:0][A]
R106
R101
R105
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
R16
R17
WAIT [T ]
R7
R6
R10
Data [D/Q]
NOTE: WAIT asserted (CR[10]=1) during asynchronous read mode.
52
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 14. Asynchronous Page-Mode Read Timing
R1
R2
A[Max:2] [A]
R10
R10
R10
R10
A[1:0]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
WAIT [T ]
R3
R8
R4
R9
R16
R17
R7
R6
R108
R108
R108
DATA [D/Q]
NOTE: WAIT asserted (CR[10]=1) during asynchronous read mode.
Figure 15. Synchronous Single-WordArray-ReadTiming
Latency Count
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R16
R307
R17
R4
R304
R305
Data [D/Q]
NOTES:
1. WAIT is driven per OE# asserted during synchronous array read, and can be configured to assert either
during or one data cycle before valid data.
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst. If this had been an access to Status, ID, or
Query space, the active-low WAIT signal would have remained asserted (low) as long as CE# was asserted
(low).
Datasheet
53
28F640L30, 28F128L30, 28F256L30
Figure 16. Continuous Burst Read, showing an Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
R2
R101
Address [A]
R106
R105
ADV# [V]
R303
R102
R3
CE# [E]
OE# [G]
R16
R307
R304
WAIT [T]
R4
R7
R305
R305
R305
R305
Data [D/Q]
NOTES:
1. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
2. WAIT asserted (CR[10]=0) during synchronous array read, and can be configured to assert either during or
one data cycle before valid data.
Figure 17. Synchronous Burst-Mode Four-WordReadTiming
R301
R302
R306
CLK [C]
R2
R101
Address [A]
ADV# [V]
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R16
R307
R304
R17
R4
R304
R305
R7
R10
Data [D/Q]
D0
D1
D2
D3
NOTE: WAIT asserted (CR[10]=0) during synchronous array read, and can be configured to assert either during
or one data cycle before valid data.
54
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 18. Burst SuspendTiming
R304
R305
R305
R305
CLK
R1
R2
Address [A]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
R3
R8
R4
R9
R4
R9
R16
R17
WAIT [T]
WE# [W]
R7
R6
R304
R304
DATA [D/Q]
Q0
Q1
Q1
Q2
NOTE: CLK can be stopped in either high or lowstate.
Datasheet
55
28F640L30, 28F128L30, 28F256L30
12.2
AC Write Specifications
Nbr.
Symbol
Parameter (1, 2)
Min
Max
Units
Notes
W1
W2
tPHWL RST# high recovery to WE# low150
tELWL CE# setup to WE# low0
tWLWH WE# write pulse width low
tDVWH Data setup to WE# high
tAVWH Address setup to WE# high
tWHEH CE# hold from WE# high
tWHDX Data hold from WE# high
tWHAX Address hold from WE# high
tWHWL WE# pulse width high
ns
1,2,3
ns
1,2,3
W3
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,4
1,2
W4
W5
W6
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
W16
tVPWH
tQVVL
V
V
setup to WE# high
PP
PP
1,2,3,7
hold from Status read
tQVBL WP# hold from Status read
tBHWH WP# setup to WE# high
tWHGL WE# high to OE# low 0
tWHQV WE# high to read valid
0
1,2,3,7
200
ns
1,2,9
t
+35
ns 1,2,3,6,10
AVQV
Write to Asynchronous ReadSpecifications
W18 tWHAV WE# high to Address valid
0
ns
1,2,3,6
Write to Synchronous ReadSpecifications
W19 tWHCH/L WE# high to Clock valid
19
19
ns
ns
1,2,3,6,10
W20
tWHVH WE# high to ADV# high
NOTES:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (t
WE# high (whichever occurs first). Hence, t
5. Write pulse width high (t
WE# low(whichever occurs last). Hence, t
or t
) is defined from CE# or WE# low(whichever occurs last) to CE# or
WLWH
ELEH
= t
= t
= t
.
WLWH
ELEH
WLEH
ELWH
or t
) is defined from CE# or WE# high (whichever occurs first) to CE# or
WHWL
EHEL
= t
= t
= t
).
WHWL
EHEL
WHEL
EHWL
6. tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
7. V and WP# should be at a valid level until erase or program success is determined.
PP
8. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See
spec W19 and W20 for synchronous read.
9. When doing a Read Status operation following a program or erase write cycle, W14 is 20ns.
10.Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read
operation to reflect this change.
56
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 19. Write to Write Timing
W5
W8
W5
W8
Address [A]
W2
W6
W2
W6
CE# [E}
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Figure 20. Asynchronous Readto Write Timing
R1
R2
W5
W8
Address [A]
R3
R8
CE# [E}
R4
R9
OE# [G]
W3
W2
W6
WE# [W]
R7
R6
W7
R10
W4
Data [D/Q]
Q
D
R5
RST# [P]
Datasheet
57
28F640L30, 28F128L30, 28F256L30
Figure 21. Write to Asynchronous ReadTiming
W5
W8
R1
Address [A]
W2
W6
R10
CE# [E}
W3
W18
WE# [W]
W14
OE# [G]
R4
R2
W7
R9
W4
R3
R8
Data [D/Q]
D
Q
W1
RST# [P]
Figure 22. Synchronous Readto Write Timing
R301
R302
R306
CLK [C]
R2
W5
R101
W18
Address [A]
R105
R102
R106
R104
W20
ADV# [V]
R303
R3
R11
W6
CE# [E]
OE# [G]
R4
R8
W19
W9
W8
W15
W2
W3
WE#
R16
R307
R304
WAIT [T]
R13
R7
R305
W7
Data [D/Q]
Q
D
D
NOTE: WAIT shown asserted (CR[10]=0) during write operation.
58
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 23. Write to Synchronous ReadTiming
R302
R301
R2
CLK
W5
W8
R306
R106
Address [A]
ADV#
R104
R303
W6
W2
R11
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
W3
W18
R4
R16
R3
R307
R304
R305
R304
W4
W7
Data [D/Q]
RST# [P]
D
Q
Q
W1
NOTE: WAIT shown asserted (CR[10]=0) during write operation.
Datasheet
59
28F640L30, 28F128L30, 28F256L30
12.3
Program andErase Characteristics
VPPL
VPPH
Nbr.
Symbol
Parameter
Units Notes
Min Typ Max Min Typ Max
Conventional WordProgramming
Single word
Single cell
150 TBD
30 TBD
150 TBD
30 TBD
Program
Time
W200
t
µs
µs
1
1
PROG/W
BufferedProgramming
W200
W201
t
t
Single word
One Buffer (32 words)
150 TBD
640 TBD
150 TBD
288 864
Program
Time
PROG/W
PROG/PB
BufferedEnhancedFactory Programming
W451
t
t
Single word
N/A N/A N/A N/A
7
21
1,2
1
BEFP/W
Program
µs
BEFP/
W452
Buffered EFP Setup
N/A N/A N/A
5
N/A N/A
Setup
Erasing andSuspending
W500
W501
W600
t
t
t
t
16-KWord Parameter
64-KWord Main
Program suspend
Erase suspend
0.4
0.8
20
2.5
4
25
25
0.4
0.7
20
2.5
4
25
25
ERS/PB
ERS/MB
SUSP/P
SUSP/E
Erase Time
s
1
Suspend
Latency
µs
W601
20
20
NOTES:
1. Typical values measured at T = +25 °C and nominal voltages. Performance numbers are valid for all speed
A
versions. Excludes system overhead. Sampled, but not 100% tested.
2. Averaged over entire device.
12.4
Reset Specifications
Nbr. Symbol
Parameter
RST# pulse width low
RST# lowto device reset during erase
RST# lowto device reset during program
Min
Max
Unit
Notes
P1
P2
P3
t
t
t
100
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
PLPH
25
25
PLRH
µs
V
Power valid to RST# de-assertion (high)
60
VCCPH
CC
NOTES:
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if t is <t MIN, but this is not guaranteed.
PLPH
PLPH
3. Not applicable if RST# is tied to Vcc.
4. Sampled, but not 100% tested.
5. If RST# is tied to the V supply, device will not be ready until t
after V >= V min.
CC CC
CC
VCCPH
6. If RST# is tied to any supply/signal with V
voltage levels, the RST# input voltage must not exceed V
CCQ
CC
until V >= V (min).
7. Reset completes within t
CC
CC
if RST# is asserted while no erase or program operation is executing.
PLPH
60
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 24. Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
readmode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
12.5
AC Test Conditions
Figure 25. AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
NOTE: AC test inputs are driven at V
for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
CCQ
at V
/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V = V Min.
CCQ
CC CC
Figure 26. Transient Equivalent Testing LoadCircuit
VCCQ
R1
Device
Under Test
Out
CL
R2
NOTES:
1. See the following table for component values.
2. Test configuration component value for worst case speed conditions.
3. C includes jig capacitance
L
.
Table 15. Test configuration component value for worst case speedconditions
Test Configuration
2.0 V Standard Test
CL (pF)
R1 (Ω)
R2 (Ω)
30
22K
22K
Datasheet
61
28F640L30, 28F128L30, 28F256L30
Figure 27. Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
12.6
Capacitance
Table 16. Capacitance
Symbol
Parameter1
Typ
Max
Unit
Condition
= 0.0 V
C
C
C
Input Capacitance
Output Capacitance
CE# Input Capacitance
6
8
10
8
12
12
pF
pF
pF
V
V
V
IN
IN
OUT
= 0.0 V
= 0.0 V
OUT
CE#
IN
NOTES:
1. TA = +25°C, f = 1 MHz.
2. Sampled, not 100% tested.
62
Datasheet
28F640L30, 28F128L30, 28F256L30
Appendix A Write State Machine (WSM)
Figure 28 shows the command state transitions (Next State Table) based on incoming commands. Only one
partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read
Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM
state does not depend on the partition’s output state.
Figure 28. Write State Machine — Next State Table (Sheet 1 of 6)
Chip
CommandIn put to Chip andresultin g
Next State
Buffered BE Confirm,
Write to
Buffered
Program Setup (4,5)
(BP)
Lock,
Unlock,
ID/Query Lock-down,
CR setup (5)
Word
Program
(4,5)
Enhanced
Factory
P/E
Resume,
ULB,
BP / Prg /
Er as e
Suspend
Clear
Status
Register (6)
Read
Array
Eras e
Read
Status
Read
(3)
Current Chip
State (8)
Pgm Setup
(4)
Conf irm (9)
(FFH)
(10H/40H)
(E8H)
(20H)
(80H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
Program
Setup
Er as e
Setup
Lock/CR
Setup
Ready
Ready
BP Setup
BEFP Setup
Ready
Ready
(Unlock
Block)
Lock/CR Setup
Ready (Lock Error [Botch])
Ready (Lock Error [Botch])
Setup
OTP
OTP Busy
Busy
Word Program Busy
Word
Setup
Program Busy
Word ProgramBusy
Busy
Word
Program
Program
Suspend
Word
Pr ogr am
Busy
Word Program Suspend
Word Program Suspend
Suspend
Setup
BP Load 1 {Give word count load [N-1]}; If N=0 (word count =1) go to BP Confirm; Else (N not = 0) go to BP Load 2
BP Load 2 (Give data load)
BP Load 1
BP Load 2
BP Confirm when count=0, ELSE BP load 2 (note: BP will Botch at this point if any block address is different from the first address)
BP
BP
Ready (Error [Botch])
BP Busy
BP Busy
Ready (Error [Botch])
BP Busy
Conf irm
BP
Suspend
BP Busy
BP
Suspend
BP Suspend
BP Suspend
BP Busy
Setup
Ready (Error [Botch])
Er as e Bus y
Erase Busy
Ready (Error [Botch])
Er as e Bus y
Eras e
Suspend
Busy
Er as e
Word
Program BP Setup in
Lock/CR
Setup in
Eras e
Eras e
Suspend
Erase Suspend
Erase Suspend
Suspend
Setup
Setup in
Er as e
Er as e
Suspend
Erase Busy
Suspend
Suspend
Word ProgramBusy in Erase Suspend
Word
Program
Word ProgramBusy in Erase Suspend
Word ProgramBusy in Erase Suspend Busy
Word Program Suspend in Erase Suspend
Busy
Word
Pr ogr am in
Eras e
Suspend
in Erase
Suspend
Word
Pr ogr am
Busy in
Er as e
Suspend
Word Program Suspend in Erase Suspend
Suspend
Suspend
Datasheet
63
28F640L30, 28F128L30, 28F256L30
Figure 28. Write State Machine — Next State Table (Sheet 2 of 6)
Setup
BPLoad 1 in Erase Suspend {Give word count load [N-1]}; If N=0 (word count =1) go to BPConfirm; Else (Nnot = 0) go to BPLoad 2
BP Load 2 in Erase Suspend (Give data load)
BPLoad 1
BPConfirmin Erase Suspend when count=0, ELSEBPload 2 (note: BPwill Botch at this point if any block address is different fromthe first
address)
BPLoad 2
BPBusy in
Erase
Suspend
BP in Erase
Suspend
BP
Conf irm
Erase Suspend (Error [Botch BP])
BPBusy in Erase Suspend
Ready ( Er ror [Botch BP] in Erase Suspend)
BP Busy in Erase Suspend
BP
Suspend in
Er as e
BP Busy
Suspend
BPBusy in
Erase
Suspend
BP
Suspend
BP Suspend in Erase Suspend
BP Suspend in Erase Suspend
Erase
Suspend
(Unlock
Block)
Lock/CR Setup in Erase
Suspend
Erase Suspend (Lock Error [Botch])
Ready (Error [Botch])
Erase Suspend (Lock Error [Botch])
Ready (Error [Botch])
BEFP
Loading
Data
Buffered
Enhanced
Factory
Pr ogr am
Mode
Setup
(X=32)
BEFP
Busy
BEFPProgramand Verify Busy (if Block Address given matches address given on BEFPSetup command). Commands treated as data. (7)
64
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 28. Write State Machine — Next State Table (Sheet 3 of 6)
Tyax Output Next State Table
CommandInput to Chip andresulting Output Mux Next State
Buffered BE Confirm,
Lock,
Unlock,
ID/Query Lock-down,
CR setup (5)
Word
Enhanced
Factory
P/ E
Resume,
ULB
Pr ogr am/
Er as e
Suspend
Clear
Status
Register (6)
Read
Array
Er as e
Setup (4,5)
Read
Status
Read
Program BPSetup
Setup (4,5)
(3)
PgmSetup
Current chip state
(4)
Confirm(9)
(FFH)
(10H/40H)
(E8H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
BEFP Setup,
BEFP Pgm &
Verify Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
Status Read
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Status Read
Status
Read
OTP Busy
Ready,
Erase Suspend,
BP Suspend
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
Output mux
Status Read does not
change.
Read
Array
Output mux does not
change.
Status Read
Status Read
ID Read
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
Datasheet
65
28F640L30, 28F128L30, 28F256L30
Figure 28. Write State Machine — Next State Table (Sheet 4 of 6)
Chip
CommandInput to Chip andresultin g
Next State
Lock
Block
Confirm (9)
Lock-Down
Block
Illegal Cmds
OTP Setup
Write CR
Confirm
Block Confirm
Address or BEFP Data
(WA0)
WSM
Operation
Completes
(5)
(9)
(9)
(2)
(all other
(XXXXH)
(C0H)
(01H)
(2FH)
(03H)
codes)
OTP Setup
Ready
Ready
(Lock Error
[Botch])
Ready
(Lock Down
Blk)
Ready
(Lock Block)
Ready
(Set CR)
Ready (Lock Error
[Botch])
N/A
OTP Busy
Ready
N/A
Word Program Busy
Word Program Busy
Ready
Word Program Suspend
BP Load 1 {Give word count load [N-1]}; If N=0 (word count =1) go to BP Confirm;
Else (N not = 0) go to BP Load 2
N/A
BP Load 2 (Give data load)
Exit
BP Confirm when count=0, ELSE BP load 2 (note: BP will Botch at this point if any
block address is different from the first address)
Ready (Error [Botch])
BP Busy
Ready
N/A
BP Suspend
Ready (Error [Botch])
Erase Busy
Ready
Erase Suspend
N/A
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Eras e
Suspend
Word Program Suspend in Erase Suspend
N/A
66
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 28. Write State Machine — Next State Table (Sheet 5 of 6)
BP Load 1 in Erase Suspend {Give word count load [N-1]}; If N=0 (word count =1)
go to BP Confirm; Else N ? 0 go to BP Load 2
BP Load 2 in Erase Suspend (Give data load)
Exit
BP Confirm in Erase Suspend when count=0, ELSE BP load 2 (note: BP will Botch
at this point if any block address is different from the first address)
N/A
Ready (Error [Botch BP] in Erase Suspend)
BP Busy in Erase Suspend
Eras e
Suspend
BP Suspend in Erase Suspend
Er as e
Suspend
(Lock Error
[Botch])
Er as e
Suspend
(Lock Down
Block)
Eras e
Suspend
(Lock Block)
Eras e
Suspend (Set
CR)
Erase Suspend (Lock
Er ror [Botc h])
N/A
Ready (Error [Botch])
BEFP Program and Verify Busy (if Block Address given
matches address given on BEFP Setup command).
Commands treated as data. (7)
Ready
Ready
BEFP Busy
Datasheet
67
28F640L30, 28F128L30, 28F256L30
Figure 28. Write State Machine — Next State Table (Sheet 6 of 6)
Tyax Output Next State Table
CommandInput to Chip andresulting Output Mux Next State
Lock
Block
Confirm (9)
Lock-Down
Block
Illegal Cmds
OTP Setup
Write CR
Confirm
Block Confirm
Address or BEFP Data
(WA0)
WSM
Operation
Completes
(5)
(9)
(9)
(2)
(all other
(FFFFH)
(C0H)
(01H)
(2FH)
(03H)
codes)
Status Read
Array
Read
Status Read
Status Read
Output mux
does not
change.
Output mux
Array
Status Read
Output mux does not change.
does not
Read
change.
68
Datasheet
28F640L30, 28F128L30, 28F256L30
NOTES:
1. The "Partition Data When Read" field shows what the user will read from the flash chip after issuing the
appropriate command given the Partition Address is not changed from the address given during the
command. "Read-while-write" functionality gives more flexibility in data output from the device. The data read
from the chip depends on the Partition Address applied to the device; Each partition is placed into one of 3
possible output states during commands: Read Array, Read Status or Read ID/CFI, depending on the
command given to the chip; This partition's output state is retained until a newcommand is given to the chip
at that Partition Address; For example, this allows the user to set partition #1's output state to Read Array,
and partition #4's output state to Read Status; Every time the partition address is changed to partition #4
(without issuing a new command), the Status will be read from the chip.
2. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm],
20H [erase], etc.)
3. If a "Read Array" is attempted from a busy partition, the result will be "garbage" data (we should not tell the
user that it will actually be Status Register data). The key point is that the output mux for that partition will be
pointing to the "array", but garbage data will be output. When the user returns to this partition address some
time in the future, the output mux will be in the "Read Array" state from its last visit. "Read ID" and "Read
Query" commands do the exact same thing in the device. The ID and Query data are located at different
locations in the address map.
4. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected
results will occur.
5. The 2nd cycle of the following 2 cycle commands will be ignored by the user interface: Program Setup, Erase
Setup, OTP Setup and Lock/Unlock/Lock-down/CR setup when issued in an "illegal condition". Illegal
conditions are such as "pgm setup while busy", "erase setup while busy", etc.
6. The Clear Status command only clears the error bits in the status register if the device is not in the following
modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).
7. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
8. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output
(Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip
does not depend on where the partition's output mux is presently pointing to.
9. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the
operation and then move to the Ready State.
Datasheet
69
28F640L30, 28F128L30, 28F256L30
Appendix B Flowcharts
Figure 29. WordProgram Flowchart
WORD PROGRAM PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = 0x40
Write
Write
Read
Setup
Addr = Location to program
Write 0x40,
(Setup)
Word Address
Data = Data to program
Addr = Location to program
Data
Write Data,
(Confirm)
Word Address
Status register data: Toggle CE# or
OE# to update Status Register
None
None
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Standby
No
Suspend?
Yes
0
SR[7] =
1
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Error
Standby
Standby
None
None
VPP Range
Error
1
1
1
SR[3] =
0
Check SR[4]:
1 = Data Program Error
Program
Error
Check SR[1]:
1 = Block locked; operation aborted
SR[4] =
0
Standby
None
SR[3] MUST be cleared before the Write State Machine will
allowfurther program attempts.
Device
SR[1] =
0
Protect Error
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register command
clears the Status Register error bits.
Program
Successful
70
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 30. Program Suspend/Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Data = 0x70
Write
Write
Status Addr = Any partition address
Write 0xB0
Any Address
(Program Suspend)
Program Data = 0xB0
Suspend Addr = Same partition address as above
Read Status
Register
Status register data
Toggle CE# or OE# to update Status
register
Read
None
0
Addr = Suspended block address
SR[7] =
1
Check SR[7]:
Idle
Idle
None
None
1 = WSM ready
0 = WSM busy
Program
Completed
0
SR[2] =
1
Check SR[2]:
1 = Program suspended
0 = Program completed
Write 0xFF
Susp Partition
(Read Array)
Read
Array
Data = 0xFF
Addr = Block address to read
Write
Read
Write
Read Array
Data
Write 0xFF
Pgm'd Partition
(Read
Array)
Read array data from block other than
the one being programmed
None
Read Array
Data
Done
Reading
No
Program Data = 0xD0
Resume Addr = Suspended block's address
Yes
If the suspendedpartition was placedin ReadArray mode:
Write 0xD0
Any Address
(Program Resume)
Return partition to Read Status Register
Read
Status Data = 0x70
Addr = Same partition
mode:
Write
Program
Resumed
Write 0x70
Same Partition
(Read Status Register)
Datasheet
71
28F640L30, 28F128L30, 28F256L30
Figure 31. BufferedProgram Flowchart
Bus
Operation
Command
Comments
Data = E8H
Write to
Buffer
Write
Read
Addr = Block Address
Start
SR.7 = Valid
Addr = Block Address
Device
Supports Buffer
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Use Single Word
Programming
Standby
No
Writes?
Yes
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes 1, 2)
Set Timeout or
Loop Counter
Write
(Notes 3, 4)
Data = Write Buffer Data
Addr = Start Address
Get Next
Target Address
Write
(Notes 5, 6)
Data = Write Buffer Data
Addr = Block Address
Issue Write to Buffer
Command E8h and
Block Address
Program
Confirm
Data = D0H
Addr = Block Address
Write
Read
Status register Data
CE# and OE# lowupdates SR
Addr = Block Address
Read Status Register
(at Block Address)
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
Standby
Timeout
or Count
Expired?
0 = N
o
Is WSM Ready?
SR.7 =
1. Word count values on DQ0-DQ7 are loaded into the Count
register. Count ranges for this device are N = 0000h to 0001Fh.
2. The device outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
Yes
1 = Yes
Write Word Count,
Block Address
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A4–A0 of the start
address = 0).
Write Buffer Data,
Start Address
5. The device aborts the Buffered Program command if the
current address is outside the original block address.
6. The Status register indicates an "improper command
sequence" if the Buffered Program command is aborted.
Followthis with a Clear Status Register command.
X = X + 1
Write Buffer Data,
Block Address
X = 0
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to reset
the partition to read array mode.
No
No
Abort Bufferred
Program?
X = N?
Yes
Yes
Write Confirm D0h
and Block Address
Write to another
Block Address
Buffered Program
Aborted
Issue Read
Status Register
Command
Another Buffered
Programming?
Yes
No
Suspend
Program
Loop
Read Status Register
No
0
Suspend
Program
Yes
SR.7 =?
1
Full Status
Check if Desired
Program Complete
72
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 32. BufferedEFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Program & Verify Phase
Exit Phase
Start
Read Status Reg.
Read Status Reg.
VPP applied,
Block unlocked
No (SR[0]=1)
No (SR[7]=0)
BEFP
Exited?
Data Stream
Ready?
Yes (SR[7]=1)
Yes (SR[0]=0)
Write 0x80 @
1ST Word Address
Initialize Count:
X = 0
Full Status Check
Procedure
Write 0xD0 @
1ST Word Address
Write Data @ 1ST
Word Address
Program
Complete
BEFP setup delay
Read Status Reg.
Increment Count:
X = X+1
N
X = 32?
Yes (SR[7]=0)
BEFP Setup
Y
Done?
Read Status Reg.
No (SR[7]=1)
No (SR[0]=1)
Check VPP, Lock
Errors (SR[3,1])
Program
Done?
Exit
Yes (SR[0]=0)
N
Last
Data?
Y
Write 0xFFFF,
Address Not within
Current Block
BEFP Setup
Bus
State
BEFP Program & Verify
BEFP Exit
Bus
State
Bus
State
Operation
Comments
Operation
Comments
Operation
Comments
Unlock
Block
Status
Data = Status Register Data
Status
Data = Status Reg. Data
Write
VPPH applied to VPP
Read
Read
Register Address = 1ST Word Addr.
Register Address = 1ST Word Addr
Write
(Note 1)
BEFP
Setup
Data = 0x80 @ 1ST Word
Address
Check SR[0]:
Data Stream
Check SR[7]:
Check Exit
Standby
Standby
0 = Ready for Data
Ready?
Standby
0 = Exit Not Completed
Status
1 = Not Ready for Data
1 = Exit Completed
BEFP
Confirm
Data = 0x80 @ 1ST
Word Address
Write
Read
Initialize
X = 0
Repeat for subsequent blocks;
Count
Status
Data = Status Reg. Data
After BEFP exit, a full Status Register check can
determine if any program error occurred;
(Note 2) Register Address = 1ST Word Addr
Write
(Note 3)
Load
Buffer
Data = Data to Program
Address = 1ST Word Addr.
BEFP
Setup
Done?
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
See full Status Register check procedure in the
Word Program flowchart.
Standby
Increment
Count
Standby
Standby
Read
X = X+1
Write 0xFF to enter Read Array state.
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Error
If SR[7] is set, check:
Buffer
Full?
Standby Condition SR[3] set = VPP Error
Check SR[1] set = Locked Block
Status
Data = Status Reg. data
Register Address = 1ST Word Addr.
Check SR[0]:
Program
Standby
0 = Program Done
Done?
1 = Program in Progress
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Write
Exit
Program & Data = 0xFFFF @ address
Verify
not in current block
Phase
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary.
2. Status Register is updated when OE# is toggled.
3. Write-buffer contents are programmed sequentially to the flash array starting at the first word address; WSM internally increments addressing.
Datasheet
73
28F640L30, 28F128L30, 28F256L30
Figure 33. Block Erase Flowchart
Start
BLOCK ERASE PROCEDURE
Bus
Command
Operation
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write
Read
Write 0x20,
(Block Erase)
Block Address
Erase
Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write 0xD0,
(Erase Confirm)
Block Address
Status Register data. Toggle CE# or
None
OE# to update Status register data
Suspend
Erase
Loop
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
None
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase or
after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Range Error
Idle
Idle
Idle
None
None
None
VPP Range
Error
1
1
1
1
SR[3] =
0
Check SR[4,5]:
Both 1 = Command Sequence Error
Command
Sequence Error
Check SR[5]:
1 = Block Erase Error
SR[4,5] =
0
Check SR[1]:
Idle
None
1 = Attempted erase of locked block;
erase aborted.
Block Erase
Error
SR[5] =
0
SR[1,3] must be cleared before the Write State Machine will
allowfurther erase attempts.
Block Locked
Error
SR[1] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
74
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 34. Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Data = 0x70
Write
Write
Status Addr = Any partition address
Write 0x70,
Same Partition
(Read Status)
Erase Data = 0xB0
Suspend Addr = Same partition address as above
Status Register data. Toggle CE# or
Write 0xB0,
Any Address
(Erase Suspend)
Read
Idle
None
None
None
OE# to update Status register;
Addr = Same partition
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
Idle
0 = Erase completed
Erase
Completed
0
SR[6] =
1
Read Array Data = 0xFF or 0x40
or Program Addr = Block to program or read
Write
Read or
Write
Read array or program data from/to
None
Read
Program
Read or
Program?
block other than the one being erased
Read Array
Data
Program
Loop
Program Data = 0xD0
Resume Addr = Any address
No
Write
Done
If the suspendedpartition was placedin
ReadArray mode or a Program Loop:
Read
Return partition to Status mode:
Write 0xD0,
Any Address
Write
Status Data = 0x70
Register Addr = Same partition
(Erase Resume)
Write 0xFF,
Erased Partition
(Read Array)
Erase Resumed
Write 0x70,
Same Partition
Read Array
Data
(Read Status)
Datasheet
75
28F640L30, 28F128L30, 28F256L30
Figure 35. Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x60,
Block Address
Lock
Setup
Data = 0x60
Addr = Block to lock/unlock/lock-down
(Lock Setup)
Write
Lock,
Unlock, or
Lock-Down
Data = 0x01 (Block Lock)
0xD0 (Block Unlock)
Write either
0x01/0xD0/0x2F,
Block Address
(Lock Confirm)
(Read Device ID)
Write
Write
0x2F (Lock-Down Block)
Confirm Addr = Block to lock/unlock/lock-down
Read Data = 0x90
(Optional) Device ID Addr = Block address + offset 2
Write 0x90
Read
(Optional)
Block Lock Block Lock status data
Status Addr = Block address + offset 2
Read Block
Lock Status
Idle
None
Confirm locking change on D[1,0].
Locking
No
Change?
Yes
Read
Array
Data = 0xFF
Addr = Block address
Write
Write 0xFF
Partition Address
(Read Array)
Lock Change
Complete
76
Datasheet
28F640L30, 28F128L30, 28F256L30
Figure 36. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup)
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
Status Register Data. Toggle CE# or
None
OE# to Update Status Register Data
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
None
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[3]:
1 =VPP Range Error
Idle
Idle
Idle
None
1
1
1
SR[3] =
0
VPP Range Error
Check SR[4]:
1 =Programming Error
None
None
Check SR[1]:
1 =Block locked; operation aborted
SR[4] =
0
Program Error
SR[3] must be cleared before the Write State Machine will allow
further program attempts.
Register Locked;
Program Aborted
SR[1] =
0
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
Program
Successful
Datasheet
77
28F640L30, 28F128L30, 28F256L30
Figure 37. ReadWhile BufferedProgramming Flowchart
Bus
Operation
Command
Comments
Data = E8H
Addr = Block Address
Status Register Data
SR.7 = Valid
Start
Buffered
Program
Write
Read
Set Timeout or
Loop Counter
Addr = Block Address
Check SR.7
Get Next
Standby
1 = Device WSM is Busy
0 = Device WSM is Ready
Target Address
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Issue Buffered Program
Command E8h and
Block Address
Write
(Notes 1, 2)
or
Read Array Data from
Block in other Partition
(NewBlock Address)
Write
(Notes 3, 4)
Data = Write Buffer Data
Addr = Start Address
Read Status Register
(at Block Address)
Write
(Notes 5, 6)
Data = Write Buffer Data
Addr = Block Address
Program
Confirm
Data = D0H
Addr = Block Address
Write
Write
Data = FFH
Addr = NewBlock Address
(Note 7, and Read Array
8)
Write Word Count,
Block Address
or
Read Array Data from
Block in other Partition
(NewBlock Address)
Check SR.7
Read Array 1 = WSM Ready
Read
0 = WSM Busy
Write Buffer Data,
Start Address
1. Word count values on DQ-DQ7 are loaded into the Count
Read Array Data from
Block in other Partition
(NewBlock Address)
0
or
register. Count ranges for this device are N = 0000h to 0001Fh
2. The device outputs the status register when read, or the
device outputs array data when read from block in other
partition (toggle OE# to update array data).
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
X = X + 1
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., 4A–A0 of the start
address = 0).
5. The device aborts the Buffered Program command if the
current address is outside the original block address.
6. The Status register indicates an "improper command
sequence" if the Buffered Program command is aborted. Follow
this with a Clear Status Register command.
7. A newwrite cycle command to read must be prec eded with
a Confirm Command.
8. If a read array operation occurs in a partition other than the
one being Programmed, that is not in read array mode, a Read
Array command must be written.
X = 0
Write Buffer Data,
Block Address
No
No
Abort
Buffered
Program?
X = N?
Yes
Read Array Data from
Block in other Partition
(NewBlock Address)
or
Yes
Write Confirm D0h
and Block Address
Write to another
Block Address
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to rese
the partition to read array mode.
Buffered Program
Aborted
Read Array Data from
Block in other Partition
(NewBlock Address)
No
Read
Status?
Yes
No
Read
Array?
Read Status Register
Yes
Write FFH to Read
from a Block in other Partition?
0
SR.7 =?
1
Read Array Data
Full Status
Check if Desired
Program Complete
78
Datasheet
28F640L30, 28F128L30, 28F256L30
Appendix C Common Flash Interface
Common Flash Interface (CFI) is part of an overall specification for multiple command-set and
control-interface descriptions. This appendix describes the database structure containing the data
returned by a read operation after issuing the CFI Query command (see Section 3.2, “Device
Commands” on page 15). System software can parse this database structure to obtain information
about the flash device, such as block size, density, bus width, and electrical specifications. The
system software will then know which command set(s) to use to properly perform flash writes,
block erases, reads and otherwise control the flash device.
C.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value
is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper
bytes. The device outputs ASCII “Q” in the low byte (DQ7-0) and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes ofinformation, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all ofthe following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 17. Summary of Query Structure Output as a Function of Device andMode
Hex
Hex
ASCII
Device
Offset Code Value
00010:
00011:
00012:
51
52
59
"Q"
"R"
"Y"
Device Addresses
Datasheet
79
28F640L30, 28F128L30, 28F256L30
Table 18. Example of Query Structure Output of x16- Devices
Word Addressing:
Byte Addressing:
Offset
AX–A0
Hex Code
Value
Offset
AX–A0
Hex Code
D7–D0
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
Value
D15–D0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
P_IDLO
P_IDHI
PLO
"Q"
"R"
"Y"
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
"Q"
"R"
"Y"
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PrVendor
ID #
ID #
PHI
...
A_IDLO
A_IDHI
...
...
C.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 19. Query Structure
Description(1)
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
Offset
00001-Fh Reserved
Sub-Section Name
00010h
0001Bh
00027h
P(3)
CFI query identification string
System interface information
Device geometry definition
Primary Intel-specific Extended Query Table
Vendor-defined additional information specific
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is
16K-word).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
80
Datasheet
28F640L30, 28F128L30, 28F256L30
C.3
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Table 20. CFI Identification
Hex
Offset
Length
Description
Query-unique ASCII string “QRY“
Add. Code Value
3
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
10h
--51
--52
--59
--03
--00
--0A
--01
--00
--00
--00
--00
"Q"
"R"
"Y"
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
13h
15h
17h
19h
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Table 21. System Interface Information
Hex
Code
--17
Offset
1Bh
Length
1
Description
Add.
1B:
Value
1.7V
V
CC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
1Ch
1Dh
1Eh
1
1
1
1C:
1D:
1E:
--20
--85
--95
2.0V
8.5V
9.5V
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µ-sec
“n” such that typical max. buffer write time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--08 256µs
--09 512µs
--0A
--00
1s
NA
--01 512µs
--01 1024µs
--02
--00
4s
NA
Datasheet
81
28F640L30, 28F128L30, 28F256L30
C.4
Device Geometry Definition
Table 22. Device Geometry Definition
Offset
27h
Length
Description
Code
See table below
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
1
27:
28:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
2
1
0
28h
2
—
—
—
—
x64
x32
x16
9
x8
8
--01
x16
64
15
14
13
12
11
10
—
—
—
—
—
—
—
—
29:
2A:
2B:
2C:
--00
--06
--00
“n” such that maximum number of bytes in write buffer = 2n
2
1
2Ah
2Ch
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
4
4
4
2Dh
31h
35h
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
64 Mbit
128 Mbit
–B
256 Mbit
–B –T
Address
–B
–T
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--17
--01
--00
--06
--00
--03
--03
--00
--80
--00
--0E
--00
--00
--02
--17
--00
--00
--04
--17
--01
--00
--06
--00
--03
--17
--00
--00
--04
--0E
--00
--00
--02
--03
--00
--80
--00
--18
--01
--00
--06
--00
--03
--03
--00
--80
--00
--1E
--00
--00
--02
--30
--00
--00
--04
--18
--01
--00
--06
--00
--03
--30
--00
--00
--04
--1E
--00
--00
--02
--03
--00
--80
--00
--19
--01
--00
--06
--00
--03
--03
--00
--80
--00
--1E
--00
--00
--02
--6F
--00
--00
--04
--19
--01
--00
--06
--00
--03
--6F
--00
--00
--04
--1E
--00
--00
--02
--03
--00
--80
--00
82
Datasheet
28F640L30, 28F128L30, 28F256L30
C.5
Intel-Specific Extended Query Table
Table 23. Primary Vendor-Specific Extended Query
Offset(1)
P= 10Ah
Hex
Length
Description
(Optional flash features and commands)
Primary extended query table
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
10A
--50
"P"
"R"
"I"
"1"
"3"
Unique ASCII string “PRI“
10B: --52
10C: --49
10D: --31
10E: --33
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
--E6
10F:
110: --03
111: --00
112: --00
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
113: --01
No
Yes
Yes
No
No
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
Yes
Yes
Yes
Yes
Yes
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
(P+9)h
1
2
bit 0 = 1
114: --03
115: --00
bit 0 = 1
Yes
(P+A)h
(P+B)h
Yes
Yes
bit 1 = 1
(P+C)h
(P+D)h
1
1
V
V
CC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
116: --18
1.8V
PP optimum program/erase supply voltage
117: --90
9.0V
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Datasheet
83
28F640L30, 28F128L30, 28F256L30
Table 24. Protection Register Information
Offset(1)
Length
Hex
Description
P= 10Ah
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
Add. Code Value
118: --02
(P+E)h
1
4
2
(P+F)h
(P+10)h
(P+11)h
(P+12)h
119: --80
11A: --00
11B: --03 8 byte
11C: --03 8 byte
80h
00h
bits 0–7 = Lock/bytes Jedec-plane physical lowaddress
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n” n = factory pgm'd groups (lowbyte)
bits 40–47 = “n” n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” n = user pgm'd groups (lowbyte)
11D: --89
11E: --00
11F: --00
120: --00
89h
00h
00h
00h
0
0
0
16
0
16
--00
--00
--00
121:
122:
123:
124: --04
--00
125:
126:
bits 64–71 = “n” n = user pgm'd groups (high byte)
bits 72–79 = “n” 2n = user programmable bytes/group
--04
84
Datasheet
28F640L30, 28F128L30, 28F256L30
Table 25. Burst ReadInformation
Offset(1)
Length
Hex
Description
(Optional flash features and commands)
Page Mode Read capability
P= 10Ah
Add. Code Value
127: --00 0 byte
(P+1D)h
1
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+1E)h
(P+1F)h
1
1
Number of synchronous mode read configuration fields that
128: --04
129: --01
4
4
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
(P+20)h
(P+21)h
(P+22)h
1
1
1
12A: --02
12B: --03
12C: --07
8
16
Cont
Table 26. Partition andErase-block Region Information
Offset(1)
P= 10Ah
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features andcommands )
Len
(P+23)h (P+23)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
12D: 12D:
Datasheet
85
28F640L30, 28F128L30, 28F256L30
Partition Region 1 Information
Offset(1)
P= 10Ah
See table below
Address
Description
Bot
Top
12E:
12F:
130:
Bottom
Top
(Optional flash features andcommands )
Number of identical partitions within the partition region
Len
2
(P+24)h (P+24)h
(P+25)h (P+25)h
12E:
12F:
130:
(P+26)h (P+26)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
1
1
bits 4–7 = number of simultaneous Erase operations
(P+27)h (P+27)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+28)h (P+28)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+29)h (P+29)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
131:
132:
133:
131:
132:
133:
1
1
(P+2A)h (P+2A)h Partition Region 1 Erase Block Type 1 Information
(P+2B)h (P+2B)h bits 0–15 = y, y+1 = number of identical-size erase blocks
(P+2C)h (P+2C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+2D)h (P+2D)h
4
134:
135:
136:
137:
138:
139:
13A:
134:
135:
136:
137:
138:
139:
13A:
Partition 1 (Erase Block Type 1)
Minimum block erase cycles x 1000
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
2
1
(P+30)h (P+30)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+31)h (P+31)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
13B:
13B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
13C:
13D:
13E:
13F:
140:
141:
Partition 1 (Erase block Type 2)
2
1
Minimum block erase cycles x 1000
(P+38)h
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
142:
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+39)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
143:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
86
Datasheet
28F640L30, 28F128L30, 28F256L30
Partition Region 2 Information
Offset(1)
P= 10Ah
See table below
Address
Len
Description
(Optional flash features andcommands )
Bot
Top
Bottom
Top
(P+3A)h (P+32)h Number of identical partitions within the partition region
(P+3B)h (P+33)h
(P+3C)h (P+34)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
2
144:
145:
146:
13C:
13D:
13E:
1
1
1
1
(P+3D)h (P+35)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+3E)h (P+36)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+3F)h (P+37)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
147:
148:
149:
13F:
140:
141:
(P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information
4
14A:
14B:
14C:
14D:
14E:
14F:
150:
142:
143:
144:
145:
146:
147:
148:
(P+41)h (P+39)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
(P+42)h (P+3A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+43)h (P+3B)h
(P+44)h (P+3C)h Partition 2 (Erase block Type 1)
(P+45)h (P+3D)h Minimum block erase cycles x 1000
(P+46)h (P+3E)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+47)h (P+3F)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
151:
149:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+40)h Partition Region 2 Erase Block Type 2 Information
14A:
14B:
14C:
14D:
14E:
14F:
150:
(P+41)h
(P+42)h
(P+43)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+44)h Partition 2 (Erase block Type 2)
(P+45)h Minimum block erase cycles x 1000
(P+46)h Partition 2 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+47)h Partition 2 (erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
151:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Datasheet
87
28F640L30, 28F128L30, 28F256L30
Partition and Erase-blockRegion Information
Address
64 Mbit
128 Mbit
–B
256 Mbit
–B
–B
–T
–T
–T
12D:
12E:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A:
13B:
--03
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--01
--03
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
--03
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--01
--03
--03
--06
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
--03
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--01
--03
--03
--0E
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
14B:
14C:
14D:
14E:
14F:
150:
151:
152:
153:
154:
155:
156:
157:
158:
159:
15A:
15B:
15C:
15D:
15E:
15F:
--06
--00
--00
--02
--64
--00
--01
--03
--01
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--01
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--06
--00
--00
--02
--64
--00
--01
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--06
--00
--00
--02
--64
--00
--01
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--02
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--03
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
--00
--02
--64
--00
--01
--03
--03
--00
--80
--00
--64
--00
--01
--03
--06
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
--00
--02
--64
--00
--01
--03
--03
--00
--80
--00
--64
--00
--01
--03
--0E
--00
--11
--00
--00
--01
--07
--00
--00
--04
--64
--00
--01
--03
--00
--02
--64
--00
--01
--03
--03
--00
--80
--00
--64
--00
--01
--03
88
Datasheet
28F640L30, 28F128L30, 28F256L30
Appendix D Mechanical Information
Figure 38. 64- and128-Mbit; 56-Ball VF BGA Package Drawing andDimensions
A1 Index
Mark
D
A1 Index
Mark
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
G
b
Top View - Ball Side Down
A1
Bottom View- Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Symbol
Min
Max Notes
1.000
Min
Max
0.0394
A
A1
A2
b
D
E
e
N
Y
S1
S2
0.150
0.0059
0.665
0.375
7.700
9.000
0.750
56
0.0262
0.0148
0.3031
0.3543
0.0295
56
0.325
7.600
8.900
0.425
7.800
9.100
0.0128
0.2992
0.3504
0.0167
0.3071
0.3583
(64Mb, 128Mb)
(64Mb, 128Mb)
0.100
1.325
2.350
0.0039
0.0522
0.0925
1.125
2.150
1.225
2.250
0.0443
0.0846
0.0482
0.0886
Datasheet
89
28F640L30, 28F128L30, 28F256L30
Figure 39. 256-Mbit; 79-Ball VF BGA Package Drawing andDimensions
S1
A1 Index
Mark
A1 Index
Mark
D
1 2
3
4
5
6
7 8 9
10 11 1213
8
1312 11 10
9
7
6 5 4 3 2 1
S2
A
B
A
B
C
D
C
D
E
E
E
F
F
G
G
e
b
Top View- Ball Side Down
Bottom View- Ball Side Up
A1
A2
A
Seating
Plane
Y
Side View
Drawing not to scale
Dimensions Table
Millimeters
Nom
Inches
Nom
Dimensions
Symbol
Min
Max Notes
Min
Max
Package Height
Ball Height
A
A1
A2
b
D
E
e
N
Y
S1
S2
1.000
0.0394
0.150
0.0059
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
0.665
0.375
11.000
9.000
0.750
79
0.0262
0.0148
0.4331
0.3543
0.0295
79
0.325
10.900
8.900
0.425
11.100
9.100
0.0128
0.4291
0.3504
0.0167
0.4370
0.3583
(256Mb)
(256Mb)
0.100
1.100
2.350
0.0039
0.0433
0.0925
0.900
2.150
1.000
2.250
0.0354
0.0846
0.0394
0.0886
90
Datasheet
28F640L30, 28F128L30, 28F256L30
Appendix E Additional Information
Order/Document
Number
Document/Tool
251902
290701
290702
290737
1.8 Volt Intel StrataFlash® Wireless Memory Datasheet
1.8 Volt Intel® Wireless Flash Memory Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3-Volt I/O Datasheet
3 Volt Synchronous Intel StrataFlash® Memory Datasheet
Migration Guide for 1.8 Volt Intel® Wireless Flash Memory (W18/W30) to 1.8 Volt Intel
StrataFlash® Wireless Memory (L18/L30), Application Note 753
251908
251909
Migration Guide for 3 Volt Synchronous Intel StrataFlash® Memory (K3/K18) to 1.8 Volt
Intel StrataFlash® Wireless Memory (L18/L30), Application Note 754
298161
297833
298136
Intel® Flash Memory Chip Scale Package User’s Guide
Intel® Flash Data Integrator (FDI) User’s Guide
Intel® Persistent Storage Manager User Guide
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.
3. For the most current information on Intel StrataFlash memory, visit our website at http://
developer.intel.com/design/flash/isf.
4. This document is not available through Intel Literature. Please visit our website at http://
developer.intel.com/design/flcomp/packdata/298049.htm.
Datasheet
91
28F640L30, 28F128L30, 28F256L30
Appendix F Ordering Information
G E 2 8 F 6 4 0
L 3 0 T 9 0
Package Designator
Extended Temperature
(-25 C to +85 C)
Access Speed(ns)
(90, 110)
GE = 0.75mm VF BGA
Product line designator
T = Top Parameter Blocking
B = Bottom Parameter Blocking
for all Intel® Flash products
Product Family
L30 = 1.8 Volt Intel StrataFlash
wireless memory with 3-Volt I/O
Device Density
®
640 = x16 (64-Mbit)
128 = x16 (128-Mbit)
256 = x16 (256-Mbit)
VCC = 1.7 V - 2.0 V
VCCQ = 2.2 V - 3.3 V
92
Datasheet
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