GT28F320W18T70 [NUMONYX]
Flash, 2MX16, 70ns, PBGA56, VFBGA-56;型号: | GT28F320W18T70 |
厂家: | NUMONYX B.V |
描述: | Flash, 2MX16, 70ns, PBGA56, VFBGA-56 |
文件: | 总80页 (文件大小:944K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1.8 Volt Intel® Wireless Flash Memory
(W18)
28F320W18, 28F640W18, 28F128W18
Preliminary Datasheet
Product Features
■ High Performance
■ Software
— 5 µs (Typ) Program Suspend
— 70 ns Initial Access Speed
— 14 ns Clock to Data Output Zero Wait-State
— 5 µs (Typ) Erase Suspend
— Intel® Flash Data Integrator (IFDI) Software
Optimized
Synchronous Burst Mode
— 20 ns Page Mode Read Speed
— 4-, 8-, and Continuous Word Burst Modes
— Burst and Page Modes in Both Parameter and
Main Partitions
— Intel Basic Command Set Compatible
— Common Flash Interface (CFI)
■ Quality and Reliability
— Programmable WAIT Configuration
— Enhanced Factory Programming Mode:
3.50 µs/Word (Typ)
— Glueless 12 V interface for Fast Factory
Programming @ 8 µs/Word (Typ)
— 1.8 V Low-Power Programming @ 12 µs/Word
(Typ)
— Extended Temperature –40 °C to +85 °C
— Minimum 100K Block Erase Cycles
— ETOX™ VII Flash Technology (0.18 µm)
■ Security
— 128-Bit Protection Register: 64 Unique Device
Identifier Bits; 64 User-Programmable OTP
Bits
— Program or Erase during Reads
■ Architecture
— Absolute Write Protection
V
= GND
PP
— Erase/Program Lockout during Power
— Multiple 4-Mbit Partitions
Transitions
— Dual-Operation: RWW or RWE (Read-While -
— Individual Dynamic Zero-Latency Block
Locking
■ Density and Packaging
Write or Read-While-Erase)
— Eight, 4-Kword Parameter Code/Data Blocks
— 32-Kword Main Code/Data Blocks
— Top and Bottom Parameter Configurations
■ Power Operation
— 32-Mbit in a VF BGA Package
— 64-Mbit and 128-Mbit in µBGA*Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
— 1.65 V to 1.95 V Read and Write Operations
µBGA* and VF BGA Packages
— 1.65 V to 1.95 V V
for I/O Isolation
CCQ
— 16-Bit Wide Data Bus
— Standby Current: 5 µA (Typ)
— 40/52/66 MHz 4-word Sync Read
Current: 7 mA (Typ)
The 1.8 Volt Intel® Wireless Flash memory with flexible multi-partition dual-operation provides high-
performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs.
Combining high read performance with flash memory’s intrinsic non-volatility, 1.8 Volt Intel® Wireless Flash
memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from
slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases
reliability and reduces overall system power consumption and cost.
The 1.8 Volt Intel® Wireless Flash memory’s flexible multi-partition architecture allows programming or erasing
to occur in one partition while reading from another partition. This allows for higher data write throughput
compared to single partition architectures. The dual-operation architecture also allows two processors to
interleave code operations while program and erase operations take place in the background. The designer can
also choose the size of the code and data partitions via the flexible multi-partition architecture.
The 1.8 Volt Intel® Wireless Flash memory is manufactured on Intel® 0.18 µm ETOX™ VII process technology.
It is available in µBGA and VF BGA packages, which are ideal for board-constrained applications.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290701-001
October 2000
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 1.8 Volt Intel® Wireless Flash memory may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000.
*Other brands and names are the property of their respective owners.
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Contents
1.0
Introduction..................................................................................................................1
1.1
1.2
Document Conventions.........................................................................................1
Product Overview..................................................................................................1
2.0
Product Description..................................................................................................2
2.1
2.2
2.3
Package and Pinouts ............................................................................................2
Ball Descriptions....................................................................................................3
Memory Partitioning ..............................................................................................5
2.3.1 Main Blocks..............................................................................................7
2.3.2 Parameter Blocks.....................................................................................8
3.0
4.0
Principles of Operation............................................................................................8
3.1
Bus Operations......................................................................................................8
3.1.1 Read.........................................................................................................8
3.1.2 Standby ....................................................................................................9
3.1.3 Write.........................................................................................................9
3.1.4 Reset........................................................................................................9
Command Definitions.............................................................................................10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Read Array Command.........................................................................................13
Read Identifier Command ...................................................................................13
Read Query Command .......................................................................................14
Read Status Register Command.........................................................................14
Clear Status Register Command.........................................................................16
Word Program Command ...................................................................................16
Enhanced Factory Program Command (EFP) ....................................................16
4.7.1 EFP Requirements.................................................................................17
4.7.2 Setup Phase...........................................................................................17
4.7.3 Program Phase ......................................................................................17
4.7.4 Verify Phase...........................................................................................17
4.7.5 Exit Phase ..............................................................................................18
Program Suspend/Resume - Erase Suspend/Resume Command .....................18
Block Erase Command........................................................................................19
Security Modes....................................................................................................19
Block Locking Command.....................................................................................20
4.11.1 Lock Block..............................................................................................21
4.11.2 Unlock Block...........................................................................................21
4.11.3 Lock-Down Block....................................................................................21
Block Lock Status................................................................................................21
Locking Operations during Erase Suspend.........................................................22
Status Register Error Checking...........................................................................22
WP# Lock-Down Control.....................................................................................22
Protection Registers............................................................................................22
Read Protection Register ....................................................................................23
Program Protection Register...............................................................................23
Lock Protection Register .....................................................................................23
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
Preliminary
iii
1.8 Volt Intel® Wireless Flash Memory (W18)
5.0
Set Configuration Register...................................................................................25
5.0.1 Read Mode.............................................................................................25
5.0.2 First Access Latency Count ...................................................................25
5.0.3 WAIT Signal Polarity ..............................................................................28
5.0.4 Data Output Configuration .....................................................................28
5.0.5 WAIT Delay Configuration......................................................................29
5.0.6 Burst Sequence Configuration ...............................................................29
5.0.7 Clock Configuration................................................................................30
5.0.8 Burst Wrap .............................................................................................30
5.0.9 Burst Length...........................................................................................31
Read-While-Write/Erase .....................................................................................31
5.1
6.0
7.0
Program and Erase Voltages ..............................................................................39
6.1
6.2
Factory Program Mode .......................................................................................39
Programming Voltage Protection (VPP)..............................................................39
Power Consumption...............................................................................................40
7.1
7.2
7.3
7.4
Active Power .......................................................................................................40
Automatic Power Savings ...................................................................................40
Standby Power....................................................................................................40
Power-Up/Down Operation .................................................................................40
7.4.1 System Reset and RST#........................................................................40
7.4.2 VCC, VPP, and RST# Transitions..........................................................41
7.4.3 Power Supply Decoupling......................................................................41
8.0
Electrical Specifications........................................................................................42
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Absolute Maximum Ratings ................................................................................42
Extended Temperature Operation.......................................................................43
Capacitance ........................................................................................................43
DC Characteristics ..............................................................................................44
AC I/O Test Conditions .......................................................................................46
AC Read Characteristics.....................................................................................47
AC Write Characteristics.....................................................................................55
Erase and Program Times ..................................................................................57
Reset Specifications............................................................................................57
Appendix A Write State Machine States.............................................................................59
Appendix B Protection Register Addressing...................................................................62
Appendix C Common Flash Interface .................................................................................63
Appendix D Mechanical Specifications..............................................................................73
Appendix E Ordering Information.........................................................................................74
iv
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Revision History
Date of
Version
Revision
Description
09/13/00
290701-001
Original Version
Preliminary
v
1.8 Volt Intel® Wireless Flash Memory (W18)
1.0
Introduction
This datasheet contains information about the 1.8 Volt Intel® Wireless Flash memory family.
Section 1.0 provides a flash memory overview. Sections 2.0 through 7.0 describe the memory
functionality. Section 8.0 describes the electrical specifications for extended temperature product
offerings.
1.1
Document Conventions
The term “1.8 V” refers to the full voltage range 1.65 V – 1.95 V (except where noted) and
“VPP = 12 V” refers to 12 V ±5%.
Throughout this document, references are made to top, bottom, parameter, and main partitions. To
clarify these references, the following conventions have been adopted:
• Top partition is located at the highest physical device address. This partition may be a main
partition or a parameter partition.
• Bottom partition is located at the lowest physical device address. This partition may be a
main partition or a parameter partition.
• Block is a group of bits (or words) that erase simultaneously with one block erase instruction.
• Partition is a group of blocks that share erase and program circuitry and a common status
register. If one block is erasing or one word is programming, only the status register, rather
than array data, is available when any address within the partition is read.
• Main partition contains only main blocks.
• Parameter partition contains a mixture of main and parameter blocks.
• Top parameter device has the parameter partition at the top of the memory map with the
parameter blocks at the top of that partition. This was formerly referred to as top-boot device.
• Bottom parameter device has the parameter partition at the bottom of the memory map with
the parameter blocks at the bottom of that partition. This was formerly referred to as bottom-
boot block flash device.
• Main block(s) 32-Kword block(s)
• Parameter block(s) 4-Kword block(s)
1.2
Product Overview
The 1.8 Volt Intel® Wireless Flash memory provides simultaneous read-while-write/erase
capability with package compatible density upgrades. The family provides high performance at
low voltage on a 16-bit data bus. Individually-erasable memory blocks are optimally-sized for code
and data storage. The eight 4-Kword parameter blocks are located in the parameter partition. The
rest of the flash memory is grouped into 32-Kword main blocks within the main and parameter
partitions. By dividing the flash memory into partitions, program or erase can take place
simultaneously during read operations.
The 1.8 Volt Intel® Wireless Flash memory consists of multiple 4-Mbit partitions. Although each
partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or
erase in one partition while other partitions are in read mode. The 1.8 Volt Intel® Wireless Flash
Preliminary
1
1.8 Volt Intel® Wireless Flash Memory (W18)
memory allows burst reads that cross partition boundaries. User application code is responsible for
ensuring that burst reads don’t cross into a partition that is programming or erasing. Usage of
simultaneous modes will be described further throughout this document.
Upon initial power up or return from reset, the device defaults to asynchronous mode read
configuration. Writing to the configuration register enables synchronous burst read. In synchronous
mode, the CLK input increments an internal burst address generator, synchronizes flash memory
with the host CPU, and outputs data every, or every other, CLK cycle after initial latency. A WAIT
output signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the 1.8 Volt Intel® Wireless Flash memory
incorporates technology that enables fast factory program and erase and low-power designs.
Designed for low-voltage systems, the 1.8 Volt Intel® Wireless Flash memory supports read
operations at 1.8 V VCC and erase and program operations at 1.8 V or
12 V VPP. The Enhanced Factory Programming (EFP) option renders the fastest program
performance, which can increase factory throughput. With the 1.8 V VPP option, VCC and VPP can
be tied together for a simple, ultra low-power design. In addition to the voltage flexibility, the
dedicated VPP pin gives complete data protection when VPP ≤ VPPLK
.
The device’s Command User Interface (CUI) is the system processor’s interface to the 1.8 Volt
Intel® Wireless Flash memory’s internal operation. Writing a valid command sequence to the CUI
initiates device Write State Machine (WSM) controlled automation that automatically executes the
erase and program algorithms and timings. The status register indicates the WSM’s erase or
program completion.
An industry-standard command sequence invokes block erase and program automation. Each erase
operation erases one block. Erase suspend allows system software to pause an erase so it can read
or program data in another block. Program suspend allows system software to pause programming
so it can read from other locations within that partition. Data is programmed in word increments.
The 1.8 Volt Intel® Wireless Flash memory offers two low-power savings features: Automatic
Power Savings (APS) and standby mode. The device automatically enters APS mode following
read cycle completion. Standby mode is initiated when the system deselects the device by driving
CE# inactive. RST# low also resets the device to read array mode, provides write protection, and
clears the status register. Combined, these two features significantly reduce power consumption.
The 1.8 Volt Intel® Wireless Flash memory’s protection register allows unique flash device
identification that can be used to increase system security.
The 1.8 Volt Intel® Wireless Flash memory’s block-lock feature allows zero-latency any-block
locking/unlocking.
2.0
Product Description
2.1
Package and Pinouts
The 1.8 Volt Intel® Wireless Flash memory is available in 56 active ball matrix µBGA* and VF
BGA Chip Scale Packages with 0.75 mm ball pitch that is ideal for board-constrained applications.
Figure 1, “56 Active Ball Matrix µBGA* and VF BGA Packages” on page 3 shows device ballout.
2
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 1. 56 Active Ball Matrix µBGA* and VF BGA Packages
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
A11
A12
A13
A15
VCCQ
VSS
D7
A8
A9
vSS
vCC
CLK
ADV#
A16
vPP
RST#
WE#
D12
A18
A6
A5
A4
A3
A4
A3
A2
A1
A0
A6
A5
A7
A18
vPP
vCC
VSS
A8
A11
A20
A17
A17
RST# CLK
A20
A9
A12
A13
A15
VCCQ
VSS
D7
A10
A14
D15
D14
VSSQ
A21
A19
A7
A2
A19
WE#
D12
D2
ADV#
A21
A10
WAIT
D6
WP#
D1
A22
CE#
D0
A1
WP#
D1
A16
WAIT
D6
A22
CE#
D0
A14
D4
D2
A0
D4
D15
D14
VSSQ
D13
D11
D10
D9
OE#
VSSQ
OE#
VSSQ
D9
D10
D11
D13
G
G
D5
vCC
D3
VCCQ
D8
D8
VCCQ
D3
VCC
D5
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
NOTES:
1. On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A and
21
A
will be NC).
22
2. See Appendix D for package mechanical specifications.
2.2
Ball Descriptions
Table 1, “Ball Descriptions” on page 4 describes ball usage.
Preliminary
3
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 1. Ball Descriptions
Symbol
A –A
Type
Name and Function
ADDRESS INPUTS: for memory addresses.
16 Mbit: A ; 32 Mbit: A ; 64 Mbit: A ; 128 Mbit A
0-22
I
0
22
0-19
0-20
0-21
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during
memory, status register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
DQ –DQ
I/O
0
15
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During
asynchronous read and write operations, ADV#’s rising edge latches addresses A –A
synchronous read operations, all addresses are latched on ADV#’s rising edge or CLK’s rising (or
falling) edge, whichever occurs first.
. During
MAX
2
ADV#
CE#
I
I
I
CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps.
CE#-high deselects the device, places it in standby state, and places data and WAIT outputs at
High-Z.
CLOCK: CLK synchronizes the device to the system bus frequency in synchronous-read
configuration and increments an internal burst address generator. During synchronous read
operations, addresses are latched on ADV#’s rising edge or CLK’s rising (or falling) edge,
whichever occurs first.
CLK
OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle.
OE#
I
I
With OE# at V , device data outputs are placed in High-Z state.
IH
RESET: When low, RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset
places the device in asynchronous read array mode.
RST#
WAIT: Indicates data valid in synchronous read modes. It is High-Z until Configuration Register bit
WAIT
WE#
O
I
10 (CR.10, WT) is written, which determines its polarity when asserted. With CE# at V , WAIT’s
IL
active output is V or V . WAIT is High-Z if CE# is V . WAIT is not gated by OE#.
OL
OH
IH
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on
the WE# pulse’s rising edge.
WRITE PROTECT: Disables/enables the lock-down function.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down
cannot be unlocked through software.
WP#
I
See Section 4.10 for details on block locking.
ERASE AND PROGRAM POWER: A valid V voltage on this pin allows erase or programming.
PP
Memory contents cannot be altered when V ≤ V
. Block erase and program at invalid V
PP
PPLK
PP
voltages should not be attempted.
Set V = V for in-system read, program, and erase operations. To accommodate resistor or
PP
CC
V
Pwr
Pwr
diode drops from the system supply, V ’s V level can be as low as V
above V
min. V must remain
PP
PP
IH
PP1 PP
min to perform in-system flash modifications.
PP1
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. V can be connected to 12 V for a cumulative total not to exceed 80 hours maximum.
Extended use of this pin at 12 V may reduce block cycling capability.
PP2
PP
DEVICE POWER SUPPLY: Writes are inhibited at V ≤ V
voltages should not be attempted.
. Device operations at invalid V
CC
CC
LKO
V
V
CC
OUTPUT POWER SUPPLY: Enables all outputs to be driven at V
directly to V
. This input may be tied
CCQ
Pwr
Pwr
CCQ
.
CC
GND
DU
GROUND: Pins for all internal device circuitry must be connected to system ground.
DON’T USE: Do not use this pin. This pin should not be connected to any power supplies, signals
or other pins and must be floated.
NC
NO CONNECT: No internal connection; can be driven or floated.
4
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
2.3
Memory Partitioning
The device is divided into 4-Mbit physical partitions which allows simultaneous read-while-write
or read-while-erase operations and allows users to segment code and data areas on
4-Mbit boundaries. The device’s asymmetrically-blocked architecture enables system code and
data integration within a single flash device. Each block can be erased independently in block erase
mode. Simultaneous program and erase is not allowed. Only one partition at a time can be in
program or erase mode. See Table 2, “Bottom Parameter Memory Map” on page 6 and Table 3,
“Top Parameter Memory Map” on page 7.
The 16-Mbit device has four 4-Mbit partitions, the 32-Mbit has eight partitions, the 64-Mbit has
16 partitions, and the 128-Mbit device has 32 partitions. Each device density contains one
“parameter” partition and several “main” partitions. The 4-Mbit parameter partition contains eight
4-KW parameter blocks, plus seven 32-KW main blocks. Each 4-Mbit “main” partition contains
eight 32-KW blocks each.
The 1.8 Volt Intel® Wireless Flash memory allows burst reads that cross partition boundaries.
.
Preliminary
5
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 2. Bottom Parameter Memory Map
Size
(KW)
Blk
#
Blk
#
Blk
#
Blk
#
16-Mbit
32-Mbit
64-Mbit
128-Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
262
135
134
71
7F8000-7FFFFF
400000-407FFF
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFF
040000-047FFF
038000-03FFFF
134
71
70
39
38
31
30
23
22
15
14
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFF
040000-047FFF
038000-03FFFF
70
39
38
31
30
23
22
15
14
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFF
040000-047FFF
038000-03FFFF
70
39
38
31
30
23
22
15
14
F8000-FFFFF
C0000-C7FFF
B8000-BFFFF
80000-87FFF
78000-7FFF
38
31
30
23
22
40000-47FFF
38000-3FFFF
15
14
32
4
8
7
08000-0FFFF
07000-07FFF
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
4
0
00000-00FFF
0
000000-000FFF
0
000000-000FFF
0
000000-000FFF
6
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 3. Top Parameter Memory Map
Size
(KW)
Blk
#
Blk
#
Blk
#
Blk
#
16-Mbit
32-Mbit
64-Mbit
128-Mbit
4
38
FF000-FFFFF
70
1FF000-1FFFFF
134
3FF000-3FFFFF
262
7FF000-7FFFFF
4
31
30
F8000-F8FFF
F0000-F7FFF
63
62
1F8000-1F8FFF
1F0000-1F7FFF
127
126
3F8000-3F8FFF
3F0000-3F7FFF
255
254
7F8000-7F8FFF
7F0000-7F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
24
23
16
15
8
C0000-C7FFF
B8000-BFFFF
80000-87FFF
78000-7FFFF
40000-47FFF
38000-3FFFF
0000-07FFF
56
55
48
47
40
39
32
31
0
1C0000-1C7FFF
1B8000-1BFFFF
18000-187FFF
178000-17FFFF
140000-147FFF
138000-13FFFF
100000-107FFF
0F8000-0FFFFF
00000-007FFF
120
119
112
111
104
103
96
3C0000-3C7FFF
3B8000-3BFFFF
380000-387FFF
378000-37FFFF
340000-347FFF
338000-33FFFF
300000-307FFF
2F8000-2FFFFF
200000-207FFF
1F8000-1FFFFF
000000-007FFF
248
247
240
239
232
231
224
223
192
191
128
127
0
7C0000-7C7FFF
7B8000-7BFFFF
780000-787FFF
778000-77FFFF
740000-747FFF
738000-73FFFF
700000-707FFF
6F8000-6FFFFF
600000-607FFF
5F8000-5FFFFF
400000-407FFF
3F8000-3FFFFF
000000-007FFF
7
0
95
64
63
0
2.3.1
Main Blocks
The bulk of the array is divided into equal-sized 32-Kword main blocks that can store code and/or
data.
Preliminary
7
1.8 Volt Intel® Wireless Flash Memory (W18)
2.3.2
Parameter Blocks
The memory architecture includes parameter blocks that allow storage of frequently updated small
parameters that would normally be stored in EEPROM. By using software techniques, the word-
rewrite functionality of EEPROMs can be emulated. The parameter partition contains eight
4-Kword (4,096-words) parameter blocks.
3.0
Principles of Operation
The 1.8 Volt Intel® Wireless Flash memory family includes an on-chip Write State Machine
(WSM) to manage block erase and program algorithms. Its Command User Interface (CUI) allows
minimal processor overhead with RAM-like interface timings.
3.1
Bus Operations
Table 4. Bus Operations
Mode
Note
RST#
CE#
OE#
WE#
ADV#
WAIT
DQ
0–15
Read (Array, Status,
Configuration, Identifier, or
Query)
Valid only in
Synchronous
Mode
1,2
V
V
V
V
V
V
V
D
OUT
IH
IL
IL
IH
IH
IL
Output Disable
Standby
Reset
3
3
V
V
V
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
IH
IL
IH
V
X
X
X
X
IH
IH
3,4
5
V
X
X
X
IL
Write
V
V
V
V
V
D
IN
IH
IL
IH
IL
IL
NOTES:
1. Manufacturer and device codes are accessed in read identifier mode (A –A
= 0).
MAX
1
2. Query accesses use only DQ –DQ . All other accesses use DQ –DQ .
0
7
0
15
3. X must be V or V for control pins and addresses.
IL
IH
4. RST# must be at GND ± 0.2 V to meet the maximum specified power-down current.
5. Refer to the Table 6, “Command Definitions” on page 12 for valid D during a write operation.
IN
3.1.1
Read
The 1.8 Volt Intel® Wireless Flash memory has several read configurations:
• Asynchronous page mode read.
• Synchronous burst mode read.
— outputs four, eight, or continuous words, from main blocks and parameter blocks.
The 1.8 Volt Intel® Wireless Flash memory’s partitions have several available read modes:
• Read array mode: read accesses return flash array data from the addressed locations.
• Read identifier mode: reads return manufacturer and device identifier data, block lock status,
and protection register data. The identification plane occupies the 4-Mbit partition address
locations corresponding to the command’s address; the flash-array at that partition is hidden.
8
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
• Read query mode: reads return device CFI (or query) data. The query plane occupies the
4-Mbit partition address locations corresponding to the command’s address; the flash-array at
that partition is hidden.
• Read status register mode: reads return status register data from the addressed partition. That
partition’s array data is not accessible. A system processor can check the status register to
determine an addressed partition’s state or monitor program and erase progress.
All partitions support synchronous burst mode that internally sequences addresses with respect to
the input CLK to select and supply data to the outputs.
Identifier codes, query data and status register read operations execute as single-synchronous or
asynchronous read cycles. WAIT is inactive during these reads.
Access to these modes listed above is independent of the VPP voltage. An appropriate Command
User Interface (CUI) command places the device in a read mode. At initial power-up or after reset,
the device defaults to asynchronous read array mode.
CE#-low enables device read operations. The device internally decodes upper address inputs to
determine which partition is accessed. ADV#-low opens the internal address latches. OE#-low
activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is
latched when ADV# goes high. In synchronous mode, the address is latched by either the rising
edge of ADV# or the rising CLK edge with ADV# low, whichever occurs first. WE# and RST#
must be at VIH.
3.1.2
3.1.3
Standby
CE#-high deselects the device and places it in standby mode, substantially reducing device power
consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a program or erase algorithm, the device will consume active power until a
program or erase operation completes.
Write
A write occurs when CE# = WE# = VIL and OE# = VIH. Flash control commands are written to the
CUI using standard microprocessor write timings. The address and data are latched on the F-WE#
pulse’s rising edge. Write operations are asynchronous; CLK is ignored.
The CUI does not occupy an addressable memory location within a partition. The system processor
must access it at the correct address range. Programming or erasing may occur in only one partition
at a time. Other partitions must be in one of the read modes or may be in an erase suspend mode.
Table 5, “Command Codes and Descriptions” on page 11 shows the available commands.
Appendix A, “Write State Machine States” provides information on moving between different
operating modes using CUI commands.
3.1.4
Reset
The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
Preliminary
9
1.8 Volt Intel® Wireless Flash Memory (W18)
After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or
PHEL) is required before a write sequence can be initiated. After this wake-up interval, normal
t
operation is restored. The device defaults to read array mode, the status register is set to 80h, and
the configuration register defaults to asynchronous page mode reads.
If RST# is driven low during a erase or program operation, the operation will be aborted and the
memory contents at the aborted block or address are no longer valid. See Figure 26, “Reset
Operations Waveforms” on page 58 for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory array. Automated flash
memories provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. Intel® Flash memories allow
proper CPU initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same RESET# signal that resets the system CPU.
4.0
Command Definitions
The device’s on-chip Write State Machine (WSM) manages erase and program algorithms. The
local CPU controls the device’s in-system read, program, and erase operations. Bus cycles to or
from the flash memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#,
and ADV# control signals dictate data flow into and out of the device. WAIT informs the CPU of
valid data during burst reads. Table 4, “Bus Operations” on page 8 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s Command User
Interface (CUI). Table 5, “Command Codes and Descriptions” on page 11 lists all possible
command codes and descriptions, Table 6, “Command Definitions” on page 12 lists command
definitions. Since commands are partition-specific, it is important to write commands within the
target address range.
Multi-cycle command writes to a flash memory partition must be issued sequentially without
intervening command writes. For example, an Erase Setup command to partition X must be
immediately followed by the Erase Confirm command in order to be executed properly. The
address given during the Erase Confirm command determines the location of the erase. If the Erase
Confirm command is given to partition X, then the command will be executed, and a block in
partition X will be erased. Alternatively, if the Erase Confirm command is given to partition Y, the
command will still be executed, and a block in partition Y will be erased. Any other command
given to ANY partition prior to the Erase Confirm command will result in a command sequence
error, which is posted in the Status Register. After the Erase is successfully started in Partition X or
Y, Read cycles can occur in any other partition Z (e.g., code execution or data reads).
10
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 5. Command Codes and Descriptions
Code Device Mode
Description
FFh Read Array
Places selected partition in read array mode so that data signals output array data.
Read Status Places partition in status register read mode. The partition automatically enters this mode after a
70h
Register
Read ID Code, Puts the addressed partition in read device identifier mode. Device reads from the partition addresses
90h Configuration output manufacturer/device codes, configuration register, block lock status, or protection register data
Program or Erase command is issued to it.
Register
on DQ
.
0–15
Puts the addressed partition in read query mode. Device reads from the partition addresses output
Common Flash Interface information on DQ
98h Read Query
.
0–7
The WSM can set the status register’s block lock (SR.1), V (SR.3), program (SR.4), and erase (SR.5)
status bits to “1” but cannot clear them. Device reset or the Clear Status Register command at any
device address clears those bits to “0.”
PP
Clear Status
50h
Register
This preferred program command’s first cycle prepares the CUI for a program operation. The second
Word Program cycle latches address and data and executes the WSM Program algorithm at this location. Status
40h
Set-Up
register updates occur when CE# or OE# is toggled. A Read Array command is required to read array
data after programming.
10h Alt Set-up
Enhanced
Equivalent to a Program Set-Up command (40h).
This program command activates Enhanced Factory Programming Mode (EFP). The first write cycle
sets up the command. If the second cycle is a Confirm command (D0h), subsequent writes provide
program data. All other commands are ignored once EFP mode begins.
Factory
Program Set-
30h
Up
If the first command was Enhanced Factory Programming Set-Up (30h), the CUI latches the address
and data and prepares the device for EFP mode.
D0h EFP Confirm
Prepares the CUI for Block Erase. The device erases the block addressed by the Erase Confirm
command. If the next command is not Erase Confirm, the CUI:
(a) sets status register bits SR.4 and SR.5 to “1,”
Block Erase
20h
Set-Up
(b) places the partition in the read status register mode, and
(c) waits for another command.
If the first command was Erase Set-Up (20h), the CUI latches address and data and erases the block
indicated by the erase confirm cycle address. During program/erase, the partition responds only to
Read Status Register, Program Suspend, and Erase Suspend commands. CE# or OE# toggle updates
status register data.
D0h Erase Confirm
This command issued at any device address initiates suspension of the currently executing program/
erase operation. The status register, invoked by a Read Status Register command, indicates successful
operation suspension by setting (1) status bits SR.2 (program suspend) or SR.6 (erase suspend) and
Program or
B0h Erase
Suspend
SR.7. The WSM remains in the Suspend mode regardless of control signal states, except RST# = V .
IL
Suspend
D0h
This command issued at any device address resumes suspended program or erase operation.
Resume
Prepares the CUI lock configuration. If the next command is not Block-Lock, Unlock, or Lock-Down, the
CUI sets SR.4 and SR.5 to indicate command sequence error.
60h Lock Set-Up
01h Lock Block
D0h Unlock Block
2Fh Lock-Down
If the previous command was Lock Set-Up (60h), the CUI locks the addressed block.
After a Lock Set-Up (60h) command, the CUI latches the address and unlocks the addressed block. If
previously locked-down, the operation has no effect.
After a Lock Set-Up (60h) command, the CUI latches the address and locks-down the addressed block.
Protection
C0h Program
Set-Up
Prepares the CUI for a protection register program operation. The second cycle latches address and
data and starts the WSM’s protection register program or lock algorithm. Toggling CE# or OE# updates
the flash Status register data. To read array data after programming, issue a Read Array command.
Configuration Prepares the CUI for device configuration. If Set Configuration Register is not the next command, the
60h
Set-Up
CUI sets SR.4 and SR.5 to indicate command sequence error.
Set
If the previous command was Configuration Set-Up (60h), the CUI latches the address and writes A
0–
03h Configuration
Register
A
data into the configuration register. Following a Set Configuration Register command, subsequent
15
read operations access array data.
NOTE: Unassigned commands should not be used. Intel reserves the right to redefine these codes for future
functions.
Preliminary
11
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 6. Command Definitions
First Bus Cycle
Second Bus Cycle
Bus
Mode
Command
Cycles
Oper
Addr(1)
Data(2,3)
Oper
Addr(1)
Data(2,3)
Read Array/Reset
1
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
PnA
PnA
PnA
PnA
XX
FFh
90h
Read Device Identification Codes
Read Query
Read
Read
Read
PnA+IA
PnA+QA
BA
IC
98h
QD
Read Status Register
Clear Status Register
Block Erase
70h
SRD
1
50h
2
BA
20h
Write
Write
Write
BA
WA
WA
D0h
WD
D0h
Word Program
2
WA
WA
XX
40h/10h
30h
Enhanced Factory Programming
Program/Erase Suspend
Program/Erase Resume
Lock Block
>2
1
B0h
D0h
60h
1
XX
2
BA
Write
Write
Write
Write
BA
BA
BA
PA
01h
D0h
2Fh
PD
Unlock Block
2
BA
60h
Lock-Down Block
2
BA
60h
Protection Program
2
PA
C0h
Lock Protection Program
Set Configuration Register
NOTES:
2
Write
LPA
C0h
Write
LPA
FFFDh
2
Write
CD
60h
Write
CD
03h
1. First cycle command addresses should be the same as the operation’s target address. Examples: the first-
cycle address for the Read Device Identification Codes command should be the same as the Identification
Code address (IA); the first cycle address for the Program command should be the same as the word
address (WA) to be programmed; the first cycle address for the Erase/Program Suspend command should
be the same as the address within the block to be suspended; etc.
XX = Any valid address within the device.
IA = Identification code address.
BA = Address within the block.
LPA = Lock Protection Address is obtained from the CFI (via the Read Query command). The 1.8 Volt Intel®
Wireless Flash memory family’s LPA is at 0080h.
PA = User programmable 4-word protection address in the device identification plane.
PnA = Address within the partition.
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Data read from the status register.
WD = Data to be written at location WA.
IC = Identifier code data.
PD = User programmable 4-word protection data.
QD = Query code data on DQ
.
0–7
CD = Configuration register code data presented on device addresses A
. A –A
address bits can
MAX
15–0
16
select any partition. See Table 11, “Configuration Register Definitions” on page 24 for configuration register
bits descriptions.
3. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
12
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
4.1
4.2
Read Array Command
The Read Array command places (or resets) the partition in read array mode. Upon initial device
power-up or after reset (RST# transitions from VIL to VIH), all partitions default to read array mode
and to asynchronous page mode read configuration. A Read Array command written to a partition
that is performing an erase or program operation will present invalid data until the operation
completes; it will then display array data when read. If an Erase- or Program-Suspend command
suspends the WSM, a subsequent Read Array command will place the addressed partition in read
array mode. The Read Array command functions independently of VPP voltage.
Read Identifier Command
The read identifier mode outputs the manufacturer/device identifier, block lock status, protection
register codes, and configuration register. The identifier plane occupies the 4-Mbit partition
address range supplied by the Read Identifier command (90h) address. Reads from addresses in
Table 7 retrieve ID information. Issuing a Read ID command to a partition that is programming/
erasing places that partition’s outputs in Read ID mode, while the partition continues to program or
erase in the background.
Table 7. Device Identification Codes
Item
Address(1)
Data
Manufacturer Code
PBA + 000000h
PBA + 000001h
PBA(3)+ 000001h
PBA + 000001h
PBA + 000001h
PBA + 000001h
PBA + 000001h
PBA + 000001h
PBA + 000001h
0089h
8860h
8861h
8862h
8863h
8864h
8865h
8866h
8867h
Lock
- T
- B
- T
- B
- T
- B
- T
- B
16 Mbit
32 Mbit
64 Mbit
128 Mbit
Device Code:
Block Lock Configuration(2)
• Block Is Unlocked
DQ = 0
0
• Block Is Locked
BBA(4)+ 000002h
DQ = 1
0
• Block Is Not Locked-Down
• Block Is Locked-Down
Configuration Register
Protection Register Lock
Protection Register
DQ = 0
1
DQ = 1
1
PBA + 000005h
PBA + 000080h
CD(5)
PR-LK(6)
PR(7)
PBA + 000081-000088h
NOTES:
1. Intel reserves other configuration address locations.
2. See Section 4.12, “Block Lock Status” on page 21 for valid lock status.
3. PBA = Partition Base Address.
4. BBA = Block Base Address.
5. CD = Configuration Register data.
6. PR-LK = Protection Register lock status.
7. PR = Protection Register data.
Preliminary
13
1.8 Volt Intel® Wireless Flash Memory (W18)
4.3
Read Query Command
The query plane comes to the foreground and occupies a 4-Mbit address range at the partition
supplied by the Read Query command address. The mode outputs Common Flash Interface (CFI)
data when partition addresses are read. Appendix C, “Common Flash Interface” on page 63 shows
query mode information and addresses. Issuing a Read Query command to a partition that is
programming or erasing places that partition’s outputs in read query mode while the partition
continues to program or erase in the background.
4.4
Read Status Register Command
The device’s status register displays program and erase operation status. A partition’s status can be
read after writing the Read Status Register command to the partition’s address range. The status
register can also be read following a Program, Erase, or Lock Block command sequence.
Subsequent single reads from that partition output its status until another valid command is written.
This mode supports single synchronous and single asynchronous reads only; it doesn’t support
page mode or burst reads. The first OE# or CE# falling edge latches and updates status register
content. The operation doesn’t affect other partitions’ modes. DQ0–7 output status register data;
DQ8–15 output 00h. See Table 8, “Status Register Definitions” on page 15.
The status register occupies the 4-Mbit partition to which the Read Status, Program, or Erase
command was issued. Status register bit SR.7 (DWS — Device Write/Erase Status) provides
program/erase status of the device. The Partition Write/Erase Status bit (PWS) tells whether the
addressed partition or some other partition is actively programming or erasing. Status register bits
SR.1-SR.6 present information about the WSM’s program, erase, suspend, VPP, and block-lock
status. Table 9, “Status Register Bits DWS and PWS Description” on page 15 presents descriptions
of DWS (SR.7) and PWS (SR.0) combinations.
14
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 8. Status Register Definitions
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
DPS
1
PWS
0
Status Register Bits
Notes
SR.7 = Device Write/erase Status (DWS)
0 = Device WSM is Busy
SR.7 indicates erase or program completion in the device.
SR.1–6 are invalid while SR.7 = “0.”
1 = Device WSM is Ready
SR.6 = Erase Suspend Status (ESS)
0 = Erase in progress/completed
1 = Erase suspended
After issuing an Erase Suspend command, the WSM halts and
sets (1) SR.7 and SR.6. SR.6 remains set until the device
receives an Erase Resume command.
SR.5 = Erase Status (ES)
0 = Successful erase
1 = Erase error
SR.5 is set (1) if an attempted erase failed.
A Command Sequence Error is indicated when SR.4, SR.5 and
SR.7 are set.
SR.4 = Program Status (PS)
0 = Successful program
1 = Program error
SR.4 is set (1) if the WSM failed to program a word.
A Command Sequence Error is indicated when SR.4, SR.5 and
SR.7 are set.
SR.3 = V Status (VPPS)
The WSM indicates the V level after program or erase
PP
PP
0 = V OK
completes. SR.3 does not provide continuous V feedback and
PP
PP
1 = V low detect, operation aborted
isn’t guaranteed when V ≠ V
.
PP
PP
PP1/2
SR.2 = Program Suspend Status (PSS)
0 = Program in progress/completed
1 = Program suspended
After receiving a Program Suspend command, the WSM halts
execution and sets (1) SR.7 & SR.2, which remains set until a
Resume command is received.
SR.1 = Device Protect Status (DPS)
0 = Unlocked
If an erase or program operation is attempted to a locked block
(if WP# = V ), the WSM sets (1) SR.1 and aborts the operation.
IL
1 = Aborted erase/program attempt on locked block
SR.0 = Partition Write/erase Status (PWS)
Addressed partition or another partition is erasing or
programming.
In EFP mode, SR.0 indicates that a data-stream word has
finished programming or verifying depending on the particular
EFP phase.
0 = Depending on SR.7’s state, the addressed partition is
busy or no other partition is busy
EFP: word program or verify done, EFP ready
1 = Another partition is busy
EFP: word program or verify busy
See Table 9 for valid SR.7 and SR.0 combinations.
Table 9. Status Register Bits DWS and PWS Description
DWS
(SR.7)
PWS
(SR.0)
Description
The addressed partition is performing a program/erase operation. No other partition is active.
Enhanced Factory Programming: device is finished programming or verifying data or is ready for data.
0
0
1
A partition other than the one currently addressed is performing a program/erase operation.
Enhanced Factory Programming: the device is either programming or verifying data.
0
1
1
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR.6 and
SR.2) indicate whether other partitions are suspended.
0
1
Enhanced Factory Programming: the device has exited EFP mode.
Won’t occur in standard program or erase modes.
Enhanced Factory Programming: this combination will not occur.
Preliminary
15
1.8 Volt Intel® Wireless Flash Memory (W18)
4.5
Clear Status Register Command
The Clear Status Register command clears the status register and leaves all partition output states
unchanged. The command functions independently of the applied VPP voltage. The WSM can set
(1) status register bits 0–7 and clear (0) bits 0, 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate
various error conditions, they can only be cleared by the Clear Status Register command. By
allowing system software to reset these bits, several operations (such as cumulatively programming
several addresses or erasing multiple blocks in sequence), may be performed before reading the
status register to determine error occurrence. The status register should be cleared before beginning
another command or sequence. Device reset (RST# = VIL) also clears the status register.
4.6
Word Program Command
Writing a program command to the device initiates internally timed sequences that program the
requested word.
Programming can occur in only one partition at a time. Other partitions must be in one of the read
modes or in an erase suspend mode.
The WSM executes a sequence of internally timed events to program desired bits at the addressed
location and verify that the bits are sufficiently programmed. Programming the memory changes
specifically addressed bits to “0.” “1” bits do not change the memory cell contents.
The status register can be examined for program progress and errors by reading any address within
the partition that’s programming. Issuing a Read Status Register command to other partitions
brings the status register to the foreground in those partitions, allowing program progress to be
monitored or detected at other device addresses. Status register bit SR.7 indicates device program
status while the program sequence executes. CE# or OE# toggle (during polling) updates the status
register. Valid commands that can be issued to the programming partition during programming are
Read Status Register, Program Suspend, Read Identifier, Read Query, and Read Array (which
returns unknown data).
When programming completes, status register bit SR.4 indicates program success if zero (0) or
failure if set (1). If SR.3 is set (1), the WSM couldn’t execute the Program command because VPP
was outside acceptable limits. If SR.1 is set (1), the program operation targeted a locked block and
was aborted.
After examining the status register, it should be cleared by the Clear Status Register command
before issuing a new command. The partition remains in status register mode until another
command is written to that partition. Any command can follow once program completes.
4.7
Enhanced Factory Program Command (EFP)
The 1.8 Volt Intel® Wireless Flash memory contains an Enhanced Factory Programming mode
(EFP). EFP substantially reduces programming time by eliminating much of the device's internal
programming overhead. Once started, host bus cycles write a data word followed by a status
register read that checks to see when the flash device is ready to accept another data write.
Following each internal program pulse, the device automatically increments its internal address to
the next word location. PROM-programming equipment can sequentially program data throughout
a block without adjusting addresses to the device buffers for each address.
16
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
4.7.1
EFP Requirements
To ensure correct operation, EFP mode requires the following conditions:
• Ambient temperature: TA = 25 °C, ±5 °C
• VCC: within device VCC operating range
• VPP: within device 12 V VPP2 range
• For optimum performance, cycling below 10 erase cycles per block is recommended. Cycling
in excess of 10 cycles per block could result in performance degradation, but flash algorithm
will continue to function properly.
• Read-while-write (code execution or data reads during programming) is not supported
• Only one block can be programmed per command
• The block must be unlocked before issuing the EFP Setup and Confirm commands. If the
block is locked, the command fails and the status register presents locked block and program
failure conditions.
• The CUI ignores erase and program suspend and resume commands.
See Figure 10, “Enhanced Factory Program Flowchart” on page 34 for a detailed flowchart on how
to implement an EFP operation.
4.7.2
4.7.3
Setup Phase
To program a block in EFP mode, execute the Enhanced Factory Program command. After
receiving a valid EFP command, the device checks for a valid VPP2 level and block lock status. To
determine the device status, poll the status register. If a proper VPP2 level does not exist and/or the
lock is locked, an error is set in the status register and the EFP operation is terminated.
Program Phase
After a successful EFP Setup, the device is ready for data-streaming where subsequent data writes
to the flash device programs a word within a block. The host processor must poll the status register
for a ‘Program Done’ (SR.0 = 0) before proceeding to the next data word.
The address for all data streaming writes must remain within the target block. The address can
either be held constant or increment within the block’s address range. The device compares the
setup and confirm address with the corresponding address bits of each successive data streaming
write. If the block address matches the stored address during the setup and confirm command block
address, the device programs the new data word. If the block address differs, the device jumps to
the new address location. If the address is outside the target block range, EFP terminates the
program phase and enters the verify phase.
The program phase terminates when the interfacing programmer writes to a block address different
from that of the EFP setup command; data must be FFFFh. Upon program phase termination, the
device then enters the EFP verify phase.
4.7.4
Verify Phase
A high percentage of the flash bits program on the first attempt. However, for those bits that do not
completely program on the first attempt, the EPF verify phase identifies these bits and applies
additional program pulses.
Preliminary
17
1.8 Volt Intel® Wireless Flash Memory (W18)
The verify phase is an identical flow to the program phase except that instead of programming data,
the device compares the incoming data with the data already programmed in the device during the
program phase. If the data comparison is correct, then proceed to the next word. However, if the
comparison is incorrect, the device applies additional program pulses to the appropriate bits.
The host programmer must reset its initial verify-word address to the address used when the EFP
setup and confirm command was issued in the program phase. The host programmer then reissues
each data word in the same order that it did during the program phase. The host programmer may
write each word to the initial verify-word address (WA0) or increment the address within the block
address range.
The verify phase terminates when the interfacing programmer writes a block address different from
that of the EFP setup command; data must be FFFFh. Upon verify phase termination, the device
then enters the EFP exit phase.
4.7.5
Exit Phase
The status register indicates when the device returns to normal operating conditions (SR.7 =1). A
full status register check should be performed to ensure no cumulative error(s) have occurred. After
exiting EFP mode, any valid CUI command can be issued.
4.8
Program Suspend/Resume - Erase Suspend/Resume
Command
The Program/Erase Suspend command halts an in-progress program or erase operation. The
command can be issued at any device address. The partition corresponding to the command’s
address remains in its previous state. The Suspend command allows data to be accessed from
memory locations other than the one being programmed or the block being erased.
A program operation can be suspended to perform reads only. An erase operation can be suspended
to perform either a program or a read operation within any block, except the block that is erase
suspended. A Program command nested within a suspended Erase can subsequently be suspended
to read yet another location. Once the program/erase process starts, the Suspend command requests
that the WSM suspend the program/erase sequence at predetermined points in the algorithm. The
partition that’s actually suspended continues to output status register data after the Suspend
command is written. An operation is suspended when Status bits SR.7 and SR.6 and/or SR.2
display “1.” tWHRH1/tEHRH1 specifies suspend latency.
To read data from blocks within the partition (other than an erase-suspended block), a Read Array
command can be written. During Erase Suspend, a Program command can be issued to a block
other than the erase-suspended block. Block erase cannot resume until program operations initiated
during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read
Query, and Program Resume are valid commands during Program or Erase Suspend. Additionally,
Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and
Lock-Down Block are valid commands during Erase Suspend.
To read data from a block in a partition that is not programming/erasing, the operation does not
need to be suspended. If the other partition is already in read array, ID, or Query mode, issuing a
valid address will return corresponding data. If the other partition is not in a read mode, one of the
read commands must be issued to the partition before data can be read.
During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP
must remain at its program level and WP# must remain unchanged while in suspend mode.
18
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
The Resume Command instructs the WSM to continue programming/erasing and automatically
clears status register bits SR.2 (or SR.6) and SR.7. This command can be written to any partition.
When read at the partition that’s programming/erasing, the device outputs data corresponding to
the partition’s last mode. If status register error bits are set, the status register can be cleared before
issuing the next instruction. RST# must remain at VIH. See Figure 9, “Program Suspend/Resume
Flowchart” on page 33 and Figure 12, “Erase Suspend/Resume Flowchart” on page 36.
A minimum tWHWH time should elapse between an Erase command and a subsequent Erase
Suspend command to ensure that the device achieves sufficient cumulative erase time. Occasional
Erase-to-Suspend interrupts do not cause problems, but Erase-to-Suspend commands issued too
frequently may produce undetermined results.
4.9
Block Erase Command
The two-cycle Block Erase command initiates one block erase at the addressed block within the
selected partition. Block Erase Set-Up (20h) and Confirm (D0h) commands are written to the
targeted erase-block address within the selected partition. Only one partition can be in an erase
mode at a time; other partitions must be in one of the read modes. The Erase Confirm command
internally latches the address of the block to be erased. Block Erase sets to “1” all bits within the
block. The Block Erase command erases only one block at a time. Status bit SR.7 is “0” while the
erase executes.
After writing the command, the device automatically outputs status register data when any address
within the partition is read. The CPU can detect block erase completion by analyzing the partition’s
status register bit SR.7. If the erase operation has failed, status register bit SR.5 will be set to “1.”
SR.3 indicates an invalid VPP supply voltage. SR.1 indicates an erase operation was attempted on a
locked block.
If an error bit was flagged, the status register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition will remain in read status register
mode until another command is written to its CUI. Any CUI instruction can follow once erasing
completes. The CUI can be set to read array mode to prevent inadvertent status register reads.
4.10
Security Modes
The 1.8 Volt Intel® Wireless Flash memory offers both hardware and software security features to
protect the flash data. The software security feature is used by executing the Lock Block command.
The hardware security feature is used by executing the Lock-Down Block command AND by
asserting the WP# signal.
Refer to Figure 2, “Block Locking State Diagram” on page 20 for a state diagram of the flash
security features. Also see Figure 13, “Locking Operations Flowchart” on page 37.
Preliminary
19
1.8 Volt Intel® Wireless Flash Memory (W18)
4.11
Block Locking Command
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection. The first allows
software-only control of block locking (useful for frequently-changed data blocks), while the
second requires hardware interaction before locking can be changed (protects infrequently changed
code blocks).
The following sections discuss the locking system operation. The term “state [XYZ]” specifies
locking states; e.g., “state [001],” where X = WP# value, Y = Block Lock status register bit
DQ1, and Z = Block Lock status register bit DQ0. Figure 2, “Block Locking State Diagram defines
possible locking states.
The following summarizes the locking functionality.
• All blocks power-up in a locked state. Unlock and Lock commands can unlock or lock these
blocks.
• The Lock-Down command locks a block and prevents it from being unlocked when
WP# = VIL.
— WP# = VIH overrides lock-down so commands can unlock/lock blocks.
— When WP# returns to VIL, previously locked-down blocks return to lock-down.
— Lock-Down is cleared only when the device is reset or powered-down.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the
following sections. Figure 2 shows the state table for the locking functions. See also Figure 13,
“Locking Operations Flowchart” on page 37.
Figure 2. Block Locking State Diagram
(X) (Y) (Z)
WP# DQ1 DQ0 Block Status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
unlocked
locked; default
invalid
locked down
unlocked
locked
Power-up
or
Reset
unlocked
locked
(001)
(101)
Notes: 1.) X = WP# = write protect signal.
2.) Y = DQ 1 = Lock-down status.
3.) Z = DQ 0 = Lock status.
Block
Locked
Unlock Cmd
(000)
Initial Lock-Down Cmd
or Assert WP #
(011)
Unlock Cmd
(110)
Unassert WP#
(111)
Lock Cmd
(001)
Block
Locked-
Down
Block
Unlocked
(100)
Initial Lock-Down Cmd
or Assert WP#
(011)
20
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
NOTES:
1. The notation (X,Y,Z) denotes the locking state of a block, The current locking state of a block is defined by the
state of WP# and the two bits of the block-lock status DQ
.
1-0
2. Solid line indicates WP# asserted (low). Dashed line indicates WP# de-asserted (high).
4.11.1
4.11.2
4.11.3
Lock Block
The blocks’ default power-up or reset status is locked (states [001] or [101]). Locked blocks are
fully protected from alteration. Attempted program or erase operations to a locked block will return
an error in status register bit SR.1. A locked block’s status can be changed to unlocked or lock-
down using the appropriate software commands. Writing the Lock Block command sequence can
lock an unlocked block.
Unlock Block
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks
return to the locked state when the device is reset or powered down. An unlocked block’s status can
be changed to the locked or locked-down state using the appropriate software commands. A locked
block can be unlocked by writing the Unlock Block command sequence if the block is not locked-
down.
Lock-Down Block
Locked-down blocks (state [011]) are protected from program and erase operations (just like
locked blocks), but software commands alone cannot change their protection status. A locked-
down block can only be unlocked when the WP# pin is high. When WP# goes low, all locked-
down blocks revert to locked. A locked or unlocked block can be locked-down by writing the
Lock-Down Block command sequence. Locked-down blocks revert to the locked state at device
reset or power-down.
4.12
Block Lock Status
Every block’s lock status can be read in the device’s read identifier mode. To enter this mode, write
90h to the device. Subsequent reads at Block Address + 00002h will output that block’s lock status.
For example, to read the block lock status of block 10, the address sent to the device should be
50002h. The lowest two data bits (DQ0 and DQ1) represent the lock status. DQ0 indicates the block
lock/unlock status and is set by the Lock command and cleared by the Unlock command. It is also
automatically set when entering Lock-Down. DQ1 indicates lock-down status and is set by the
Lock-Down command. It cannot be cleared by software, only by device reset or power-down. See
Table 10.
Table 10. Write Protection Truth Table
V
WP#
RST#
Write Protection
Device inaccessible
PP
X
X
X
V
IL
Word program and block erase
prohibited
V
V
IL
IH
X
V
V
V
All Lock-Down Blocks Locked
IL
IH
X
V
All Lock-Down Blocks Unlockable
IH
IH
Preliminary
21
1.8 Volt Intel® Wireless Flash Memory (W18)
4.13
Locking Operations during Erase Suspend
Block lock configurations can be performed during an erase suspend by using the standard locking
command sequences to unlock, lock, or lock-down a block. This is useful when another block
needs to be updated while an erase operation is suspended.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the status register until it indicates that the erase operation has suspended. Next write the
desired lock command sequence to a block; the lock status will be changed. After completing lock,
read, or program operations, resume the erase operation with the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits will change immediately. But, when resumed, the erase operation will complete.
Locking operations cannot occur during program suspend. Appendix A, “Write State Machine
States” shows valid commands during erase suspend.
4.14
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into status register results.
Since two-cycle command sequences perform locking changes, e.g., 60h followed by 01h to lock a
block, following the Configuration Setup command (60h) with an invalid command produces a
lock command status register error (SR.4 and SR.5 will be set to 1). If a Lock Block command
error occurs during erase suspend, SR.4 and SR.5 are set to 1 and remain at 1 after the erase is
resumed. When erase is complete, possible errors during the erase cannot be detected via the status
register because of the previous locking command error. A similar situation occurs if a program
operation error is nested within an erase suspend.
4.15
WP# Lock-Down Control
WP# allows the block lock-down to be overridden. Table 10, “Write Protection Truth Table” on
page 21 defines the write protection methods.
The WP# pin controls the lock-down function. WP# = VIL(0) protects lock-down blocks [011]
from program, erase, and lock status changes. When WP# = VIH(1), the lock-down function is
disabled [111] and a software command can individually unlock locked-down blocks [110] so they
can be erased and programmed. When the lock-down function is disabled, locked-down blocks
remain locked, and must first be unlocked by writing the Unlock command prior to modifying data
in these blocks. These blocks can then be re-locked [111] and unlocked [110] while WP# remains
high. When WP# goes low, previously locked-down blocks return to the lock-down state [011]
regardless of changes made while WP# was high. Device reset or power-down resets all blocks to
the locked state [101] or [001], including lock-down blocks.
4.16
Protection Registers
The device includes two 64-bit protection registers that can be used to increase system security.
The protection register value can match the flash component to the system’s CPU or ASIC to
prevent device substitution.
22
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
One of the 64-bit protection registers is programmed at Intel’s factory with an unchangeable unique
64-bit number. The other 64-bit register is blank so customers can program it as desired. Once
programmed, the customer segment can be locked to prevent further reprogramming.
4.17
4.18
Read Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time
from addresses shown in Table 7, “Device Identification Codes” on page 13. The ID plane,
containing the protection registers, appears over partition addresses corresponding to the partition
address supplied with the command. Writing the Read Array command returns the device to read
array mode.
Program Protection Register
The Protection Program command should be issued only at the bottom partition followed by the
data to be programed at the specified location. It programs the 64-bit user protection register 16 bits
at a time. Table 7, “Device Identification Codes” on page 13 and Appendix B, “Protection Register
Addressing” on page 62 show allowable addresses. See also Figure 14, “Protection Register
Programming Flowchart” on page 38. Issuing a Protection Program command outside the
registers’ address space results in a status register error (SR.4 = 1).
4.19
Lock Protection Register
The protection register’s user-programmable segment is lockable by programming “0” to the
PR-LOCK register bits “1” using the Protection Program command (Figure 3, “Protection Register
Locking). PR-LOCK register bit “0” is programmed to 0 at the Intel factory to protect the unique
device number. PR-LOCK register bit 1 can be programmed by the user to lock the 64-bit user
register. This bit is set using the Protection Program command to program “FFFDh” into PR-
LOCK register 0.
After PR-LOCK register bits have been programmed, no further changes can be made to the
protection register’s stored values. Protection Program commands written to a locked section result
in a status register error (program error bit SR.4 and lock error bit SR.1 are set to 1). Once locked,
protection register states are not reversible.
Figure 3. Protection Register Locking
0088h
4 Words (64 bits)
User Programmed
0085h
0084h
4 Words (64 bits)
Intel Factory Programmed
0081h
0080h
1 Word (16bits)
Lock Register 0
Preliminary
23
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 11. Configuration Register Definitions
Sync/
Page
Wait
Data
Wait Burst Clock
Burst
Wrap
Res’d
Res’d First Access Latency
Res’d
Burst Length
Hi/Lo Hold Delay Order Edge
RM
15
R
LC2
13
LC1
12
LC0
11
WT
10
DOC
9
WC
8
BS
7
CC
6
R
5
R
4
BW
3
BL2
BL1
1
BL0
14
2
0
Configuration Register Bits
Notes:
CR.15 = READ MODE (RM)
Synchronous and page read mode configurations affect reads
from main blocks and parameter blocks. Status register and
configuration reads support single read cycles. CR.15 = 1
disables configuration set by CR.0-14.
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set reserved bits to “0.”
CR.13–11 = FIRST ACCESS LATENCY COUNT (LC2-0)
000 = Code 0 Reserved for Future Use
001 = Code 1 Reserved for Future Use
010 = Code 2
See Section 5.0.2 for information about the first access
latency count and its effect on the initial read.
Undocumented combinations of bits CR.13–11 are reserved
by Intel Corporation for future implementations.
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6 Reserved for Future Use
111 = Code 7 Reserved for Future Use (Default)
CR.10 = WAIT SIGNAL POLARITY (WT)
0 = WAIT signal is active low (data not ready when pin is low)
1 = WAIT signal is active high (data not ready when pin is
high) (Default)
See WAIT Pin Polarity, Section 5.0.3, for more information.
CR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
See the Data Output Configuration, Section 5.0.4, for more
information.
1 = Hold Data for Two Clock (Default)
CR.8 = WAIT CONFIGURATION (WC)
See the WAIT Delay Configuration, Section 5.0.5, for more
information.
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
CR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
See the Burst Sequence Configuration, Section 5.0.6, for
more information.
1 = Linear Burst Order (Default)
CR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
See the Clock Configuration, Section 5.0.7, for more
information.
CR. 5 = RESERVED FOR FUTURE ENHANCEMENTS (R)
CR.4 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set reserved bits to “0.”
These bits are reserved for future use. Set reserved bits to “0.”
CR.3 = BURST WRAP (BW)
See Section 5.0.8 for information about the burst wrap
configuration.
0 = Wrap bursts within burst length set by CR.2–0
1 = Don’t wrap accesses within burst length set by
CR.2–0.(Default)
CR.2–0 = BURST LENGTH (BL2–0)
001 = 4 Word Burst
Set the synchronous burst length. In asynchronous page
mode, the burst length always equals four words. Intel
Corporation reserves undocumented bit combinations for
future implementation.
010 = 8 Word Burst
011 = Reserved for Future Enhancements
111 = Continuous (Linear) Burst (Default)
24
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
5.0
Set Configuration Register
The Set Configuration Register command sets the burst order, frequency configuration, burst
length, and other parameters.
A two-bus cycle command sequence initiates this operation. The configuration register data is
placed on the low 16 bits of the address bus (A15:0) during both bus cycles. The Set Configuration
Register command is written along with the read configuration data (on the address bus). This is
followed by a second write that confirms the operation and again presents the configuration
register data on the address bus. The configuration register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the
applied VPP voltage. After executing this command, the device returns to read array mode. The
configuration register’s contents can be examined by writing the Read Device Identification Codes
command and then reading location 05h.
5.0.1
5.0.2
Read Mode
All partitions support two high-performance read configurations: synchronous burst mode and
asynchronous page mode (default). Configuration register bit CR.15 sets the read configuration to
one of these modes.
Status register, query, and identifier modes support only asynchronous and single-synchronous read
operations.
First Access Latency Count
The First Access Latency Count configuration tells the device how many clocks must elapse from
ADV#-high (VIH) before the first data word should be driven onto its data pins. The input clock
frequency determines this value. See Table 11, “Configuration Register Definitions” on page 24 for
latency values. Figure 6, “First Access Latency Configuration” on page 27 shows data output
latency from ADV#-active for different latencies.
Use these equations to calculate First Access Latency Count:
{1/ Frequency} = CLK Period
(1)
n (CLK Period) ≥ tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) (2)
n-2 = First Access Latency Count (LC) *
(3)
n: # of Clock periods (rounded up to the next integer)
*Must use LC = n - 1 when the starting address is not aligned to a four-word boundary and CR.3 =
1 (No Wrap).
)
Preliminary
25
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 12. First Latency Count (LC)
Aligned To 4-word
Boundary
Wait Asserted on 16 Word
Boundary Crossing
LC Setting
Mode
Wrap
n-1
n-2
n-2
n-2
n-1
4 or 8
4 or 8
disabled
disabled
enabled
enabled
X
no
yes
no
yes, occurs on the every occurrence
no
4 or 8
no
no
4 or 8
yes
X
continuous
yes, occurs once
Figure 4. Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0 1 2 3 4 5 6 7 8 9 A B C D E F
16 Word Boundary
4 Word Boundary
NOTE:
1. The 16 word boundary is the end of the device sense word-line.
Parameters defined by CPU:
t
ADD-DELAY = Clock to CE#, ADV#, or Address Valid whichever occurs last.
tDATA = Data set up to Clock.
Parameters defined by flash:
AVQV = Address to Output Delay.
t
Example:
CPU Clock Speed = 52 MHz
tADD-DELAY = 6 ns (typical speed from CPU) (max)
tDATA = 4 ns (typical speed from CPU) (min)
tAVQV = 60 ns (from AC Characteristic - Read Only Operations Table)
From Eq. (1):
From Eq. (2)
1/52 (MHz) = 19.2 ns
n(19.2 ns) ≥ 60 ns + 6 ns + 4 ns
n(19.2 ns) ≥ 70 ns
n ≥ 70/19.2 = 3.65 = 4 (Integer)
n - 2 = 4 - 2 = 2
From Eq. (3)
First Access Latency Count Setting to the CR is Code 2.
(Figure 5, “Data Output with LC Setting at Code 2” on page 27 displays example data)
The formula tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) is also known as initial access time.
26
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 5 shows the data output available and valid after four latencies from ADV# going low in the
first clock period with the LC setting at 2.
Figure 5. Data Output with LC Setting at Code 2
tADD
tDATA
3rd
1st
2nd
4th
5th
CLK (C)
CE#
ADV#
AMAX-0
Valid Address
High Z
Code 2
Valid
Output
Valid
Output
DQ15-0 (D/Q)
R103
Figure 6. First Access Latency Configuration
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Code 3
Code 4
Code 5
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 6 (Reserved)
Code 7 (Reserved)
Valid
Output
Valid
Output
Valid
Output
FREQCONF.WMF
Preliminary
27
1.8 Volt Intel® Wireless Flash Memory (W18)
5.0.3
WAIT Signal Polarity
Configuration register bit CR.10 (WT) determines the WAIT signal’s polarity. WAIT is High-Z
until WT is written or while the device is in standby. When the device is active and data is valid,
WT determines if WAIT goes to VOH or VOL. Invalid data drives WAIT to the opposite polarity.
When the device is active in synchronous mode, WAIT asynchronously reflects invalid data and
synchronously reflects valid data. Systems may tie several components’ WAIT signals together.
5.0.4
Data Output Configuration
The Data Output Configuration determines the number of clock cycles per data word output. The
data hold time is configurable as either one or two clocks. Whether or not to configure the device to
hold data for one or two clocks is dependent on the flash memory’s clock to data output delay, as
well as the processor’s minimum data set-up time. A method for determining what this
configuration should be set at is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
As an example, a clock frequency of 52 MHz will be used. The clock period is 19.2 ns. This data is
applied to the formula above for the subsequent reads assuming the data output hold time is one
clock:
12 ns + 4 ns ≤ 19.2 ns
This equation is satisfied and data output will be available and valid at every clock period.
If tDATA is long, hold for two cycles.
Now assume the clock frequency is 66 MHz. This corresponds to a 15 ns period. The initial access
time is calculated to be 75 ns (LC 3). This condition satisfies tAVQV (ns) + tADD-DELAY (ns) +
tDATA (ns) = 60 ns + 6 ns + 4 ns < 75 ns as shown above in the First Access Latency Count
equations. However, the data output hold time of one clock violates the one-clock data hold
condition:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period
12 ns + 4 ns = 16 ns is not less than one clock period of 15 ns. To satisfy the formula above, the
data output hold time must be set at 2 clocks to correctly allow for data output setup time. This
formula is also satisfied if the CPU has tDATA (ns) ≤ 2 ns, which yields:
12 ns + 2 ns ≤ 14 ns
In page mode reads the initial access time can be determined by the formula:
tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)
and subsequent reads in page mode are defined by:
tAPA (ns) + tDATA (ns) (minimum time)
28
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 7. Output Configuration
CLK [C]
1 CLK
Data Hold
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
2 CLK
Data Hold
Valid
Output
Valid
Output
OUT_CONF.WMF
5.0.5
WAIT Delay Configuration
In linear burst mode, WAIT is set to assert one data cycle before or during an output delay. If the
Data Output Configuration is set at one-clock data hold, this corresponds to a one-clock data cycle;
if the Data Output Configuration is set at two-clock data hold, this corresponds to a two-clock data
cycle. This configuration bit’s setting depends on the system and CPU characteristics. WAIT
indicates data valid for all synchronous read modes. With CE# at VIH, WAIT is disabled and placed
in a high impedance state. In synchronous mode, WAIT is asserted by CE#-active. Section 5.0.9.1,
“Linear Burst Accesses” on page 31 describes WAIT signal functionality and Section 8.6, “AC
Read Characteristics” on page 47 specifies WAIT timing.
5.0.6
Burst Sequence Configuration
The burst sequence specifies the synchronous burst mode data order (Table 13, “Sequence and
Burst Length” on page 30). Set this bit for linear or Intel burst order. Continuous burst mode
supports only linear burst order.
Preliminary
29
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 13. Sequence and Burst Length
Burst Addressing Sequence (Dec)
Start Addr.
(Dec)
Wrap
CR.3= 0
No Wrap
CR.3= 1
4-Word Burst Length
8-Word Burst Length
CR. 2–0 = 010
Continuous Burst
CR.2–0 = 111
CR. 2–0 = 001
Linear
Intel
Linear
Intel
Linear
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3-
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
14
15
0
0
14-15-16-17-18-19-20-...
15-16-17-18-19-20-21-...
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
NA
NA
NA
NA
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
NA
NA
NA
NA
NA
NA
NA
NA
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
14
15
1
1
14-15-16-17-18-19-20-...
15-16-17-18-19-20-21-...
5.0.7
Clock Configuration
Clock-edge facilitates easy memory interface to a wide range of burst CPUs. Clock configuration
sets the device to start a burst cycle, output data, and assert WAIT on the clock’s rising or falling
edge.
5.0.8
Burst Wrap
The burst wrap bit determines whether 4-, or 8-word burst-accesses wrap within the burst-length
boundary or whether they cross word-length boundaries to perform linear accesses. No-wrap mode
(CR.3 = 1) enables WAIT to hold off the system processor, as it does in the continuous burst mode,
until valid data is available. In the no-wrap mode (CR.3 = 0), the device operates similar to
continuous linear burst mode but consumes less power during 4-, or 8- word bursts.
For example, if CR.3 = 0 (wrap mode) and CR.2–0 = 001 (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
30
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
If CR.3 = 1 (no-wrap mode) and CR.2–0 = 001 (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR.3 = 1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting CR.2-–0 bits for continuous linear burst mode [111] also achieves the above 4-word burst
sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for
example, will consume power during the initial access, again during the internal pipeline lookup as
the processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the device pipelines the next 4-word sequence. CR.3 = 1 while in 4-word burst mode
(no wrap mode) reduces this excess power consumption.
5.0.9
Burst Length
The burst length is the number of words the device outputs in a synchronous read access. 4-, 8-, and
continuous burst lengths are supported. In 4-, or 8-word burst configuration, the burst wrap bit
(CR.3) determines if burst accesses wrap within word-length boundaries or whether they cross
word-length boundaries to perform a linear access. Once an address is given, the device will output
data until it reaches the end of its burstable address space. Continuous burst access are linear only
and do not wrap within word length boundaries. (see Table 13, “Sequence and Burst Length” on
page 30). Configuration register bits CR.2–0 set the burst length.
5.0.9.1
Linear Burst Accesses
When operating in a linear burst mode, either 4-, or 8-word burst length with the burst wrap bit
(CR.3) set, or in continuous burst mode, the device may incur an output delay when the burst
sequence crosses the first 16-word boundary. (See Figure 4 on page 26 for word boundary
description.) This is dependent on the starting address. If the starting address is aligned to a four-
word boundary, the delay will not occur. If the starting address is the end of a four-word boundary,
the output delay will be one clock cycle less than the First Access Latency Count; this is the worst
case delay. The delay will take place only once and will not happen if the burst sequence does not
cross a 16-word boundary. The WAIT pin informs the system of this delay. See Figure 22 on
page 52 through Figure 24 on page 54 for timing diagrams of WAIT functionality.
5.1
Read-While-Write/Erase
The 1.8 Volt Intel® Wireless Flash memory supports flash multi-partition architecture. By dividing
the flash memory into many separate partitions, the device is capable of reading from one partition
while programing or erasing in another partition; hence the terms, Read-While-Write (RWW) and
Read-While-Erase (RWE). Both of these features greatly enhance flash storage capabilities.
To perform a RWW operation, execute the Word Program command to one partition. While this
operation is being performed by the flash WSM, execute the Read Array command to another
partition.
To perform a RWE operation, execute the Block Erase command to one partition. While this
operation is being performed by the flash WSM, execute the Read Array command to another
partition.
The 1.8 Volt Intel® Wireless Flash memory does not support simultaneous program and erase
operations. Attempting to perform operations such as these will result in a command sequence
error. Only one partition may be programming or erasing while another partition is reading.
Preliminary
31
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 8. Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = 40h
Program Word
Write 40h,
Word Address
Write
Write
Read
Setup
Data
Addr = Location to program (WA)
Data = Data to program (WD)
Addr = Location to program (WA)
Data/
Confirm
Write Data
Word Address
Status register data. Toggle CE# or
OE# to update Status register
Suspend
Program
Loop
Read Status
Register
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
No
Yes
Suspend
Program
0
SR.7 =
1
Repeat for subsequent programming operations.
Full Status register check can be done after each program or
after a sequence of program operations.
Full Status
Check
Write FFh after the last operation to enter read array mode.
(if desired)
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR.3
1 = VPP error
Standby
Standby
VPP Range
Error
1
1
1
SR.3 =
0
Check SR.4
1 = Data program error
Check SR.1
Program
Error
SR.4 =
0
Standby
1 = Attempted program to locked block
Program aborted
SR.3 MUST be cleared before the Write State Machine will
allow further program attempts
Device
Protect Error
SR.1 =
0
Only the Clear Staus Register command clears SR.1, 3, 4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
PGM_WRD.WMF
Successful
32
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 9. Program Suspend/Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = B0h
Suspend Addr = Block to suspend (BA)
Program Suspend
Write B0h
Any Address
Write
Write
Read
Data = 70h
Read Status
Write 70h
Status
Addr = Same partition
Same Partition
Status register data
Toggle CE# or OE# to update Status
register
Addr = Suspended block (BA)
Read
Read Status
Register
Check SR.7
Standby
Standby
1 = WSM ready
0 = WSM busy
0
SR.7 =
1
Check SR.2
1 = Program suspended
0 = Program completed
Program
Completed
0
SR.2 =
1
Read
Array
Data = FFh
Addr = Block address to read (BA)
Write
Read
Write
Read Array
Write FFh
Susp Partition
Read array data from block other than
the one being programmed
Read Array
Data
Program Data = D0h
Resume Addr = Suspended block (BA)
If the suspended partition was placed in Read Array mode:
Done
No
Reading
Return partition to Status mode:
Read
Write
Data = 70h
Yes
Status
Addr = Same partition
Program Resume
Read Array
Write FFh
Write D0h
Any Address
Pgm’d Partition
Program
Resumed
Read Array
Data
Read Status
Write 70h
PGM_SUS.WMF
Same Partition
Preliminary
33
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 10. Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE
EFP Setup
EFP Program
EFP Verify
EFP Exit
Read
Status Register
Read
Status Register
Read
Status Register
Start
VPP = 12V
Unlock Block
SR.0=1=N
SR.0=1=N
SR.7=0=N
Data Stream
Ready?
Verify Stream
Ready?
EFP
Exited?
SR.0 = 0 = Y
SR.0 = 0 = Y
SR.7 = 1 = Y
Write 30h
Address = WA0
Write Data
Address = WA0
Write Data
Address = WA0
Full Status Check
Procedure
Write D0h
Address = WA0
Read
Status Register
Read
Status Register
Operation
Complete
EFP setup time
Program
Done?
Verify
Done?
Read
Status Register
SR.0 = 0 = Y
SR.0 = 0 = Y
N
N
Last
Data?
Last
Data?
EFP Setup
Done?
Y
Y
SR.7 = 1 = N
Check VPP & Lock
errors (SR.3, SR.1)
Write FFFFh
Write FFFFh
Address ≠ BBA
Address
≠
BBA
Exit
EFP Setup
EFP Program
EFP Verify
Bus
State
Bus
State
Bus
State
Comments
Comments
Comments
Read
Status Register
Check SR.0
Read
Status Register
Verify Check SR.0
Unlock VPP = 12V
Block Unlock block
Write
Write
Write
Data
Standby Stream 0 = Ready for data
Ready? 1 = Not ready for data
Standby Stream 0 = Ready for verify
Ready? 1 = Not ready for verify
EFP Data = 30h
Setup Address = WA0
EFP Data = D0h
Write
(note 1)
Data = Data to program
Address = WA0
Write
(note 2)
Data = Word to verify
Address = WA0
Confirm Address = WA0
Read
Status Register
Read
Status Register
Standby
Read
EFP setup time
Check SR.0
0 = Program done
1 = Program not done
Check SR.0
0 = Verify done
1 = Verify not done
Program
Done?
Standby Verify
(note 3) Done?
Status Register
Standby
EFP
Check SR.7
Standby Setup 0 = EFP ready
Done? 1 = EFP not ready
Last
Device automatically
Last
Device automatically
Standby
Standby
Data? increments address.
Data? increments address.
If SR.7 = 1:
Error
Exit Data = FFFFh
Write Program Address not within same
Phase BBA
Exit Data = FFFFh
Verify Address not within same
Phase BBA
Check SR.3, SR.1
Standby Condition
SR.3 = 1 = VPP error
Check
Write
SR.1 = 1 = locked block
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur, the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal to WA
terminates the EFP verify phase, and instructs the device to exit EFP .
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR.4=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
Read
Status Register
Check SR.7
EFP
Standby
0 = Exit not finished
Exited?
1 = Exit completed
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
See the Full Status Check procedure in the
Word Program flowchart.
34
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 11. Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Block Erase
Write 20h
Block Address
Write
Write
Read
Erase
Data = D0h
Erase Confirm
Write D0h and
Block Address
Confirm Addr = Block to be erased (BA)
Status register data. Toggle CE# or
OE# to update Status register data
Suspend
Erase
Loop
Read Status
Register
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
No
Suspend
Erase
0
Yes
SR.7 =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase or
after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write FFh after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR.3
1 = VPP error
Standby
Standby
Standby
VPP Range
Error
1
1
1
1
SR.3 =
0
Check SR.4,5
Both 1 = Command sequence error
Command
Sequence Error
Check SR.5
1 = Block erase error
SR.4,5 =
0
Check SR.1
Standby
1 = Attempted erase of locked block
Erase aborted
Block Erase
Error
SR.5 =
0
SR. 1 and 3 MUST be cleared before the Write State Machine
will allow further erase attempts.
Erase of
Locked Block
Aborted
SR.1 =
0
Only the Clear Staus Register command clears SR.1, 3, 4, 5.
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
ERAS_BLK.WMF
Block Erase
Successful
Preliminary
35
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 12. Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Erase
Data = B0h
Erase Suspend
Write B0h
Any Address
Write
Write
Suspend Addr = Any address
Read
Status
Data = 70h
Addr = Same partition
Read Status
Write 70h
Same Partition
Status register data. Toggle CE# or
OE# to update Status register
Addr = Same partition
Read
Read Status
Register
Check SR.7
Standby
1 = WSM ready
0 = WSM busy
0
0
SR.7 =
1
Check SR.6
1 = Erase suspended
0 = Erase completed
Standby
Write
Erase
Completed
SR.6 =
1
Read Array Data = FFh or 40h
or Program Addr = Block to program or read
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
Read Array
Data
Program
Loop
Program Data = D0h
Resume Addr = Any address
No
Write
If the suspended partition was placed in
Read Array mode or a Program Loop:
Done?
Yes
Return partition to Status mode:
Read
Erase Resume
Read Array
Write
Data = 70h
Status
Write D0h
Any Address
Write FFh
Erased Partition
Addr = Same partition
Read Array
Data
Erase Resumed
Read Status
Write 70h
ERAS_SUS.WMF
Same Partition
36
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 13. Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Bus
Operation
Start
Command
Comments
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Lock Setup
Write 60h
Block Address
Write
Write
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
Lock Confirm
Write 01,D0,2Fh
Block Address
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Read ID Plane
Write 90h
Write
(Optional)
Read ID Data = 90h
Plane
Addr = Block address offset +2 (BA+2)
Read
(Optional)
Block Lock Block Lock status data
Read Block Lock
Status
Status
Addr = Block address offset +2 (BA+2)
Confirm locking change on DQ 1, DQ0.
(See Block Locking State Transitions Table
for valid combinations.)
Standby
(Optional)
Locking
Change?
No
Yes
Read
Array
Data = FFh
Addr = Block address (BA)
Write
Read Array
Write FFh
Partition Address
Lock Change
Complete
LOCK_OP.WMF
Preliminary
37
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 14. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Protection
Program
Setup
Data = C0H
Addr = First Location to Program
Program Setup
Write C0h
Addr=Prot addr
Write
Write
Read
Protection Data = Data to Program
Program Addr = Location to Program
Confirm Data
Write Protect.
Register
Status Register Data Toggle CE# or
OE# to Update Status Register Data
Address / Data
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Protection Program operations addresses must be within the
protection register address space. Addresses outside this
space will return an error.
No
SR.7 = 1?
Yes
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status register check can be done after each program or
after a sequence of program operations.
Write FFh after the last operation to enter read array mode.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
SR.1 SR.3 SR.4
Standby
Standby
Standby
0
0
1
0
1
1
VPP Error
1,1
0,1
1,1
SR.3, SR.4 =
SR.1, SR.4 =
SR.1, SR.4 =
VPP Range Error
Prot. Reg.
Prog. Error
1
0
1
Register Locked:
Aborted
Programming Error
SR.3 MUST be cleared before the Write State Machine will
allow further program attempts.
Locked-Register
Program Aborted
Only the Clear Staus Register command clears SR.1, 3, 4.
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
Program
PROTFLOW.WMF
Successful
38
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
6.0
Program and Erase Voltages
The 1.8 Volt Intel® Wireless Flash memory provides in-system program and erase at VPP1. For
factory programming, it also includes a low-cost, backward-compatible 12 V programming feature.
It also includes an Enhanced Factory Programming (EFP) feature.
6.1
Factory Program Mode
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through the
V
CC pin. Note that if VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to
perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device
draws program and erase current directly from the VPP pin. This eliminates the need for an external
switching transistor to control the VPP voltage. Figure 15, “Example VPP Power Supply
Configuration shows examples of flash power supply usage in various configurations.
The 12 V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during program and erase operations as specified in Section 8.2, “Extended
Temperature Operation” on page 43. VPP may be connected to 12 V for a total of tPPH hours
maximum. Stressing the device beyond these limits may cause permanent damage.
6.2
Programming Voltage Protection (V )
PP
In addition to the flexible block locking, holding the VPP programming voltage low can provide
absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or
erase operations will result in an error displayed in the status register bit SR.3 (set to 1).
Figure 15. Example VPP Power Supply Configuration
System supply
VCC
System supply
VCC
VPP
12 V supply
VPP
Prot# (logic signal)
≤
10K Ω
•
•
12 V fast programming
Absolute write protection with VPP
•
•
Low-voltage programming
Absolute write protection via logic signal
≤
VPPLK
System supply
VCC
(Note 1)
System supply
VCC
VPP
VPP
12 V supply
•
Low voltage and 12 V fast programming
•
Low-voltage programming
NOTE:
1. If the V supply can sink adequate current, an appropriately valued resistor can be used.
CC
Preliminary
39
1.8 Volt Intel® Wireless Flash Memory (W18)
7.0
Power Consumption
Intel flash devices have a layered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If CE# is de-asserted, the memory enters its
standby mode, where current consumption is even lower. The combination of these features can
minimize memory power consumption, and therefore, overall system-power consumption.
7.1
7.2
Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to the Section 8.4, “DC
Characteristics” on page 44, for ICC values.
Automatic Power Savings
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to ICCS. The flash stays in this static state with outputs valid,
OE# low, until a new location is read.
7.3
Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables
most device circuitry and substantially reduces power consumption. Outputs are placed in a high-
impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or
program operations, the device will continue to perform the operation and consume corresponding
active power until the operation is complete.
7.4
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
It does not matter whether VPP or VCC powers-up first. Power supply sequencing is not required.
7.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RST# to
the system CPU RESET# signal to allow proper CPU/flash initialization at system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RST# is brought to VIH, regardless of its control input states. By
40
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
holding the device in reset (RST# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
7.4.2
7.4.3
V
, V , and RST# Transitions
CC PP
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions
or WSM actions. Read array mode is its power-up default state after exit from reset mode or after
V
CC transitions above VLKO (Lockout voltage).
After completing program or block erase operations (even after VPP transitions below VPPLK), the
Read Array command must reset the CUI to read array mode if flash memory array access is
desired.
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise. To minimize the effect
of this transient noise, device de-coupling capacitors are required. Transient current magnitudes
depend on the device outputs’ capacitive and inductive loading. Two-line control and proper de-
coupling capacitor selection will suppress these transient voltage peaks. Each flash device should
have a 0.1 µF ceramic capacitor connected between each VCC, VCCQ, VPP, and GND. High-
frequency, inherently low-inductance capacitors should be as close as possible to package leads.
Preliminary
41
1.8 Volt Intel® Wireless Flash Memory (W18)
8.0
Electrical Specifications
8.1
Absolute Maximum Ratings
Parameter
Note
Maximum Rating
–40 °C to +85 °C
Temperature under Bias
Storage Temperature
–65 °C to +125 °C
–0.5 V to +2.45 V
–0.2 V to +14 V
–0.2 V to +2.45 V
100 mA
Voltage On Any Pin (except V , V
)
1
1,2,3
1
CC
PP
V
V
Voltage
PP
CC
and V
Voltage
CCQ
Output Short Circuit Current
4
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and
–0.2 V on V and V pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns which,
CC
PP
during transitions, may overshoot to V +2.0 V for periods <20 ns.
CC
2. Maximum DC voltage on V may overshoot to +14.0 V for periods <20 ns.
PP
3. V program voltage is normally V
. V can be 12V ±0.6V for 1000 cycles on the main blocks and 2500
PP
PP1
PP
cycles on the parameter blocks during program/erase.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Notice: This datasheet contains preliminary information on new products in production. Specifications are
subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet
before finalizing a design.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
42
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
8.2
Extended Temperature Operation
Symbol
Parameter(1)
Note
Min
Nom
Max
Unit
T
Operating Temperature
Supply Voltage
–40
1.7
25
85
°C
V
A
V
V
3
3
2
2
2
1.80
1.80
1.80
12.0
1.95
1.95
1.95
12.6
80
CC
CCQ
PP1
PP2
PPH
CC
V
V
V
I/O Supply Voltage
Voltage Supply (Logic Level)
1.7
V
V
0.90
11.4
PP
V
Factory Programming V
PP
t
Maximum V Hours
V
= 12 V
Hours
PP
PP
Main and Parameter
blocks
V ≤ V
2
100,000
PP
CC
Block
Erase
Cycles
Cycles
Main Blocks
V
= 12 V
= 12 V
2
2
1000
2500
PP
PP
Parameter Blocks
V
NOTES:
1. See DC Characteristics tables for voltage-range specific specifications.
2. V program voltage is normally V . V can be connected to 11.4 V–12.6 V for 1000 cycles on main
PP
PP1
PP
blocks for extended temperatures and 2500 cycles at extended temperature on parameter blocks.
3. Contact your Intel field representative for enhanced V /V operations down to 1.65 V or greater than
CC CCQ
1.95 V.
8.3
Capacitance
TA = +25°C, f = 1 MHz
Sym
Parameter(1)
Typ
Max
Unit
Condition
V = 0.0 V
IN
C
C
C
Input Capacitance
6
8
8
pF
pF
pF
IN
Output Capacitance
CE# Input Capacitance
12
12
V
= 0.0 V
OUT
CE
OUT
10
V
= 0.0 V
IN
NOTE: 1. Sampled, not 100% tested.
Preliminary
43
1.8 Volt Intel® Wireless Flash Memory (W18)
8.4
DC Characteristics
Sym
Parameter (1)
Note
Typ
Max
Unit
Test Condition
= V Max
V
V
V
CC
CC
I
Input Load Current
±1
µA
= V
Max
LI
CCQ
CCQ
= V
or GND
IN
CCQ
Output
Leakage
Current
V
V
V
= V Max
CC CC
I
DQ –DQ
±1
15
µA
µA
= V Max
LO
0
15
CCQ CC
= V
or GND
CCQ
IN
V
V
= V Max
CC
CC
= V
Max
CCQ
CCQ
I
V
Standby Current
5
CCS
CC
CE# = V
CC
RST# =V or GND
CC
6
8
10
14
mA
mA
Burst length = 4
Burst length = 8
Synchronous
CLK = 40 MHz
2, 3
2, 3
Burst length =
V
= V Max
11
20
mA
CC
CC
Average
Read
Continuous
CE# = V
IL
I
V
CCR
CC
OE# = V
,
IH
7
13
18
mA
mA
Burst length = 4
Burst length = 8
Current
Inputs = V or V
IH
IL
Synchronous
CLK = 52 MHz
10
Burst length =
Continuous
13
25
mA
V
V
V
V
= V
= V
= V
= V
Program in Progress
Program in Progress
18
8
40
15
40
15
15
15
mA
mA
mA
mA
µA
PP
PP
PP
PP
PP1,
PP2,
PP1,
PP2,
I
I
V
V
Program Current
4, 5
4, 6
CCW
CC
Block Erase in Progress
Block Erase in Progress
18
8
Block Erase Current
CCE
CC
CE# = V
CE# = V
Program Suspend in Progress
Erase Suspend in Progress
I
I
I
V
V
Program Suspend Current
Erase Suspend Current
4, 7
4, 7
5
CC,
CC,
CCWS
CCES
PPS
CC
5
µA
CC
V
V
V
Standby Current
PP
PP
PP
Program Suspend Current
Erase Suspend Current
4
0.2
5
µA
V
V
<V
CC
(I
I
PP
PPWS,
)
PPES
≤ V
I
I
V
Read Current
2
0.05
8
15
0.10
22
µA
PP
CC
PPR
PP
PP
V
V
V
V
= V
= V
= V
= V
Program in Progress
Program in Progress
Erase in Progress
Erase in Progress
PP
PP
PP
PP
PP1,
PP2,
PP1,
PP2,
V
Program Current
4
4
mA
PPW
0.05
8
0.10
22
I
V
Erase Current
mA
PPE
PP
44
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
DC Characteristics, continued
Sym
IL
Parameter
Note
Min
Typ
Max
Unit
Test Condition
V
V
V
Input Low Voltage
8
0
0.4
V
V
CCQ
Input High Voltage
Output Low Voltage
8
V
V
V
IH
CCQ
– 0.4
V
V
= V Min
CC
OL
CC
0.1
= V
Min
CCQ
CCQ
I
= 100 µA
OL
V
Output High Voltage
V
V
= V Min
CC CC
OH
V
– 0.1
CCQ
V
= V
Min
CCQ
CCQ
I
= –100 µA
OH
V
V
V
V
Lock-Out Voltage
Lock Voltage
9
0.4
V
V
PPLK
PP
1.0
LKO
CC
NOTES:
1. All currents are RMS unless noted. Typical values at typical V , T = +25 °C.
CC
A
2. Automatic Power Savings (APS) reduces I
to approximately standby levels in static operation.
CCR
3. The burst wrap bit (CR.3) determines whether 4-, or 8-word burst accesses wrap within the burst-length
boundary or whether they cross word-length boundaries to perform linear accesses. In the no-wrap mode
(CR.3 = 1), the device operates similar to continuous linear burst mode but consumes less power.
4. Sampled, not 100% tested.
5. V read + program current is the summation of V read and V program currents.
CC
CC
CC
6. V read + erase current is the summation of V read and V block erase currents.
CC
CC
CC
7. I
I
is specified with device deselected. If device is read while in erase suspend, current draw is sum of
CCES
CCES
and I
.
CCR
8. V can undershoot to –0.4 V and V can overshoot to V +0.4 V for durations of 20 ns or less.
IL
IH
CCQ
9. Erase and program operations are inhibited when V ≤ V
and not guaranteed outside valid V
and
PP
PPLK
PP1
V
ranges.
PP2
Preliminary
45
1.8 Volt Intel® Wireless Flash Memory (W18)
8.5
AC I/O Test Conditions
Figure 16. AC Input/Output Reference Waveform
VCCQ
Input
VCCQ/2
Test Points
VCCQ/2
Output
0V
NOTE: AC test inputs are driven at V
for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and
CCQ
output timing ends, at V
/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed
CCQ
conditions are when V = V Min.
CC
CC
Figure 17. Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
0672_22
NOTE: See table for component values.
Test configuration component value for worst case speed conditions
Test Configuration
Min Standard Test
C
(pF)
R (Ω)
R (Ω)
2
L
1
V
30
16.7K
16.7K
CCQ
NOTE:C includes jig capacitance.
L
Figure 18. Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
CLKINPUT.WMF
46
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
8.6
AC Read Characteristics
Speed
–70
–85
#
Sym
Parameter (1,2)
Unit
Note
Min
Max
Min
Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
3
3
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
Address to Output Delay
70
70
85
85
CE# Low to Output Delay
OE# Low to Output Delay
RST# High to Output Delay
CE# Low to Output in Low-Z
OE# Low to Output in Low-Z
CE# High to Output in High-Z
OE# High to Output in High-Z
CE#, (OE#) High to Output in Low-Z
5
30
30
150
150
6
0
0
0
0
5, 6
6
20
20
25
25
5,6
5,6
0
0
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
t
t
t
t
t
t
t
Address Setup to ADV# High
CE# Low to ADV# High
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
AVVH
ELVH
VLQV
VLVH
VHVL
VHAX
APA
ADV# Low to Output Delay
ADV# Pulse Width Low
70
85
10
10
9
10
10
9
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
4
8
20
52
25
40
Clock Specifications
R200
R201
R202
R203
f
t
t
t
CLK Frequency
MHz
ns
CLK
CLK Period
19
5
25
5
CLK
CLK High or Low Time
CLK Fall or Rise Time
ns
CH/L
CHCL
3
3
ns
Preliminary
47
1.8 Volt Intel® Wireless Flash Memory (W18)
Speed
–70
–85
#
Sym
Parameter (1,2)
Unit
Note
Min
Max
Min
Max
Synchronous Specifications
R301
R302
R303
R304
R305
R306
t
t
t
t
t
t
t
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Delay
9
10
9
9
10
9
ns
ns
ns
ns
ns
ns
AVCH
VLCH
ELCH
CHQV
CHQX
CHAX
CHTL/
8
4
14
14
18
18
Output Hold from CLK
Address Hold from CLK
5
5
10
10
R307
CLK to WAIT Asserted
ns
H
R308
R309
R310
t
t
t
CE# Low to WAIT active
CE# High to WAIT High-Z
CE# Pulse Width High
7
6,7
7
14
20
18
25
ns
ns
ns
ELTL
EHTZ
EHEL
15
20
NOTES:
1. See Figure 16, “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum
allowable input slew rate.
2. AC specifications assume the data bus voltage is less than or equal to V
initiated.
when a read operation is
CCQ
3. t
t
t
= 85 ns for 128-Mbit device.
AVAV, ELQV, AVQV
4. Address hold in synchronous burst-mode is defined as t
satisfied first.
or t
, whichever timing specification is
VHAX
CHAX
5. OE# may be delayed by up to t
6. Sampled, not 100% tested.
– t
after the falling edge of CE# without impact to t
.
ELQV GLQV
ELQV
7. Applies only to subsequent synchronous reads.
8. Contact your field representative for operations up to 66 MHz.
48
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 19. Asynchronous Read Operation Waveform
R1
VIH
VIL
Valid
Address
Address [A]
CE# [E]
R2
R3
VIH
VIL
R8
R9
VIH
VIL
R4
OE# [G]
R7
VIH
VIL
WE# [W]
Data [D/Q]
RST# [P]
VOH
VOL
High Z
Valid
Output
R5
R10
VIH
VIL
Generic_Async_Rd
Preliminary
49
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 20. Latched Asynchronous Read Operation Waveform
R1
VIH
Valid
Valid
AMAX-2 [A]
Address
Address
VIL
VIH
Valid
Valid
A1-0 [A]
Address
Address
VIL
R2
R101
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R104
R102
R103
VIH
VIL
R3
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
R7
VIH
VIL
VOH
VOL
High Z
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Generic_Latch_Async_Rd
50
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 21. Page Mode Read Operation Waveform
R1
VIH
Valid
A
MAX-2 [A]
Address
VIL
R2
VIH
VIL
Valid
Address
Valid
Address
Valid
Address
Valid
Address
A1-0 [A]
R101
R105
VIH
R106
R103
ADV# [V]
CE# [E]
VIL
R104
R102
R107
R3
VIH
VIL
R4
R8
R6
VIH
VIL
OE# [G]
WE# [W]
R7
R9
VIH
VIL
R108
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
Preliminary
51
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 22. Single Synchronous Read Operation Waveform
VIH
Note 1
CLK [C]
VIL
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
RST# [P]
R303
R7
VIH
VIL
R309
R10
R308
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 5.0.2, “First Access Latency Count” on page 25 describes how to insert clock cycles during the initial
access.
2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.
52
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 23. Synchronous Four-Word Burst Read Operation Waveform
VIH
VIL
Note 1
CLK [C]
0
1
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R107
R103
R310
R8
VIH
VIL
R3
R102
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
RST# [P]
R303
R7
R9
VIH
VIL
R309
R10
R308
R307
VOH
VOL
High Z
High Z
Note 2
R305
R304
VOH
VOL
High Z
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 5.0.2, “First Access Latency Count” on page 25 describes how to insert clock cycles during the initial
access.
2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.
Preliminary
53
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 24. WAIT Functionality for EOWL (End of Word Line) Condition Waveform
VIH
Note 1
CLK [C]
0
1
VIL
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R107
R103
VIH
VIL
R3
R102
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
RST# [P]
R303
R7
VIH
VIL
R308
R307
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 5.0.2, “First Access Latency Count” on page 25 describes how to insert clock cycles during the initial
access.
2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.
54
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
8.7
AC Write Characteristics
Speed
–70
–85
#
Sym
Parameter (1,2)
Unit
Note
Min
Max
Min
Max
t
(t
PHWL
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
RST# High Recovery to WE# (CE#) Low
CE# (WE#) Setup to WE# (CE#) Low
WE# (CE#) Write Pulse Width Low
Data Setup to WE# (CE#) High
3
4
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
PHEL
t
(t
ELWL
WLEL
0
45
45
45
0
0
60
60
60
0
)
t
WLWH
(t
)
ELEH
t
DVWH
(t
)
DVEH
t
AVWH
Address Setup to WE# (CE#) High
(t
)
AVEH
t
(t
WHEH
EHWH
CE# (WE#) Hold from WE# (CE#) High
)
t
WHDX
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
0
0
(t
)
EHDX
t
WHAX
0
0
(t
)
EHAX
t
WHWL
5, 6, 7
3
25
200
25
200
(t
)
EHEL
t
VPWH
V
V
Setup to WE# (CE#) High
PP
(t
)
VPEH
QVVL
QVBL
W11
W12
t
Hold from Valid Status Register Data
3, 8
3, 8
0
0
0
0
ns
ns
PP
t
WP# Hold from Valid Status Register Data
WP# Setup to WE# (CE#) High
t
BHWH
W13
W14
W16
3
200
0
200
0
ns
ns
ns
(t
)
BHEH
t
WHGL
Write Recovery before Read
WE# High to Valid Data
(t
)
EHGL
t
+
t
+
AVQV
50
AVQV
40
t
6
WHQV
NOTES:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE# or
WLWH
ELEH
WE# high (whichever occurs first). Hence, t
= t
= t
= t
= t
.
WP
WLWH
ELEH
WLEH
ELWH
5. Write pulse width high (t
or t
) is defined from CE# or WE# high (whichever is first) to CE# or WE#
WHWL
EHEL
low (whichever is last). Hence, t
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
6. t
is t
+ 50 ns. System designers should take this into account and may insert a software No-Op
WHQV
AVQV
instruction to delay the first read after issuing a command.
7. For command other than resume commands.
8. V should be held at V
or V
until block erase or program success is determined.
PP
PP1
PP2
Preliminary
55
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 25. Write Operations Waveform
W5
W8
Note 1
VIH
Note 2
Note 3
Note 4
Note 5
Valid
Address
Valid
Address
Valid
Address
Address [A]
CE# (WE#) [E(W)]
OE# [G]
VIL
VIH
VIL
W2
W6
VIH
VIL
W3
W9
W14
W16
VIH
VIL
Note 6
WE# (CE#) [W(E)]
Data [D/Q]
W1
W7
VIH
VIL
Valid
SRD
Data In
Data In
W4
VIH
VIL
RST# [P]
W13
W10
W12
W11
VIH
VIL
WP# [B]
VPP1 or VPP2
VPP [V]
VIL
NOTES:
1. V power-up and standby.
CC
2. Write Program or Erase Set-up command.
3. Write valid address and data (for program) or Erase Confirm command.
4. Automated program/erase delay.
5. Read status register data (SRD) to determine program/erase operation completion.
6. OE# and CE# must be driven active (low) and WE# must be de-asserted (high) for read operations.
56
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
8.8
Erase and Program Times
Extended Temperatures
V
V
PP2
PP1
Notes
Unit
#
Operation
Symbol
Parameter
Typ
Max
Typ
Max
1-Word
1,2,3,4
1,3,4
12
150
n/a
8
130
t
t
/
WHQV1
EHQV1
Word
Block
µs
Enhanced Factory
Programming Mode
n/a
3.5
16
t
t
t
4-KW Parameter
32-KW Main
1,2,3,4
1,2,3,4
0.05
0.4
0.23
1.8
0.03
0.24
0.07
0.6
s
s
s
BWPB
BWMB
BWPB
Program
Time
Enhanced 4-KW Parameter
Factory
1,2,3,4,5
n/a
n/a
0.015
n/a
Programm
ing Mode
t
32-KW Main
1,2,3,4,5
n/a
n/a
0.12
n/a
s
BWMB
W0
4-KW Parameter
Block
1,2,3,4
1,2,3,4
0.3
0.7
2.5
4
0.25
0.4
2.5
4
s
s
t
t
/
WHQV2
EHQV2
Erase Time
32-KW Main
t
t
/
/
WHRH1
EHRH1
Program Suspend
Erase Suspend
1,2,3,4
1,2,3,4
5
5
10
20
5
5
10
20
Suspend
Latency
µs
µs
t
t
WHRH2
EHRH2
t
t
t
EFP Set Up
1,3,4
1,3,4
1,3,4
n/a
n/a
n/a
n/a
n/a
n/a
n/a
2.7
1.7
5
EFP-SETUP
EFP-TRAN
EFP Latency
Program to Verify Transition
Verify
5.6
130
EFP-VERIFY
NOTES:
1. Typical values measured at T = +25 °C and nominal voltages.
A
2. Excludes external system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested.
5. Exact results may vary based on system overhead.
8.9
Reset Specifications
#
Symbol
Parameter(1)
Note
Min
100
Max
Unit
P1
P2
P3
t
t
t
RST# Low to Reset during Read
2, 3, 4
3, 4, 5
3, 4, 5
3, 4
ns
PLPH
RST# Low to Reset during Block Erase
RST# Low to Reset during Program
20
10
60
PLRH
µs
V
Power Valid to Reset
VCCPH
CC
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. The device may reset if t is <t Min, but this is not guaranteed.
PLPH
PLPH
3. Not applicable if RST# is tied to V
4. Sampled, but not 100% tested.
.
CC
5. Reset will complete within t
executing.
if RST# is asserted while a block erase or program operation is not
PLPH
Preliminary
57
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 26. Reset Operations Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
RST# [P]
RST# [P]
RST# [P]
VCC
read mode
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
RESET.WMF
58
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Appendix A Write State Machine States
This table shows the command state transitions based on incoming commands. Only one partition can be
actively programming or erasing at a time. Each partition stays in its last output state (Array, ID/CFI or Status)
until a new command changes it. The next WSM state does not depend on the partition’s output state.
Figure 27. Write State Machine — Next State Table (Sheet 1 of 2)
Chip
Next State after Command Input
Enhanced BE Confirm,
Program/
Clear
Status
Register(6)
Read
Array(3)
Program
Setup(4,5)
Erase
Setup(4,5)
Factory P/E Resume,
Read
Status
Read
ID/Query
Current Chip
State(8)
Erase
Suspend
Pgm
ULB
Confirm(9)
Setup(4)
(FFH)
Ready
(10H/40H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
Program
Setup
Erase
Setup
EFP
Setup
Ready
Ready
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Setup
Busy
Program Busy
Program
Erase
Program Busy
Pgm Susp
Program Busy
Suspend
Setup
Busy
Program Suspend
Ready (Error)
Pgm Busy
Program Suspend
Ready (Error)
Erase Busy
Erase Busy
Erase Susp
Erase Busy
Pgm in
Erase
Susp Setup
Erase
Suspend
Suspend
Erase Suspend
Erase Busy
Erase Suspend
Setup
Busy
Program in Erase Suspend Busy
Pgm Susp in
Erase Susp
Program in
Erase Suspend
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Pgm in Erase
Susp Busy
Suspend
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Suspend (Lock Error)
Ready (Error)
Erase Susp
Setup
EFP Busy
EFP Busy(7)
Verify Busy(7)
Ready (Error)
Enhanced
Factory
EFP Busy
EFP Verify
Program
Output
Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
OTP Busy
Status
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
Output
does not
change
Array(3)
Status
Output does not change
Status
ID/Query
Preliminary
59
1.8 Volt Intel® Wireless Flash Memory (W18)
Figure 27. Write State Machine — Next State Table (Sheet 2 of 2)
Chip
Next State after Command Input
Lock,
Unlock,
Lock-down,
CR setup(5)
Lock-
Down
Block
Confirm(9)
Enhanced
Fact Pgm
Exit (blk add
<> WA0)
Lock
Block
Confirm(9)
Illegal
commands or
EFP data(2)
OTP
Setup(5)
Write CR
Confirm(9)
WSM
Operation
Completes
Current Chip
State(8)
(60H)
(C0H)
(01H)
(2FH)
(03H)
Ready
Ready
(XXXXH)
(other codes)
Lock/CR
Setup
OTP
Setup
Ready
N/A
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Ready
N/A
Setup
Busy
Program Busy
Program Busy
Program Suspend
Ready (Error)
Program
Erase
Ready
Suspend
Setup
Busy
N/A
Erase Busy
Erase Busy
Ready
Lock/CR
Setup in
Erase Susp
Suspend
Erase Suspend
N/A
Setup
Busy
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Erase
Suspend
Program in
Erase Suspend
Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)
N/A
Setup
Ready (Error)
EFP Verify
Enhanced
Factory
Program
EFP Busy(7)
Verify Busy(7)
EFP Busy(7)
EFP Verify(7)
EFP Busy
EFP Verify
Ready
Ready
Output
Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
Array
Status
Output does
not change
OTP Busy
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Output does
not change
Status
Output does not change
Array
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
60
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
NOTES:
1. The output state shows the type of data that appears at the outputs if the partition address is the same as the
command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the
command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command
changes it. The next WSM state does not depend on the partition’s output state. For example, if partition #1’s
output state is Read Array and partition #4’s output state is Read Status, every read from partition #4 (without
issuing a new command) outputs the Status register.
2. Illegal commands are those not defined in the command set.
3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition
results in undermined data when a partition address is read.
4. Both cycles of 2-cycle commands should be issued to the same partition address. If they are issued to
different partitions, the second write determines the active partition. Both partitions will output status
information when read.
5. If the WSM is active, both cycles of a 2-cycle command are ignored. This differs from previous Intel devices.
6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy,
Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm
Suspend, Pgm Suspend In Erase Suspend).
7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP
Confirm command. Any other commands are treated as data.
8. The "current state" is that of the WSM, not the partition.
9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the
operation and then move to the Ready State.
Preliminary
61
1.8 Volt Intel® Wireless Flash Memory (W18)
Appendix B Protection Register Addressing
Word
Use
ID Offset
A
A
A
A
A
A
A
A
0
7
6
5
4
3
2
1
LOCK
Both
Intel
PBA+000080h
PBA+000081h
PBA+000082h
PBA+000083h
PBA+000084h
PBA+000085h
PBA+000086h
PBA+000087h
PBA+000088h
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Intel
Intel
Intel
Customer
Customer
Customer
Customer
NOTE: Addresses A -A should be set to zero. A -A = partition base address (PBA)
18 MAX
8
17
62
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Appendix C Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
C.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper
bytes. The device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table C1. Summary of Query Structure Output as a Function of Device and Mode
Hex
Hex
ASCII
Device
Offset Code Value
00010:
00011:
00012:
51
52
59
"Q"
"R"
"Y"
Device Addresses
Preliminary
63
1.8 Volt Intel® Wireless Flash Memory (W18)
Table C2. Example of Query Structure Output of x16- and x8 Devices
Word Addressing:
Byte Addressing:
Offset
AX–A0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
Hex Code
D15–D0
0051
0052
0059
P_IDLO
P_IDHI
PLO
Value
Offset
AX–A0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
Hex Code
Value
D7–D0
"Q"
"R"
"Y"
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
"Q"
"R"
"Y"
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PrVendor
ID #
ID #
PHI
...
A_IDLO
A_IDHI
...
...
C.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table C3. Query Structure
Description(1)
Manufacturer Code
Offset
00000h
Sub-Section Name
00001h
(BA+2)h(2)
Device Code
Block-specific information
Block Status register
00004-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
0001Bh
00027h
CFI query identification string
System interface information
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Intel-specific Extended Query Table
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is
32K-word).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
C.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation. Only issuing another operation to the block resets
this bit. The Block Status Register is accessed from word address 02h within each block.
64
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Table C4. Block Status Register
Offset
Length
Description
Block Lock Status Register
BSR.0 Block lock status
0 = Unlocked
Add.
Value
(BA+2)h(1)
1
BA+2 --00 or --01
BA+2 (bit 0): 0 or 1
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
BA+2 (bit 1): 0 or 1
BSR 2–7: Reserved for future use
BA+2 (bit 2–7): 0
NOTE: BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64KB block) beginning
location in word mode)
Preliminary
65
1.8 Volt Intel® Wireless Flash Memory (W18)
C.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Table C5. CFI Identification
Hex
Offset
Length
Description
Query-unique ASCII string “QRY“
Add. Code Value
10h
3
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
--51
--52
--59
--03
--00
--39
--00
--00
--00
--00
--00
"Q"
"R"
"Y"
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Table C6. System Interface Information
Hex
Offset
Length
Description
Add. Code Value
1Bh
1
V
CC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1B:
1C:
1D:
1E:
--17 1.7V
--19 1.9V
--B4 11.4V
--C6 12.6V
--04 16µs
1Ch
1Dh
1Eh
1
1
1
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µ-sec
“n” such that typical max. buffer write time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
NA
1s
NA
--04 256µs
--00
--03
--00
NA
8s
NA
66
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
C.5
Device Geometry Definition
Table C7. Device Geometry Definition
Offset
27h
Length
Description
Code
27: See table below
1
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
2
1
x16
9
0
x8
8
28h
2
—
15
—
—
14
—
—
13
—
—
12
—
x64
11
x32
10
28:
--01
x16
0
—
—
—
—
29:
2A:
2B:
2C:
--00
--00
--00
2Ah
2Ch
2
1
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2Dh
31h
35h
4
4
4
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
Address
16 Mbit
32 Mbit
64 Mbit
128 Mbit
–B
–T
–B
–T
–B
–T
–B
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
--00
--00
--00
--00
--15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--00
--00
--00
--00
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--07
--00
--20
--00
--7E
--00
--00
--01
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--7E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--07
--00
--20
--00
--FE
--00
--00
--01
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--FE
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
Preliminary
67
1.8 Volt Intel® Wireless Flash Memory (W18)
C.6
Intel-Specific Extended Query Table
Table C8. Primary Vendor-Specific Extended Query
Offset(1)
P = 39h
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
Hex
Length
Description
(Optional flash features and commands)
Primary extended query table
Unique ASCII string “PRI“
Add. Code Value
3
39:
3A:
3B:
3C:
3D:
3E:
3F:
40:
41:
--50
--52
--49
--31
--33
--E6
--03
--00
--00
"P"
"R"
"I"
"1"
"3"
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
No
Yes
Yes
Yes
Yes
Yes
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
(P+9)h
1
2
42:
--01
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
bit 0 = 1
Yes
(P+A)h
(P+B)h
43:
44:
--03
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
(P+C)h
(P+D)h
1
1
V
CC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
45:
46:
--18 1.8V
VPP optimum program/erase supply voltage
--C0 12.0V
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
68
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Table C9. Protection Register Information
Offset(1)
Length
Hex
Description
P = 39h
(P+E)h
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
Add. Code Value
1
4
47:
--01
1
(P+F)h
(P+10)h
(P+11)h
(P+12)h
48:
49:
4A:
4B:
--80
--00
--03 8 byte
--03 8 byte
80h
00h
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Table C10. Burst Read Information
Offset(1)
Length
Hex
Description
P = 39h
(Optional flash features and commands)
Add. Code Value
(P+13)h
1
Page Mode Read capability
4C:
--03 8 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
(P+14)h
(P+15)h
1
1
Number of synchronous mode read configuration fields that
4D:
4E:
--03
--01
3
4
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
(P+16)h
(P+17)h
1
1
Synchronous mode read capability configuration 2
4F:
50:
--02
--07 Cont
8
Synchronous mode read capability configuration 3
Table C11. Partition and Erase-block Region Information
(1)
P = 39h
See table below
Address
Description
Bot
Top
Bottom
Top
(Optional flash features and commands)
Len
(P+18)h (P+18)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
51:
51:
Preliminary
69
1.8 Volt Intel® Wireless Flash Memory (W18)
Partition Region 1 Information
(1)
P = 39h
See table below
Address
Description
Bot
52:
53:
54:
Top
52:
53:
54:
Bottom
Top
(Optional flash features and commands)
Len
2
(P+19)h (P+19)h Number of identical partitions within the partition region
(P+1A)h (P+1A)h
(P+1B)h (P+1B)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
1
1
(P+1C)h (P+1C)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1E)h (P+1E)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
55:
56:
57:
55:
56:
57:
1
1
(P+1F)h (P+1F)h Partition Region 1 Erase Block Type 1 Information
4
58:
59:
5A:
5B:
5C:
5D:
5E:
58:
59:
5A:
5B:
5C:
5D:
5E:
(P+20)h (P+20)h
(P+21)h (P+21)h
(P+22)h (P+22)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+23)h (P+23)h Partition 1 (Erase Block Type 1)
(P+24)h (P+24)h
Minimum block erase cycles x 1000
(P+25)h (P+25)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+26)h (P+26)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
5F:
5F:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+27)h
(P+28)h
(P+29)h
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase block Type 2)
Minimum block erase cycles x 1000
60:
61:
62:
63:
64:
65:
66:
2
1
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+2E)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
67:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
70
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Partition Region 2 Information
(1)
P = 39h
See table below
Address
Description
Bot
68:
69:
6A:
Top
60:
61:
62:
Bottom
Top
(Optional flash features and commands)
Len
2
(P+2F)h (P+27)h Number of identical partitions within the partition region
(P+30)h (P+28)h
(P+31)h (P+29)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
1
1
1
1
(P+32)h (P+2A)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+33)h (P+2B)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+34)h (P+2C)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
6B:
6C:
6D:
63:
64:
65:
(P+35)h (P+2D)h Partition Region 2 Erase Block Type 1 Information
4
6E:
6F:
70:
71:
72:
73:
74:
66:
67:
68:
69:
6A:
6B:
6C:
(P+36)h (P+2E)h
(P+37)h (P+2F)h
(P+38)h (P+30)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+39)h (P+31)h Partition 2 (Erase block Type 1)
(P+3A)h (P+32)h Minimum block erase cycles x 1000
(P+3B)h (P+33)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+3C)h (P+34)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
75:
6D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+35)h Partition Region 2 Erase Block Type 2 Information
6E:
6F:
70:
71:
72:
73:
74:
(P+36)h
(P+37)h
(P+38)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+39)h Partition 2 (Erase Block Type 2)
(P+3A)h Minimum block erase cycles x 1000
(P+3B)h Partition 2 (Erase Block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+3C)h Partition 2 (Erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
75:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Preliminary
71
1.8 Volt Intel® Wireless Flash Memory (W18)
(P+3D)h (P+3D)h Features Space definitions (Reserved for future use)
(P+3E)h (P+3E)h Reserved for future use
TBD
Resv’d 77:
76:
76:
77:
Partition and Erase-block Region Information
Address
16 Mbit
32 Mbit
64Mbit
128Mbit
–B –T
–B
–T
–B
–T
–B
–T
51:
52:
53:
54:
55:
56:
57:
58:
59:
5A:
5B:
5C:
5D:
5E:
5F:
60:
61:
62:
63:
64:
65:
66:
67:
68:
69:
6A:
6B:
6C:
6D:
6E:
6F:
70:
71:
72:
73:
74:
75:
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--03
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--03
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
NOTES:
1. The variable P is a pointer which is defined at CFI offset 15h.
2. For a 16Mb the 1.8 Volt Intel® Wireless Flash memory z1 = 0100h = 256 256 * 256 = 64K, y1 = 17h = 23d
y1+1 = 24
24 * 64K = 1½MB
Partition 2’s offset is 0018 0000h bytes (000C 0000h words).
3. TPD - Top parameter device; BPD - Bottom parameter device.
4. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and
parameter blocks.
5. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains
all the partitions that are made up of main blocks only. B. contains the partition that is made up of the
parameter and the main blocks.
72
Preliminary
1.8 Volt Intel® Wireless Flash Memory (W18)
Appendix D Mechanical Specifications
D.7
The 1.8 Volt Intel® Wireless Flash memory 56 Active Ball
Matrix (7x8) 0.75 mm Ball Pitch Package Specifications
7 x 8 Package
E
D
Mechanical Specifications
D (Width)(1)
(± 0.1 mm)
E (Length)(2)
(± 0.1 mm)
Height
(max)
Pkg Type
Density
VF BGA
32 Mbit
64 Mbit
128 Mbit
7.7 mm
7.7 mm
9.0 mm
9.0 mm
1.0 mm
1.0 mm
1.0 mm
µBGA* CSP
µBGA
< 10.7 mm
<12.5 mm
NOTES:
1. 8 Ball direction of the matrix runs parallel to this dimension
2. 7 Ball direction of the matrix runs parallel to this dimension
Preliminary
73
1.8 Volt Intel® Wireless Flash Memory (W18)
Appendix E Ordering Information
Component Ordering Information
W
GT 2 8 F 6 4 0 1 8 T 7 0
Access Speed (ns)
(70, 85)
Package
GT = Extended temp.
56-Ball 7x8 matrix
µBGA* CSP or VF
BGA
T = Top Parameter
Blocking
B = Bottom Parameter
Blocking
Product line designator
for all Intel® Flash
products
Product Family
Device Density
W18 = 1.8 Volt Intel®
Wireless Flash Memory
VCC = 1.7 V - 1.95 V
VPP = 0.9 V - 1.95 V or
11.4 V - 12.6 V
32 = x16 (32-Mbit)
64 = x16 (64-Mbit)
128 = x16 (128-Mbit)
74
Preliminary
相关型号:
©2020 ICPDF网 联系我们和版权申明