GT28F640W18B70 [NUMONYX]

Flash, 4MX16, 70ns, PBGA56, 0.75 MM PITCH, CSP, MICRO, BGA-56;


型号：	GT28F640W18B70
厂家：	NUMONYX B.V
描述：	Flash, 4MX16, 70ns, PBGA56, 0.75 MM PITCH, CSP, MICRO, BGA-56 内存集成电路闪存
文件：	总84页 (文件大小：2071K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1.8 Volt Intel^®Wireless Flash Memory

(W18)

28F320W18, 28F640W18, 28F128W18

Preliminary Datasheet

Product Features

■ Performance

■ Software

— 5 µs (Typ) Program Suspend

— 70 ns Asynchronous reads for 32 and 64 Mbit,

90 ns for 128 Mbit

— 5 µs (Typ) Erase Suspend

— Intel^®Flash Data Integrator (FDI) Software

Optimized

— 14 ns Clock to Data Output (t

— 20 ns Page Mode Read Speed

)

CHQV

— 4-Word, 8-Word, and Continuous-Word Burst

— Intel Basic Command Set Compatible

— Common Flash Interface (CFI)

■ Quality and Reliability

— Extended Temperature: –40 °C to +85 °C

— Minimum 100,000 Erase Cycles per Block

— ETOX™ VII Flash Technology (0.18 µm)

■ Security

Modes

— Burst and Page Modes in Parameter and Main

Partitions

— Programmable WAIT Configuration

— Enhanced Factory Programming Mode@

3.50 µs/Word (Typ)

— Glueless 12 V interface for Fast Factory

Programming @ 8 µs/Word (Typ)

— 1.8 V Low-Power Programming @ 12 µs/Word

(Typ)

— 128-bit Protection Register: 64 Unique Device

Identifier Bits; 64 User-Programmable OTP

Bits

— Absolute Write Protection

= GND

— Program or Erase during Reads

■ Architecture

— Erase/Program Lockout during Power

Transitions

— Multiple 4-Mbit Partitions

— Dual-Operation: Read-While-Write or Read-

While-Erase

— Individual Dynamic Zero-Latency Block

Locking

— Individual Block Lock-Down

■ Density and Packaging

— Eight, 4-Kword Parameter Code and Data

Blocks

— 32 Mbit and 128 Mbit in a VF BGA Package

— 64 Mbit in a µBGA*Package

— 56 Active Ball Matrix, 0.75 mm Ball-Pitch

µBGA* and VF BGA Packages

— 32-Kword Main Code and Data Blocks

— Top and Bottom Parameter Configurations

■ Power Operation

— 1.7 V to 1.95 V Read and Write Operations

— 16-bit wide Data Bus

— 1.7 V to 2.24 V V

for I/O Isolation

CCQ

— Standby Current: 5 µA (Typ)

— Read Current: 7 mA (Typ)

The 1.8 Volt Intel^®Wireless Flash memory with flexible multi-partition dual-operation provides high-

performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs.

Combining high read performance with flash memory’s intrinsic non-volatility, 1.8 Volt Intel Wireless Flash

memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from

slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases

reliability and reduces overall system power consumption and cost.

The 1.8 Volt Intel Wireless Flash memory’s flexible multi-partition architecture allows programming or erasing to

occur in one partition while reading from another partition. This allows for higher data write throughput

compared to single partition architectures. The dual-operation architecture also allows two processors to

interleave code operations while program and erase operations take place in the background. The designer can

also choose the size of the code and data partitions via the flexible multi-partition architecture.

The 1.8 Volt Intel Wireless Flash memory is manufactured on Intel’s 0.18 µm ETOX™ VII process technology. It

is available in µBGA and VF BGA packages which are ideal for board-constrained applications.

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

290701-003

June 2001

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no

liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are

not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 1.8 Volt Intel® Wireless Flash memory may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

*Other names and brands may be claimed as the property of others.

1.8 Volt Intel® Wireless Flash Memory (W18)

Contents

1.0

Introduction..................................................................................................................1

1.1

1.2

Document Conventions.........................................................................................1

Product Overview..................................................................................................2

2.0

Product Description..................................................................................................4

2.1

2.2

2.3

Package and Ballouts............................................................................................4

Signal Descriptions................................................................................................4

Memory Partitioning ..............................................................................................6

3.0

4.0

Principles of Operation............................................................................................9

3.1

Bus Operations......................................................................................................9

3.1.1 Read.........................................................................................................9

3.1.2 Standby ..................................................................................................10

3.1.3 Write.......................................................................................................10

3.1.4 Reset......................................................................................................10

Command Definitions.............................................................................................11

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Read-While-Write and Read-While-Erase...........................................................11

Read Array Command.........................................................................................14

Read Identifier Command ...................................................................................14

Read Query Command .......................................................................................15

Read Status Register Command.........................................................................15

Clear Status Register Command.........................................................................17

Word Program Command ...................................................................................17

Block Erase Command........................................................................................18

Program Suspend, Program Resume, Erase Suspend,

Erase Resume Commands .................................................................................20

Enhanced Factory Program Command (EFP) ....................................................23

4.10.1 EFP Requirements and Considerations.................................................23

4.10.2 Setup Phase...........................................................................................24

4.10.3 Program Phase ......................................................................................24

4.10.4 Verify Phase...........................................................................................24

4.10.5 Exit Phase ..............................................................................................25

Security Modes....................................................................................................27

Block Locking Commands...................................................................................27

4.12.1 Lock Block..............................................................................................28

4.12.2 Unlock Block...........................................................................................28

4.12.3 Lock-Down Block....................................................................................28

4.12.4 Block Lock Status...................................................................................29

4.12.5 Locking Operations During Erase Suspend ...........................................29

4.12.6 Status Register Error Checking..............................................................29

4.12.7 WP# Lock-Down Control........................................................................30

Protection Register..............................................................................................30

Read Protection Register ....................................................................................31

Program Protection Register...............................................................................31

4.15.1 Lock Protection Register ........................................................................32

Set Configuration Register ..................................................................................34

4.10

4.11

4.12

4.13

4.14

4.15

4.16

iii

1.8 Volt Intel® Wireless Flash Memory ( W18)

4.16.1 Read Mode (CR.15)...............................................................................35

4.16.2 First Access Latency Count (CR.13-11).................................................35

4.16.3 WAIT Signal Polarity (CR.10).................................................................37

4.16.4 WAIT Signal Function ............................................................................38

4.16.5 Data Output Configuration (CR.9)..........................................................38

4.16.6 WAIT Delay Configuration (CR.8)..........................................................39

4.16.7 Burst Sequence Configuration (CR.7)....................................................40

4.16.8 Clock Configuration (CR.6) ....................................................................41

4.16.9 Burst Wrap (CR.5)..................................................................................41

4.16.10 Burst Length (CR.2-0)............................................................................42

5.0

6.0

Program and Erase Voltages ..............................................................................43

5.1

5.2

Factory Program Mode .......................................................................................43

Programming Voltage Protection (VPP)..............................................................43

Power Consumption...............................................................................................44

6.1

6.2

6.3

6.4

Active Power .......................................................................................................44

Automatic Power Savings ...................................................................................44

Standby Power....................................................................................................44

Power-Up/Down Operation .................................................................................44

6.4.1 System Reset and RST#........................................................................44

6.4.2 VCC, VPP, and RST# Transitions..........................................................45

6.4.3 Power Supply Decoupling......................................................................45

7.0

Electrical Specifications........................................................................................46

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Absolute Maximum Ratings ................................................................................46

Extended Temperature Operation.......................................................................47

Capacitance ........................................................................................................47

DC Characteristics ..............................................................................................48

AC I/O Test Conditions .......................................................................................50

AC Read Characteristics.....................................................................................51

AC Write Characteristics.....................................................................................61

Erase and Program Times ..................................................................................63

Reset Specifications............................................................................................63

Appendix A Write State Machine States.............................................................................65

Appendix B Common Flash Interface .................................................................................68

Appendix C Mechanical Specifications..............................................................................76

Appendix D Ordering Information.........................................................................................77

1.8 Volt Intel® Wireless Flash Memory (W18)

Revision History

Date of

Version

Revision

Description

09/13/00

01/29/01

290701-001

290701-002

Original Version

Deleted 16-Mbit density

Revised ADV#, Section 2.2

Revised Protection Registers, Section 4.16

Revised Program Protection Register, Section 4.18

Revised Example in First Access Latency Count, Section 5.0.2

Revised Figure 5, Data Output with LC Setting at Code 3

Added WAIT Signal Function, Section 5.0.3

Revised WAIT Signal Polarity, Section 5.0.4

Revised Data Output Configuration, Section 5.0.5

Added Figure 7, Data Output Configuration with WAIT Signal Delay

Revised WAIT Delay Configuration, Section 5.0.6

Changed V

Spec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2,

CCQ

Extended Temperature Operation

Changed I

Spec from 15 µA to 18 µA in Section 8.4, DC

CCS

Characteristics

Changed I

Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13

CCR

mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in

Section 8.4, DC Characteristics

Changed I

Spec from 15 µA to 18 µA in Section 8.4, DC

Spec from 5ns to 3ns in Section 8.6, AC Read

CCWS

Characteristics

Changed I

Characteristics

CCES

Changed t

Characteristics

CHQX

Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation

Waveform

Added Figure 26, WAIT Signal in Asynchronous Page Mode Read

Operation Waveform

Added Figure 27, WAIT Signal in Asynchronous Single Word Read

Operation Waveform

Revised Appendix E, Ordering Information

06/12/01

290701-003

Revised entire Section 4.10, Enhanced Factory Program Command (EFP)

and Figure 6, Enhanced Factory Program Flowchart

Revised Section 4.13, Protection Register

Revised Section 4.15, Program Protection Register

Revised Section 7.3, Capacitance, to include 128-Mbit specs

Revised Section 7.4, DC Characteristics, to include 128-Mbit specs

Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device

specifications

Added t

Spec in Section 7.6, AC Read Characteristics

VHGL

Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device

specifications

Minor text edits

1.8 Volt Intel^®Wireless Flash Memory (W18)

1.0

Introduction

This datasheet contains information about the 1.8 Volt Intel^®Wireless Flash memory family.

Section 1.0 provides a flash memory overview. Section 2.0 through Section 6.0 describe the

memory functionality. Section 7.0 describes the electrical specifications for extended temperature

product offerings.

1.1

Document Conventions

Many terms and phrases are used throughout this document as a short-hand version of full, and

more accurate verbiage:

• The term “1.8 V” refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted)

and “V_PP= 12 V” refers to 12 V ±5%.

• When referring to registers, the term set means the bit is a ‘1’, and clear means the bit is a ‘0’.

• Even though this product supports multiple package types, the terms pin and signal are often

used interchangeably to refer to the external signal connections on the package. (e.g., balls in

the case of µBGA*).

• A word is 2 bytes, or 16 bits.

• For voltage and ground signals, the signal name is denoted in all CAPS as seen in Section 2.2,

“Signal Descriptions” on page 4, whereas the voltage applied to the signal uses subscripted

notation. For example VPP refers to a signal, while V_PPis a voltage level.

Throughout this document, references are made to top, bottom, parameter, and main partitions. To

clarify these references, the following conventions have been adopted:

• A block is a group of bits (or words) that erase simultaneously with one block erase

instruction.

• A main block contains 32 Kwords.

• A parameter block contains 4 Kwords.

• The Block Base Address (BBA) is the first address of a block.

• A partition is a group of blocks that share erase and program circuitry and a common status

than array data, is available when any address within the same partition is read.

• The Partition Base Address (PBA) is the first address of a partition. For example, on a 32-

Mbit top-parameter device, partition number 5 has a PBA of 140000h.

• The top partition is located at the highest physical device address. This partition may be a

main partition or a parameter partition.

• The bottom partition is located at the lowest physical device address. This partition may be a

main partition or a parameter partition.

• A main partition contains only main blocks.

• A parameter partition contains a mixture of main and parameter blocks.

• A top parameter device (TPD) has the parameter partition at the top of the memory map with

the parameter blocks at the top of that partition. This was formerly referred to as top-boot

device.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

• A bottom parameter device (BPD) has the parameter partition at the bottom of the memory

map with the parameter blocks at the bottom of that partition. This was formerly referred to as

bottom-boot block flash device.

Additionally, many acronyms which describe product features or usage are used throughout the

document. They are defined here:

• EFP: Enhanced Factory Programming

• RWW: Read-While-Write

• RWE: Read-While-Erase

• CFI: Common Flash Interface

• CUI: Command User Interface

• WSM: Write State Machine

• OTP: One-Time Programmable

• PBA: Partition Base Address

• BBA: Block Base Address

• APS: Automatic Power Savings

• FDI: Flash Data Integrator

• SRD: Status Register Data

1.2

Product Overview

The 1.8 Volt Intel^®Wireless Flash memory provides RWW/RWE capability with high-

performance synchronous and asynchronous reads on package-compatible densities with a 16-bit

data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight

4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the

memory map. The rest of the memory array is grouped into 32-Kword main blocks.

The memory architecture for the 1.8 V Intel Wireless Flash memory consists of multiple 4-Mbit

partitions, the exact number depending on device density. By dividing the memory array into

partitions, program or erase operations can take place simultaneously during read operations. Burst

reads can traverse partition boundaries, but user application code is responsible for ensuring that

they don’t extend into a partition that is actively programming or erasing. Although each partition

has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in

one partition while other partitions are in a read mode.

Augmented erase suspend functionality further enhances the RWW capabilities of this device. An

erase can be suspended to perform a program or read operation within any block, except that which

is erase-suspended. A program operation nested within a suspended erase can subsequently be

suspended to read yet another memory location.

After device power-up or reset, the 1.8 Volt Intel Wireless Flash memory defaults to asynchronous

read configuration. Writing to the device’s configuration register enables synchronous burst-mode

read operation. In synchronous mode, the CLK input increments an internal burst address

generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every,

or on every other, CLK cycle after initial latency. A programmable WAIT output signal provides

easy CPU-to-flash memory synchronization.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

In addition to its enhanced architecture and interface, the 1.8 Volt Intel Wireless Flash memory

incorporates technology that enables fast factory programming and low-power designs. The EFP

option renders the fastest available program performance, which can increase a factory’s

manufacturing throughput.

The device supports read operations at 1.8 V V_CCand erase and program operations at 1.8 V or 12

V V_PP. With the 1.8 V V_PPoption, VCC and VPP can be tied together for a simple, ultra-low-

power design. In addition to voltage flexibility, the dedicated VPP input provides complete data

protection when V_PP≤ V_PPLK

A 128-bit protection register enhances the user’s ability to implement new security techniques and

data protection schemes. Unique flash device identification and fraud-, cloning-, or content-

protection schemes are possible via a combination of Intel-programmed and user-OTP data cells.

Zero-latency locking/unlocking on any memory block provides instant and complete protection for

critical system code and data. An additional block lock-down capability provides hardware

protection where software commands alone cannot change the block’s protection status.

The device’s CUI is the system processor’s link to internal flash memory operation. A valid

command sequence written to the CUI initiates device WSM operation that automatically executes

the algorithms, timings, and verifications necessary to manage flash memory program and erase.

An internal status register provides ready/busy indication results of the operation (success, fail,

etc.).

Three power-savings features, APS, standby, and RST#, can significantly reduce power

consumption. The device automatically enters APS mode following read cycle completion.

Standby mode begins when the system deselects the flash memory by deasserting CE#. Driving

RST# low produces power savings similar to standby mode. It also resets the part to read array

mode (important for system-level reset), clears internal status registers, and provides an additional

level of flash write protection.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

2.0

Product Description

2.1

Package and Ballouts

The 1.8 Volt Intel^®Wireless Flash memory is available in 56 active ball matrix µBGA* and VF

BGA Chip Scale Packages with 0.75 mm ball pitch that is ideal for board-constrained applications.

Figure 1, “56 Active Ball Matrix µBGA* and VF BGA Packages” on page 4 shows device ballout.

Figure 1. 56 Active Ball Matrix µBGA* and VF BGA Packages

A11

VSS

A20

A21

VCC

CLK

VPP

A18

A17

A19

A18

A17

A19

VPP

VCC

CLK

VSS

A20

A21

A11

A12

A13

A12

A13

RST#

WE#

RST#

WE#

A10

ADV#

A15

A14 WAIT

DQ15 DQ5

A16

DQ12

DQ2

WP#

DQ1

A22

CE#

WP#

DQ1

DQ12

DQ2

A16

WAIT A14

DQ5 DQ15

A15

VCCQ

DQ4

CE#

DQ4

VCCQ

VSS

DQ7

DQ14 DQ13

VSSQ DQ5

DQ11 DQ10

DQ9

DQ0

OE#

DQ0

DQ9

DQ10 DQ11

DQ13 DQ14

DQ5 VSSQ

VSS

DQ7

VCC

DQ3

VCCQ DQ8

VSSQ

DQ8 VCCQ

DQ3

VCC

Top View - Ball Side Down

Complete Ink Mark Not Shown

Bottom View - Ball Side Up

NOTES:

1. On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A[21]

and A[22] will be NC).

2. See Appendix C, “Mechanical Specifications” on page 76 for package mechanical specifications.

2.2

Signal Descriptions

Table 1, “Signal Descriptions” on page 5 describes ball usage.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 1. Signal Descriptions

Symbol

A[22:0]

Type

Name and Function

ADDRESS INPUTS: for memory addresses.

32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]

DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory,

status register, protection register, and configuration code reads. Data pins float when the chip or

outputs are deselected. Data is internally latched during writes.

DQ[15:0]

I/O

ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous

read operations, all addresses are latched on ADV#’s rising edge or CLK’s rising (or falling) edge,

whichever occurs first.

ADV#

CE#

CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#-

high deselects the device, places it in standby state, and places data and WAIT outputs at High-Z.

CLOCK: CLK synchronizes the device to the system bus frequency in synchronous-read configuration

and increments an internal burst address generator. During synchronous read operations, addresses

are latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.

CLK

OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle. With

OE#

OE# at V , device data outputs are placed in High-Z state.

RESET: When low, RST# resets internal automation and inhibits write operations. This provides data

protection during power transitions. RST#-high enables normal operation. Exit from reset places the

device in asynchronous read array mode.

RST#

WAIT: Indicates data valid in synchronous read modes. Configuration Register bit 10 (CR.10, WT)

WAIT

WE#

determines its polarity when set to ‘1’. With CE# at V , WAIT’s active output is V or V . WAIT is

IL OL OH

High-Z if CE# is V . WAIT is not gated by OE#.

WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the

WE# pulse’s rising edge.

WRITE PROTECT: Disables/enables the lock-down function.

When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot

be unlocked through software.

WP#

See Section 4.12, “Block Locking Commands” on page 27 for details on block locking.

ERASE AND PROGRAM POWER: A valid V voltage on this pin allows erase or programming.

Memory contents cannot be altered when V ≤ V

. Block erase and program at invalid V

PPLK

voltages should not be attempted.

Set V = V for in-system program and erase operations. To accommodate resistor or diode drops

VPP

VCC

Pwr/I

Pwr

from the system supply, V ’s V level can be as low as V

to perform in-system flash modification. VPP may be 0 V during read operations.

min. V must remain above V

min

PP1

can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.

VPP can be connected to 12 V for a cumulative total not to exceed 80 hours maximum. Extended use

of this pin at 12 V may reduce block cycling capability.

PP2

DEVICE POWER SUPPLY: Writes are inhibited at V ≤ V

voltages should not be attempted.

. Device operations at invalid V

LKO

OUTPUT POWER SUPPLY: Enables all outputs to be driven at V

VCC.

. This input may be tied directly to

CCQ

VCCQ

VSS

Pwr

GROUND: Pins for all internal device circuitry must be connected to system ground.

OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied

directly to VSS.

VSSQ

DON’T USE: Do not use this pin. This pin should not be connected to any power supplies, signals or

other pins and must be floated.

NO CONNECT: No internal connection; can be driven or floated.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

2.3

Memory Partitioning

The 1.8 Volt Intel^®Wireless Flash memory is divided into 4-Mbit physical partitions which allows

simultaneous RWW or RWE operations and allows users to segment code and data areas on 4-Mbit

boundaries. The device’s asymmetrically-blocked architecture enables system code and data

integration within a single flash device. Each block can be erased independently in block erase

mode. Simultaneous program and erase is not allowed. Only one partition at a time can be actively

programming or erasing. See Table 2, “Bottom Parameter Memory Map” on page 7 and Table 3,

“Top Parameter Memory Map” on page 8.

The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit

device has 32 partitions. Each device density contains one parameter partition and several main

partitions: the 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-

Kword main blocks; and each 4-Mbit main partition contains eight 32-Kword blocks each.

The bulk of the array is divided into main blocks that can store code or data, and parameter blocks

allow storage of frequently updated small parameters that would normally be stored in EEPROM.

By using software techniques, the word-rewrite functionality of EEPROMs can be emulated.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 2. Bottom Parameter Memory Map

Size

(KW)

Blk

32 Mbit

64 Mbit

128 Mbit

262

135

134

7F8000-7FFFFF

400000-407FFF

3F8000-3FFFFF

200000-207FFF

1F8000-1FFFFF

100000-107FFF

0F8000-0FFFFF

0C0000-0C7FFF

0B8000-0BFFFF

080000-087FFF

078000-07FFFF

040000-047FFF

038000-03FFFF

134

3F8000-3FFFFF

200000-207FFF

1F8000-1FFFFF

100000-107FFF

0F8000-0FFFFF

0C0000-0C7FFF

0B8000-0BFFFF

080000-087FFF

078000-07FFFF

040000-047FFF

038000-03FFFF

1F8000-1FFFFF

100000-107FFF

0F8000-0FFFFF

0C0000-0C7FFF

0B8000-0BFFFF

080000-087FFF

078000-07FFFF

040000-047FFF

038000-03FFFF

008000-00FFFF

007000-007FFF

008000-00FFFF

007000-007FFF

008000-00FFFF

007000-007FFF

000000-000FFF

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 3. Top Parameter Memory Map

Size

(KW)

Blk

32 Mbit

64 Mbit

128 Mbit

1FF000-1FFFFF

134

3FF000-3FFFFF

262

7FF000-7FFFFF

1F8000-1F8FFF

1F0000-1F7FFF

127

126

3F8000-3F8FFF

3F0000-3F7FFF

255

254

7F8000-7F8FFF

7F0000-7F7FFF

1C0000-1C7FFF

1B8000-1BFFFF

18000-187FFF

178000-17FFFF

140000-147FFF

138000-13FFFF

100000-107FFF

0F8000-0FFFFF

000000-007FFF

120

119

112

111

104

103

3C0000-3C7FFF

3B8000-3BFFFF

380000-387FFF

378000-37FFFF

340000-347FFF

338000-33FFFF

300000-307FFF

2F8000-2FFFFF

200000-207FFF

1F8000-1FFFFF

000000-007FFF

248

247

240

239

232

231

224

223

192

191

128

127

7C0000-7C7FFF

7B8000-7BFFFF

780000-787FFF

778000-77FFFF

740000-747FFF

738000-73FFFF

700000-707FFF

6F8000-6FFFFF

600000-607FFF

5F8000-5FFFFF

400000-407FFF

3F8000-3FFFFF

000000-007FFF

3.0

Principles of Operation

The 1.8 Volt Intel^®Wireless Flash memory family includes an on-chip WSM to manage block

erase and program algorithms. Its CUI allows minimal processor overhead with RAM-like

interface timings.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

3.1

Bus Operations

Table 4. Bus Operations

Mode

Note

RST#

CE#

OE#

WE#

ADV#

WAIT

DQ[15:0]

Read (Array, Status,

Configuration, Identifier, or

Query)

Valid only in

Synchronous

Mode

1,2

OUT

Output Disable

Standby

Reset

High-Z

3,4

Write

NOTES:

1. Manufacturer and device codes are accessed in read identifier mode (A[MAX:1]=0).

2. Query accesses use only DQ[7:0]. All other accesses use DQ[15:0].

3. X must be V or V for control pins and addresses.

4. RST# must be at V ± 0.2 V to meet the maximum specified power-down current.

5. Refer to the Table 6, “Bus Cycle Definitions” on page 13 for valid D during a write operation.

3.1.1

Read

The 1.8 Volt Intel Wireless Flash memory has several read configurations:

• Asynchronous page mode read.

• Synchronous burst mode read.

— outputs four, eight, or continuous words, from main blocks and parameter blocks.

The device’s partitions have several available read modes:

• Read array mode: read accesses return flash array data from the addressed locations.

• Read identifier mode: reads return manufacturer and device identifier data, block lock status,

and protection register data. The identification plane occupies the 4-Mbit partition address

locations corresponding to the command’s address; the flash array is not accessible in read

identifier mode.

• Read query mode: reads return device CFI data. The query plane occupies the

4-Mbit partition address locations corresponding to the command’s address; the flash array is

not accessible in read query mode.

• Read status register mode: reads return status register data from the addressed partition. That

partition’s array data is not accessible. A system processor can check the status register to

determine an addressed partition’s state or monitor program and erase progress.

All partitions support synchronous burst mode that internally sequences addresses with respect to

the input CLK to select and supply data to the outputs.

Identifier codes, query data, and status register read operations execute as single-synchronous or

asynchronous read cycles. WAIT is inactive during these reads.

Access to the modes listed above is independent of V_PP. An appropriate CUI command places the

device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read

array mode.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Asserting CE# enables device read operations. The device internally decodes upper address inputs

to determine which partition is accessed. ADV#-active opens the internal address latches.

Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous

mode, the address is latched when ADV# is deasserted (when the device is configured to use

ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the

rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST#

must be at deasserted during read operations.

3.1.2

3.1.3

Standby

CE# inactive deselects the device and places it in standby mode, substantially reducing device

power consumption. In standby mode, outputs are placed in a high-impedance state independent of

OE#. If deselected during a program or erase algorithm, the device will consume active power until

the program or erase operation completes.

Write

A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control commands

are written to the CUI using standard microprocessor write timings. The address and data are

latched on the rising edge of WE#. Write operations are asynchronous; CLK is ignored.

The CUI does not occupy an addressable memory location within any partition. The system

processor must access it at the correct address range depending on the kind of command executed.

Programming or erasing may occur in only one partition at a time. Other partitions must be in one

of the read modes or erase suspend mode.

Table 5, “Command Codes and Descriptions” on page 12 shows the available commands.

Appendix A, “Write State Machine States” on page 65 provides information on moving between

different operating modes using CUI commands.

3.1.4

Reset

The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned

off and outputs are placed in a high-impedance state.

After returning from reset, a time t_PHQVis required until outputs are valid, and a delay (t_PHWV) is

required before a write sequence can be initiated. After this wake-up interval, normal operation is

restored. The device defaults to read array mode, the status register is set to 80h, and the

configuration register defaults to asynchronous page-mode reads.

If RST# is asserted during an erase or program operation, the operation will be aborted and the

memory contents at the aborted block or address are invalid. See Figure 29, “Reset Operations

Waveforms” on page 64 for detailed information regarding reset timings.

Like any automated device, it is important to assert RST# during system reset. When the system

comes out of reset, the processor expects to read from the flash memory array. Automated flash

memories provide status information when read during program or erase operations. If a CPU reset

occurs with no flash memory reset, proper CPU initialization may not occur because the flash

memory may be providing status information instead of array data. 1.8 Volt Intel^®Flash memories

allow proper CPU initialization following a system reset through the use of the RST# input. In this

application, RST# is controlled by the same CPU reset signal, RESET#.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.0

Command Definitions

The device’s on-chip WSM manages erase and program algorithms. The local CPU controls the

device’s in-system read, program, and erase operations. Bus cycles to or from the flash memory

conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV# control signals

dictate data flow into and out of the device. WAIT informs the CPU of valid data during burst

reads. Table 4, “Bus Operations” on page 9 summarizes bus operations.

Device operations are selected by writing specific commands into the device’s CUI. Table 5,

“Command Codes and Descriptions” on page 12 lists all possible command codes and

descriptions, Table 6, “Bus Cycle Definitions” on page 13 lists command definitions. Since

commands are partition-specific, it is important to issue write commands within the target address

range.

Multi-cycle command writes to a flash memory partition must be issued sequentially without

intervening command writes. For example, an Erase Setup command to partition X must be

immediately followed by the Erase Confirm command in order to be executed properly. The

address given during the Erase Confirm command determines the location of the erase. If the Erase

Confirm command is given to partition X, then the command will be executed and a block in

partition X will be erased. Alternatively, if the Erase Confirm command is given to partition Y, the

command will still be executed and a block in partition Y will be erased. Any other command

given to any partition prior to the Erase Confirm command will result in a command sequence

error, which is posted in the status register. After the erase is successfully started in partition X or

Y, read cycles may occur in any other partition Z (e.g., code or data reads).

4.1

Read-While-Write and Read-While-Erase

The 1.8 Volt Intel^®Wireless Flash memory supports flexible multi-partition dual-operation

architecture. By dividing the flash memory into many separate partitions, the device is capable of

reading from one partition while programing or erasing in another partition; hence the terms, RWW

and RWE. Both of these features greatly enhance data storage performance.

The product does not support simultaneous program and erase operations. Attempting to perform

operations such as these will result in a command sequence error. Only one partition may be

programming or erasing while another partition is reading. However, one partition may be in erase

suspend mode while a second partition is performing a program operation, and yet another partition

may be executing a Read Array command.

Table 5. Command Codes and Descriptions

Code

Device Command

Description

FFh Read Array

Places selected partition in read array mode.

Places selected partition in status register read mode. The partition enters this mode after a

Program or Erase command is issued to it.

70h Read Status Register

Puts the selected partition in read identifier mode. Device reads from partition addresses

output manufacturer/device codes, configuration register data, block lock status, or

protection register data on DQ[15:0].

90h Read Identifier

98h Read Query

Puts the addressed partition in read query mode. Device reads from the partition addresses

output CFI information on DQ[7:0].

The WSM can set the status register’s block lock (SR.1), V (SR.3), program (SR.4), and

50h Clear Status Register erase (SR.5) status bits, but it cannot clear them. SR.1,3,4,5 can only be cleared by a device

reset or through the Clear Status Register command.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 5. Command Codes and Descriptions

Code

Device Command

Description

This preferred program command’s first cycle prepares the CUI for a program operation. The

second cycle latches address and data and executes the WSM Program algorithm at this

location. Status register updates occur when CE# or OE# is toggled. A Read Array command

is required to read array data after programming.

Word Program

Setup

40h

10h Alternate Setup

30h EFP Setup

Equivalent to a Program Setup command (40h).

This program command activates EFP mode. The first write cycle sets up the command. If

the second cycle is an EFP Confirm command (D0h), subsequent writes provide program

data. All other commands are ignored once EFP mode begins.

If the first command was EFP Setup (30h), the CUI latches the address and data and

prepares the device for EFP mode.

D0h EFP Confirm

20h Erase Setup

Prepares the CUI for Block Erase. The device erases the block addressed by the Erase

Confirm command. If the next command is not Erase Confirm, the CUI:

(a) sets status register bits SR.4 and SR.5,

(b) places the partition in the read status register mode, and

If the first command was Erase Setup (20h), the CUI latches address and data and erases

the block indicated by the erase confirm cycle address. During program or erase, the

partition responds only to Read Status Register, Program Suspend, and Erase Suspend

commands. CE# or OE# toggle updates status register data.

D0h Erase Confirm

This command issued at any device address suspends the currently executing program or

erase operation. The status register, invoked by a Read Status Register command, indicates

successful operation suspension by setting status bits SR.2 (program suspend) or SR.6

(erase suspend) and SR.7. The WSM remains in the suspend mode regardless of control

Program Suspend or

Erase Suspend

B0h

signal states, except RST# = V .

This command issued at any device address resumes suspended program or erase

operation.

D0h Suspend Resume

Prepares the CUI lock configuration. If the next command is not Block-Lock, Unlock, or Lock-

Down, the CUI sets SR.4 and SR.5 to indicate command sequence error.

60h Lock Setup

01h Lock Block

D0h Unlock Block

If the previous command was Lock Setup (60h), the CUI locks the addressed block.

If the previous command was Lock Setup (60h) command, the CUI latches the address and

unlocks the addressed block. If previously locked-down, the operation has no effect.

If the previous command was Lock Setup (60h) command, the CUI latches the address and

locks-down the addressed block.

2Fh Lock-Down

Prepares the CUI for a protection register program operation. The second cycle latches

address and data and starts the WSM’s protection register program or lock algorithm.

Toggling CE# or OE# updates the flash status register data. To read array data after

programming, issue a Read Array command.

Protection Program

Setup

C0h

Prepares the CUI for device configuration. If Set Configuration Register is not the next

command, the CUI sets SR.4 and SR.5 to indicate command sequence error.

60h Configuration Setup

If the previous command was Configuration Setup (60h), the CUI latches the address and

writes A[15:0] data into the configuration register. Following a Set Configuration Register

command, subsequent read operations access array data.

Set Configuration

03h

NOTE: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 6. Bus Cycle Definitions

First Bus Cycle

Second Bus Cycle

Bus

Mode

Command

Cycles

Oper

Addr⁽¹⁾

Data^(2,3)

Oper

Addr⁽¹⁾

Data^(2,3)

Read Array/Reset

≥ 2

Write

PnA

FFh

90h

Read Identifier

Read

PBA+IA

PBA+QA

Read Query

98h

Read Status Register

Clear Status Register

Block Erase

70h

SRD

50h

20h

Write

D0h

Word Program

40h/10h

30h

EFP

Program/Erase Suspend

Program/Erase Resume

Lock Block

B0h

D0h

60h

Write

01h

D0h

2Fh

Unlock Block

60h

Lock-Down Block

Protection Program

60h

C0h

Lock Protection Program

Write

LPA

C0h

Write

LPA

FFFDh

Set Configuration Register

Write

60h

Write

03h

NOTES:

1. First cycle command addresses should be the same as the operation’s target address. Examples: the first-

cycle address for the Read Identifier command should be the same as the Identification code address (IA);

the first cycle address for the Word Program command should be the same as the word address (WA) to be

programmed; the first cycle address for the Erase/Program Suspend command should be the same as the

address within the block to be suspended; etc.

XX = Any valid address within the device.

IA = Identification code address.

BA = Block Address. Any address within a specific block.

LPA = Lock Protection Address is obtained from the CFI (via the Read Query command). The 1.8 Volt Intel

Wireless Flash memory family’s LPA is at 0080h.

PA = User programmable 4-word protection address in the device identification plane.

PnA = Any address within a specific partition.

PBA = Partition Base Address. The very first address of a particular partition.

QA = Query code address.

WA = Word address of memory location to be written.

2. SRD = Data read from the status register.

WD = Data to be written at location WA.

IC = Identifier code data.

PD = User programmable 4-word protection data.

QD = Query code data on DQ[7:0].

CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can

select any partition. See Table 12, “Configuration Register Definitions” on page 34 for configuration register

bits descriptions.

3. Commands other than those shown above are reserved by Intel for future device implementations and

should not be used.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.2

Read Array Command

The Read Array command places (or resets) the partition in read array mode. Upon initial device

power-up or after reset (RST# transitions from V_ILto V_IH), all partitions default to read array mode

and to asynchronous page mode read configuration. A Read Array command written to a partition

that is performing an erase or program operation will present invalid data until the operation

completes; it will then display array data when read. If an Erase- or Program-Suspend command

suspends the WSM, a subsequent Read Array command will place the addressed partition in read

array mode. The Read Array command functions independently of V_PP.

4.3

Read Identifier Command

The read identifier mode outputs the manufacturer/device identifier, block lock status, protection

address range supplied by the Read Identifier command (90h) address. Reads from addresses in

Table 7 retrieve ID information. Issuing a Read Identifier command to a partition that is

programming or erasing places that partition’s outputs in read ID mode while the partition

continues to program or erase in the background.

Table 7. Device Identification Codes

Address⁽¹⁾

Item

Data

Description

Base

Offset

Manufacturer ID

Partition

00h

0089h

8862h

32-Mbit TPD

8863h

32-Mbit BPD

8864h

64-Mbit TPD

Device ID

01h

8865h

64-Mbit BPD

8866h

128-Mbit TPD

8867h

128-Mbit BPD

DQ[0] = 0

DQ[0] = 1

DQ[1] = 0

DQ[1] = 1

Lock Data

Block is unlocked

Block is locked

Block is not locked-down

Block is locked down

Block Lock Status⁽²⁾

Block

02h

Block Lock-Down Status⁽²⁾

Configuration Register

Partition

05h

80h

Protection Register Lock Status

Multiple reads required to read

Protection Register

Partition

81h - 88h

NOTES:

1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status

for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e. 0F8002h.

Then examine bit 0 of the data to determine if the block is locked.

2. See Section 4.12.4, “Block Lock Status” on page 29 for valid lock status.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.4

4.5

Read Query Command

The query plane comes to the foreground and occupies a 4-Mbit address range at the partition

supplied by the Read Query command address. The mode outputs CFI data when partition

addresses are read. Appendix B, “Common Flash Interface” on page 68 shows query mode

information and addresses. Issuing a Read Query command to a partition that is programming or

erasing places that partition’s outputs in read query mode while the partition continues to program

or erase in the background.

Read Status Register Command

The device’s status register displays program and erase operation status. A partition’s status can be

read after writing the Read Status Register command to the partition’s address range. The status

Subsequent single reads from that partition will return its status until another valid command is

written.

The read status mode supports single synchronous and single asynchronous reads only; it doesn’t

support page mode or burst reads. The first OE# or CE# falling edge latches and updates status

data while DQ[15:8] outputs 00h. See Table 8, “Status Register Definitions” on page 16.

The status register occupies the 4-Mbit partition to which the Read Status, Program, or Erase

command was issued. Status register bit SR.7 is the DWS (Device WSM Status) bit and provides

program and erase status of the device. The PWS (Partition Write/Erase Status) bit tells whether the

addressed partition or some other partition is actively programming or erasing. Status register bits

SR.6-1 present information about the WSM’s program, erase, suspend, V_PP, and block-lock status.

Table 9, “Status Register DWS and PWS Description” on page 16 presents descriptions of DWS

(SR.7) and PWS (SR.0) combinations.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 8. Status Register Definitions

DWS

ESS

VPPS

PSS

DPS

PWS

Bit

Name

DWS

State

0 = Device WSM is Busy

Description

SR.7 indicates erase or program completion in the

device. SR.1–6 are invalid while SR.7 = 0. See Table 9

for valid SR.7 and SR.0 combinations.

Device WSM Status 1 = Device WSM is Ready

After issuing an Erase Suspend command, the WSM

halts and sets SR.7 and SR.6. SR.6 remains set until

the device receives an Erase Resume command.

ESS

0 = Erase in progress/completed

Erase Suspend Status 1 = Erase suspended

SR.5 is set if an attempted erase failed.

A Command Sequence Error is indicated when SR.4,

SR.5 and SR.7 are set.

0 = Erase successful

1 = Erase error

Erase Status

0 = Program successful

1 = Program error

SR.4 is set if the WSM failed to program a word.

Program Status

The WSM indicates the V level after program or erase

VPPS

0 = V OK

completes. SR.3 does not provide continuous V

VPP Status

1 = V low detect, operation aborted

feedback and isn’t guaranteed when V ≠ V

PP1/2

PSS

After receiving a Program Suspend command, the

WSM halts execution and sets SR.7 & SR.2. They

remain set until a Resume command is received.

0 = Program in progress/completed

1 = Program suspended

Program Suspend

Status

0 = Unlocked

If an erase or program operation is attempted to a

DPS

locked block (if WP# = V ), the WSM sets SR.1 and

1 = Aborted erase/program attempt on

locked block

Device Protect Status

aborts the operation.

Addressed partition or another partition is erasing or

programming. In EFP mode, SR.0 indicates that a data-

stream word has finished programming or verifying

depending on the particular EFP phase. See Table 9 for

valid SR.7 and SR.0 combinations.

0 = Depending on SR.7’s state, the

addressed partition is busy or no

other partition is busy.

PWS

Partition Write Status

1 = Another partition is busy

Table 9. Status Register DWS and PWS Description

DWS

(SR.7)

PWS

(SR.0)

Description

The addressed partition is performing a program/erase operation.

EFP: device is finished programming or verifying data or is ready for data.

A partition other than the one currently addressed is performing a program/erase operation.

EFP: the device is either programming or verifying data.

No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR.6 and

SR.2) indicate whether other partitions are suspended.

EFP: the device has exited EFP mode.

Won’t occur in standard program or erase modes.

EFP: this combination will not occur.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.6

4.7

Clear Status Register Command

The Clear Status Register command clears the status register and leaves all partition output states

unchanged. The command functions independently of the applied V_PPvoltage. The WSM can set

all status register bits and clear bits 0, 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate various error

conditions, they can only be cleared by the Clear Status Register command. By allowing system

software to reset these bits, several operations (such as cumulatively programming several

addresses or erasing multiple blocks in sequence), may be performed before reading the status

another command or sequence. Device reset (RST# = V_IL) also clears the status register.

Word Program Command

Writing a Word Program command to the device initiates internally timed sequences that program

the requested word.

Programming can occur in only one partition at a time. Other partitions must be in one of the read

modes or in erase suspend mode. Note that only one partition at a time can be in erase suspend

mode.

The WSM executes a sequence of internally timed events to program desired bits at the addressed

location and verify that the bits are sufficiently programmed. Programming the memory changes

specifically addressed bits to ‘0.’ ‘1’ bits do not change the memory cell contents.

The status register can be examined for program progress and errors by reading any address within

the partition that’s programming. Issuing a Read Status Register command to other partitions

brings the status register to the foreground in those partitions, allowing program progress to be

monitored or detected at other device addresses. Status register bit SR.7 indicates device program

status while the program sequence executes. CE# or OE# toggle (during polling) updates the status

Read Status Register, Program Suspend, Read Identifier, Read Query, and Read Array (which

returns unknown data).

When programming completes, SR.4=1 indicates program failure. If SR.3 is set, the WSM couldn’t

execute the Word Program command because V_PPwas outside acceptable limits. If SR.1 is set, the

program operation targeted a locked block and was aborted.

After examining the status register, it should be cleared by the Clear Status Register command

before issuing a new command. The partition remains in status register mode until another

command is written to that partition. Any command can follow once program completes.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 2. Word Program Flowchart

WORD PROGRAM PROCEDURE

Bus

Start

Command

Operation

Comments

Program Data = 40h

Write

Read

Setup

Data

Addr = Location to program (WA)

Write 40h,

Word Address

Data = Data to program (WD)

Addr = Location to program (WA)

Write Data

Word Address

Read SRD

Toggle CE# or OE# to update SRD

Suspend

Program

Loop

Read Status

Check SR.7

1 = WSM ready

0 = WSM busy

Standby

Yes

Suspend

Program

SR.7 =

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of program operations.

Full Program

Status Check

(if desired)

Program

Complete

FULL PROGRAM STATUS CHECK PROCEDURE

Read Status

Bus

Command

Operation

Comments

Check SR.3

1 = V_PPerror

Standby

V_PPRange

Error

SR.3 =

Check SR.4

1 = Data program error

Check SR.1

Program

Error

SR.4 =

Standby

1 = Attempted program to locked block

Program aborted

SR.3 MUST be cleared before the WSM will allow further

program attempts

Device

Protect Error

SR.1 =

Only the Clear Staus Register command clears SR.1, 3, 4.

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Program

Successful

4.8

Block Erase Command

The two-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm

(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode

at a time; other partitions must be in a read mode. The Erase Confirm command internally latches

the address of the block to be erased. Erase forces all bits within the block to ‘1’. SR.7 is cleared

while the erase executes.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

After writing the Erase Confirm command, the selected partition is placed in read status register

mode and reads performed to that partition will return current status data. The CPU can detect

block erase completion by analyzing SR.7 of that partition. SR.5=1 indicates an erase failure,

SR.3=1 indicates an invalid V_PPsupply voltage, and SR.1=1 indicates an erase operation was

attempted on a locked block.

If an error bit was flagged, the status register can be cleared by issuing the Clear Status Register

command before attempting the next operation. The partition will remain in read status register

mode until another command is written to its CUI. Any CUI instruction can follow once erasing

completes. The CUI can be set to read array mode to prevent inadvertent status register reads.

Figure 3. Block Erase Flowchart

BLOCK ERASE PROCEDURE

Bus

Start

Command

Operation

Comments

Block

Erase

Setup

Data = 20h

Addr = Block to be erased (BA)

Write

Read

Write 20h

Block Address

Erase

Data = D0h

Confirm Addr = Block to be erased (BA)

Write D0h and

Block Address

Read SRD

Toggle CE# or OE# to update SRD

Suspend

Erase

Loop

Read Status

Check SR.7

1 = WSM ready

0 = WSM busy

Standby

Suspend

Erase

Yes

SR.7 =

Repeat for subsequent block erasures.

Full status register check can be done after each block erase

or after a sequence of block erasures.

Full Erase

Status Check

(if desired)

Block Erase

Complete

FULL ERASE STATUS CHECK PROCEDURE

Read Status

Bus

Command

Operation

Comments

Check SR.3

1 = V_PPerror

Standby

V_PPRange

Error

SR.3 =

Check SR.4,5

Both 1 = Command sequence error

Command

Sequence Error

Check SR.5

1 = Block erase error

SR.4,5 =

Check SR.1

Standby

1 = Attempted erase of locked block

Erase aborted

Block Erase

Error

SR.5 =

SR. 1 and 3 must be cleared before the WSM will allow further

erase attempts.

Erase of

Locked Block

Aborted

SR.1 =

Only the Clear Status Register command clears SR.1, 3, 4, 5.

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

Block Erase

Successful

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.9

Program Suspend, Program Resume

Erase Suspend, Erase Resume Commands

The Program Suspend and Erase Suspend commands halt an in-progress program or erase

operation. The command can be issued at any device address. The partition corresponding to the

command’s address remains in its previous state. The Suspend command allows data to be

accessed from memory locations other than the one being programmed or the block being erased.

A program operation can be suspended to perform reads only. An erase operation can be suspended

to perform either a program or a read operation within any block, except the block that is erase

suspended. A Program command nested within a suspended erase can subsequently be suspended

to read yet another location. Once a program/erase process starts, the Suspend command requests

that the WSM suspend the program/erase sequence at predetermined points in the algorithm. The

partition that is actually suspended continues to output status register data after the Suspend

command is written. An operation is suspended when status bits SR.7 and SR.6 and/or SR.2

display ‘1’. t_WHRH1/t_EHRH1specifies suspend latency.

To read data from blocks within the partition (other than an erase-suspended block), a Read Array

command can be written. During Erase Suspend, a Program command can be issued to a block

other than the erase-suspended block. Block erase cannot resume until program operations initiated

during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read

Query, and Program Resume are valid commands during Program or Erase Suspend. Additionally,

Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and

Lock-Down Block are valid commands during erase suspend.

To read data from a block in a partition that is not programming/erasing, the operation does not

need to be suspended. If the other partition is already in read array, ID, or Query mode, issuing a

valid address will return corresponding data. If the other partition is not in a read mode, one of the

read commands must be issued to the partition before data can be read.

During a suspend, CE# = V_IHplaces the device in standby state, which reduces active current. V_PP

must remain at its program level and WP# must remain unchanged while in suspend mode.

A Resume command instructs the WSM to continue programming or erasing and clears status

read at the partition that is programming or erasing, the device outputs data corresponding to the

partition’s last mode. If status register error bits are set, the status register can be cleared before

issuing the next instruction. RST# must remain at V_IH. See Figure 4, “Program Suspend/Resume

Flowchart” on page 21 and Figure 5, “Erase Suspend/Resume Flowchart” on page 22.

If a suspended partition was placed in read array, read status register, read identifier (ID), or read

query mode during the suspend, the device remains in that mode and outputs data corresponding to

that mode after the program or erase operation is resumed. After resuming a suspend operation,

issue the read command appropriate to the read operation. To read status after resuming a

suspended operation, issue a Read Status Register command (70h) to return the suspended partition

to status mode.

A minimum t_WHWHtime should elapse between an Erase command and a subsequent Erase

Suspend command to ensure that the device achieves sufficient cumulative erase time. Occasional

Erase-to-Suspend interrupts do not cause problems, but Erase-to-Suspend commands issued too

frequently may produce undetermined results.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 4. Program Suspend/Resume Flowchart

PROGRAM SUSPEND / RESUME PROCEDURE

Bus

Operation

Start

Command

Comments

Data = B0h

Addr = Any address within programming

partition

Program

Suspend

Write

Write B0h

Any Address

Read

Data = 70h

Status Addr = Any address in same partition

Write 70h

Same Partition

Read SRD

Read

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Read Status

Check SR.7

Standby

1 = WSM ready

0 = WSM busy

SR.7 =

Check SR.2

1 = Program suspended

0 = Program completed

Program

Completed

SR.2 =

Data = FFh

Addr = Any device address (except word

being programmed)

Read

Array

Write

Read

Write

Write FFh

Susp Partition

Read array data from block other than

the one being programmed

Read Array

Data

Program Data = D0h

Resume Addr = any device address

If the suspended partition was placed in Read Array mode:

Done

Reading

Return partition to status mode:

Read

Write

Data = 70h

Yes

Status

Addr = address within same partition

Write D0h

Write FFh

Any Address

Pgm’d Partition

Program

Resumed

Read Array

Data

Write 70h

Same Partition

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 5. Erase Suspend/Resume Flowchart

ERASE SUSPEND / RESUME PROCEDURE

Bus

Operation

Start

Command

Comments

Erase

Data = B0h

Write

Suspend Addr = Any address

Write B0h

Any Address

Read Data = 70h

Status Addr = Any address in same partition

Write 70h

Same Partition

Read SRD

Read

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Read Status

Check SR.7

Standby

1 = WSM ready

0 = WSM busy

SR.7 =

Check SR.6

1 = Erase suspended

0 = Erase completed

Standby

Write

Erase

Completed

SR.6 =

Data = FFh or 40h

Read Array

Addr = Any device address (except

or Program

block being erased)

Read or

Write

Read array or program data from/to

block other than the one being erased

Read

Program

Read or

Program?

Read Array

Data

Program

Loop

Erase

Data = D0h

Write

Resume Addr = Any address

If the suspended partition was placed in

Read Array mode or a Program Loop:

Done?

Yes

Return partition to status mode:

Data = 70h

Status

Read

Write

Write D0h

Any Address

Write FFh

Erased Partition

Addr = Address within same partition

Read Array

Data

Erase Resumed

Write 70h

Same Partition

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.10

Enhanced Factory Program Command (EFP)

EFP substantially improves device programming performance via a number of enhancements to

the conventional 12-volt word program algorithm. EFP’s more efficient WSM algorithm eliminates

the traditional overhead delays of conventional word program mode in both the host programming

system and the flash device. Changes to the conventional word programming flowchart and

internal WSM routine were developed because of today’s beat-rate-sensitive manufacturing

environments; a balance between programming speed and cycling performance was struck.

After a single command sequence, host programmer bus cycles write data words followed by status

checks to determine when the next data word is ready to be accepted. This modification essentially

cuts write bus cycles in half. Following each internal program pulse, the WSM increments the

device’s address to the next physical location. Now, programming equipment can sequentially

stream program data throughout an entire block without having to setup and present each new

address. In combination, these enhancements reduce much of the host programmer overhead,

enabling more of a data streaming approach to device programming.

Additionally, EFP speeds up programming by performing internal code verification. With this,

PROM programmers can rely on the device to verify that it’s been programmed properly. From the

device side, EFP streamlines internal overhead by eliminating the delays previously associated to

switch voltages between programming and verify levels at each memory-word location.

EFP consists of four phases: setup, program, verify and exit. Refer to Figure 6, “Enhanced Factory

Program Flowchart” on page 26 for a detailed graphical representation on how to implement EFP.

4.10.1

EFP Requirements and Considerations

EFP requirements:

• Ambient temperature: T_A= 25 °C ±5 °C

• V_CCwithin specified operating range

• V_PPwithin specified V_PP2range

• Target block unlocked

EFP considerations:

• Block cycling below 10 erase cycles ⁽¹⁾

• RWW not supported⁽²⁾

• EFP programs one block at a time

• EFP cannot be suspended

1. Recommended for optimum performance. Some degradation in performance may occur if this limit is

exceeded, but the internal algorithm will continue to work properly.

2. Code or data cannot be read from another partition during EFP.

See Figure 6, “Enhanced Factory Program Flowchart” on page 26 for a detailed flowchart on how

to implement an EFP operation.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.10.2

Setup Phase

After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR.7 transitions

from a ’1’to a ’0’indicating that the WSM is busy with EFP algorithm startup. A delay before

checking SR.7 is required to allow the WSM time to perform all of its setups and checks (V_PPlevel

and block lock status). If an error is detected, status register bits SR.4, SR.3 and/or SR.1 are set and

EFP operation terminates.

NOTE: After the EFP Setup and Confirm command sequence, reads from the device automatically

output status register data. Do not issue the Read Status Register command; it will be interpreted as

data to program at WA0.

4.10.3

Program Phase

After setup completion, the host programming system must check SR.0 to determine "data-stream

ready" status (SR.0=0). Each subsequent write after this is a program-data write to the flash array.

Each cell within the memory word to be programmed to ‘0’ will receive one WSM pulse;

additional pulses, if required, occur in the verify phase. SR.0=1 indicates that the WSM is busy

applying the program pulse.

The host programmer must poll the device's status register for the "program done" state after each

data-stream write. SR.0=0 indicates that the appropriate cell(s) within the accessed memory

location have received their single WSM program pulse, and that the device is now ready for the

next word. Although the host may check full status for errors at any time, it is only necessary on a

block basis, after EFP exit.

Addresses must remain within the target block. Supplying an address outside the target block

immediately terminates the program phase; the WSM then enters the EFP verify phase.

The address can either hold constant or it can increment. The device compares the incoming

address to that stored from the setup phase (WA₀); if they match, the WSM programs the new data

word at the next sequential memory location. If they differ, the WSM jumps to the new address

location.

The program phase concludes when the host programming system writes to a different block

address, data supplied must be FFFFh. Upon program phase completion, the device enters the EFP

verify phase.

4.10.4

Verify Phase

A high percentage of the flash bits program on the first WSM pulse. However, for those cells that

do not completely program on their first attempt, EFP internal verification identifies them and

applies additional pulses as required.

The verify phase is identical in flow to that of the program phase, except that instead of

programming incoming data, the WSM compares the verify-stream data to that which was

previously programmed into the block. If the data compares correctly, the host programmer

proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s).

The host programmer must reset its initial verify-word address to the same starting location

supplied during the program phase. It then reissues each data word in the same order it did during

the program phase. Like programming, the host may write each subsequent data word to WA₀or it

may increment up through the block addresses.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

The verification phase concludes when the interfacing programmer writes to a different block

address; data supplied must be FFFFh. Upon verify phase completion, the device enters the EFP

exit phase.

4.10.5

Exit Phase

SR.7=1 indicates that the device has returned to normal operating conditions. A full status check

should be performed at this time to ensure the entire block programmed successfully. After EFP

exit, any valid CUI command can be issued.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 6. Enhanced Factory Program Flowchart

ENHANCED FACTORY PROGRAMMING PROCEDURE

EFP Setup

EFP Program

EFP Verify

EFP Exit

Read

Status Register

Read

Status Register

Read

Status Register

Start

V_PP= 12V

Unlock Block

SR.0=1=N

SR.7=0=N

Data Stream

Ready?

Verify Stream

Ready?

EFP

Exited?

SR.0 = 0 = Y

SR.7 = 1 = Y

Write 30h

Address = WA₀

Write Data

Address = WA₀

Write Data

Address = WA₀

Full Status Check

Procedure

Write D0h

Address = WA₀

Read

Status Register

Read

Status Register

Operation

Complete

EFP setup time

Program

Done?

Verify

Done?

Read

Status Register

SR.0 = 0 = Y

Last

Data?

Last

Data?

EFP Setup

Done?

SR.7 = 1 = N

Check V_PP& Lock

errors (SR.3, SR.1)

Write FFFFh

Address ≠ BBA

Address

≠

BBA

Exit

EFP Setup

EFP Program

EFP Verify

Bus

State

Bus

State

Bus

State

Comments

Read

Status Register

Check SR.0

Read

Status Register

Verify Check SR.0

Unlock V_PP= 12V

Block Unlock block

Write

Data

Standby Stream 0 = Ready for data

Ready? 1 = Not ready for data

Standby Stream 0 = Ready for verify

Ready? 1 = Not ready for verify

EFP Data = 30h

Setup Address = WA₀

EFP Data = D0h

Confirm Address = WA₀

Write

(note 1)

Data = Data to program

Address = WA₀

Write

(note 2)

Data = Word to verify

Address = WA₀

Read

Status Register

Read

Status Register

Standby

Read

EFP setup time

Status Register

Check SR.0

0 = Program done

1 = Program not done

Check SR.0

0 = Verify done

1 = Verify not done

Program

Done?

Standby Verify

(note 3) Done?

Standby

EFP

Check SR.7

Standby Setup 0 = EFP ready

Done? 1 = EFP not ready

Last

Device automatically

Last

Device automatically

Standby

Data? increments address.

If SR.7 = 1:

Error

Exit Data = FFFFh

Write Program Address not within same

Phase BBA

Exit Data = FFFFh

Verify Address not within same

Phase BBA

Check SR.3, SR.1

Standby Condition

SR.3 = 1 = V_PPerror

Check

Write

SR.1 = 1 = locked block

EFP Exit

1. WA₀= first Word Address to be programmed within the target block. The BBA (Block Base

Address) must remain constant throughout the program phase data stream; WA can be held

constant at the first address location, or it can be written to sequence up through the addresses

within the block. Writing to a BBA not equal to that of the block currently being written to

terminates the EFP program phase, and instructs the device to enter the EFP verify phase.

2. For proper verification to occur, the verify data stream must be presented to the device in the

same sequence as that of the program phase data stream. Writing to a BBA not equal to WA

terminates the EFP verify phase, and instructs the device to exit EFP .

3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive

additional program-pulse attempts during the EFP verify phase. The device will report any

program failure by setting SR.4=1; this check can be performed during the full status check after

EFP has been exited for that block, and will indicate any error within the entire data stream.

Read

Status Register

Check SR.7

EFP

Standby

0 = Exit not finished

Exited?

1 = Exit completed

Repeat for subsequent operations.

After EFP exit, a Full Status Check can

determine if any program error occurred.

See the Full Status Check procedure in the

Word Program flowchart.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.11

4.12

Security Modes

The 1.8 Volt Intel^®Wireless Flash memory offers both hardware and software security features to

protect the flash data. The software security feature is used by executing the Lock Block command.

The hardware security feature is used by executing the Lock-Down Block command and by

asserting the WP# signal.

Refer to Figure 7, “Block Locking State Diagram” on page 28 for a state diagram of the flash

security features. Also see Figure 8, “Locking Operations Flowchart” on page 30.

Block Locking Commands

Individual instant block locking protects code and data by allowing any block to be locked or

unlocked with no latency. This locking scheme offers two levels of protection. The first allows

software-only control of block locking (useful for frequently changed data blocks), while the

second requires hardware interaction before locking can be changed (protects infrequently changed

code blocks).

The following sections discuss the locking system operation. The term “state [XYZ]” specifies

locking states; e.g., “state [001],” where X = WP# value, Y = Block Lock status register bit

DQ₁, and Z = Block Lock status register bit DQ₀. Figure 7, “Block Locking State Diagram defines

possible locking states.

The following summarizes the locking functionality.

• All blocks power-up in a locked state. Unlock commands can unlock these blocks.

• The Lock-Down command locks a block and prevents it from being unlocked when

WP# = V_IL.

— WP# = V_IHoverrides lock-down so commands can unlock or lock blocks.

— When WP# returns to V_IL, previously locked-down blocks return to lock-down.

— The Lock-Down state is cleared only when the device is reset or powered-down.

Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the

following sections. Figure 7, “Block Locking State Diagram” on page 28 shows the state table for

the locking functions. See also Figure 8, “Locking Operations Flowchart” on page 30.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 7. Block Locking State Diagram

Unlock cmd

WP#=x

Locked

[x01]

Unlocked

[x00]

Device in Reset

or Powered-Down

Lock cmd

WP#=x

Locked

[111]

WP# DQ[1] DQ[0] Block Status

Unlocked

Locked

Locked Down

Unlocked

Locked

Locked-

Down

[011]

(all other combinations are invalid)

Unlocked

[110]

WP#=0

WP# write protection is enabled in these states while the

lock-down status bit is set. (DQ[1]=1)

NOTES:

1. The notation [X,Y,Z] denotes the locking state of a block, The current locking state of a block is defined by the

state of WP# and the two bits of the block-lock status DQ[1:0].

4.12.1

4.12.2

Lock Block

All blocks default to locked (states [001] or [101]) after initial power-up or reset. Locked blocks

are fully protected from alteration. Attempted program or erase operations to a locked block will

return an error in SR.1. Unlocked blocks can be locked by using the Lock Block command

sequence. Similarly, a locked block’s status can be changed to unlocked or lock-down using the

appropriate software commands.

Unlock Block

Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks

return to the locked state when the device is reset or powered-down. An unlocked block’s status

can be changed to the locked or locked-down state using the appropriate software commands. A

locked block can be unlocked by writing the Unlock Block command sequence if the block is not

locked-down.

4.12.3

Lock-Down Block

Locked-down blocks (state [011]) offer the user an addition level of write protection beyond that of

a regular locked block. A block that is locked-down cannot have it’s state changed by software if

WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

command sequence. If a block was set to locked-down, then later changed to unlocked, asserting

WP# will force that block back to the locked-down. When WP# is deasserted, locked-down blocks

are changed to the locked state and can then be unlocked by Unlock Block command. Locked-

down blocks revert to the locked state at device reset or power-down.

4.12.4

Block Lock Status

Every block’s lock status can be read in read identifier mode. To enter this mode, write 90h to the

device. Subsequent reads at Block Address + 02h will output that block’s lock status. For example,

to read the block lock status of block 10, the address sent to the device should be 50002h (for a top-

parameter device). The lowest two data bits, DQ[1] and DQ[0], represent the lock status. DQ[0]

indicates the block lock status. It is set by the Lock Block command and cleared by the Block

Unlock command. It is also set when entering lock-down state. DQ[1] indicates lock-down status

and is set by the Lock-Down command. The lock-down status bit cannot be cleared by software,

only by device reset or power-down. See Table 10.

Table 10. Write Protection Truth Table

VPP

WP#

RST#

Write Protection

Device inaccessible

Word program and block erase prohibited

All lock-down blocks locked

All lock-down blocks can be unlocked

4.12.5

Locking Operations During Erase Suspend

Block lock configurations can be performed during an erase suspend operation by using the

standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful

when another block requires immediate updating.

To change block locking during an erase operation, first write the Erase Suspend command. After

checking SR.6 to determine the erase operation has suspended, write the desired lock command

sequence to a block; the lock status will be changed. After completing lock, unlock, read, or

program operations, resume the erase operation with the Erase Resume command (D0h).

If a block is locked or locked-down during a suspended erase of the same block, the locking status

bits will change immediately. But, when resumed, the erase operation will complete.

Locking operations cannot occur during program suspend. Appendix A, “Write State Machine

States” on page 65 shows valid commands during erase suspend.

4.12.6

Status Register Error Checking

Using nested locking or program command sequences during erase suspend can introduce

ambiguity into status register results.

Since locking changes require two-cycle command sequences, e.g., 60h followed by 01h to lock a

block, following the Configuration Setup command (60h) with an invalid command produces a

command sequence error (SR.4=1 and SR.5=1). If a Lock Block command error occurs during

erase suspend, the device sets SR.4 and SR.5 to ‘1’ even after the erase is resumed. When erase is

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

complete, possible errors during the erase cannot be detected via the status register because of the

previous locking command error. A similar situation occurs if a program operation error is nested

within an erase suspend.

4.12.7

WP# Lock-Down Control

WP# allows block lock-down to be overridden. Table 10, “Write Protection Truth Table” on

page 29 defines the write protection methods.

WP# controls the lock-down function. WP# = V_ILprotects locked-down blocks [011] from

program, erase, and lock status changes. When WP# = V_IH, the block’s lock-down state reverts to

locked [111]. A software command can then individually unlock a block [110] for erase or program

operations. These blocks can then be re-locked [111] while WP# remains high. When WP# returns

low, previously locked-down blocks are forced back to the lock-down state [011] regardless of

changes made while WP# was high. Device reset or power-down resets all blocks to the locked

state [101] or [001].

Figure 8. Locking Operations Flowchart

LOCKING OPERATIONS PROCEDURE

Start

Bus

Operation

Command

Comments

Write 60h

Block Address

Lock

Setup

Data = 60h

Addr = Block to lock/unlock/lock-down (BA)

Write

Write 01,D0,2Fh

Block Address

Lock,

Unlock, or

Lockdown

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lockdown block)

Confirm Addr = Block to lock/unlock/lock-down (BA)

Write 90h

BBA + 02h

Write

Read ID Data = 90h

(Optional)

Plane

Addr = BBA + 02h

Read Block Lock

Status

Read

(Optional)

Block Lock Block Lock status data

Status Addr = BBA + 02h

Locking

Change?

Confirm locking change on DQ[1:0].

(See Block Locking State Transitions Table

for valid combinations.)

Standby

(Optional)

Yes

Read

Array

Data = FFh

Addr = Any address in same partition

Write

Write FFh

Partition Address

Lock Change

Complete

4.13

Protection Register

The 1.8 Volt Intel^®Wireless Flash Memory includes a 128-bit protection register. This protection

substitution.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

The lower 64 bits within the protection register are programmed by Intel with a unique number in

each flash device. The upper 64 OTP bits within the protection register are left for the customer to

program. Once programmed, the customer segment can be locked to prevent further programming.

Note that the individual bits of the user segment of the protection register are OTP, not the register

in total. The user may program each OTP bit individually, one at a time, if desired. Once the

protection register is locked, however, the entire user segment is locked and no more user bits may

be programmed.

The protection register shares some of the same internal flash resources as the parameter partition.

Therefore, RWW is only allowed between the protection register and main partitions. Table 11

describes the operations allowed in the protection register, parameter partition, and main partition

during RWW and RWE.

Table 11. Simultaneous Operations Allowed with the Protection Register

Parameter

Partition

Array Data

Protection

Main

Partitions

Description

While programming or erasing in a main partition, the protection register may be

read from any other partition. Reading the parameter partition data is not allowed

if the protection register is being read from addresses within the parameter

partition.

See

Description

Read

Write/Erase

While programming or erasing in a main partition, read operations are allowed in

Write/Erase the parameter partition. Accessing the protection registers from parameter

partition addresses is not allowed.

See

Description

Read

While programming or erasing in a main partition, read operations are allowed in

the parameter partition. Accessing the protection registers in a partition that is

different from the one being programed/erased, and also different from the

parameter partition, is allowed.

Read

Write

Write/Erase

While programming the protection register, reads are only allowed in the other

main partitions. Access to the parameter partition is not allowed. This is because

programming of the protection register can only occur in the parameter partition,

No Access

Allowed

Read

so it will exist in status mode.

While programming or erasing the parameter partition, reads of the protection

registers are not allowed in any partition. Reads in other main partitions are

supported.

No Access

Allowed

Write/Erase

Read

4.14

Read Protection Register

Writing the Read Identifier command allows the protection register data to be read 16 bits at a time

from addresses shown in Table 7, “Device Identification Codes” on page 14. The protection

Array command returns the device to read array mode.

4.15

Program Protection Register

The Protection Program command should be issued only at the bottom partition followed by the

data to be programed at the specified location. It programs the upper 64 bits of the protection

addresses. See also Figure 9, “Protection Register Programming Flowchart” on page 32. Issuing a

Protection Program command outside the register’s address space results in a status register error

(SR.4=1).

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.15.1

Lock Protection Register

PR-LK.0 is programmed to ‘0’ by Intel to protect the unique device number. PR-LK.1 can be

programmed by the user to lock the user portion (upper 64 bits) of the protection register (see

Figure 10, “Protection Register Locking). This bit is set using the Protection Program command to

program “FFFDh” into PR-LK.

After PR-LK register bits are programmed (locked), the protection register’s stored values can’t be

changed. Protection Program commands written to a locked section result in a status register error

(SR.4=1, SR.5=1).

Figure 9. Protection Register Programming Flowchart

PROTECTION REGISTER PROGRAMMING PROCEDURE

Bus

Operation

Start

Command

Comments

Protection

Program

Setup

Data = C0h

Addr = Protection address

Write

Read

Write C0h

Addr=Prot addr

Protection Data = Data to program

Program Addr = Protection address

Write Protect.

Address / Data

Read SRD

Toggle CE# or OE# to update SRD

Read Status

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

SR.7 = 1?

Yes

Protection Program operations addresses must be within the

protection register address space. Addresses outside this

space will return an error.

Repeat for subsequent programming operations.

Full Status

Check

(if desired)

Full status register check can be done after each program or

after a sequence of program operations.

Program

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read SRD

Command

Comments

SR.1 SR.3 SR.4

Standby

V_PPError

1,1

0,1

1,1

SR.3, SR.4 =

V_PPRange Error

Protection register

program error

Operation aborted

SR.1, SR.4 =

Programming Error

SR.3 MUST be cleared before the WSM will allow further

program attempts.

Locked-Register

Program Aborted

Only the Clear Staus Register command clears SR.1, 3, 4.

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Program

Successful

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 10. Protection Register Locking

88h

4 Words (64 bits)

User Programmed

Group 1

85h

84h

4 Words (64 bits)

Intel Factory Programmed

Lock Register 0

Group 0

81h

80h

PROT_REG.WMF

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

4.16

Set Configuration Register

The Set Configuration Register command sets the burst order, frequency configuration, burst

length, and other parameters.

A two-bus cycle command sequence initiates this operation. The configuration register data is

placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set

Configuration Register command is written along with the configuration data (on the address bus).

This is followed by a second write that confirms the operation and again presents the configuration

ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the

applied V_PPvoltage. After executing this command, the device returns to read array mode. The

configuration register’s contents can be examined by writing the Read Identifier command and

then reading location 05h.

Table 12. Configuration Register Definitions

Data

Output

Config

Read

Mode

WAIT

Polarity

WAIT

Config

Burst

Seq

Clock

Config

Burst

Wrap

Res’d

First Access Latency Count

Res’d

Burst Length

LC2

LC1

LC0

DOC

BL2

BL1

BL0

Bit

Name

Description

Notes⁽¹⁾

0 = Synchronous Burst Reads Enabled

1 = Asynchronous Reads Enabled (Default)

Read Mode

Reserved

000 = Code 0 (Reserved)

100 = Code 4

101 = Code 5

110 = Code 6 (Reserved)

111 = Code 7 (Reserved) (Default)

LC2-0

001 = Code 1 (Reserved)

010 = Code 2

011 = Code 3

13-11

First Access Latency

Count

0 = WAIT signal is active low

1 = WAIT signal is active high (Default)

WAIT Signal Polarity

DOC

0 = Hold Data for One Clock

1 = Hold Data for Two Clock (Default)

Data Output Configuration

0 = WAIT Asserted During Delay

1 = WAIT Asserted One Data Cycle before Delay (Default)

WAIT Configuration

0 = Intel Burst Order

1 = Linear Burst Order (Default)

Burst Sequence

0 = Burst Starts and Data Output on Falling Clock Edge

1 = Burst Starts and Data Output on Rising Clock Edge (Default)

Clock

Configuration

Reserved

0 = Wrap bursts within burst length set by CR.2–0

1 = Don’t wrap accesses within burst length set by CR.2–0.(Default)

Burst Wrap

001 = 4-Word Burst

010 = 8-Word Burst

BL2-0

2-0

011 = Reserved

111 = Continuous Burst (Default)

Burst Length

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

NOTES:

1. Undocumented combinations of bits are reserved by Intel for future implementations.

2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks.

Status register and configuration reads support single read cycles. CR.15=1 disables configuration set by

CR.14-1.

3. Data is not ready when WAIT is active.

4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.

4.16.1

4.16.2

Read Mode (CR.15)

All partitions support two high-performance read configurations: synchronous burst mode and

asynchronous page mode (default). CR.15 sets the read configuration to one of these modes.

Status register, query, and identifier modes support only asynchronous and single-synchronous read

operations.

First Access Latency Count (CR.13-11)

The First Access Latency Count (CR.13-11) configuration tells the device how many clocks must

elapse from ADV#-inactive (V_IH) before the first data word should be driven onto its data pins.

The input clock frequency determines this value. See Table 12, “Configuration Register

Definitions” on page 34 for latency values. Figure 13, “First Access Latency Configuration” on

page 37 shows data output latency from ADV#-active for different latencies.

Use these equations to calculate First Access Latency Count:

(1)

(2)

{1/ Frequency} = CLK Period

n (CLK Period) ≥ t_AVQV(ns) + t_ADD-DELAY(ns) + t_DATA(ns)

(3)

n-2 = First Access Latency Count (LC) *

n: # of Clock periods (rounded up to the next integer)

*Must use LC = n - 1 when the starting address is not aligned to a four-word boundary and CR.3=1

(No Wrap).

)

Table 13. First Latency Count (LC)

Aligned To 4-word

Boundary

Wait Asserted on 16-Word

Boundary Crossing

LC Setting

Mode

Wrap

n-1

n-2

n-1

4 or 8

disabled

enabled

yes

yes, occurs on the every occurrence

4 or 8

yes

continuous

yes, occurs once

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 11. Word Boundary

Word 0 - 3

Word 4 - 7

Word 8 - B

Word C - F

1 2 3 4 5 6 7 8 9 A B C D E F

16 Word Boundary

4 Word Boundary

NOTE:

1. The 16-word boundary is the end of the device sense word-line.

Parameters defined by CPU:

t_ADD-DELAY= Clock to CE#, ADV#, or Address Valid whichever occurs last.

t_DATA= Data set up to Clock.

Parameters defined by flash:

t_AVQV= Address to Output Delay.

Example:

CPU Clock Speed = 52 MHz

t_ADD-DELAY= 6 ns (typical speed from CPU) (max)

_DATA= 4 ns (typical speed from CPU) (min)

t_AVQV= 70 ns (from AC Characteristic - Read Only Operations Table)

From Eq. (1):

From Eq. (2)

1/52 (MHz) = 19.2 ns

n(19.2 ns) ≥ 70 ns + 6 ns + 4 ns

n(19.2 ns) ≥ 80 ns

n ≥ 80/19.2 = 4.17 = 5 (Integer)

n - 2 = 5 - 2 = 3

From Eq. (3)

First Access Latency Count Setting to the CR is Code 3.

(Figure 12, “Data Output with LC Setting at Code 3” on page 37 displays

example data)

The formula t_AVQV(ns) + t_ADD-DELAY(ns) + t_DATA(ns) is also known as initial access time.

Figure 12 shows the data output available and valid after four clocks from ADV# going low in the

first clock period with the LC setting at 3.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 12. Data Output with LC Setting at Code 3

t_ADD

t_DATA

3rd

1st

2nd

4th

5th

CLK [C]

CE# [E]

ADV# [V]

Valid Address

High Z

Address [A]

Code 3

Valid

Output

Valid

Output

DQ[15:0] [Q]

R103

Figure 13. First Access Latency Configuration

CLK [C]

Valid

Address

Address [A]

ADV# [V]

Code 0 (Reserved)

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

DQ[15:0] [Q]

Code 1

(Reserved

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 2

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 3

Code 4

Code 5

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 6 (Reserved)

Code 7 (Reserved)

Valid

Output

Valid

Output

Valid

Output

4.16.3

WAIT Signal Polarity (CR.10)

The WAIT signal polarity is set by CR.10 (WT).

If the WT bit is cleared (CR.10=0), then WAIT is configured to be active low. This means that a ‘0’

on the WAIT signal indicates that data is not ready and the data bus contains invalid data.

Conversely, if CR.10 is set (CR.10=1), then WAIT is active high. In either case, if WAIT is

deasserted, then data is ready and valid.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

WAIT is High-Z until the device is active (CE# = V_IL). In synchronous read array mode, when the

device is active (CE# = V_IL) and data is valid, CR.10 determines if WAIT goes to V_OHor V_OL. The

WAIT signal is only “deasserted” once data is valid on the bus. Invalid data drives the WAIT signal

to the asserted state. WAIT is asserted during asynchronous page mode reads.

4.16.4

WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous burst mode

(CR.15=0), and when addressing a partition that is currently in read array mode. The WAIT signal

is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-read array mode, such as read status, read ID, or

read query, WAIT is set to an “asserted” state as determined by CR.10. Figure 25, “WAIT Signal in

Synchronous Non-Read Array Operation Waveform” on page 58 displays WAIT Signal in

Synchronous Non-Read Array Operation Waveform.

When the device is operating in asynchronous page mode or asynchronous single word read mode,

WAIT is set to an “asserted” state as determined by CR.10. See Figure 26, “WAIT Signal in

Asynchronous Page-Mode Read Operation Waveform” on page 59 and Figure 27, “WAIT Signal in

Asynchronous Single-Word Read Operation Waveform” on page 60.

From a system perspective, the WAIT signal will be in the asserted state (based on CR.10) when

the device is operating in synchronous non-read array mode (such as Read ID, Read Query, or

Read Status), or if the device is operating in asynchronous mode (CR.15=1). In these cases, the

system software should ignore (mask) the WAIT signal, as it does not convey any useful

information about the validity of what is appearing on the data bus.

Systems may tie several components’ WAIT signals together.

4.16.5

Data Output Configuration (CR.9)

The Data Output Configuration bit (CR.9) determines whether a data word remains valid on the

data bus for one or two clock cycles. The processor’s minimum data set-up time and the flash

memory’s clock-to-data output delay determine whether one or two clocks are needed.

If the Data Output Configuration is set at one-clock data hold, this corresponds to a one-clock data

cycle; if the Data Output Configuration is set at two-clock data hold, this corresponds to a two-

clock data cycle. This configuration bit’s setting depends on the system and CPU characteristics.

Refer to Figure 14, “Data Output Configuration with WAIT Signal Delay” on page 39 for

clarification.

A method for determining what this configuration should be set at is shown below.

To set the device at one clock data hold for subsequent reads, the following condition must be

satisfied:

t_CHQV(ns) + t_DATA(ns) ≤ One CLK Period (ns)

As an example, a clock frequency of 52 MHz will be used. The clock period is 19.2 ns. This data is

applied to the formula above for the subsequent reads assuming the data output hold time is one

clock:

14 ns + 4 ns ≤ 19.2 ns

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

This equation is satisfied and data output will be available and valid at every clock period. If t_DATA

is long, hold for two cycles.

Now assume the clock frequency is 66 MHz. This corresponds to a 15 ns period. The initial access

time is calculated to be 80 ns (Latency Count = Code 4). This condition satisfies t_AVQV(ns) +

t_ADD-DELAY(ns) + t_DATA(ns) = 70 ns + 6 ns + 4 ns = 80 ns, as shown above in the First Access

Latency Count equations. However, the data hold time of one clock violates the one-clock data

hold condition:

t_CHQV(ns) + t_DATA(ns) ≤ One CLK Period

14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. To satisfy the formula above, the

data output hold time must be set at 2 clocks to correctly allow for data output setup time. This

formula is also satisfied if the CPU has t_DATA(ns) ≤ 1 ns, which yields:

14 ns + 1 ns ≤ 15 ns

In page-mode reads, the initial access time can be determined by the formula:

t_ADD-DELAY(ns) + t_DATA(ns) + t_AVQV(ns)

and subsequent reads in page mode are defined by:

t_APA(ns) + t_DATA(ns)

(minimum time)

Figure 14. Data Output Configuration with WAIT Signal Delay

CLK [C]

WAIT (CR.8 = 1)

Note 1

t_CHQV

WAIT (CR.8 = 0)

1 CLK

Data Hold

Valid

Output

Valid

Output

Valid

Output

DQ[15:0] [Q]

WAIT (CR.8 = 0)

Note 1

t_CHTL/H

t_CHQV

WAIT (CR.8 = 1)

DQ[15:0] [Q]

Note 1

2 CLK

Data Hold

Valid

Output

Valid

Output

Note1: WAIT shown active high (CR.10 = 1)

4.16.6

WAIT Delay Configuration (CR.8)

The WAIT configuration bit (CR.8) controls WAIT signal delay behavior for all synchronous read

array modes. Its setting depends on the system and CPU characteristics. The WAIT can be asserted

either during or one data cycle before a valid output.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

In synchronous linear read array (no-wrap mode CR.3=1) of 4-, 8-, or continuous-word burst

mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-

word boundary). If the burst start address is four-word boundary aligned, the delay will not occur.

If the start address is misaligned to a four-word boundary, the delay occurs once per burst-mode

read sequence. The WAIT signal informs the system of this delay.

4.16.7

Burst Sequence Configuration (CR.7)

The burst sequence specifies the synchronous burst mode data order (Table 14, “Sequence and

Burst Length” on page 41). Set this bit for linear or Intel burst order. Continuous burst mode

supports only linear burst order.

When operating in a linear burst mode, either 4-word or 8-word burst length with the burst wrap bit

(CR.3) set, or in continuous burst mode, the device may incur an output delay when the burst

sequence crosses the first 16-word boundary. (See Figure 11, “Word Boundary” on page 36 for

word boundary description.) This is dependent on the starting address. If the starting address is

aligned to a four-word boundary, the delay will not occur. If the starting address is the end of a

four-word boundary, the output delay will be one clock cycle less than the First Access Latency

Count; this is the worst-case delay. The delay will take place only once and will not happen if the

burst sequence does not cross a 16-word boundary. The WAIT pin informs the system of this delay.

See Figure 22, “Single Synchronous Read Operation Waveform” on page 55 through Figure 24,

“WAIT Functionality for EOWL (End of Word Line) Condition Waveform” on page 57 for timing

diagrams of WAIT functionality.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table 14. Sequence and Burst Length

Burst Addressing Sequence (Dec)

Start Addr.

(Dec)

Wrap

CR.3= 0

No Wrap

CR.3= 1

4-Word Burst Length

8-Word Burst Length

Continuous Burst

CR.2–0 = 111

CR.2–0 = 001

CR.2–0 = 010

Linear

Intel

Linear

Intel

Linear

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3-

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0-1-2-3-4-5-6-...

1-2-3-4-5-6-7-...

2-3-4-5-6-7-8-...

3-4-5-6-7-8-9-...

4-5-6-7-8-9-10...

5-6-7-8-9-10-11...

6-7-8-9-10-11-12-...

7-8-9-10-11-12-13...

14-15-16-17-18-19-20-...

15-16-17-18-19-20-21-...

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

0-1-2-3-4-5-6-...

1-2-3-4-5-6-7-...

2-3-4-5-6-7-8-...

3-4-5-6-7-8-9-...

4-5-6-7-8-9-10...

5-6-7-8-9-10-11...

6-7-8-9-10-11-12-...

7-8-9-10-11-12-13...

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

14-15-16-17-18-19-20-...

15-16-17-18-19-20-21-...

4.16.8

Clock Configuration (CR.6)

Clock-edge facilitates easy memory interface to a wide range of burst CPUs. Clock configuration

sets the device to start a burst cycle, output data, and assert WAIT on the clock’s rising or falling

edge.

4.16.9

Burst Wrap (CR.5)

The burst wrap bit determines whether 4-word or 8-word burst accesses wrap within the burst-

length boundary or whether they cross word-length boundaries to perform linear accesses. No-

wrap mode (CR.3=1) enables WAIT to hold off the system processor, as it does in the continuous

burst mode, until valid data is available. In the no-wrap mode (CR.3=0), the device operates similar

to continuous linear burst mode but consumes less power during 4 or 8-word bursts.

For example, if CR.3=0 (wrap mode) and CR.2–0 = 1h (4-word burst), possible linear burst

sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

If CR.3=1 (no-wrap mode) and CR.2–0 = 1h (4-word burst length), then possible linear burst

sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR.3=1 not only enables limited non-aligned

sequential bursts, but also reduces power by minimizing the number of internal read operations.

Setting CR.2-0 bits for continuous linear burst mode (7h) also achieves the above 4-word burst

sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for

example, will consume power during the initial access, again during the internal pipeline lookup as

the processor reads word 2, and possibly again, depending on system timing, near the end of the

sequence as the device pipelines the next 4-word sequence. CR.3=1 while in 4-word burst mode

(no wrap mode) reduces this excess power consumption.

4.16.10

Burst Length (CR.2-0)

The burst length is the number of words the device outputs in a synchronous read access. 4-, 8-, and

continuous burst lengths are supported. In 4- or 8-word burst configuration, the burst wrap bit

(CR.3) determines if burst accesses wrap within word-length boundaries or whether they cross

word-length boundaries to perform a linear access. Once an address is given, the device will output

data until it reaches the end of its burstable address space. Continuous burst access are linear only

and do not wrap within word-length boundaries. (see Table 14, “Sequence and Burst Length” on

page 41).

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

5.0

Program and Erase Voltages

The 1.8 Volt Intel^®Wireless Flash memory provides in-system program and erase at V_PP1. For

factory programming, it also includes a low-cost, backward-compatible 12 V programming feature.

The EFP feature can also be used to greatly improve factory program performance.

5.1

Factory Program Mode

The standard factory programming mode uses the same commands and algorithm as the Word

Program mode (40h/10h). When V_PPis at V_PP1, program and erase currents are drawn through

VCC. Note that if VPP is driven by a logic signal, V_PP1must remain above the V_PP1Min value to

perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device

draws program and erase current directly from VPP. This eliminates the need for an external

switching transistor to control the V_PPvoltage. Figure 15, “Example VPP Power Supply

Configuration shows examples of flash power supply usage in various configurations.

The 12 V V_PPmode enhances programming performance during the short time period typically

found in manufacturing processes; however, it is not intended for extended use. 12 V may be

applied to V_PPduring program and erase operations as specified in Section 7.2, “Extended

Temperature Operation” on page 47. VPP may be connected to 12 V for a total of t_PPHhours

maximum. Stressing the device beyond these limits may cause permanent damage.

5.2

Programming Voltage Protection (V )

In addition to the flexible block locking, holding the V_PPprogramming voltage low can provide

absolute hardware write protection of all flash-device blocks. If V_PPis below V_PPLK, program or

erase operations will result in an error displayed in SR.3.

Figure 15. Example VPP Power Supply Configuration

System supply

V_CC

V_PP

12 V supply

V_PP

Prot# (logic signal)

(Note 2)

≤

10K Ω

•

12 V fast programming

Absolute write protection with V _PP

•

Low-voltage programming

Absolute write protection via logic signal

≤

V_PPLK

System supply

V_CC

(Note 1)

System supply

V_CC

V_PP

12 V supply

•

Low voltage and 12 V fast programming

•

Low-voltage programming

VPPSUPLY.WMF

NOTE:

1. If the V supply can sink adequate current, an appropriately valued resistor can be used.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

6.0

Power Consumption

1.8 Volt Intel^®Flash memory devices have a layered approach to power savings that can

significantly reduce overall system power consumption. The APS feature reduces power

consumption when the device is selected but idle. If CE# is de-asserted, the memory enters its

standby mode, where current consumption is even lower. Asserting RST# provides current savings

similar to standby mode. The combination of these features can minimize memory power

consumption, and therefore, overall system power consumption.

6.1

6.2

Active Power

With CE# at V_ILand RST# at V_IH, the device is in the active mode. Refer to the Section 7.4, “DC

Characteristics” on page 48, for I_CCvalues.

Automatic Power Savings

APS mode provides low-power operation during read mode. After data is read from the memory

array and the address lines are quiescent, APS circuitry places the device in a mode where typical

current is comparable to I_CCS. The flash stays in this static state with outputs valid, OE# low, until

a new location is read.

6.3

Standby Power

With CE# at V_IHand the device in read mode, the flash memory is in standby mode, which disables

most device circuitry and substantially reduces power consumption. Outputs are placed in a high-

impedance state independent of the OE# signal state. If CE# transitions to V_IHduring erase or

program operations, the device will continue to perform the operation and consume corresponding

active power until the operation is complete.

6.4

Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions.

It does not matter whether V_PPor V_CCpowers-up first. Power supply sequencing is not required.

6.4.1

System Reset and RST#

The use of RST# during system reset is important with automated program/erase devices since the

system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs

without a flash memory reset, proper CPU initialization will not occur because the flash memory

may be providing status information instead of array data. Intel recommends connecting RST# to

the system CPU RESET# signal to allow proper CPU/flash initialization at system reset.

System designers must guard against spurious writes when VCC voltages are above V_LKO. Since

both WE# and CE# must be low for a command write, driving either signal to V_IHwill inhibit

writes to the device. The CUI architecture provides additional protection since alteration of

memory contents can only occur after successful completion of the two-step command sequences.

The device is also disabled until RST# is brought to V_IH, regardless of its control input states. By

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

holding the device in reset (RST# connected to system PowerGood) during power-up/down,

invalid bus conditions during power-up can be masked, providing yet another level of memory

protection.

6.4.2

6.4.3

VCC, VPP, and RST# Transitions

The CUI latches commands issued by system software and is not altered by VPP or CE# transitions

or WSM actions. Read array mode is its power-up default state after exit from reset mode or after

VCC transitions above V_LKO(Lockout voltage).

After completing program or block erase operations (even after VPP transitions below V_PPLK), the

Read Array command must reset the CUI to read array mode if flash memory array access is

desired.

Power Supply Decoupling

When the device is accessed, many internal conditions change. Circuits are enabled to charge

pumps and switch voltages. This internal activity produces transient noise. To minimize the effect

of this transient noise, device decoupling capacitors are required. Transient current magnitudes

depend on the device outputs’ capacitive and inductive loading. Two-line control and proper

decoupling capacitor selection will suppress these transient voltage peaks. Each flash device

should have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP)_,and

ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as

close as possible to package signals.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.0

Electrical Specifications

7.1

Absolute Maximum Ratings

Parameter

Note

Maximum Rating

–40 °C to +85 °C

Temperature under Bias

Storage Temperature

–65 °C to +125 °C

–0.5 V to +2.45 V

–0.2 V to +14 V

–0.2 V to +2.45 V

100 mA

Voltage On Any Pin (except VCC, VCCQ, VPP)

VPP Voltage

1,2,3

VCC and VCCQ Voltage

Output Short Circuit Current

NOTES:

1. All specified voltages are with respect to VSS. Minimum DC voltage is –0.5 V on input/output pins and

–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns

which, during transitions, may overshoot to V +2.0 V for periods < 20 ns.

2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.

3. V program voltage is normally V

. V can be 12V ± 0.6 V for 1000 cycles on the main blocks and 2500

PP1

cycles on the parameter blocks during program/erase.

4. Output shorted for no more than one second. No more than one output shorted at a time.

Notice: This datasheet contains preliminary information on new products in production. Specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet

before finalizing a design.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.2

Extended Temperature Operation

Symbol

Parameter⁽¹⁾

Note

Min

Nom

Max

Unit

Operating Temperature

Supply Voltage

–40

1.7

°C

1.80

12.0

1.95

2.24

1.95

12.6

CCQ

PP1

PP2

PPH

I/O Supply Voltage

Voltage Supply (Logic Level)

1.7

0.90

11.4

Factory Programming V

Maximum V Hours

= 12 V

Hours

Main and Parameter

blocks

≤ V

100,000

Cycles

Block

Erase

Cycles

Main Blocks

= 12 V

1000

2500

Cycles

Parameter Blocks

NOTES:

1. See DC Characteristics tables for voltage-range specific specifications.

2. VPP is normally V . VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended

PP1

temperatures and 2500 cycles at extended temperature on parameter blocks.

3. Contact your Intel field representative for enhanced V /V

operations down to 1.65 V.

CC CCQ

7.3

Capacitance

T_A= +25 °C, f = 1 MHz

32/64 Mbit

128 Mbit

Unit

Sym

Parameter⁽¹⁾

Condition

Typ

Max

Typ

Max

Input

Capacitance

= 0.0 V

Output

Capacitance

= 0.0 V

OUT

CE# Input

Capacitance

= 0.0 V

NOTE: Sampled, not 100% tested.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.4

DC Characteristics

32/64 Mbit

128 Mbit

Sym

Parameter ⁽¹⁾

Note

Unit

Test Condition

Typ

Max

Typ

Max

= V Max

Input Load Current

Output

±1

µA

= V

Max

CCQ

= V

or GND

CCQ

= V Max

Leakage

Current

DQ[15:0]

= V

Max

CCQ

= V

or GND

CCQ

= V Max

= V

Max

CCQ

Standby Current

µA

CCS

CE# = V

RST# =V or GND

Burst

length = 4

Burst

length = 8

Synchronous

CLK = 40 MHz

2, 3

Burst

mA length =

Continuous

= V Max

Average

V Read

Current

CE# = V

OE# = V

Inputs = V or V

CCR

Burst

length = 4

Burst

Synchronous

CLK = 52 MHz

2, 3

length = 8

Burst

mA length =

Continuous

= V

Program in Progress

Block Erase in

PP1,

PP2,

PP1,

Program Current

4, 5

4, 6

CCW

Progress

Block Erase Current

Program Suspend

CCE

= V

Block Erase in

PP2,

Progress

CE# = V

Program Suspended

Erase Suspended

CC,

4, 7

µA

CCWS

Current

CE# = V

Erase Suspend Current

CC,

CCES

Standby Current

PPS

Program Suspend Current

Erase Suspend Current

0.2

µA

PPWS,

)

PPES

≤ V

Read Current

0.05

0.10

0.05

0.10

µA

PPR

= V

Program in Progress

Erase in Progress

PP1,

PP2,

PP1,

PP2,

Program Current

PPW

0.05

0.10

0.05

0.10

Erase Current

PPE

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

DC Characteristics, continued

Sym

Parameter

Note

Min

Typ

Max

Unit

Test Condition

Input Low Voltage

0.4

CCQ

Input High Voltage

Output Low Voltage

CCQ

– 0.4

= V Min

0.1

= V

Min

CCQ

= 100 µA

Output High Voltage

= V Min

CC CC

– 0.1

CCQ

= V

Min

CCQ

= –100 µA

Lock-Out Voltage

Lock Voltage

0.4

PPLK

1.0

LKO

NOTES:

1. All currents are RMS unless noted. Typical values at typical V , T = +25 °C.

2. APS reduces I

to approximately standby levels in static operation.

CCR

3. CR.3 determines whether 4- or 8-word burst accesses wrap within the burst-length boundary or whether they

cross word-length boundaries to perform linear accesses. In the no-wrap mode (CR.3=1), the device

operates similar to continuous linear burst mode but consumes less power.

4. Sampled, not 100% tested.

5. V read + program current is the summation of V read and V program currents.

6. V read + erase current is the summation of V read and V block erase currents.

7. I

is specified with device deselected. If device is read while in erase suspend, current draw is sum of

CCES

and I

CCR

8. V can undershoot to –0.4 V and V can overshoot to V +0.4 V for durations of 20 ns or less.

CCQ

9. Erase and program operations are inhibited when V ≤ V

and not guaranteed outside valid V

and

PPLK

PP1

ranges.

PP2

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.5

AC I/O Test Conditions

Figure 16. AC Input/Output Reference Waveform

V_CCQ

Input

V_CCQ/2

Test Points

V_CCQ/2

Output

NOTE: AC test inputs are driven at V

for a Logic ‘1’ and 0.0 V for a Logic ‘0’. Input timing begins, and output

CCQ

timing ends, at V

/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are

CCQ

when V = V Min.

Figure 17. Transient Equivalent Testing Load Circuit

V_CCQ

R₁

Device

Under Test

Out

C_L

R₂

0672_22

NOTE: See table for component values.

Test configuration component value for worst case speed conditions

Test Configuration

Min Standard Test

(pF)

R (Ω)

16.7K

CCQ

NOTE:C includes jig capacitance.

Figure 18. Clock Input AC Waveform

R201

V_IH

V_IL

CLK [C]

R202

R203

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.6

AC Read Characteristics

32/64 Mbit

128 Mbit

-90

Sym

Parameter ^(1,2)

Notes

–70

–85

Unit

Min

Max

Min

Max

Min

Max

Asynchronous Specifications

R10

Read Cycle Time

AVAV

AVQV

ELQV

GLQV

PHQV

ELQX

GLQX

EHQZ

GHQZ

Address to Output Delay

CE# Low to Output Delay

OE# Low to Output Delay

RST# High to Output Delay

CE# Low to Output in Low-Z

OE# Low to Output in Low-Z

CE# High to Output in High-Z

OE# High to Output in High-Z

CE# (OE#) High to Output in Low-Z

150

4,5

Latching Specifications

R101

R102

R103

R104

R105

R106

R108

Address Setup to ADV# High

CE# Low to ADV# High

AVVH

ELVH

VLQV

VLVH

VHVL

VHAX

APA

ADV# Low to Output Delay

ADV# Pulse Width Low

ADV# Pulse Width High

Address Hold from ADV# High

Page Address Access Time

Clock Specifications

R200

R201

R202

R203

CLK Frequency

MHz

CLK

CLK Period

CLK

CLK High or Low Time

CLK Fall or Rise Time

CH/L

CHCL

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

32/64 Mbit

128 Mbit

-90

Sym

Parameter ^(1,2)

Notes

–70

–85

Unit

Min

Max

Min

Max

Min

Max

Synchronous Specifications

R301

R302

R303

R304

R305

R306

R307

R308

R309

R310

Address Valid Setup to CLK

ADV# Low Setup to CLK

CE# Low Setup to CLK

CLK to Output Valid

AVCH

VLCH

ELCH

CHQV

CHQX

CHAX

CHTV

ELTV

Output Hold from CLK

Address Hold from CLK

CLK to WAIT Valid

3.5

CE# Low to WAIT Valid

CE# High to WAIT High-Z

CE# Pulse Width High

5,6

EHTZ

EHEL

NOTES:

1. See Figure 16, “AC Input/Output Reference Waveform” on page 50 for timing measurements and maximum

allowable input slew rate.

2. AC specifications assume the data bus voltage is less than or equal to V

initiated.

when a read operation is

CCQ

3. Address hold in synchronous burst-mode is defined as t

satisfied first.

or t

, whichever timing specification is

CHAX

VHAX

4. OE# may be delayed by up to t

5. Sampled, not 100% tested.

– t

after the falling edge of CE# without impact to t

ELQV

ELQV GLQV

6. Applies only to subsequent synchronous reads.

Figure 19. Asynchronous Read Operation Waveform

V_IH

Address [A]

V_IL

Valid

Address

V_IH

F-CE# [E]

V_IL

V_IH

F-OE# [G]

V_IL

V_IH

F-WE# [W]

V_IL

V_OH

High Z

Valid

Data [D/Q]

V_OL

Output

R10

V_IH

F-RST# [P]

V_IL

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 20. Latched Asynchronous Read Operation Waveform

V_IH

V_IL

Valid

Address

Valid

Address

A[MAX:2] [A]

A[1:0] [A]

V_IH

V_IL

Valid

Address

Valid

Address

R101

R104

R102

R105

V_IH

R106

R103

ADV# [V]

CE# [E]

V_IL

V_IH

V_IL

V_IH

V_IL

OE# [G]

WE# [W]

Data [Q]

RST# [P]

V_IH

V_IL

V_OH

V_OL

High Z

Valid

Output

R10

V_IH

V_IL

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 21. Page-Mode Read Operation Waveform

V_IH

Valid

A[MAX:2] [A]

Address

V_IL

V_IH

Valid

A[1:0] [A]

Address

V_IL

R101

R105

V_IH

R106

R103

ADV# [V]

CE# [E]

V_IL

R104

R102

V_IH

V_IL

V_IH

V_IL

OE# [G]

WE# [W]

Data [Q]

RST# [P]

V_IH

V_IL

R108

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

R10

V_IH

V_IL

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 22. Single Synchronous Read Operation Waveform

V_IH

V_IL

Note 1

CLK [C]

R301

R306

V_IH

V_IL

Valid

Address

Address [A]

R101

R302

R104

R105

V_IH

R106

ADV# [V]

CE# [E]

V_IL

R103

V_IH

V_IL

R102

V_IH

V_IL

OE# [G]

WE# [W]

WAIT [T]

Data [Q]

RST# [P]

R303

V_IH

V_IL

R309

R10

R308

V_OH

V_OL

High Z

Note 2

R304

R305

V_OH

V_OL

High Z

Valid

Output

V_IH

V_IL

NOTES:

1. Section 4.16.2, “First Access Latency Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 23. Synchronous Four-Word Burst Read Operation Waveform

V_IH

Note 1

CLK [C]

V_IL

R301

R306

V_IH

V_IL

Valid

Address

Address [A]

R101

R302

R104

R105

V_IH

R106

ADV# [V]

CE# [E]

V_IL

R103

R310

V_IH

V_IL

R102

V_IH

V_IL

OE# [G]

WE# [W]

WAIT [T]

Data [Q]

RST# [P]

R303

V_IH

V_IL

R309

R10

R308

R307

V_OH

V_OL

High Z

Note 2

R305

R304

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

V_IH

V_IL

NOTES:

1. Section 4.16.2, “First Access Latency Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 24. WAIT Functionality for EOWL (End of Word Line) Condition Waveform

V_IH

V_IL

Note 1

CLK [C]

R301

R306

V_IH

V_IL

Valid

Address

Address [A]

R101

R302

R104

R105

V_IH

R106

ADV# [V]

CE# [E]

V_IL

R103

V_IH

V_IL

R102

V_IH

V_IL

OE# [G]

WE# [W]

WAIT [T]

Data [D/Q]

R303

V_IH

V_IL

R308

R307

V_OH

V_OL

High Z

Note 2

R304

R305

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

V_IH

RST# [P]

V_IL

NOTES:

1. Section 4.16.2, “First Access Latency Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 25. WAIT Signal in Synchronous Non-Read Array Operation Waveform

V_IH

Note 1

CLK [C]

V_IL

R301

R306

V_IH

V_IL

Valid

Address

Address [A]

R101

R302

R104

R105

V_IH

R106

ADV# [V]

CE# [E]

V_IL

R103

V_IH

V_IL

R102

V_IH

V_IL

OE# [G]

WE# [W]

WAIT [T]

Data [Q]

RST# [P]

R303

V_IH

V_IL

R309

R10

R308

V_OH

V_OL

High Z

Note 2

R304

R305

V_OH

V_OL

High Z

Valid

Output

V_IH

V_IL

NOTES:

1. Section 4.16.2, “First Access Latency Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT shown active low.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 26. WAIT Signal in Asynchronous Page-Mode Read Operation Waveform

V_IH

V_IL

Valid

Address

A[MAX:2] [A]

A[1:0] [A]

V_IH

V_IL

Valid

Address

R101

R105

V_IH

R106

R103

ADV# [V]

CE# [E]

OE# [G]

V_IL

R104

R102

V_IH

V_IL

V_IH

V_IL

V_IH

WE# [W]

WAIT [T]

V_IL

V_OH

High Z

R108

Note 1

V_OL

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Data [D/Q]

RST# [P]

R10

V_IH

V_IL

NOTES:

1. WAIT shown active low.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 27. WAIT Signal in Asynchronous Single-Word Read Operation Waveform

V_IH

Valid

Address [A]

Address

V_IL

V_IH

CE# [E]

V_IL

V_IH

V_IL

OE# [G]

V_IH

V_IL

WE# [W]

WAIT [T]

V_OH

V_OL

High Z

Note 1

V_OH

V_OL

High Z

Valid

Output

Data [D/Q]

RST# [P]

R10

V_IH

V_IL

NOTES:

1. WAIT shown active low.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.7

AC Write Characteristics

32 Mbit / 64 Mbit

–70 –85

128 Mbit

-90

Sym

Parameter ^(1,2)

Notes

Unit

Min

Max

Min

Max

Min

Max

PHWL

W10

RST# High Recovery to WE# (CE#) Low

CE# (WE#) Setup to WE# (CE#) Low

WE# (CE#) Write Pulse Width Low

Data Setup to WE# (CE#) High

150

)

PHEL

ELWL

WLEL

)

WLWH

)

ELEH

DVWH

)

DVEH

AVWH

Address Setup to WE# (CE#) High

CE# (WE#) Hold from WE# (CE#) High

Data Hold from WE# (CE#) High

Address Hold from WE# (CE#) High

WE# (CE#) Pulse Width High

)

AVEH

WHEH

)

EHWH

WHDX

)

EHDX

WHAX

)

EHAX

WHWL

5, 6, 7

200

)

EHEL

VPWH

VPP Setup to WE# (CE#) High

)

VPEH

QVVL

QVBL

W11

W12

VPP Hold from Valid SRD

WP# Hold from Valid SRD

3, 8

BHWH

W13

W14

W16

WP# Setup to WE# (CE#) High

Write Recovery before Read

WE# High to Valid Data

200

)

BHEH

WHGL

)

EHGL

AVQV

+ 50

AVQV

+ 40

AVQV

+ 50

WHQV

W18

W19

W20

WE# High to Address Valid

WE# High to CLK Valid

WE# High to ADV# High

NOTES:

WHAV

WHCV

WHVH

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (t

or t

) is defined from CE# or WE# low (whichever occurs last) to CE# or

WLWH

ELEH

WE# high (whichever occurs first). Hence, t

= t

WLWH

ELEH

WLEH

ELWH

5. Write pulse width high (t

or t

) is defined from CE# or WE# high (whichever is first) to CE# or WE#

WHWL

EHEL

low (whichever is last). Hence, t

= t

WHWL

EHEL

WHEL

EHWL

6. t

is t

+ 50 ns. System designers should take this into account and may insert a software No-Op

WHQV

AVQV

instruction to delay the first read after issuing a command.

7. For command other than resume commands.

8. V should be held at V

or V

until block erase or program success is determined.

PP1

PP2

9. Applicable during asynchronous reads following a write.

10.During synchronous reads, either t or t must be met, whichever occurs first.

WHCV

WHVH

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 28. Write Operations Waveform

V_IH

CLK [C]

V_IL

W19

Note 1

Note 2

Note 3

Note 4

W18

Note 5

V_IH

V_IL

Valid

Address

Valid

Address

Valid

Address

Address [A]

R101

R105

V_IH

R106

ADV# [V]

V_IL

R104

W20

V_IH

V_IL

Note 6

CE# (WE#) [E(W)]

OE# [G]

V_IH

V_IL

W14

V_IH

V_IL

Note 6

WE# (CE#) [W(E)]

Data [Q]

W16

V_IH

V_IL

Valid

SRD

Data In

V_IH

V_IL

RST# [P]

W13

W10

W12

W11

V_IH

V_IL

WP# [B]

V_PPH

V_PPLK

V_IL

VPP [V]

NOTES:

1. V power-up and standby.

2. Write Program or Erase Setup command.

3. Write valid address and data (for program) or Erase Confirm command.

4. Automated program/erase delay.

5. Read status register data (SRD) to determine program/erase operation completion.

6. OE# and CE# must be asserted and WE# deasserted for read operations.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

7.8

Erase and Program Times

PP2

PP1

Operation

Symbol

Parameter

Description

Notes

Unit

Typ

Max

Typ

Max

Erasing and Suspending

W500

W501

W600

W601

4-KW Parameter Block

32-KW Main Block

Program Suspend

Erase Suspend

1,2

0.3

0.7

2.5

0.25

0.4

2.5

ERS/PB

ERS/MB

SUSP/P

SUSP/E

Erase Time

µs

Suspend

Latency

Conventional Word Programming

W200

W201

W202

Single Word

0.05

0.4

150

.23

1.8

130

0.07

0.6

µs

PROG/W

PROG/PB

PROG/MB

Program

Time

4-KW Parameter Block

32-KW Main Block

1,2

0.03

0.24

Enhanced Factory Programming

W400

W401

W402

W403

W404

W405

Single Word

3.5

µs

EFP/W

Program

4-KW Parameter Block

32-KW Main Block

EFP Setup

1,2

EFP/PB

120

EFP/MB

EFP/SETUP

EFP/TRAN

EFP/VERIFY

Operation

Latency

Program to Verify Transition

Verify

2.7

1.7

5.6

130

µs

Unless noted otherwise, all above parameters are measured at T_A= +25 °C and nominal voltages,

and they are sampled, not 100% tested.

NOTES:

1. Excludes external system-level overhead.

2. Exact results may vary based on system overhead.

7.9

Reset Specifications

Symbol

Parameter⁽¹⁾

RST# Low Pulse Width

Notes

Min

Max

Unit

2, 3, 4

3, 4, 5

100

µs

PLPH

RST# Low to device reset during Block Erase

RST# Low to device reset during Program

VCC Power Valid to RST# High

PLRH

3, 4, 5

1,3,4,5,6

VCCPH

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. The device may reset if t < t Min, but this is not guaranteed.

PLPH PLPH

3. Not applicable if RST# is tied to VCC.

4. Sampled, but not 100% tested.

5. If RST# is tied to VCC, the device is not ready until t

after time when V ≥ V Min.

CC CC

VCCPH

6. If RST# is tied to any supply/signal with V

voltage levels, the RST# input voltage must not exceed V

CCQ

until V ≥ V Min.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Figure 29. Reset Operations Waveforms

V_IH

V_IL

(

A) Reset during

RST# [P]

VCC

read mode

Abort

Complete

(B) Reset during

V_IH

V_IL

program or block erase

≤ P2

Abort

Complete

V_IH

V_IL

program or block erase

≥ P2

V_CC

(D) VCC Power-up to

RST# high

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Appendix A Write State Machine States

This table shows the command state transitions based on incoming commands. Only one partition can be

actively programming or erasing at a time. Each partition stays in its last output state (Array, ID/CFI or Status)

until a new command changes it. The next WSM state does not depend on the partition’s output state.

Table A1. Write State Machine - Next State Table

Next State After Command Input

Block Erase

Clear

Program Erase

Confirm,

Pgm/Erase

Resume,

Program/

Erase

Read

Identifier/

Query

Read

EFP

Status

S₍e₄t_,5u₎p

Status

Array⁽³⁾

Setup⁽⁴⁾

Suspend Register

(6)

ULB Confirm⁽⁹⁾

(10h/

40h)

(FFh)

(20h)

(30h)

(D0h)

(B0h)

(70h)

(50h)

(90h, 98h)

Current State

Program Erase

Setup Setup

EFP

Setup

Ready

Ready (Lock Error)

Lock/CR Setup

OTP

Ready (Lock Error)

Ready

Setup

Busy

Setup

OTP Busy

Program Busy

Program

Suspend

Program

Erase

Busy

Program Busy

Suspend

Setup

Program Suspend

Ready (Error)

Program Busy

Erase Busy

Program Suspend

Ready (Error)

Erase

Suspend

Busy

Erase Busy

Program

in Erase

Suspend Suspend

Setup

Erase

Suspend

Erase Suspend

Erase Busy

Erase Suspend

Setup

Busy

Program in Erase Suspend Busy

Program in

Program in Erase

Suspend

Program in Erase Suspend Busy

Erase

Program in Erase Suspend Busy

Program in Erase Suspend

Suspend

Program in Erase

Suspend Busy

Suspend

Program in Erase Suspend

Lock/CR Setup in Erase Suspend

Setup

Erase Suspend (Lock Error)

Ready (Error)

Erase Suspend

Erase Suspend (Lock Error)

Ready (Error)

EFP Busy

EFP

Busy

EFP Busy⁽⁷⁾

Verify Busy⁽⁷⁾

Verify

State Output After Command Input

Program Erase

Erase Setup

OTP Setup

Program in Erase Suspend

EFP Setup, EFP Busy

Verify Busy

Status

Lock/CR Setup

Lock/CR Setup in Erase Suspend

Status

Output

doesn’t

change

OTP Busy

Array⁽³⁾

Array

Status

Output doesn’t change

Status

Ready

Program Busy

Program Suspend

Erase Busy

Erase Suspend

Program in Erase Suspend

Pgm Suspend in Erase Suspend

Output

doesn’t

change

Output doesn’t change

ID/Query

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table A1. Write State Machine -- Next State Table (continued)

Next State After Command Input

Lock,

Lock

Lock-Dwn

Block

Illegal

WSM

Unlock,

OTP

Block

Write CR

EFP Exit

Cmds or

Operation

Lock-Dwn, Setup⁽⁵⁾Confirm

Confirm⁽⁹⁾

(BlkAdr≠WAO)

Confirm⁽⁹⁾

EFP Data⁽²⁾Completes

CR Setup⁽⁵⁾

(9)

(other

codes)

(60h)

(C0h)

(01h)

(2Fh)

(03h)

(XXXXh)

Current State

Lock/CR

Setup

OTP

Setup

Ready

N/A

Lock/CR Setup

OTP

Ready (Lock Error)

Ready

Ready (Lock Error)

N/A

Setup

Busy

OTP Busy

Ready

N/A

Setup

Busy

Program Busy

Program Suspend

Ready (Error)

Erase Busy

Program

Erase

Ready

N/A

Suspend

Setup

Busy

N/A

Ready

Lock/CR

Setup in

Erase

Suspend

Erase Suspend

N/A

Suspend

Setup

Program in Erase Suspend Busy

Program in

Erase Suspend

Erase

Suspend

Busy

Suspend

N/A

Erase

Suspend

(Lock Error)

Erase Suspend

(Lock Error)

Lock/CR Setup in Erase

Suspend

Erase Suspend

Ready (Error)

Setup

N/A

EFP

Busy

EFP Busy⁽⁷⁾

Verify Busy⁽⁷⁾

EFP Verify EFP Busy⁽⁷⁾

Verify

Ready

EFP Verify⁽⁷⁾

Ready

State Output After Command Input

Program Erase

Erase Setup

OTP Setup

Output

doesn’t

change

Program in Erase Suspend

EFP Setup

Status

EFP Busy

Verify Busy

Lock/CR Setup

Lock/CR Setup in Erase

Suspend

Output

doesn’t

change

Status

Array

Status

Output

doesn’t

change

OTP Busy

Status⁽⁷⁾

Status

Output doesn’t change

Array

Status

Ready

Program Busy

Program Suspend

Erase Busy

Erase Suspend

Program in Erase Suspend

Pgm Suspend in Erase Suspend

Output

doesn’t

change

Output doesn’t change

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

NOTES:

1. The output state shows the type of data that appears at the outputs if the partition address is the same as the

command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the

command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command

changes it. The next WSM state does not depend on the partition’s output state. For example, if partition #1’s

output state is Read Array and partition #4’s output state is Read Status, every read from partition #4 (without

issuing a new command) outputs the status register.

2. Illegal commands are those not defined in the command set.

3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition

results in undermined data when a partition address is read.

4. Both cycles of 2-cycle commands should be issued to the same partition address. If they are issued to

different partitions, the second write determines the active partition. Both partitions will output status

information when read.

5. If the WSM is active, both cycles of a 2-cycle command are ignored. This differs from previous Intel devices.

6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy,

Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm

Suspend, Pgm Suspend In Erase Suspend).

7. EFP writes are allowed only when status register bit SR.0=0. EFP is busy if Block Address = address at EFP

Confirm command. Any other commands are treated as data.

8. The "current state" is that of the WSM, not the partition.

9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the

operation and then move to the Ready State.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Appendix B Common Flash Interface

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

B.1

B.2

Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.

This section describes the device’s CFI-compliant interface that allows access to Query data.

Query data are presented on the lowest-order data outputs (DQ[7:0]) only. The numerical offset

value is the address relative to the maximum bus width supported by the device. On this family of

devices, the Query table device starting address is a 10h, which is a word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on

the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper

bytes. The device outputs ASCII “Q” in the low byte (DQ[7:0]) and 00h in the high byte

(DQ[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is “00h,” the

leading “00” has been dropped from the table notation and only the lower byte value is shown. Any

x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Query Structure Overview

The Read Query command causes the flash component to display the CFI Query structure or

“database.” The structure subsections and address locations are summarized below.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B1. Query Structure

Offset

Subsection

Description⁽¹⁾

00h

01h

Manufacturer Code

Device Code

BBA + 02h⁽²⁾

04h to 0Fh

10h

Block Status Register

Reserved

Block-specific information

Reserved for vendor-specific information

Command set ID and vendor data offset

Device timing and voltage information

Flash device layout

CFI Query identification string

System interface information

Device geometry definition

1Bh

27h

Addition vendor-defined information specific

to the Primary Vendor Algorithm

P⁽³⁾

Primary Intel-specific Extended Query Table

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BBA = Block Base Address beginning location (i.e., 08000h is block 1’s beginning location when the block

size is 32K-word).

3. Offset 15h defines “P” which points to the Primary Intel-specific Extended Query Table.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

B.3

CFI Query Identification String

The Identification String provides verification that the component supports the CFI specification. It

also indicates the specification version and supported vendor-specified command set(s).

Table B2. CFI Identification

Address

Offset

Description

Data

Value

CFI Identification

10h

51h

52h

59h

03h

00h

39h

00h

‘Q’

‘R’

‘Y’

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

Query unique ASCII string “QRY”

Primary vendor command set and control interface ID code. 16-bit ID

code for vendor-specified algorithms

Extended Query Table primary algorithm address.

(Denotes the starting offset address for the vendor-specific query table.)

Alternate vendor command set and control interface ID code. 0000h

means no second vendor-specified algorithm exists

Secondary algorithm Extended Query Table address. 0000h means none

exists.

System Interface Information

Vcc logic supply minimum program/erase voltage

DQ[7:4] = Volts (BCD)

DQ[3:0] = 100mV (BCD)

1Bh

1Ch

1Dh

1Eh

17h

19h

B4h

C6h

1.7 V

1.9 V

Vcc logic supply maximum program/erase voltage

DQ[7:4] = Volts (BCD)

DQ[3:0] = 100mV (BCD)

Vcc programming supply minimum program/erase voltage

DQ[7:4] = Volts (BCD)

DQ[3:0] = 100mV (BCD)

11.4 V

Vcc programming supply minimum program/erase voltage

DQ[7:4] = Volts (HEX)

DQ[3:0] = 100mV (BCD)

12.6 V

16 µs

1Fh

20h

21h

22h

23h

24h

25h

26h

n such that typical single-word program time-out = 2ⁿµs

n such that typical buffer write time-out = 2ⁿµs

n such that typical block erase time-out = 2ⁿms

n such that typical full-chip erase time-out = 2ⁿms

n such that max single-word program time-out = 2ⁿµs

n such that max buffer write time-out = 2ⁿµs

04h

00h

0Ah

00h

04h

00h

03h

00h

1 s

256 µs

8 s

n such that max block erase time-out = 2ⁿms

n such that max full-chip erase time-out = 2ⁿms

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B2. CFI Identification (Continued)

Address

Offset

Description

Data

Value

Device Geometry Definition

16h

17h

18h

32Mbit

64Mbit

128Mbit

27h

Flash density: 2ⁿbytes

28h

29h

2Ah

2Bh

Data bus width (low byte): 00h=x8, 01h=x16, 02h=x32, 03h=x64

Data bus width (high byte): not used

01h

00h

x16

Write buffer size: 2ⁿbytes

Number of erase block regions (x) within device:

1. x = 0 means no erase blocking; the device erases in bulk

2Ch

02h

2. x specifies the number of device regions with one or more contiguous

same-size erase blocks.

3. Symmetrically blocked partition

2Dh

2Eh

2Fh

Erase Block Region 1 Information

Bits 0–15 = y, y+1 = number of identical-size erase blocks

Bits 16–31 = z, region erase block(s) size are z x 256 bytes

See Description

BPD: 00200007h

TPD: 32Mb = 0100 003Eh, 64Mb = 0100 007Eh, 128Mb = 0100 00FEh

30h

31h

32h

33h

34h

35h

36h

37h

38h

Erase Block Region 2 Information

Bits 0–15 = y, y+1 = number of identical-size erase blocks

Bits 16–31 = z, region erase block(s) size are z x 256 bytes

BPD: 32Mb = 0100 003Eh, 64Mb = 0100 007Eh, 128Mb = 0100 00FEh

TPD: 0020 0007h

Reserved for future erase block region information

Primary Vendor-Specific Extended Query

39h⁽¹⁾

50h

52h

49h

31h

33h

‘P’

‘R’

‘I’

3Ah

3Bh

3Ch

3Dh

Primary Extended Query Table, Unique ASCII string: “PRI”

Major version number, ASCII

Minor version number, ASCII

‘1’

‘3’

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B2. CFI Identification (Continued)

Address

Offset

Description

Data

Value

3Eh

3Fh

40h

Optional feature and command support:

66h

03h

00h

Bit Feature

0 - Full chip erase

1 - Erase suspend

bit 0=no

bit 1=yes

bit 2=yes

bit 3=no

bit 4=no

bit 5=yes

bit 6=yes

bit 7=no

bit 8=yes

bit 9=yes

2 - Program Suspend

3 - Legacy lock/unlock

4 - Queued erase

5 - Instant individual block locking

6 - Protection bits

7 - Pagemode read

8 - Synchronous read

9 - Simultaneous operations

41h

00h

bits 10-31 are Reserved.

Supported functions after Program/Erase Suspend (besides Read Array,

Read Status, and Read Query):

42h

01h

bit 0=yes

Bit Feature

0 - Program after Erase Suspend

Block Status Register Mask (bits 2-16 are reserved)

bit 0=yes

bit 1=yes

43h

44h

03h

00h

Bit Feature

0 - Block Lock status active

1 - Block Lock-down status active

Highest V Supported:

45h

46h

Bits 0-3 : 100mV (BCD)

Bits 4-7 : Volts (BCD)

18h

C0h

1.8 V

Highest V Supported:

Bits 0-3 : 100mV (BCD)

Bits 4-7 : Volts (HEX)

12.0 V

Protection Register Information

Number of protection register fields in JEDEC ID space.

‘00h’ indicates that 256 fields are available

47h

01h

48h

49h

5Ah

5Bh

80h

00h

03h

Protection Field 1: Protection Description

0080h

Bits 0-7 : Lower byte of protection register address

Bits 8-15 : Upper byte of protection register address

Bits 16-23 : 2ⁿbytes in factory pre-programmed region

Bits 24-31 : 2ⁿbytes in user-programmable region

8 bytes

Burst Read Information

Page Mode Read Buffer Size

BIts 0-7 : 2ⁿbytes in read page-mode buffer

(00h indicates no page buffer exists for reads)

5Ch

5Dh

00h

03h

None

Number of Synchronous Read configurations fields that follow. 00h

indicates no burst capability

3 fields

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B2. CFI Identification (Continued)

Address

Offset

Description

Data

Value

Synchronous Read Field 1

5Eh

Bits 0-1 : 2ⁿ⁺¹words per synchronous read

Bits 2-7 : Reserved

01h

4-words

Synchronous Read Field 2

Bits 0-1 : 2ⁿ⁺¹words per synchronous read

Bits 2-7 : Reserved

5Fh

60h

02h

07h

8-words

Synchronous Read Field 3

Bits 0-1 : 2ⁿ⁺¹words per synchronous read

Continuous

Bits 2-7 : Reserved

Table B3. Partition and Erase Block Region Information

Bottom-Parameter

Top-Parameter

Feature Description

128

Mbit

128

Mbit

Adrs

32 Mbit 62 Mbit

Adrs

32 Mbit 64 Mbit

Number of device hardware partition regions

51h

n = number of partition regions containing one or more contiguous erase

block regions

Partition Region 1 Information

52h

53h

52h

53h

Number of identical partitions within partition region 1

Number of program or erase operations allowed in partition region 1:

54h

55h

54h

55h

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

Number of program or erase operations allowed in other partitions while

a partition in this region is Programming

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

Number of program or erase operations allowed in other partitions while

a partition in this region is Erasing

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

56h

57h

56h

57h

Types of erase block regions in partition region 1

n = number of erase block regions w/ contiguous same-size erase locks.

Symmetrically blocked partitions have one blocking region.

58h

59h

5Ah

5Bh

5Ch

5Dh

58h

59h

5Ah

5Bh

5Ch

5Dh

Partition Region 1 Erase Block Type 1 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

Partition Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

Partition Region 1 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved

5Eh

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B3. Partition and Erase Block Region Information (Continued)

Bottom-Parameter

Top-Parameter

Feature Description

128

Mbit

128

Mbit

Adrs

32 Mbit 62 Mbit

Adrs

32 Mbit 64 Mbit

Partition Region 1 (Erase Block Type 1): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

5Fh

60h

61h

62h

63h

64h

65h

Partition Region 1 Erase Block Type 2 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

Partition Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000

Partition Regions 1 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved

66h

Partition Region 1 (Erase Block Type 2): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

67h

Partition Region 2 Information

68h

69h

60h

61h

Number of identical partitions within partition region 2

Number of program or erase operations allowed in partition region 2:

6Ah

6Bh

62h

63h

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

Number of program or erase operations allowed in other partitions while

a partition in this region is Programming

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

Number of program or erase operations allowed in other partitions while

a partition in this region is Erasing

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations

6Ch

6Dh

64h

65h

Types of erase block regions in partition region 2

n = number of erase block regions w/ contiguous same-size erase locks.

Symmetrically blocked partitions have one blocking region.

6Eh

6Fh

70h

71h

72h

73h

66h

67h

68h

69h

6Ah

6Bh

Partition Region 2 Erase Block Type 1 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

Partition Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000

Partition Region 2 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved

74h

6Ch

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Table B3. Partition and Erase Block Region Information (Continued)

Bottom-Parameter

Top-Parameter

Feature Description

128

Mbit

128

Mbit

Adrs

32 Mbit 62 Mbit

Adrs

32 Mbit 64 Mbit

Partition Region 2 (Erase Block Type 1): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

75h

6Dh

6Eh

6Fh

70h

71h

72h

73h

Partition Region 2 Erase Block Type 2 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

Partition Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

Partition Region 2 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved

74h

Partition Region 2 (Erase Block Type 2): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

75h

Feature Space definitions : Reserved

Reserved

76h

77h

76h

77h

NOTES:

1. The variable P is a pointer which is defined at CFI offset 15h.

2. For a 16Mb the 1.8 Volt Intel^®Wireless Flash memory z1 = 0100h = 256

y1+1 = 24

256²= 64K, y1 = 17h = 23d

24 * 64K = 1½MB

Partition 2’s offset is 0018 0000h bytes (000C 0000h words).

3. TPD - Top parameter device; BPD - Bottom parameter device.

4. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains

all the partitions that are made up of main blocks only. B. contains the partition that is made up of the

parameter and the main blocks.

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Appendix C Mechanical Specifications

C.4

The 1.8 Volt Intel^®Wireless Flash memory 56 Active Ball

Matrix (7x8) 0.75 mm Ball Pitch Package Specifications

7 x 8 Ball Matrix

Note 3

Mechanical Specifications

D (Width)⁽¹⁾

(± 0.1 mm)

E (Length)⁽²⁾

(± 0.1 mm)

Height

(max)

Pkg Type

Density

VF BGA

32 Mbit

64 Mbit

128 Mbit

7.7 mm

12.5 mm

9.0 mm

12.0 mm

1.0 mm

µBGA* CSP

VF BGA

NOTES:

1. 8 Ball direction of the matrix runs parallel to this dimension

2. 7 Ball direction of the matrix runs parallel to this dimension

3. 4 outrigger support balls on 128-Mbit density only

Preliminary

1.8 Volt Intel^®Wireless Flash Memory (W18)

Appendix D Ordering Information

Component Ordering Information

F 6 4 0

1 8 T 7 0

G T 2 8

Package Designator

Extended Temperature

(-25°C to +85°C)

Access Speed (ns)

(70, 85, 90)

GT = .75mm µBGA*

GE = .75mm VFBGA

56-Ball 7x8 matrix

Parameter Parition

T = Top Parameter

Device

B = Bottom Parameter

Device

Product line designator

for all Intel^®Flash products

Device Density

Product Family

320 = x16 (32-Mbit)

640 = x16 (64-Mbit)

128 = x16 (128-Mbit)

W18 = 1.8 Volt Intel®

Wireless Flash Memory

V_CC= 1.7 V - 1.95 V

V_CCQ= 1.7 V - 2.24 V

Preliminary

GT28F640W18B70 [NUMONYX]

相关型号：

GT28F640W18B85

GT28F640W18B90

GT28F640W18BC60

GT28F640W18BC70

GT28F640W18BC80

GT28F640W18BC85

GT28F640W18BD60

GT28F640W18BD80

GT28F640W18T70

GT28F640W18T85

GT28F640W18TC60

GT28F640W18TC80