JS28F128J3D75B [NUMONYX]
Flash, 8MX16, 75ns, PDSO56, 14 X 20 MM, LEAD FREE, TSOP-56;型号: | JS28F128J3D75B |
厂家: | NUMONYX B.V |
描述: | Flash, 8MX16, 75ns, PDSO56, 14 X 20 MM, LEAD FREE, TSOP-56 光电二极管 内存集成电路 存储 闪存 |
文件: | 总66页 (文件大小:959K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Intel Embedded Flash Memory (J3 v. D)
32, 64, 128, and 256 Mbit (Monolithic)
Datasheet
Product Features
Architecture
Security
— Symmetrical 128-Kbyte blocks
— 256 Mbit (256 blocks)
— 128 Mbit (128 blocks)
— 64 Mbit (64 blocks)
— 32 Mbit (32 blocks)
— Enhanced security options for code
protection
— 128-bit Protection Register:
64-bits Unique device identifier bits
64-bits User-programmable OTP bits
— Absolute protection with VPEN = GND
— Individual block locking
Performance
— Block erase/program lockout during power
transitions
— 75 ns Initial Access Speed (32,64,128
Mbit densities)
— 95 ns Initial Access Speed (256Mbit only)
— 25 ns 8-word and 4-word Asynchronous
page-mode reads
Software
— Program and erase suspend support
— Flash Data Integrator (FDI), Common Flash
Interface (CFI) Compatible
— 32-Byte Write buffer;
4 µs per Byte Effective programming time
Quality and Reliability
System Voltage
— Operating temperature:
-40 °C to +85 °C
— 100K Minimum erase cycles per block
— 0.13 µm ETOX™ VIII Process technology
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Packaging
— 56-Lead TSOP (32, 64, 128, 256 Mbit)
— 64-Ball Intel® Easy BGA package (32, 64,
128 and 256 Mbit)
Document Number: 316577-006
December 2007
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All Rights Reserved.
Datasheet
2
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Contents
1.0 Introduction..............................................................................................................6
1.1
1.2
1.3
Nomenclature.....................................................................................................6
Acronyms...........................................................................................................6
Conventions .......................................................................................................7
2.0 Functional Overview..................................................................................................8
2.1
2.2
Block Diagram .................................................................................................. 10
Memory Map..................................................................................................... 11
3.0 Package Information...............................................................................................12
3.1
3.2
56-Lead TSOP Package, 32-, 64-, 128-, and 256-Mbit............................................ 12
Easy BGA Package, 32-, 64-, 128-, and 256-Mbit ..................................................13
4.0 Ballouts and Signal Descriptions.............................................................................. 15
4.1
4.2
4.3
Easy BGA Ballout, 32-, 64-,128-, 256-Mbit ...........................................................15
56-Lead TSOP Package Pinout, 32-, 64-,128-, 256-Mbit..........................................16
Signal Descriptions............................................................................................ 16
5.0 Maximum Ratings and Operating Conditions............................................................ 18
5.1
5.2
5.3
Absolute Maximum Ratings.................................................................................18
Operating Conditions .........................................................................................18
Power Up/Down ................................................................................................18
5.3.1 Power-Up/Down Characteristics................................................................18
5.3.2 Power Supply Decoupling ........................................................................19
Reset...............................................................................................................19
5.4
6.0 Electrical Characteristics .........................................................................................20
6.1
6.2
6.3
DC Current Specifications................................................................................... 20
DC Voltage specifications.................................................................................... 21
Capacitance......................................................................................................22
7.0 AC Characteristics ................................................................................................... 23
7.1
7.2
7.3
7.4
Read Specifications............................................................................................ 24
Program, Erase, Block-Lock Specifications ............................................................ 29
Reset Specifications........................................................................................... 29
AC Test Conditions ............................................................................................ 30
8.0 Bus Interface........................................................................................................... 31
8.1
Bus Reads........................................................................................................32
8.1.1 Asynchronous Page Mode Read ................................................................32
8.1.1.1 Enhanced Configuration Register.................................................32
8.1.2 Output Disable.......................................................................................33
Bus Writes........................................................................................................33
Standby........................................................................................................... 34
8.3.1 Reset/Power-Down.................................................................................34
Device Commands............................................................................................. 34
8.2
8.3
8.4
9.0 Flash Operations ..................................................................................................... 36
9.1
Status Register .................................................................................................36
9.1.1 Clearing the Status Register .................................................................... 37
Read Operations ...............................................................................................37
9.2.1 Read Array............................................................................................ 37
9.2.2 Read Status Register .............................................................................. 38
9.2.3 Read Device Information.........................................................................38
9.2.4 CFI Query ............................................................................................. 38
Programming Operations.................................................................................... 38
9.2
9.3
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Datasheet
3
Intel® Embedded Flash Memory (J3 v. D)
9.3.1 Single-Word/Byte Programming................................................................38
9.3.2 Buffered Programming ............................................................................39
Block Erase Operations.......................................................................................40
Suspend and Resume.........................................................................................41
Status Signal ....................................................................................................42
Security and Protection.......................................................................................43
9.7.1 Normal Block Locking..............................................................................43
9.7.2 Configurable Block Locking.......................................................................44
9.7.3 OTP Protection Registers..........................................................................44
9.7.4 Reading the OTP Protection Register..........................................................44
9.7.5 Programming the OTP Protection Register..................................................44
9.7.6 Locking the OTP Protection Register ..........................................................44
9.7.7 VPP/ VPEN Protection ..............................................................................46
9.4
9.5
9.6
9.7
10.0 ID Codes..................................................................................................................47
11.0 Device Command Codes ...........................................................................................48
12.0 Flow Charts..............................................................................................................49
13.0 Common Flash Interface..........................................................................................58
13.1 Query Structure Output ......................................................................................58
13.2 Query Structure Overview...................................................................................59
13.3 Block Status Register .........................................................................................60
13.4 CFI Query Identification String ............................................................................60
13.5 System Interface Information..............................................................................61
13.6 Device Geometry Definition.................................................................................61
13.7 Primary-Vendor Specific Extended Query Table......................................................62
A
B
Additional Information.............................................................................................64
Ordering Information...............................................................................................65
Datasheet
4
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Revision History
Date
Revision Description
February 2007
001
Initial release
Revised the following graphics to support 256Mbit:
•
Figure 1, “Intel® Embedded Flash Memory (J3 v. D) Memory Block Diagram (32, 64 and
128, 256Mbit)” on page 10.
March 2007
002
•
•
Figure 5, “Easy BGA Ballout (32/64/128/256 Mbit)” on page 15.
Figure 28, “Decoder for Discrete Family, 32-, 64-, 128-, 256-Mbit (monolithic)” on
page 67.
May 2007
003
004
005
006
Minor revisions
August 2007
Updated title page to reflect a 256-Mbit monolithic die.
Updated the 65nm pre-enabling information
Revised the Signal Description Table and clarified Chip Enable (CE) definitions
November 2007
December 2007
December 2007
Document Number: 316577-006
Datasheet
5
Intel® Embedded Flash Memory (J3 v. D)
1.0
Introduction
This document contains information pertaining to the Intel® Embedded Flash Memory
(J3 v. D) device features, operation, and specifications.
The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved
mainstream performance with enhanced security features, taking advantage of the
high quality and reliability of the NOR-based Intel 0.13 µm ETOX™ VIII process
technology. Offered in 256-Mbit, 128-Mbit, 64-Mbit, and 32-Mbit densities, theIntel®
Embedded Flash Memory (J3 v. D)device brings reliable, low-voltage capability (3 V
read, program, and erase) with high speed, low-power operation. The Intel® Embedded
Flash Memory (J3 v. D) device takes advantage of proven manufacturing experience
and is ideal for code and data applications where high density and low cost are
required, such as in networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.Intel® Flash Memory components also deliver a new
generation of forward-compatible software support. By using the Common Flash
Interface (CFI) and Scalable Command Set (SCS), customers can take advantage of
density upgrades and optimized write capabilities of future Intel® Flash Memory
devices.
The J3v.D product family is also planned on the Intel 65nm process lithography, 65nm
AC timing changes are noted in this datasheet and should be taken into account for all
new designs.
1.1
Nomenclature
All Densities
All Densities
32 Mbit
AMIN = A0 for x8
AMIN = A1 for x16
AMAX = A21
AMIN
AMAX
64 Mbit
AMAX = A22
128 Mbit
256 Mbit
AMAX = A23
AMAX = A24
Block
Clear
Program
Set
A group of flash cells that share common erase circuitry and erase simultaneously.
Indicates a logic zero (0)
Writes data to the flash array
Indicates a logic one (1)
VPEN
VPEN
Refers to a signal or package connection name
Refers to timing or voltage levels
1.2
Acronyms
CUI
OTP
PLR
Command User Interface
One Time Programmable
Protection Lock Register
Datasheet
6
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
PR
Protection Register
PRD
RFU
SR
Protection Register Data
Reserved for Future Use
Status Register
SRD
WSM
ECR
Status Register Data
Write State Machine
Enhanced Configuration Register
1.3
Conventions
h:
Hexadecimal Suffix
1,000
k (noun):
M (noun):
Nibble
Byte:
1,000,000
4 bits
8 bits
Word:
Kword:
Kb:
16 bits
1,024 words
1,024 bits
1,024 bytes
1,048,576 bits
1,048,576 bytes
KB:
Mb:
MB:
Brackets:
Square brackets ([]) will be used to designate group membership or to
define a group of signals with similar function (i.e. A[21:1], SR[4,1]
and D[15:0]).
00FFh:
Denotes 16-bit hexadecimal numbers
00FF 00FFh: Denotes 32-bit hexadecimal numbers
DQ[15:0]: Data I/O signals
December 2007
Document Number: 316577-006
Datasheet
7
Intel® Embedded Flash Memory (J3 v. D)
2.0
Functional Overview
The Intel® Embedded Flash Memory (J3 v. D) family contains high-density memory
organized in any of the following configurations:
• 32 Mbytes or 16 Mwords (256-Mbit), organized as two-hundred-fifty-six 128-Kbyte
erase blocks.
• 16 Mbytes or 8 Mwords (128-Mbit), organized as one-hundred-twenty-eight 128-
Kbyte erase blocks.
• 8 Mbytes or 4 Mwords (64-Mbit), organized as sixty-four 128-Kbyte erase blocks.
• 4 Mbytes or 2 Mwords (32-Mbit), organized as thirty-two 128-Kbyte erase blocks.
These devices can be accessed as 8- or 16-bit words. See Figure 1, “Memory Block
Diagram, 32-, 64-, 128-, and 256-Mbit (monolithic)” on page 10 for further details.
A 128-bit Protection Register has multiple uses, including unique flash device
identification.
The Intel® Embedded Flash Memory (J3 v. D) device includes new security features
that were not available on the (previous) 0.25µm and 0.18µm versions of the J3 family.
These new security features prevent altering of code through different protection
schemes that can be implemented, based on user requirements.
The Intel® Embedded Flash Memory (J3 v. D) optimized architecture and interface
dramatically increases read performance by supporting page-mode reads. This read
mode is ideal for non-clock memory systems.
Its Common Flash Interface (CFI) permits software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
The Scalable Command Set (SCS) allows a single, simple software driver in all host
systems to work with all SCS-compliant flash memory devices, independent of system-
level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally,
SCS provides the highest system/device data transfer rates and minimizes device and
system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence written to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one
second, independent of other blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software to suspend block erase to
read or program data from any other block. Similarly, program suspend allows system
software to suspend programming (byte/word program and write-to-buffer operations)
to read data or execute code from any other block that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum
programming performance. By using the Write Buffer data is programmed more
efficiently in buffer increments.
Datasheet
8
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Memory Blocks are selectively and individually lockable in-system. Individual block
locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase
and program operations. Lock-bit configuration operations set and clear lock-bits (using
the Set Block Lock-Bit and Clear Block Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design
(see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31)
reduces decoder logic typically required for multi-chip designs. External logic is not
required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM
module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
byte.
• BYTE#-high enables16-bit operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care).
Figure 1, “Memory Block Diagram, 32-, 64-, 128-, and 256-Mbit (monolithic)” on
page 10 shows a device block diagram.
When the device is disabled (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128-
and 256-Mb” on page 31), with CEx at VIH and RP# at VIH, the standby mode is
enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is
required from RP# going high until data outputs are valid. Likewise, the device has a
wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at
VIL, the WSM is reset and the Status Register is cleared.
December 2007
Document Number: 316577-006
Datasheet
9
Intel® Embedded Flash Memory (J3 v. D)
2.1
Block Diagram
Figure 1.
Memory Block Diagram, 32-, 64-, 128-, and 256-Mbit (monolithic)
DQ0 - DQ15
Output
VCCQ
Input Buffer
Buffer
VCC
Query
I/O Logic
BYTE#
CE0
CE1
CE2
WE#
OE#
RP#
Identifier
Register
CE
Logic
Command
User
Interface
Status
Register
Multiplexer
A - A2
0
Data
Comparator
32-Mbit: A0- A21
64-Mbit: A0 - A22
128-Mbit: A0 - A23
256-Mbit: A0 - A24
Y-Decoder
X-Decoder
Y-Gating
STS
Input Buffer
Write State
Machine
Program /Erase
Voltage Switch
VPEN
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred twenty
eight
Address
Latch
-
VCC
256-Mbit: Two-hundred fifty -six
GND
128 -Kbyte blocks
Address
Counter
Datasheet
10
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
2.2
Memory Map
Figure 2.
Intel® Embedded Flash Memory (J3 v. D) Memory Map
A[24-0]: 256 Mbit
A[24-1]: 256 Mbit
A [23-1]: 128 Mbit
A [22-1]: 64 Mbit
A [21-1]: 32 Mbit
A [23-0]:128 Mbit
A [22-0]: 64 Mbit
A [21-0]: 32 Mbit
1FFFFFF
FFFFFF
128-Kbyte Block
64-Kword Block
255
128-Kbyte Block 127
128-Kbyte Block 63
255
1FE0000
FF0000
0FFFFFF
0FE0000
7FFFFF
7F0000
64-Kword Block 127
07FFFFF
07E0000
3FFFFF
3F0000
64-Kword Block
64-Kword Block
63
31
03FFFFF
03E0000
1FFFFF
1F0000
31
128-Kbyte Block
003FFFF
01FFFF
1
1
0
128-Kbyte Block
64-Kword Block
64-Kword Block
0020000
001FFFF
010000
00FFFF
128-Kbyte Block
0
0000000
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
December 2007
Document Number: 316577-006
Datasheet
11
Intel® Embedded Flash Memory (J3 v. D)
3.0
Package Information
3.1
56-Lead TSOP Package, 32-, 64-, 128-, and 256-Mbit
Figure 3.
56-Lead TSOP Package Mechanical
Z
A
2
See Note 2
See Notes 1 and 3
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Notes:
1.
2.
3.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Table 1.
56-Lead TSOP Dimension Table
Millimeters
Nom
Inches
Nom
Parameter
Symbol
Min
Max
Min
Max
Package Height
Standoff
A
A1
A2
b
1.200
0.047
0.050
0.965
0.100
0.100
18.200
13.800
0.002
0.038
0.004
0.004
0.717
0.543
Package Body Thickness
Lead Width
0.995
0.150
0.150
18.400
14.000
0.500
20.00
0.600
1.025
0.200
0.039
0.006
0.006
0.724
0.551
0.0197
0.787
0.024
0.040
0.008
0.008
0.732
0.559
Lead Thickness
Package Body Length
Package Body Width
Lead Pitch
c
0.200
D1
E
18.600
14.200
e
Terminal Dimension
Lead Tip Length
D
L
19.800
0.500
20.200
0.700
0.780
0.020
0.795
0.028
Datasheet
12
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 1.
56-Lead TSOP Dimension Table
Millimeters
Nom
Inches
Nom
Parameter
Symbol
Min
Max
Min
Max
Lead Count
N
q
Y
Z
56
3°
56
3°
Lead Tip Angle
0°
5°
0°
5°
Seating Plane Coplanarity
Lead to Package Offset
0.100
0.350
0.004
0.014
0.150
0.250
0.006
0.010
3.2
Easy BGA Package, 32-, 64-, 128-, and 256-Mbit
Figure 4.
Easy BGA Mechanical Specifications
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
E
G
H
G
H
e
b
Bottom View - Ball Side Up
Top View - Plastic Backside
Complete Ink Mark Not Shown
A1
A2
A
Seating
Plane
Y
Table 2.
Easy BGA Package Dimensions Table (Sheet 1 of 2)
Millimeters
Inches
Symb
Parameter
ol
Note
s
Min
Nom
Max
Min
Nom
Max
Package Height (32, 64, 128, 256 Mbit)
Ball Height
A
1.200
0.0472
A1
A2
b
0.250
0.330
0.0098
0.0130
Package Body Thickness (32, 64, 128, 256 Mbit)
Ball (Lead) Width
0.780
0.430
0.0307
0.0169
0.530
0.0209
December 2007
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Datasheet
13
Intel® Embedded Flash Memory (J3 v. D)
Table 2.
Easy BGA Package Dimensions Table (Sheet 2 of 2)
Millimeters
Inches
Nom
Symb
ol
Parameter
Note
s
Min
Nom
Max
Min
Max
Package Body Width
Package Body Length
Pitch
D
9.900
10.000
13.000
1.000
64
10.100
13.100
1
0.3898
0.5079
0.3937
0.5118
0.0394
64
0.3976
0.5157
E
12.900
1
[e]
N
Ball (Lead) Count
Seating Plane Coplanarity
Y
0.100
1.600
0.0039
0.0630
Corner to Ball A1 Distance Along D (32/64/128/
256 Mb)
S1
S2
1.400
2.900
1.500
3.000
1
1
0.0551
0.1142
0.0591
0.1181
Corner to Ball A1 Distance Along E (32/64/128/
256 Mb)
3.100
0.1220
Notes:
1.
For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at:
www.intel.com/design/packtech/index.htm
Datasheet
14
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
4.0
Ballouts and Signal Descriptions
Intel® Embedded Flash Memory (J3 v. D) is available in two package types. All
densities of the Intel® Embedded Flash Memory (J3 v. D) devices are supported on
both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. The
figures below show the ballouts.
4.1
Easy BGA Ballout, 32-, 64-,128-, 256-Mbit
Figure 5.
Easy BGA Ballout (32/64/128/256 Mbit)
5
8
8
5
1
2
3
4
6
7
7
6
4
3
2
1
A
B
C
D
A
A1
A6 A8 VPEN A13 VCC A18 A22
A22 A18 VCC A13 VPEN A8
A6
A1
B
C
A2 VSS A9 CE0 A14 RFU A19 CE1
CE1 A19 RFU A14 CE0 A9 VSS A2
A3
A4
D8
A7 A10 A12 A15 RFU A20 A21
A5 A11 RP# RFU RFU A16 A17
A21 A20 RFU A15 A12 A10
A7
A3
A4
D8
D
E
A17 A16 RFU RFU RP# A11 A5
E
F
D1 D9
D3
D4 RFU D15 STS
STS D15 RFU D4
D3
D9
D1
F
BYTE# D0 D10 D11 D12 RFU RFU OE#
OE# RFU RFU D12 D11 D10 D0 BYTE#
G
H
G
A23 A0 D2 VCCQ D5 D6 D14 WE#
128M
WE# D14 D6 D5 VCCQ D2 A0 A23
128M
H
CE2 RFU VCC VSS D13 VSS D7 A24
A24 D7 VSS D13 VSS VCC RFU CE2
256M 256M
Easy BGA
Easy BGA
Top View- Ball side down
Bottom View- Ball side up
Notes:
1.
2.
3.
Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
Address A24 is only valid on 256-Mbit density, otherwise, it is a no connect (NC).
December 2007
Document Number: 316577-006
Datasheet
15
Intel® Embedded Flash Memory (J3 v. D)
4.2
56-Lead TSOP Package Pinout, 32-, 64-,128-, 256-Mbit
Figure 6.
56-Lead TSOP Package Pinout (32/64/128/256 Mbit)
A
24
A22
CE
A211
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WE#
OE#
STS
DQ
DQ
DQ
DQ
GND
DQ
DQ
DQ
DQ
VCCQ
GND
DQ
DQ
DQ
DQ
VCC
DQ
DQ
DQ
DQ
A
BYTE#
A
CE
15
7
14
Intel® Embedded Flash Memory
(28FXXXJ3D)
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
13
5
12
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
4
CE
0
VPEN
RP#
A11
11
3
A10
10
A
2
9
32/64/128/256 Mbit
A
8
GND
9
A
1
7
A
8
6
A
0
5
A
0
4
A
3
A
23
2
A
2
1
Notes:
1.
2.
3.
A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC).
A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC)
A24 exists on 256-Mbit densities and on the other densities this signal is a no-connect (NC).
4.3
Signal Descriptions
Table 3 lists the active signals used on Intel® Embedded Flash Memory (J3 v. D) and
provides a description of each.
Table 3.
Signal Descriptions for Intel® Embedded Flash Memory (J3 v. D) (Sheet 1 of 2)
Symbol
Type
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
A0
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
32-Mbit — A[21:1]
64-Mbit— A[22:1]
128-Mbit — A[23:1]
256-Mbit — A[24:1]
A[MAX:1]
D[7:0]
Input
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
Input/
Output
Datasheet
16
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 3.
Signal Descriptions for Intel® Embedded Flash Memory (J3 v. D) (Sheet 2 of 2)
Symbol
Type
Name and Function
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
Input/
Output
D[15:8]
CE[2:0]
RP#
CHIP ENABLE: Activate the 32-, 64-, 128-, and 256-Mbit devices’ control logic, input buffers,
decoders, and sense amplifiers. When the device is de-selected (see Table 16, “Chip Enable Truth
Table for 32-, 64-, 128- and 256-Mb” on page 31), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128-
and 256-Mb” on page 31).
Input
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
Input
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
OE#
WE#
Input
Input
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and Section 9.6, “Status Signal” on page 42. STS is to be tied to VCCQ
with a pull-up resistor.
Open Drain
Output
STS
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
BYTE#
Input
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
VPEN
VCC
Input
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
≤ Vlko
.
Power
Caution: Device operation at invalid Vcc voltages should not be attempted.
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC
GROUND: Ground reference for device logic voltages. Connect to system ground.
No Connect: Lead is not internally connected; it may be driven or floated.
VCCQ
GND
NC
Power
Supply
—
.
Reserved for Future Use: Balls designated as RFU are reserved by Intel for future device
functionality and enhancement.
RFU
—
December 2007
Document Number: 316577-006
Datasheet
17
Intel® Embedded Flash Memory (J3 v. D)
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without
notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Table 4.
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Notes
Temperature under Bias Expanded (TA, Ambient)
–40
–65
–2.0
–2.0
–2.0
—
+85
+125
°C
°C
V
—
—
2
Storage Temperature
VCC Voltage
+5.6
VCCQ
+5.6
V
2
Voltage on any input/output signal (except VCC, VCCQ)
ISH Output Short Circuit Current
Notes:
V
CCQ (max) + 2.0
100
V
1
mA
3
1.
2.
3.
Voltage is referenced to VSS. During infrequent non-periodic transitions, the voltage potential between VSS and input/
output pins may undershoot to –2.0 V for periods < 20 ns or overshoot to VCCQ (max) + 2.0 V for periods < 20 ns.
During infrequent non-periodic transitions, the voltage potential between VCC and the supplies may undershoot to –2.0
V for periods < 20 ns or VSUPPLY (max) + 2.0 V for periods < 20 ns.
Output shorted for no more than one second. No more than one output shorted at a time
5.2
Operating Conditions
Warning:
Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability
Table 5.
Temperature and VCC Operating Condition
Symbol
Parameter
Min
-40.0
Max
Unit
Test Condition
TA
+85
3.6
3.6
°C
V
Ambient Temperature
VCC
VCCQ
VCC Supply Voltage
2.70
2.70
—
—
VCCQ Supply Voltage
V
5.3
Power Up/Down
This section provides an overview of system level considerations with regards to the
flash device. It includes a brief description of power-up, power-down and decoupling
design considerations.
5.3.1
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the
power-up/power-down sequence shown in Table 6 is recommended. For DC voltage
characteristics refer to Table 8. Note that each power supply must reach its minimum
voltage range before applying/removing the next supply voltage.
Datasheet
18
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 6.
Power-Up/Down Sequence
Power Supply
Power-UpSequence
Power-Down Sequence
Voltage
VCC(min)
VCCQ(min)
VPEN(min)
1st
2nd
3rd
1st
3rd
2nd
1st
2nd
1st†
2nd†
Sequencingnot
required†
Sequencingnot
required†
2nd†
1st†
2nd
1st
† Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RP# should be low during power transitions.
5.3.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized,
charge pumps are switched on, and internal voltage nodes are ramped. All of this
internal activities produce transient signals. The magnitude of the transient signals
depends on the device and system loading. To minimize the effect of these transient
signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal.
Capacitors should be placed as close as possible to device connections.
Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be
placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor
should help overcome voltage slumps caused by PCB trace inductance.
5.4
Reset
By holding the flash device in reset during power-up and power-down transitions,
invalid bus conditions may be masked. The flash device enters reset mode when RP# is
driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-
impedance state. After return from reset, a certain amount of time is required before
the flash device is able to perform normal operations. After return from reset, the flash
device defaults to asynchronous page mode. If RP# is driven low during a program or
erase operation, the program or erase operation will be aborted and the memory
contents at the aborted block or address are no longer valid. See Figure 14, “AC
Waveform for Reset Operation” on page 29 for detailed information regarding reset
timings.
December 2007
Document Number: 316577-006
Datasheet
19
Intel® Embedded Flash Memory (J3 v. D)
6.0
Electrical Characteristics
6.1
DC Current Specifications
Table 7.
DC Current Characteristics (Sheet 1 of 2)
VCCQ
VCC
Parameter
2.7 - 3.6V
2.7 - 3.6V
Test Conditions
Notes
Symbol
Typ
Max
Unit
VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or VSS
ILI
Input and VPEN Load Current
Output Leakage Current
1
μA
μA
1
1
VCC= VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or VSS
ILO
10
CMOS Inputs, VCC = VCC Max; Vccq =
VccqMax
32, 64, 128, 256
Device is disabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31),
50
120
μA
Mbit
RP# = VCCQ ± 0.2 V
ICCS
VCC Standby Current
1,2,3
TTL Inputs, VCC = VCC Max,
Vccq = VccqMax
32, 64, 128, 256
Mbit
0.71
50
2
mA
Device is disabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31), RP# = VIH
ICCD
VCC Power-Down Current
120
μA
RP# = GND ± 0.2 V, IOUT (STS) = 0 mA
CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ
Max
Device is enabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31)
15
24
20
29
mA
mA
f = 5 MHz, IOUT = 0 mA
4-Word
Page
CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ
Max
Device is enabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31)
1,3
f = 33 MHz, IOUT = 0 mA
ICCR
CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads.
VCC Page Mode Read Current
10
30
15
54
mA
mA
Device is enabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31)
f = 5 MHz, IOUT = 0 mA
8-Word Page
CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads.
Device is enabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31)
f = 33 MHz, IOUT = 0 mA
35
40
60
70
mA
mA
CMOS Inputs, VPEN = VCC
TTL Inputs, VPEN = VCC
VCC Program or Set
ICCW
1,4
Lock-Bit Current
Datasheet
20
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 7.
DC Current Characteristics (Sheet 2 of 2)
VCCQ
VCC
Parameter
2.7 - 3.6V
2.7 - 3.6V
Test Conditions
Notes
Symbol
Typ
35
Max Unit
VCC Block Erase or
Clear Block Lock-Bits
Current
70
80
mA
mA
CMOS Inputs, VPEN = VCC
ICCE
1,4
1,5
40
TTL Inputs, VPEN = VCC
VCC Program
Suspend or Block
Erase Suspend
Current
Device is enabled (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31)
ICCWS
ICCES
10
mA
Notes:
1.
All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and
speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical
specifications.
Includes STS.
2.
3.
4.
5.
CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH
Sampled, not 100% tested.
ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend
mode, the device’s current draw is ICCR and ICCWS
.
.
6.2
DC Voltage specifications
Table 8.
DC Voltage Characteristics (Sheet 1 of 2)
VCCQ
VCC
Parameter
2.7 - 3.6 V
2.7 - 3.6 V
Test Conditions
Notes
Symbol
Min
Max
Unit
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
2.0
0.8
V
V
2, 5, 6
2, 5, 6
VCCQ + 0.5V
VCC = VCCMin
0.4
0.2
V
V
V
VCCQ = VCCQ Min
IOL = 2 mA
VOL
Output Low Voltage
Output High Voltage
1, 2
VCC = VCCMin
VCCQ = VCCQ Min
IOL = 100 µA
VCC = VCCMIN
VCCQ = VCCQ Min
IOH = –2.5 mA
0.85 × VCCQ
VOH
1, 2
2, 3
VCC = VCCMIN
VCCQ = VCCQ Min
IOH = –100 µA
VCCQ – 0.2
V
V
VPEN Lockout during Program,
Erase and Lock-Bit Operations
VPENLK
2.2
December 2007
Document Number: 316577-006
Datasheet
21
Intel® Embedded Flash Memory (J3 v. D)
Table 8.
DC Voltage Characteristics (Sheet 2 of 2)
VCCQ
VCC
Parameter
2.7 - 3.6 V
2.7 - 3.6 V
Max
Test Conditions
Notes
Symbol
Min
Unit
VPEN during Block Erase, Program,
or Lock-Bit Operations
VPENH
2.7
3.6
2.0
V
V
3
4
VLKO
VCC Lockout Voltage
Notes:
1.
2.
3.
Includes STS.
Sampled, not 100% tested.
Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed
in the range between VPENLK (max) and VPENH (min), and above VPENH (max).
Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in
the range between VLKO (min) and VCC (min), and above VCC (max).
4.
5.
6.
Includes all operational modes of the device including standby and power-up sequences
Input/Output signals can undershoot to -1.0v referenced to VSS and can overshoot to VCCQ = 1.0v for
duration of 2ns or less, the VCCQ valid range is referenced to VSS
.
6.3
Capacitance
Table 9.
Capacitance
Symbol
Parameter1
Type
Max
Unit
Condition2
CIN
Input Capacitance
Output Capacitance
32, 64, 128, 256 Mb
32, 64, 128, 256 Mb
VIN = 0.0 V
6
8
8
pF
pF
COUT
VOUT = 0.0 V
12
Notes:
1.
2.
sampled.not 100% tested.
TA = +25 °C, f = 1 MHZ
Datasheet
22
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention
Figure 7.
Timing Signal Naming Convention
E L Q V
t
Source Signal
Source State
Target State
Target Signal
Figure 8.
Timing Signal Name Decoder
Signal
Code
State
Code
Address
A
Q
D
E
High
H
L
Data - Read
Low
Data - Write
High-Z
Low-Z
Valid
Z
X
V
I
Chip Enable (CE)
Output Enable (OE#)
Write Enable (WE#)
Address Valid (ADV#)
Reset (RP#)
G
W
V
P
Invalid
Clock (CLK)
C
T
WAIT
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s
data sheet, and is the address-to-data delay for subsequent page-mode reads.
December 2007
Document Number: 316577-006
Datasheet
23
Intel® Embedded Flash Memory (J3 v. D)
7.1
Read Specifications
Table 10.
Read Operations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Density
Min
Max
Unit
Notes
32 Mbit
64 Mbit
128 Mbit
256 Mbit
32 Mbit
64 Mbit
128 Mbit
256 Mbit
32 Mbit
64 Mbit
128 Mbit
256 Mbit
All
75
75
75
95
1,2
1,2
R1
tAVAV
Read/Write Cycle Time
ns
1,2
1,2
75
75
1,2
1,2
R2
tAVQV
Address to Output Delay
ns
75
1,2
95
1,2
75
1,2
75
1,2
R3
R4
R5
tELQV
tGLQV
tPHQV
CEX to Output Delay
ns
ns
ns
75
1,2
95
1,2
OE# to Non-Array Output Delay
RP# High to Output Delay
25
1,2,4
1,2
32 Mbit
64 Mbit
128 Mbit
256 Mbit
150
180
210
210
1,2
1,2
1,2
R6
R7
R8
R9
tELQX
tGLQX
tEHQZ
tGHQZ
CEX to Output in Low Z
0
0
ns
ns
ns
ns
1,2,5
1,2,5
1,2,5
1,2,5
OE# to Output in Low Z
CEX High to Output in High Z
OE# High to Output in High Z
25
15
All
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
R10
tOH
0
0
ns
1,2,5
R11
R12
R13
R14
R15
R16
tELFL/ ELFH
t
CEX Low to BYTE# High or Low
10
1
ns
µs
µs
ns
ns
ns
1,2,5
1,2
t
FLQV/tFHQV BYTE# to Output Delay
tFLQZ
tEHEL
tAPA
tGLQV
BYTE# to Output in High Z
CEx High to CEx Low
1
1,2,5
1,2,5
5, 6
All
All
Page Address Access Time
OE# to Array Output Delay
25
25
1,2,4
Notes:
1.
CE low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE high is defined as the first edge of
X X
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on
page 31).
2.
3.
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 16, “Chip
Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31) without impact on tELQV
.
4.
See Figure 15, “AC Input/Output Reference Waveform” on page 30 and Figure 16, “Transient Equivalent Testing Load
Circuit” on page 30 for testing characteristics.
5.
6.
Sampled, not 100% tested.
For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Datasheet
24
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Figure 9.
Single Word Asynchronous Read Waveform
R1
R2
Address [A]
CEx [E]
R3
R8
R9
OE# [G]
WE# [W]
R4
R16
R7
R6
R10
Data [D/Q]
BYTE#[F]
R12
R11
R13
R5
RP# [P]
Notes:
1.
CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined as the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on
page 31).
2.
When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
Figure 10.
4-Word Asynchronous Page Mode Read Waveform
R1
R2
A[MAX:3] [A]
A[2:1] [A]
00
01
10
11
R3
CEx [E]
R4
OE# [G]
WE# [W]
R8
R10
R9
R6
R7
R10
R15
D[15:0] [Q]
RP# [P]
1
2
3
4
R5
Note: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined as the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on
page 31).
December 2007
Document Number: 316577-006
Datasheet
25
Intel® Embedded Flash Memory (J3 v. D)
Figure 11.
8-Word Asynchronous Page Mode Read
R1
R2
A[MAX:4] [A]
A[3:1] [A]
CEx [E]
R3
R4
OE# [G]
WE# [W]
R10
R8
R9
R6
R5
R10
R7
R15
D[15:0] [Q]
1
2
7
8
RP# [P]
BYTE#
Notes:
1.
CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on
page 31).
2.
In this diagram, BYTE# is asserted high
Table 11.
AC Read Specifications differences for 65nm
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Package
Min
Max
Unit
Notes
95
1
1
1
1
1
1
R1
tAVAV
tAVQV
tELQV
Read/Write Cycle Time
ns
TSOP
TSOP
TSOP
105
95
105
95
R2
R3
Address to Output Delay
CEX to Output Delay
ns
ns
105
Notes:
1.
This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs that
will use the 65nm lithography.
Datasheet
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Intel® Embedded Flash Memory (J3 v. D)
C
Table 12.
Write Operations
Valid for All
Speeds
#
Symbol
Parameter
Density
Unit
Notes
Min
Max
32 Mbit
64 Mbit
150
180
210
210
0
1,2,3
W1
tPHWL (tPHEL
)
RP# High Recovery to WE# (CEX) Going Low
128 Mbit
256 Mbit
W2
W3
t
ELWL (tWLEL
tWP
DVWH (tDVEH
)
CEX (WE#) Low to WE# (CEX) Going Low
Write Pulse Width
1,2,4
1,2,4
1,2,5
1,2,5
1,2,
60
50
55
0
W4
t
)
)
Data Setup to WE# (CEX) Going High
Address Setup to WE# (CEX) Going High
CEX (WE#) Hold from WE# (CEX) High
Data Hold from WE# (CEX) High
Address Hold from WE# (CEX) High
Write Pulse Width High
W5
tAVWH (tAVEH
ns
W6
tWHEH (tEHWH
tWHDX (tEHDX
)
W7
)
0
1,2,
All
W8
t
WHAX (tEHAX
tWPH
VPWH (tVPEH
WHGL (tEHGL
)
0
1,2,
W9
30
0
1,2,6
1,2,3
1,2,7
1,2,8
1,2,3,8,9
W11
W12
W13
W15
Notes:
t
t
)
)
)
VPEN Setup to WE# (CEX) Going High
Write Recovery before Read
35
tWHRL (tEHRL
tQVVL
WE# (CEX) High to STS Going Low
VPEN Hold from Valid SRD, STS Going High
500
0
CE low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE high is defined at the first edge of CE0, CE1, or CE2 that
X
X
disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb” on page 31).
1.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
2.
3.
4.
A write operation can be initiated and terminated with either CEX or WE#.
Sampled, not 100% tested.
Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH
.
5.
6.
Refer to Table 17, “Enhanced Configuration Register” on page 33 for valid AIN and DIN for block erase, program, or lock-
bit configuration.
Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going
low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
7.
8.
9.
For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
STS timings are based on STS configured in its RY/BY# default mode.
VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1] =
0).
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Intel® Embedded Flash Memory (J3 v. D)
Figure 12.
Asynchronous Write Waveform
W5
W8
W6
W9
ADDRESS [A]
CEx (WE#) [E (W)]
W2
W3
WE# (CEx) [W (E)]
OE# [G]
W4
W7
DATA [D/Q]
STS[R]
D
W13
W1
RP# [P]
W11
VPEN [V]
Figure 13.
Asynchronous Write to Read Waveform
W5
W8
W6
Address [A]
CE# [E]
W2
W3
WE# [W]
W12
OE# [G]
W4
W7
Data [D/Q]
RST#/ RP# [P]
VPEN [V]
D
W1
W11
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Intel® Embedded Flash Memory (J3 v. D)
7.2
Program, Erase, Block-Lock Specifications
Table 13.
Configuration Performance
#
Symbol
Parameter
Typ
Max(8)
Unit
Notes
Write Buffer Byte Program Time
(Time to Program 32 bytes/16 words)
W16
128
654
µs
1,2,3,4,5,6,7
Byte Program Time (Using Word/Byte Program Command)
for 130nm
40
175
µs
1,2,3,4
tWHQV3
tEHQV3
W16
Byte Program Time (Using Word/Byte Program Command)
for 65nm
125
0.53
1.0
150
2.4
4.0
µs
1,2,3,4
1,2,3,4
1,2,3,4
Block Program Time (Using Write to Buffer Command)
Block Erase Time
sec
sec
tWHQV4
tEHQV4
W16
W16
W16
W16
tWHQV5
tEHQV5
Set Lock-Bit Time
50
0.5
15
60
0.70
20
µs
sec
µs
1,2,3,4,9
1,2,3,4,9
1,2,3,9
tWHQV6
tEHQV6
Clear Block Lock-Bits Time
Program Suspend Latency Time to Read
tWHRH1
tEHRH1
tWHRH
tEHRH
W16
WY
Erase Suspend Latency Time to Read
STS Pulse Width Low Time
15
20
µs
ns
1,2,3,9
1
tSTS
500
Notes:
1.
Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2.
3.
4.
5.
6.
7.
8.
9.
These performance numbers are valid for all speed versions.
Sampled but not 100% tested.
Excludes system-level overhead.
These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
Effective per-byte program time (tWHQV1, tEHQV1) is 4µs/byte (typical).
Effective per-word program time (tWHQV2, tEHQV2) is 8µs/word (typical).
Max values are measured at worst case temperature, data pattern and VCC corner after 100k cycles (except as noted).
Max values are expressed at 25 °C/-40 °C.
7.3
Reset Specifications
Figure 14.
AC Waveform for Reset Operation
STS (R)
P1
P2
RP# (P)
P3
Vcc
Note: STS is shown in its default mode (RY/BY#)
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29
Intel® Embedded Flash Memory (J3 v. D)
Table 14.
Reset Specifications
#
Symbol
tPLPH
tPHRH
Parameter
Min
Max
Unit
Notes
RP# Pulse Low Time
P1
25
µs
1,2
(If RP# is tied to VCC, this specification is not applicable)
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
P2
P3
100
ns
1,3
60
µs
µs
Vcc Power Valid to RP# de-assertion (high) 130nm
Vcc Power Valid to RP# de-assertion (high) 65nm
tVCCPH
300
Notes:
1.
2.
These specifications are valid for all product versions (packages and speeds).
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
valid.
3.
7.4
AC Test Conditions
Figure 15.
AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Figure 16.
Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Note: CL Includes Jig Capacitance
Figure 17.
Test Configuration
Test Configuration
CL (pF)
VCCQ = VCCQMIN
30
Datasheet
30
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Intel® Embedded Flash Memory (J3 v. D)
8.0
Bus Interface
This section provides an overview of Bus operations. Basically, there are three
operations you can do with flash memory: Read, Program (Write), and Erase.The on-
chip Write State Machine (WSM) manages all erase and program algorithms. The
system CPU provides control of all in-system read, write, and erase operations through
the system bus. All bus cycles to or from the flash memory conform to standard
microprocessor bus cycles. Table 15 summarizes the necessary states of each control
signal for different modes of operations.
Table 15.
Bus Operations
STS
(Default
Mode)
OE#(2) WE#(2)
VPEN
DQ15:0
Notes
(1)
(3)
Mode
RP#
CEx
Async., Status, Query and
Identifier Reads
VIH
VIH
VIH
Enabled
Enabled
VIL
VIH
X
VIH
VIH
X
X
X
X
DOUT
High Z
High Z
High Z
High Z
High Z
4,6
Output Disable
Standby
Disable
d
Reset/Power-down
Command Writes
Array Writes(8)
VIL
VIH
VIH
X
X
X
X
X
High Z
DIN
High Z
High Z
VIL
Enabled
Enabled
VIH
VIH
VIL
VIL
6,7
8,5
VPENH
X
Notes:
1.
2.
3.
4.
5.
6.
See Table 16 for valid CEx Configurations.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
RDeQferrefteorsDCtocDhQar[a7c:t0e}riswthicesn. WBYhTeEn#VPisENlow a≤ndVDPEQN[L1K5:0] if BYTE# is high.
, memory contents can be read but not altered.
X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH
.
In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is VOH (pulled up by an external pull up resistance ~= 10k) when the WSM is not busy, in block erase
suspend mode (with programming inactive), program suspend mode, or reset power-down mode.
See Table 19, “Command Bus Operations” on page 35 for valid DIN (user commands) during a Write operation
Array writes are either program or erase operations. /
7.
8.
Table 16.
Chip Enable Truth Table for 32-, 64-, 128- and 256-Mb
CE2
CE1
CE0
DEVICE
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Note: For single-chip applications, CE2 and CE1 can be connected to
.
GND
The next few sections detail each of the basic flash operations and some of the
advanced features available on flash memory.
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Intel® Embedded Flash Memory (J3 v. D)
8.1
Bus Reads
Reading from flash memory outputs stored information to the processor or chipset, and
does not change any contents. Reading can be performed an unlimited number of
times. Besides array data, other types of data such as device information and device
status is available from the flash.
To perform a bus read operation, CEx (refer to Table 16 on page 31) and OE# must be
asserted. CEx is the device-select control; when active, it enables the flash memory
device. OE# is the data-output control; when active, the addressed flash memory data
is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See
Section 9.2, “Read Operations” on page 37.
8.1.1
Asynchronous Page Mode Read
There are two Asynchronous Page mode configurations available on Intel® Embedded
Flash Memory (J3 v. D), depending on the system design requirements:
• Four-Word Page mode: This is the default mode on power-up or reset. Array data
can be sensed up to four words (8 Bytes) at a time.
• Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a
time. This mode must be enabled on power-up or reset by using the command
sequence described in Table 19 on page 35. Address bits A[3:1] determine which
word is output during a read operation, and A[3:0] determine which byte is output
for a x8 bus width.
After the initial access delay, the first word out of the page buffer corresponds to the
initial address. In Four-Word Page mode, address bits A[2:1] determine which word is
output from the page buffer for a x16 bus width, and A[2:0] determine which byte is
output from the page buffer for a x8 bus width. Subsequent reads from the device
come from the page buffer. These reads are output on D[15:0] for a x16 bus width and
D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page
mode) or A[3:0] (Eight-Word Page mode).
Data can be read from the page buffer multiple times, and in any order. In Four-Word
Page mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at
any time, or if CEx# is toggled, the device will sense and load new data into the page
buffer. Asynchronous Page mode is the default read mode on power-up or reset.
To perform a Page mode read after any other operation, the Read Array command must
be issued to read from the flash array. Asynchronous Page mode reads are permitted in
all blocks and are used to access register information. During register access, only one
word is loaded into the page buffer.
8.1.1.1
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile storage register that when
addressed by the Set ECR command can select between Four-Word Page mode and
Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when
RP# is deasserted or power is removed from the device. To modify ECR settings, use
the Set ECR command. The Set ECR command is written along with the configuration
register value, which is placed on the lower 16 bits of the address bus A[15:0]. This is
followed by a second write that confirms the operation and again presents the ECR data
on the address bus. After executing this command, the device returns to Read Array
mode.
The ECR is shown in Table 17. 8-word page mode Command Bus-Cycle is captured in
Table 18.
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Intel® Embedded Flash Memory (J3 v. D)
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on
Intel® Embedded Flash Memory (J3 v. D), a Clear Status Register command must be
executed after issuing the Set ECR command. See Table 18 for further details.
Table 17.
Enhanced Configuration Register
Page
Length
Reserved
Reserved
ECR
15
ECR
14
ECR
13
ECR
12
ECR
11
ECR
10
ECR
9
ECR
8
ECR
7
ECR
6
ECR
5
ECR
4
ECR
3
ECR
2
ECR
1
ECR
0
BITS
DESCRIPTION
NOTES
ECR[15:14]
ECR[13]
RFU
All bits should be set to 0.
All bits should be set to 0.
•
•
“1” = 8 Word Page mode
“0” = 4 Word Page mode
ECR[12:0]
RFU
Table 18.
Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
First Bus Cycle
Addr(1)
Second Bus Cycle
Bus
Command
Cycles
Required
Oper
Data
Oper
Addr(1)
Data
0004h
Set Enhanced Configuration
Register (Set ECR)
2
Write
ECD
0060h
Write
ECD
1.. ECD = Enhanced Configuration Register Data
8.1.2
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled.
Output signals D[15:0] are placed in a high-impedance state.
8.2
Bus Writes
Writing or Programming to the device, is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
• Reading of array data
• Common Flash Interface (CFI) data
• Identifier codes, inspection, and clearing of the Status Register
• Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH
)
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
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Intel® Embedded Flash Memory (J3 v. D)
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables
the device (see Table 16 on page 31). Standard microprocessor write timings are used.
8.3
Standby
CE0, CE1, and CE2 can disable the device (see Table 16 on page 31) and place it in
standby mode. This manipulation of CEx substantially reduces device power
consumption. D[15:0] outputs are placed in a high-impedance state independent of
OE#. If deselected during block erase, program, or lock-bit configuration, the WSM
continues functioning, and consuming active power until the operation completes.
8.3.1
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-
impedance state, and turns off numerous internal circuits. RP# must be held low for a
minimum of tPLPH. Time tPHQV is required after return from reset mode until initial
memory access outputs are valid. After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and Status Register is set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and remains low for a maximum time
of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted after a program or partially
altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When
the system comes out of reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed during Block Erase, Program,
or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the flash memory may be providing status
information instead of array data. Intel® Flash memories allow proper initialization
following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
8.4
Device Commands
When VPEN ≤ VPENLK, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase,
program, and lock-bit configuration operations. Device operations are selected by
writing specific commands to the Command User Interface (CUI). The CUI does not
occupy an addressable memory location. It is the mechanism through which the flash
device is controlled.
A command sequence is issued in two consecutive write cycles - a Setup command
followed by a Confirm command. However, some commands are single-cycle
commands consisting of a setup command only. Generally, commands that alter the
contents of the flash device, such as Program or Erase, require at least two write cycles
to guard against inadvertent changes to the flash device. Flash commands fall into two
categories: Basic Commands and Extended Commands. Basic commands are
recognized by all Intel® Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks.
Extended commands are product-dependant; they are used to perform additional
features such as software block locking. Table 19 describes all applicable commands on
Intel® Embedded Flash Memory (J3 v. D).
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Intel® Embedded Flash Memory (J3 v. D)
Table 19.
Command Bus Operations
Setup Write Cycle
Confirm Write Cycle
Command
Data
Bus
Address Bus
Address Bus
Data Bus
Program Enhanced Configuration Register
Program OTP Register
Register Data
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
0060h
00C0h
0050h
00B8h
00FFh
0070h
0090h
0098h
Register Data
0004h
Register Offset
Register Data
Clear Status Register
---
---
Program STS Configuration Register
Read Array
Device Address
Register Data
---
---
---
---
---
---
---
---
Read Status Register
Read Identifier Codes (Read Device Information)
CFI Query
0040h/
0010h
Word/Byte Program
Device Address
Device Address
Array Data
Buffered Program
Block Erase
Word Address
Block Address
Device Address
00E8h
0020h
00B0h
Device Address
Block Address
---
00D0h
00D0h
---
Program/Erase Suspend
Program/Erase Resume
Lock Block
Device Address
Block Address
00D0h
0060h
---
---
Block Address
0001h
Unlock Block
Device Address
0060h
Device Address
00D0h
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Datasheet
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Intel® Embedded Flash Memory (J3 v. D)
9.0
Flash Operations
This section describes the operational features of flash memory. Operations are
command-based, wherein command codes are first issued to the device, then the
device performs the desired operation. All command codes are issued to the device
using bus-write cycles (see Chapter 8.0, “Bus Interface”). A complete list of available
command codes can be found in Section 11.0, “Device Command Codes” on page 48.
9.1
Status Register
The Status Register (SR) is an 8-bit, read-only register that indicates device status and
operation errors. To read the Status Register, issue the Read Status Register command.
Subsequent reads output Status Register information on DQ[7:0], and 00h on
DQ[15:8].
SR status bits are set and cleared by the device. SR error bits are set by the device, but
must be cleared using the Clear Status Register command. Upon power-up or exit from
reset, the Status Register defaults to 80h. Page-mode reads are not supported in this
read mode. Status Register contents are latched on the falling edge of OE# or the first
edge of CEx that enables the device. OE# must toggle to VIH or the device must be
disabled before further reads to update the Status Register latch. The Read Status
Register command functions independently of VPEN voltage.
Table 20 shows Status Register bit definitions.
Table 20.
Status Register Bit Definitions
Status Register (SR)
Default Value = 80h
Program/
Erase
Voltage
Error
Erase
Ready
Program
Suspend
Status
Erase
Error
Program
Error
Block-Locked
Suspend
Status
Error
Status
7
6
5
4
3
2
1
0
Bit
Name
Ready Status
Description
0 = Device is busy; SR[6:] are invalid (Not driven);
1 = Device is ready; SR[6:0] are valid.
7
6
5
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
Erase Suspend Status
SR.5 SR.4
Erase Error
0
0
1
1
0
1
0
1
= Program or erase operation successful.
= Program error - operation aborted.
= Erase error - operation aborted.
Command
Sequence
Error
Program
Error
4
= Command sequence error - command aborted.
0 = within acceptable limits during program or erase operation.
3
2
Error
1 = not within acceptable limits during program or erase operation. Operation
aborted.
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
Block-Locked Error
0 = Block NOT locked during program or erase - operation successful.
1 = Block locked during program or erase - operation aborted.
1
0
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Intel® Embedded Flash Memory (J3 v. D)
9.1.1
Clearing the Status Register
The Status Register (SR) contain Status and error bits which are set by the device. SR
status bits are cleared by the device, however SR error bits are cleared by issuing the
Clear SR command (see Table 21). Resetting the device also clears the SR.
Table 21.
Clear Status Register Command Bus-Cycle
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
--- ---
Command
Address Bus
Device Address
Data Bus
Clear Status Register
0050h
Issuing the Clear SR command places the device in Read SR mode.
Note:
Care should be taken to avoid SR ambiguity. If a command sequence error occurs while
in an Erase Suspend condition, the SR will indicate a Command Sequence error by
setting SR.4 and SR.5. When the erase operation is resumed (and finishes), any errors
that may have occurred during the erase operation will be masked by the Command
Sequence error. To avoid this situation, clear the Status Register prior to resuming a
suspended erase operation. The Clear SR command functions independent of the
voltage level on VPEN.
9.2
Read Operations
Four types of data can be read from the device: array data, device information, CFI
data, and device status. Upon power-up or return from reset, the device defaults to
Read Array mode. To change the device’s read mode, the appropriate command must
be issued to the device. Table 22 shows the command codes used to configure the
device for the desired read mode. The following sections describe each read mode.
Table 22.
Read Mode Command Bus-Cycles
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
Command
Address Bus
Data Bus
Read Array
Device Address
Device Address
Device Address
Device Address
00FFh
0070h
0090h
0098h
---
---
---
---
---
---
---
---
Read Status Register
Read Device Information
CFI Query
9.2.1
Read Array
Upon power-up or return from reset, the device defaults to Read Array mode. Issuing
the Read Array command places the device in Read Array mode. Subsequent reads
output array data on DQ[15:0]. The device remains in Read Array mode until a
different read command is issued, or a program or erase operation is performed, in
which case, the read mode is automatically changed to Read Status.
To change the device to Read Array mode while it is programming or erasing, first issue
the Suspend command. After the operation has been suspended, issue the Read Array
command. When the program or erase operation is subsequently resumed, the device
will automatically revert back to Read Status mode.
Note:
Issuing the Read Array command to the device while it is actively programming or
erasing causes subsequent reads from the device to output invalid data. Valid array
data is output only after the program or erase operation has finished.
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The Read Array command functions independent of the voltage level on VPEN.
9.2.2
Read Status Register
Issuing the Read Status Register command places the device in Read Status Register
mode. Subsequent reads output Status Register information on DQ[7:0], and 00h on
DQ[15:8]. The device remains in Read Status Register mode until a different read-
mode command is issued. Performing a program, erase, or block-lock operation also
changes the device’s read mode to Read Status Register mode.
The Status Register is updated on the falling edge of CE, or OE# when CE is active.
Status Register contents are valid only when SR.7 = 1. When WSM is active, SR.7
indicates the WSM’s state and SR[6:0] are in high-Z state.
The Read Status Register command functions independent of the voltage level on
VPEN.
9.2.3
Read Device Information
Issuing the Read Device Information command places the device in Read Device
Information mode. Subsequent reads output device information on DQ[15:0].
The device remains in Read Device Information mode until a different read command is
issued. Also, performing a program, erase, or block-lock operation changes the device
to Read Status Register mode.
The Read Device Information command functions independent of the voltage level on
VPEN.
9.2.4
CFI Query
The CFI query table contains an assortment of flash product information such as block
size, density, allowable command sets, electrical specifications, and other product
information. The data contained in this table conforms to the (CFI) protocol.
Issuing the CFI Query command places the device in CFI Query mode. Subsequent
reads output CFI information on DQ[15:0]. The device remains in CFI Query mode until
a different read command is issued, or a program or erase operation is performed,
which changes the read mode to Read Status Register mode.
The CFI Query command functions independent of the voltage level on VPEN.
9.3
Programming Operations
All programming operations require the addressed block to be unlocked, and a valid
VPEN voltage applied throughout the programming operation. Otherwise, the
programming operation will abort, setting the appropriate Status Register error bit(s).
The following sections describe each programming method.
9.3.1
Single-Word/Byte Programming
Array programming is performed by first issuing the Single-Word/Byte Program
command. This is followed by writing the desired data at the desired array address. The
read mode of the device is automatically changed to Read Status Register mode, which
remains in effect until another read-mode command is issued.
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During programming, STS and the Status Register indicate a busy status (SR.7 = 0).
Upon completion, STS and the Status Register indicate a ready status (SR.7 = 1). The
Status Register should be checked for any errors (SR.4), then cleared.
Note:
Issuing the Read Array command to the device while it is actively programming causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the program operation has finished.
Standby power levels are not be realized until the programming operation has finished.
Also, asserting RP# aborts the programming operation, and array contents at the
addressed location are indeterminate. The addressed block should be erased, and the
data re-programmed. If a Single-Word/Byte program is attempted when the
corresponding block lock-bit is set, SR.1 and SR.4 will be set.
9.3.2
Buffered Programming
Buffered programming operations simultaneous program multiple words into the flash
memory array, significantly reducing effective word-write times. User-data is first
written to a write buffer, then programmed into the flash memory array in buffer-size
increments. For additional details, see the flow chart of the buffered-programming
operation.
Note:
Optimal performance and power consumption is realized only by aligning the start
address on 32-word boundaries (i.e., A[4:0] = 0b00000b). Crossing a 32-word
boundary during a buffered programming operation can cause programming time to
double.
To perform a buffered programming operation, first issue the Buffered Program setup
command at the desired starting address. The read mode of the device/addressed
partition is automatically changed to Read Status Register mode.
Polling SR.7 determines write-buffer availability (0 = not available, 1 = available). If
the write buffer is not available, re-issue the setup command and check SR.7; repeat
until SR.7 = 1.
Next, issue the word count at the desired starting address. The word count represents
the total number of words to be written into the write buffer, minus one. This value can
range from 00h (one word) to a maximum of 1Fh (32 words). Exceeding the allowable
range causes an abort.
Following the word count, the write buffer is filled with user-data. Subsequent bus-
write cycles provide addresses and data, up to the word count. All user-data addresses
must lie between <starting address> and <starting address + word count>, otherwise
the WSM continues to run as normal but, user may advertently change the content in
unexpected address locations.
Note:
Note:
User-data is programmed into the flash array at the address issued when filling the
write buffer.
After all user-data is written into the write buffer, issue the confirm command. If a
command other than the confirm command is issued to the device, a command
sequence error occurs and the operation aborts.
After issuing the confirm command, write-buffer contents are programmed into the
flash memory array. The Status Register indicates a busy status (SR.7 = 0) during
array programming.Issuing the Read Array command to the device while it is actively
programming or erasing causes subsequent reads from the device to output invalid
data. Valid array data is output only after the program or erase operation has finished.
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Intel® Embedded Flash Memory (J3 v. D)
Upon completion of array programming, the Status Register indicates ready (SR.7 = 1).
A full Status Register check should be performed to check for any programming errors,
then cleared by using the Clear Status Register command.
Additional buffered programming operations can be initiated by issuing another setup
command, and repeating the buffered programming bus-cycle sequence. However, any
errors in the Status Register must first be cleared before another buffered
programming operation can be initiated.
9.4
Block Erase Operations
Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation
must be performed (see Section 9.3, “Programming Operations”). Erasing is performed on a
block basis - an entire block is erased each time an erase command sequence is issued.
Once a block is fully erased, all addressable locations within that block read as logical
ones (FFFFh). Only one block-erase operation can occur at a time, and is not permitted
during a program suspend.
To perform a block-erase operation, issue the Block Erase command sequence at the
desired block address. Table 23, “Block-Erase Command Bus-Cycle” on page 40 shows
the two-cycle Block Erase command sequence.
Table 23.
Block-Erase Command Bus-Cycle
Setup Write Cycle
Confirm Write Cycle
Command
Address Bus
Device Address
Data Bus
Address Bus
Data Bus
00D0h
Block Erase
0020h
Block Address
Note:
A block-erase operation requires the addressed block to be unlocked, and a valid
voltage applied to VPEN throughout the block-erase operation. Otherwise, the
operation will abort, setting the appropriate Status Register error bit(s).
The Erase Confirm command latches the address of the block to be erased. The
addressed block is preconditioned (programmed to all zeros), erased, and then verified.
The read mode of the device is automatically changed to Read Status Register mode,
and remains in effect until another read-mode command is issued.
During a block-erase operation, STS and the Status Register indicates a busy status
(SR.7 = 0). Upon completion, STS and the Status Register indicates a ready status
(SR7 = 1). The Status Register should be checked for any errors, then cleared. If any
errors did occur, subsequent erase commands to the device are ignored unless the
Status Register is cleared.
The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, and Erase Suspend. After the block-erase operation has
completed, any valid command can be issued.
Note:
Issuing the Read Array command to the device while it is actively erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only
after the block-erase operation has finished.
Standby power levels are not be realized until the block-erase operation has finished.
Also, asserting RP# aborts the block-erase operation, and array contents at the
addressed location are indeterminate. The addressed block should be erased before
programming within the block is attempted.
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9.5
Suspend and Resume
An erase or programming operation can be suspended to perform other operations, and
then subsequently resumed. Table 24 shows the Suspend and Resume command bus-
cycles.
Note:
All erase and programming operations require the addressed block to remain unlocked
with a valid voltage applied to VPEN throughout the suspend operation. Otherwise, the
block-erase or programming operation will abort, setting the appropriate Status
Register error bit(s). Also, asserting RP# aborts suspended block-erase and
programming operations, rendering array contents at the addressed location(s)
indeterminate.
Table 24.
Suspend and Resume Command Bus-Cycles
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
Command
Address Bus
Data Bus
Suspend
Resume
Device Address
Device Address
00B0h
00D0h
---
---
---
---
To suspend an on-going erase or program operation, issue the Suspend command to
any device address. The program or erase operation suspends at pre-determined points
during the operation after a delay of tSUSP. Suspend is achieved whenSTS (in RY/BY#
mode) goes high, SR[7,6] = 1 (erase-suspend) or SR[7,2] = 1 (program-suspend).
Note:
Issuing the Suspend command does not change the read mode of the device. The
device will be in Read Status Register mode from when the erase or program command
was first issued, unless the read mode was changed prior to issuing the Suspend
command.
Not all commands are allowed when the device is suspended. Table 25 shows which
device commands are allowed during Program Suspend or Erase Suspend.
Table 25.
Valid Commands During Suspend (Sheet 1 of 2)
Device Command
Program Suspend
Erase Suspend
STS Configuration
Read Array
Allowed
Allowed
Allowed
Allowed
Read Status Register
Clear Status Register
Read Device Information
CFI Query
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Word Program
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Buffered Program
Block Erase
Allowed
Not Allowed
Allowed
Program Suspend
Erase Suspend
Not Allowed
Allowed
Program/Erase Resume
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Intel® Embedded Flash Memory (J3 v. D)
Table 25.
Valid Commands During Suspend (Sheet 2 of 2)
Device Command
Program Suspend
Erase Suspend
Lock Block
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Unlock Block
Program OTP Register
During Suspend, array-read operations are not allowed in blocks being erased or
programmed.
A block-erase under program-suspend is not allowed. However, word-program under
erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-
suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.
To resume a suspended program or erase operation, issue the Resume command to
any device address. The read mode of the device is automatically changed to Read
Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes
low, and the respective Status Register bits are cleared.
When the Resume command is issued during a simultaneous erase-suspend/ program-
suspend condition, the programming operation is resumed first. Upon completion of the
programming operation, the Status Register should be checked for any errors, and
cleared. The resume command must be issued again to complete the erase operation.
Upon completion of the erase operation, the Status Register should be checked for any
errors, and cleared.
9.6
Status Signal
The STATUS (STS) signal can be configured to different states using the STS
Configuration command (Table 26). Once the STS signal has been configured, it
remains in that configuration until another Configuration command is issued or RP# is
asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low
indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready
for a new operation or suspended. Table 27 displays possible STS configurations.
Table 26.
STS Configuration Register
Setup Write Cycle
Address Bus Data Bus
Device Address 00B8h
Confirm Write Cycle
Command
Address Bus
Device Address
Data Bus
STS Configuration
Register Data
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is
given followed by the desired configuration code. The three alternate configurations are
all pulse mode for use as a system interrupt as described in the following paragraphs.
For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1
controls Program Complete interrupt pulse. Supplying the 00h configuration code with
the Configuration command resets the STS signal to the default RY/BY# level mode.
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note:
STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
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Table 27.
STS Configuration Coding Definitions
D7
D6
D5
D4
D3
D2
D1
D0
Pulse on
Program
Complete
(1)
Pulse on
Erase
Complete
(1)
Reserved3
D[1:0] = STS Configuration Codes
Notes
00 = default, level mode;
device ready indication
Controls HOLD to a memory controller to prevent accessing a flash memory
subsystem while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array has
completed a block erase. Helpful for reformatting blocks after file system free
space reclamation or “cleanup.”
01 = pulse on Erase Complete
10 = pulse on Program Complete
Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when either
erase or program operations are completed, when a common interrupt service
routine is desired.
11 = pulse on Erase or Program Complete
Notes:
1.
2.
3.
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
An invalid configuration code will result in both SR.4 and SR.5 being set.
Reserved bits are invalid should be ignored.
9.7
Security and Protection
Intel® Embedded Flash Memory (J3 v. D) device offer both hardware and software
security features. Block lock operations, PRs and VPEN allow users to implement
various levels of data protection.
9.7.1
Normal Block Locking
Intel® Embedded Flash Memory (J3 v. D) has the unique capability of Flexible Block
Locking (locked blocks remain locked upon reset or power cycle): All blocks are
unlocked at the factory. Blocks can be locked individually by issuing the Set Block Lock
Bit command sequence to any address within a block. Once locked, blocks remain
locked when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed. Table 28 summarizes the command bus-cycles.
Table 28.
Block Locking Command Bus-Cycles
Setup Write Cycle
Confirm Write Cycle
Command
Address Bus
Data Bus
Address Bus
Data Bus
Set Block Lock Bit
Block Address
Device Address
0060h
0060h
Block Address
Device Address
0001h
00D0h
Clear Block Lock Bits
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup
command, the device’s read mode is automatically changed to Read Status Register
mode. After issuing the confirm command, completion of the operation is indicated by
STS (in RY/BY# mode) going high and SR.7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device
is suspended. Reliable block lock and unlock operations occur only when VCC and VPEN
are valid. When VPEN ≤ VPENLK, block lock-bits cannot be changed.
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When the set lock-bit operation is complete, SR.4 should be checked for any error.
When the clear lock-bit operation is complete, SR.5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
9.7.2
9.7.3
Configurable Block Locking
One of the unique new features on the Intel® Embedded Flash Memory (J3 v. D),which
did not exist on the previous generations of this product family, is the ability to protect
and/or secure the user’s system by offering multiple level of securities: Non-Volatile
Temporary; Non-Volatile Semi-Permanent or Non-Volatile Permanent. For additional
information and collateral request, please contact your filed representative.
OTP Protection Registers
Intel® Embedded Flash Memory (J3 v. D) includes a 128-bit Protection Register (PR)
that can be used to increase the security of a system design. For example, the number
contained in the PR can be used to “match” the flash component with other system
components such as the CPU or ASIC, hence preventing device substitution.
The 128-bits of the PR are divided into two 64-bit segments:
• One segment is programmed at the Intel factory with a unique unalterable 64-bit
number.
• The other segment is left blank for customer designers to program as desired. Once
the customer segment is programmed, it can be locked to prevent further
programming.
9.7.4
9.7.5
Reading the OTP Protection Register
The Protection Register is read in Identification Read mode. The device is switched to
this mode by issuing the Read Identifier command (0090h). Once in this mode, read
cycles from addresses shown in Table 29, “Word-Wide Protection Register Addressing”
or Table 30, “Byte-Wide Protection Register Addressing” retrieve the specified
information. To return to Read Array mode, write the Read Array command (00FFh).
Programming the OTP Protection Register
PR bits are programmed using the two-cycle Protection Program command. The 64-bit
number is programmed 16 bits at a time for word-wide configuration and eight bits at a
time for byte-wide configuration. First write the Protection Program Setup command,
00C0h. The next write to the device will latch in address and data and program the
specified location. The allowable addresses are shown in Table 29, “Word-Wide
Protection Register Addressing” on page 45 or Table 30, “Byte-Wide Protection Register
Addressing” on page 46. See Figure 27, “Protection Register Programming Flowchart”
on page 57. Any attempt to address Protection Program commands outside the defined
PR address space will result in a Status Register error (SR.4 will be set). Attempting to
program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will
be set).
9.7.6
Locking the OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Intel factory to protect the unique device number. Bit 1 is set using the Protection
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Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Figure 18.
Protection Register Memory Map
A[24:1]: 256 Mbit A[22:1]: 64 Mbit
Word
A[23:1]: 128 Mbit A[21:1]: 32 Mbit
Address
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Note: A0 is not used in x16 mode when accessing the protection register map. See Table 29 for x16 addressing. In x8 mode A0
is used, see Table 30 for x8 addressing.
Table 29.
Word-Wide Protection Register Addressing
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
Both
Factory
Factory
Factory
Factory
User
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
User
User
User
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
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Intel® Embedded Flash Memory (J3 v. D)
Table 30.
Byte-Wide Protection Register Addressing
Byte
Use
A8
A7
A6
A5
A4
A3
A2
A1
A0
LOCK
Both
Both
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOCK
0
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
User
1
2
3
4
5
6
7
8
9
User
A
User
B
User
C
User
D
E
User
User
F
User
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0.
9.7.7
VPP/ VPEN Protection
When it’s necessary to protect the entire array, global protection can be achieved using
a hardware mechanism using VPP or VPEN. Whenever a valid voltage is present on VPP
or VPEN, blocks within the main flash array can be erased or programmed. By
grounding VPP or VPEN, blocks within the main array cannot be altered – attempts to
program or erase blocks will fail resulting in the setting of the appropriate error bit in
the Status Register. By holding VPP or VPEN low, absolute write protection of all blocks
in the array can be achieved.
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10.0
ID Codes
Table 31.
Read Identifier Codes
Code
Address
Data
32-Mbit
64-Mbit
00001h
00001h
00001h
00001h
0016h
0017h
0018h
001Dh
Device Code
128-Mbit
256-Mbit
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Intel® Embedded Flash Memory (J3 v. D)
11.0
Device Command Codes
For a complete definition on device operations refer to Section 8.4, “Device Commands”
on page 34. The list of all applicable commands are included here one more time for
the convenience.
Table 32.
Command Bus Operations for
Setup Write Cycle
Confirm Write Cycle
Command
Address Bus
Data Bus
Address Bus
Data Bus
Program Enhanced Configuration Register
Program OTP Register
Register Data
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
0060h
00C0h
0050h
00B8h
00FFh
0070h
0090h
0098h
Register Data
0004h
Register Offset
Register Data
Clear Status Register
---
---
Program STS Configuration Register
Read Array
Device Address
Register Data
---
---
---
---
---
---
---
---
Read Status Register
Read Identifier Codes (Read Device Information)
CFI Query
0040h/
0010h
Word/Byte Program
Device Address
Device Address
Array Data
Buffered Program
Block Erase
Word Address
Block Address
Device Address
00E8h
0020h
00B0h
Device Address
Block Address
---
00D0h
00D0h
---
Program/Erase Suspend
Program/Erase Resume
Lock Block
Device Address
Block Address
00D0h
0060h
---
---
Block Address
0001h
Unlock Block
Device Address
0060h
Device Address
00D0h
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12.0
Flow Charts
Figure 19.
Write to Buffer Flowchart
Start
Setup
- Write 0xE8
- Block Address
Check Buffer Status
- Perform read operation
- Read Ready Status on signal SR7
No
SR7 = 1?
Yes
Word Count
- Address = block address
- Data =word count minus 1
(Valid range = 0x00 to0x1F)
Load Buffer
- Fill write buffer up to word count
- Address = within buffer range
- Data = user data
Confirm
- Write 0xD0
- Block address
Read Status
Register (SR)
No
SR7 = 1?
Yes
Full Status Register
Check
(if desired)
End
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Intel® Embedded Flash Memory (J3 v. D)
Figure 20.
Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Yes
Yes
Error
Command Sequence
SR5 = '1'
SR4 = '1'
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register
Yes
Yes
Error
VPEN < VPENLK
SR3 = '1'
Command
No
Error
Block Locked
SR1 = '1'
No
End
Datasheet
50
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Figure 21.
Byte/Word Program Flowchart
Start
Bus
Operation
Command
Comments
Setup Byte/
Data = 40H
Write 40H,
Address
Write
Write
Word Program Addr = Location to Be Programmed
Byte/Word
Program
Data = Data to Be Programmed
Addr = Location to Be Programmed
Write Data and
Address
Read
(Note 1)
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status
Register
Standby
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
0
SR.7 =
1
SR full status check can be done after each program operation, or
after a sequence of programming operations.
Full Status
Write FFH after the last program operation to place device in read
array mode.
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Check SR.3
1 = Programming to Voltage Error
Detect
Read Status
Register Data
(See Above)
Standby
1
Check SR.1
SR.3 =
SR.1 =
SR.4 =
Voltage Range Error
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit Is Set
Only required for systems
implemeting lock-bit configuration.
Standby
Standby
0
0
0
1
1
Check SR.4
1 = Programming Error
Device Protect Error
Programming Error
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
Byte/Word
Program
Successful
If an error is detected, clear the status register before attempting retry
or other error recovery.
December 2007
Document Number: 316577-006
Datasheet
51
Intel® Embedded Flash Memory (J3 v. D)
Figure 22.
Program Suspend/Resume Flowchart
Bus
Operation
Start
Command
Comments
Data = B0H
Program
Suspend
Write
Read
Addr = X
Write B0H
Status Register Data
Addr = X
Check SR.7
Standby
Standby
1 - WSM Ready
0 = WSM Busy
Read Status Register
Check SR.6
1 = Programming Suspended
0 = Programming Completed
0
SR.7 =
Data = FFH
Addr = X
Write
Read
Write
Read Array
1
Read array locations other
than that being programmed.
0
SR.2 =
Programming Completed
Program
Resume
Data = D0H
Addr = X
1
Write FFH
Read Data Array
No
Done Reading
Yes
Write D0H
Write FFH
Programming Resumed
Read Array Data
Datasheet
52
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Figure 23.
Block Erase Flowchart
Bus
Operation
Command
Comments
Data = 20H
Start
Write
Erase Block
Addr = Block Address
Erase
Confirm
Data = D0H
Addr = Block Address
Write (Note 1)
Issue Single Block Erase
Command 20H, Block
Address
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Read
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Write Confirm D0H
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Read
Status Register
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
No
Suspend
Erase Loop
0
Yes
SR.7 =
1
Suspend Erase
Full Status
Check if Desired
Erase Flash
Block(s) Complete
December 2007
Document Number: 316577-006
Datasheet
53
Intel® Embedded Flash Memory (J3 v. D)
Figure 24.
Block Erase Suspend/Resume Flowchart
Bus
Operation
Start
Command
Comments
Data = B0H
Write
Read
Erase Suspend
Addr = X
Write B0H
Status Register Data
Addr = X
Check SR.7
Standby
1 - WSM Ready
0 = WSM Busy
Read Status Register
Check SR.6
Standby
Write
1 = Block Erase Suspended
0 = Block Erase Completed
0
0
SR.7 =
1
Data = D0H
Addr = X
Erase Resume
SR.6 =
Block Erase Completed
1
Read
Program
Read or Program?
Read Array
Data
Program
Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Datasheet
54
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Figure 25.
Set Block Lock-Bit Flowchart
Start
Bus
Operation
Command
Comments
Set Block Lock-Bit Data = 60H
Write 60H,
Block Address
Write
Setup
Addr =Block Address
Set Block Lock-Bit Data = 01H
Write
Read
Confirm
Addr = Block Address
Write 01H,
Block Address
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Repeat for subsequent lock-bit operations.
0
SR.7 =
1
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in read
array mode.
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus
Operation
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
1
Standby
SR.3 =
Voltage Range Error
Check SR.4, 5
Standby
Standby
Both 1 = Command Sequence
Error
0
SR.4,5 =
0
1
1
Command Sequence
Error
Check SR.4
1 = Set Lock-Bit Error
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
command, in cases where multiple lock-bits are set before full status is
checked.
SR.4 =
0
Set Lock-Bit Error
If an error is detected, clear the status register before attempting retry
or other error recovery.
Set Lock-Bit
Successful
December 2007
Document Number: 316577-006
Datasheet
55
Intel® Embedded Flash Memory (J3 v. D)
Figure 26.
Clear Lock-Bit Flowchart
Start
Bus
Operation
Command
Comments
Data = 60H
Clear Block
Lock-Bits Setup
Write
Write 60H
Write D0H
Addr = X
Clear Block or
Lock-Bits Confirm
Data = D0H
Addr = X
Write
Read
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
0
SR.7 =
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Read Status Register
Data (See Above)
Check SR.3
Standby
1 = Programming Voltage Error
Detect
1
SR.3 =
0
Voltage Range Error
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Standby
1
1
Check SR.5
1 = Clear Block Lock-Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
Clear Block Lock-Bits
Error
SR.5 =
0
If an error is detected, clear the status register before attempting retry
or other error recovery.
Clear Block Lock-Bits
Successful
Datasheet
56
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Figure 27.
Protection Register Programming Flowchart
Start
Bus Operation
Write
Command
Comments
Protection Program
Setup
Data = C0H
Write C0H
(Protection Reg.
Program Setup)
Data = Data to Program
Addr = Location to Program
Write
Protection Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write Protect. Register
Address/Data
Read
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Read Status Register
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
No
SR.7 = 1?
Yes
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Full Status
Check if Desired
Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Standby
Command
Comments
SR.1 SR.3 SR.4
Read Status Register
Data (See Above)
0
1
1
V PEN Low
1, 1
0
0
1
Prot. Reg.
Prog. Error
Standby
SR.3, SR.4 =
SR.1, SR.4 =
VPEN Range Error
1
0
1
Register
Locked:
Aborted
0,1
1,1
Standby
Protection Register
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Register -
Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
SR.1, SR.4 =
If an error is detected, clear the status register before attempting retry or other
error recovery.
Program Successful
December 2007
Document Number: 316577-006
Datasheet
57
Intel® Embedded Flash Memory (J3 v. D)
13.0
Common Flash Interface
The (CFI) specification outlines device and host system software interrogation
handshake which allows specific vendor-specified software algorithms to be used for
entire families of devices. This allows device independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. It allows flash vendors to standardize their existing interfaces for long-term
compatibility.
This section defines the data structure or “database” returned by the (CFI) Query
command. System software should parse this structure to gain critical information such
as block size, density, x8/x16, and electrical specifications. Once this information has
been obtained, the software will know which command sets to use to enable flash
writes, block erases, and otherwise control the flash component. The Query is part of
an overall specification for multiple command set and control interface descriptions
called CFI.
13.1
Query Structure Output
The Query “database” allows system software to gain information for controlling the
flash component. This section describes the device’s CFI-compliant interface that allows
the host system to access Query data.
Query data are always presented on the lowest-order data outputs (D[7:0]) only. The
numerical offset value is the address relative to the maximum bus width supported by
the device. On this family of devices, the Query table device starting address is a 10h,
which is a word address for x16 devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in
ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant
device outputs 00h data on upper bytes. Thus, the device outputs ASCII “Q” in the low
byte (D[7:0]) and 00h in the high byte (D[15:8]).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 33.
Summary of Query Structure Output as a Function of Device and Mode
Query data with maximum device
Query data with byte addressing
bus width addressing
Device
Type/
Mode
Query start location in
maximum device bus
width addresses
Hex
ASCII
Value
Hex
Offset
ASCII
Value
Hex Code
Hex Code
Offset
x16 device
x16 mode
10h
10:
11:
12:
0051
0052
0059
“Q”
“R”
“Y”
20:
21:
22:
20:
51
00
52
51
“Q”
“Null”
“R”
x16 device
“Q”
Datasheet
58
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 33.
Summary of Query Structure Output as a Function of Device and Mode
Query data with maximum device
bus width addressing
Query data with byte addressing
Device
Type/
Mode
Query start location in
maximum device bus
width addresses
Hex
ASCII
Value
Hex
ASCII
Value
Hex Code
Hex Code
Offset
Offset
x8 mode
N/A(1)
N/A(1)
21:
22:
51
52
“Q”
“R”
Note:
1.
The system must drive the lowest order addresses to access all the device's array data when the device is configured in
x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable"
for x8-configured devices.
Table 34.
Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
Value
Offset
A7–A0
Value
A
15–A0
D15–D0
D7–D0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
0051
0052
0059
P_IDLO
P_IDHI
PLO
“Q”
“R”
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
51
51
“Q”
“Q”
“Y”
52
“R”
PrVendor
ID #
52
“R”
59
“Y”
PrVendor
TblAdr
AltVendor
ID #
59
“Y”
PHI
P_IDLO
P_IDLO
P_IDHI
...
PrVendor
PrVendor
ID #
...
A_IDLO
A_IDHI
...
...
13.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below. See AP-646 Common Flash Interface (CFI) and
Command Sets (order number 292204) for a full description of CFI.
The following sections describe the Query structure sub-sections in detail.
Table 35.
Query Structure
Offset
Sub-Section Name
Description
Notes
00h
01h
Manufacturer Code
Device Code
1
1
(BA+2)h(2)
04-0Fh
10h
Block Status Register
Block-Specific Information
1,2
1
Reserved
Reserved for Vendor-Specific Information
Reserved for Vendor-Specific Information
Command Set ID and Vendor Data Offset
CFI Query Identification String
System Interface Information
1
1Bh
1
December 2007
Document Number: 316577-006
Datasheet
59
Intel® Embedded Flash Memory (J3 v. D)
Table 35.
Query Structure
Offset
Sub-Section Name
Description
Flash Device Layout
Notes
27h
Device Geometry Definition
1
Primary Intel-Specific Extended Query
Table
Vendor-Defined Additional Information Specific to
the Primary Vendor Algorithm
P(3)
1,3
Notes:
1.
2.
3.
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is
128 Kbyte).
Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.
13.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations.
Table 36.
Block Status Register
Offset
Length
Description
Address
Value
(BA+2)h(1)
1
Block Lock Status Register
BA+2:
--00 or --01
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked
BA+2:
BA+2:
(bit 0): 0 or 1
(bit 1–15): 0
BSR 1–15: Reserved for Future Use
Note:
1.
BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location in word
mode).
13.4
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports
the Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Table 37.
CFI Identification
Hex
Code
Offset
Length
Description
Add.
Value
10
--51
--52
--59
--01
--00
--31
--00
--00
--00
--00
--00
“Q”
“R”
“Y”
10h
13h
15h
17h
19h
3
2
2
2
2
Query-unique ASCII string “QRY”
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Datasheet
60
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
13.5
System Interface Information
The following device information can optimize system interface software.
Table 38.
System Interface Information
Hex
Code
Offset
Length
Description
Add.
Value
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
1Bh
1Ch
1Dh
1Eh
1
1B:
--27
--36
--00
--00
2.7 V
bits 4–7 BCD volts
V
V
V
CC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1
1
1
1C:
1D:
1E:
3.6 V
0.0 V
0.0 V
PP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
“n” such that typical single word program time-out = 2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
1F:
20:
21:
22:
23:
24:
25:
26:
--06
--07
--0A
--00
--02
--03
--02
--00
64 µs
128 µs
1 s
“n” such that typical full chip erase time-out = 2n ms
NA
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
256 µs
1024 µs
4 s
NA
13.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 39.
Device Geometry Definition
Offset
Length
Description
Code See Table Below
27h
1
2
“n” such that device size = 2n in number of bytes
27:
x8/
x16
28h
Flash device interface: x8 async x16 async x8/x16 async
28:
--02
28:00,29:00 28:01,29:00 28:02,29:00
29:
2A:
2B:
--00
--05
--00
2Ah
2
1
“n” such that maximum number of bytes in write buffer = 2n
32
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or more
contiguous same-size erase blocks
2Ch
2Dh
2C:
--01
1
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
2D:
2E:
2F:
30:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
4
December 2007
Document Number: 316577-006
Datasheet
61
Intel® Embedded Flash Memory (J3 v. D)
Table 40.
Device Geometry: Address Codes
Address
32 Mbit
64 Mbit
128 Mbit
256 Mbit
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
--16
--02
--00
--05
--00
--01
--1F
--00
--00
--02
--17
--02
--00
--05
--00
--01
--3F
--00
--00
--02
--18
--02
--00
--05
--00
--01
--7F
--00
--00
--02
--19
--02
--00
--05
--00
--01
--FF
--00
--00
--02
13.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific
Extended Query table specifies this and other similar information.
Table 41.
Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
3
Primary extended query table
31:
32:
33:
34:
35:
36:
37:
38:
39:
--50
--52
--49
--31
--31
--CE
--00
--00
--00
“P”
“R”
“I”
Unique ASCII string “PRI”
1
1
4
Major version number, ASCII
Minor version number, ASCII
“1”
“1”
Optional feature and command support (1=yes, 0=no)
Undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of optional features follows at
the end of the bit-30 field.
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
Yes(1)
No
bit 1 Suspend erase supported
bit 1 = 1
(P+5)h
(P+6)h
(P+7)h
(P+8)h
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 2 = 1
bit 3 = 1(1)
bit 4 = 0
bit 5 = 0
bit 6 = 1
bit 7 = 1
bit 8 = 0
bit 9 = 0
bit 30 = 0
bit 31 = 0
bit 5 Instant Individual block locking supported
bit 6 Protection bits supported
No
Yes
Yes
No
bit 7 Page-mode read supported
bit 8 Synchronous read supported
bit9 Simultaneous Operation Supported
bit 30 CFI Link(s) to follow (32, 64, 128, 256 Mb)
bit 31 Another “Optional Feature” field to follow
No
No
No
Datasheet
62
December 2007
Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Table 41.
Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3A:
--01
(P+9)h
1
bit 0 Program supported after erase suspend
Block Status Register mask
bit 0 = 1
Yes
3B:
3C:
--01
--00
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
(P+A)h
(P+B)h
2
bit 0 = 1
bit 1 = 0
Yes
No
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
(P+C)h
1
1
3D:
--33
--00
3.3 V
0.0 V
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
(P+D)h
3E:
Note:
1.
2.
Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value of “0.”
Setting this bit, will lead to the extension of the CFI table.
Table 42.
Protection Register Information
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+E)h
1
3F:
--01
01
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits 0-15 point
to the protection register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
40:
41:
42:
43:
--80
--00
--03
--03
80h
00h
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
8bytes
8bytes
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
Note:
1.
The variable P is a pointer which is defined at CFI offset 15h.
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Datasheet
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Intel® Embedded Flash Memory (J3 v. D)
Table 43.
Burst Read Information
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of read-
page bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
(P+13)h
(P+14)h
1
1
44:
45:
--03
8 byte
0
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
--00
--00
Synchronous Mode Read Capability Configuration 1
Bits 3-7 = Reserved
bits 0-2 = “n” such that 2n+1 HEX value represents the maximum
number of continuous synchronous burst reads when the device is
configured for its maximum word width. A value of 07h indicates that
the device is capable of continuous linear bursts until that will output
data until the internal burst counter reaches the end of the device’s
burstable address space. This field’s 3-bit value can be written directly
to the Read Configuration Register Bits 0-2 if the device is configured for
its maximum word width. See offset 1Fh for word width to determine
the burst data output width.
(P+15)h
1
46:
n/a
(P+16h)h
(P+45h)h
Note:
1
1
Synchronous Mode Read Capability Configuration 2
J3C mark for VIL fix for customers
47:
76:
--00
--01
n/a
01
1.
The variable P is a pointer which is defined at CFI offset 15h.
Appendix A Additional Information
Order Number
Document/Tool
Intel® StrataFlash™ Memory (J3); 28F256J3, 28F128J3, 28F640J3, 28F320J3 Specification
Update
298130
298136
297833
290606
292204
253418
Intel® Persistent Storage Manager (IPSM) User’s Guide Software Manual
Intel® Flash Data Integrator (FDI) User’s Guide Software Manual
5 Volt Intel® StrataFlash™ MemoryI28F320J5 and 28F640J5 datasheet
AP-646 Common Flash Interface (CFI) and Command Sets
Intel® Wireless Communications and Computing Package User’s Guide
1.
Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2.
3.
Visit the Intel home page http://www.intel.com for technical documentation and tools.
For the most current information on Intel® Embedded Flash Memory (J3 v. D), visit http://developer.intel.com/design/
flash/isf.
Datasheet
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Document Number: 316577-006
Intel® Embedded Flash Memory (J3 v. D)
Appendix B Ordering Information
Figure 28.
Decoder for Discrete Family, 32-, 64-, 128-, 256-Mbit (monolithic)
l
R C 2 8 F 2 5 6 J 3 D 0 9 5
Package
TE = 56-Lead TSOP
JS = Lead Free 56L TSOP
RC = 64-Ball Easy BGA
PC = Lead Free 64 Easy BGA
Access Speed(ns)
256 Mbit = 95
32/64/128 Mbit = 75
Lithography
Intel® 0.13 micron ETOX™
VIII Process Technology
Product line designator
for Intel® Flash products
Voltage(VCC/VCCQ
)
3 = 3 V/3 V
Device Density
256 = x8/x16 (256 Mbit)
128 = x8/x16 (128 Mbit)
640 = x8/x16 (64 Mbit)
320 = x8/x16 (32 Mbit)
Product Family
J = Intel® Embedded Flash memory,
2 bits-per-cell
Table 44.
Valid Combinations
32-Mbit
64-Mbit
TE 28F640J3D-75
128-Mbit
TE 28F128J3D-75
256-Mbit
TE 28F320J3D-75
JS28F320J3D-75
RC 28F320J3D-75
PC 28F320J3D-75
TE 28F256J3D-95
JS28F256J3D-95
RC 28F256J3D-95
PC 28F256J3D-95
JS28F640J3D-75
RC 28F640J3D-75
PC 28F640J3D-75
JS28F128J3D-75
RC 28F128J3D-75
PC 28F128J3D-75
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Document Number: 316577-006
Datasheet
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Intel® Embedded Flash Memory (J3 v. D)
Datasheet
66
December 2007
Document Number: 316577-006
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