M25P05-AVMN6G_技术文档

M25P05-A

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Features

■ 512 Kbits of flash memory

■ Page program (up to 256 bytes) in 1.4 ms

(typical)

■ Sector erase (256 Kbits) in 0.65 s (typical)

■ Bulk erase (512 Kbits) in 0.85 s (typical)

■ 2.3 to 3.6 V single supply voltage

■ SPI bus compatible serial interface

■ 50 MHz clock rate (maximum)

SO8 (MN)

150 mil width

■ Deep power-down mode 1 µA (typical)

■ Electronic signatures

– JEDEC standard two-byte signature

(2010h)

VFQFPN8 (MP)

(MLP8)

– RES instruction, one-byte, signature (05h),

for backward compatibility

■ More than 100,000 erase/program cycles per

sector

■ More than 20 years data retention

■ ECOPACK® packages available

TSSOP8 (DW)

UFDFPN8 (MB)

2 x 3 mm

April 2008

Rev 11

1/52

www.numonyx.com

1

Contents

M25P05-A

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V_CCsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_SSground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

4

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1

4.2

4.3

4.4

4.5

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12

Active power, standby power and deep power-down modes . . . . . . . . . . 12

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5.1

4.5.2

4.5.3

4.5.4

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6

4.7

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5

6

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1

6.2

6.3

Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/52

M25P05-A

Contents

6.4

Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.1

6.4.2

6.4.3

6.4.4

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.5

6.6

6.7

6.8

6.9

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 27

Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.10 Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.12 Release from deep power-down and read electronic signature (RES) . . 33

7

Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8

9

10

11

12

13

3/52

List of tables

M25P05-A

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Instruction times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

AC characteristics (40 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 45

VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 47

UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

Table 20.

Table 21.

2 x 3 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22.

Table 23.

4/52

M25P05-A

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SO, VFQFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21

Figure 10. Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 23

Figure 11. Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12. Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26

Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. Release from deep power-down and read electronic signature (RES)

instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19. Release from deep power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23. Write protect setup and hold timing during WRSR when SRWD =1. . . . . . . . . . . . . . . . . . 43

Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 26. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 45

Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 29. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

2 x 3 mm package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5/52

Description

M25P05-A

1

Description

The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write

protection mechanisms, accessed by a high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the page program

instruction.

The memory is organized as 2 sectors, each containing 128 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.

The whole memory can be erased using the bulk erase instruction, or a sector at a time,

using the sector erase instruction.

Figure 1.

Logic diagram

V

CC

D

C

S

Q

M25P05-A

W

HOLD

V

SS

AI05757

Table 1.

Signal names

Signal name

Function

Direction

C

Serial Clock

Input

D

Serial Data input

Input

Q

Serial Data output

Chip Select

Write Protect

Hold

Output

Input

S

W

Input

HOLD

V_CC

V_SS

Input

Supply voltage

Ground

Supply

6/52

M25P05-A

Description

Figure 2.

SO, VFQFPN and TSSOP connections

M25P05-A

S

Q

1

2

3

4

8

V

CC

HOLD

7

W

6

5

C

D

V

SS

AI05758B

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to

V_SS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

7/52

Signal descriptions

M25P05-A

2

Signal descriptions

2.1

Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2

2.3

2.4

Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data output (Q) changes after the falling edge of Serial Clock (C).

Chip Select (S)

When this input signal is High, the device is deselected and Serial Data output (Q) is at high

impedance. Unless an internal program, erase or write status register cycle is in progress,

the device will be in the standby mode (this is not the deep power-down mode). Driving Chip

Select (S) Low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

2.6

Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are don’t care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against program or erase instructions (as specified by the values in the BP1 and

BP0 bits of the status register).

8/52

M25P05-A

Signal descriptions

2.7

V_CCsupply voltage

V

is the supply voltage.

CC

2.8

V_SSground

V

is the reference for the V supply voltage.

CC

SS

9/52

SPI modes

M25P05-A

3

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

■

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the

bus master is in standby mode and not transferring data:

■

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 3.

Bus master and memory devices on the SPI bus

V

SS

CC

R

SDO

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDI

SCK

V

CC

C

Q

D

C

Q

D

C Q D

CC

V

R

V

SS

SPI bus master

SPI memory

device

SPI memory

device

SPI memory

device

R

CS3 CS2 CS1

S

W

HOLD

W

HOLD

W

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one

device is selected at a time, so only one device drives the Serial Data output (Q) line at a

time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure

that the M25P05-A is not selected if the bus master leaves the S line in the high impedance

state. As the bus master may enter a state where all inputs/outputs are in high impedance at

the same time (for example, when the bus master is reset), the clock line (C) must be

connected to an external pull-down resistor so that, when all inputs/outputs become high

impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and

C do not become High at the same time, and so, that the t

requirement is met). The

SHCH

typical value of R is 100 kΩ, assuming that the time constant R*C (C = parasitic

p

capacitance of the bus line) is shorter than the time during which the bus master leaves the

SPI bus in high impedance.

10/52

M25P05-A

SPI modes

Example: C = 50 pF, that is R*C = 5 µs <=> the application must ensure that the bus

p

master never leaves the SPI bus in the high impedance state for a time period shorter than

5 µs.

Figure 4.

SPI modes supported

CPOL CPHA

C

0

1

0

1

D

MSB

Q

MSB

AI01438B

11/52

Operating features

M25P05-A

4

Operating features

4.1

Page programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one

byte, and a page program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal program cycle (of duration t ).

PP

To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Section 6.8: Page

program (PP) and Table 14: Instruction times).

4.2

Sector erase and bulk erase

The page program (PP) instruction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved either a sector at a time, using the sector erase (SE) instruction, or throughout the

entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of

duration t or t ).

SE

BE

The erase instruction must be preceded by a write enable (WREN) instruction.

4.3

4.4

Polling during a write, program or erase cycle

A further improvement in the time to write status register (WRSR), program (PP) or erase

(SE or BE) can be achieved by not waiting for the worst case delay (t , t , t , or t ). The

W

PP SE

BE

write in progress (WIP) bit is provided in the status register so that the application program

can monitor its value, polling it to establish when the previous write cycle, program cycle or

erase cycle is complete.

Active power, standby power and deep power-down modes

When Chip Select (S) is Low, the device is selected, and in the active power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the active power

mode until all internal cycles have completed (program, erase, write status register). The

device then goes in to the standby power mode. The device consumption drops to I

.

CC1

The deep power-down mode is entered when the specific instruction (the deep power-down

(DP) instruction) is executed. The device consumption drops further to I . The device

CC2

remains in this mode until another specific instruction (the release from deep power-down

and read electronic signature (RES) instruction) is executed.

While in the deep power-down mode, the device ignores all write, program and erase

instructions (see Section 6.11: Deep power-down (DP)). This can be used as an extra

software protection mechanism, when the device is not in active use, to protect the device

from inadvertent write, program or erase instructions.

12/52

M25P05-A

Operating features

4.5

Status register

The status register contains a number of status and control bits, as shown in Table 6, that

can be read or set (as appropriate) by specific instructions.

4.5.1

WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

register, program or erase cycle.

4.5.2

4.5.3

WEL bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch.

BP1, BP0 bits

The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against program and erase instructions.

4.5.4

SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal

allow the device to be put in the hardware protected mode. In this mode, the non-volatile bits

of the status register (SRWD, BP1, BP0) become read-only bits.

13/52

Operating features

M25P05-A

4.6

Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P05-A features the following data protection mechanisms:

■

Power on reset and an internal timer (t

) can provide protection against inadvertent

PUW

changes while the power supply is outside the operating specification

■

Program, erase and write status register instructions are checked that they consist of a

number of clock pulses that is a multiple of eight, before they are accepted for

execution

■

All instructions that modify data must be preceded by a write enable (WREN)

instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state

by the following events:

–

Power-up

Write disable (WRDI) instruction completion

Write status register (WRSR) instruction completion

Page program (PP) instruction completion

Sector erase (SE) instruction completion

Bulk erase (BE) instruction completion

■

The block protect (BP1, BP0) bits allow part of the memory to be configured as read-

only. This is the software protected mode (SPM)

The Write Protect (W) signal, in co-operation with the status register write disable

(SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable

(SRWD) bit to be write-protected. This is the hardware protected mode (HPM)

■

In addition to the low power consumption feature, the deep power-down mode offers

extra software protection, as all write, program and erase instructions are ignored.

Table 2.

Protected area sizes

Status Register

Memory content

content

BP1 bit

BP0 bit

Protected area

Unprotected area

All sectors (sectors 0 and 1)

0

1

0

1

0

1

none

No protection against page program (PP) and sector erase (SE)

All sectors (sectors 0 and 1) protected against bulk erase (BE)

All sectors (sectors 0 and 1)

none

1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0.

14/52

M25P05-A

Operating features

4.7

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

write status register, program or erase cycle that is currently in progress.

To enter the hold condition, the device must be selected, with Chip Select (S) Low.

The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes

Low (this is shown in Figure 5).

During the hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are don’t care.

Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration

of the hold condition. This is to ensure that the state of the internal logic remains unchanged

from the moment of entering the hold condition.

If Chip Select (S) goes High while the device is in the hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the hold condition.

Figure 5.

Hold condition activation

C

HOLD

Hold

condition

(standard use)

(non-standard use)

AI02029D

15/52

Memory organization

M25P05-A

5

Memory organization

The memory is organized as:

■

65,536 bytes (8 bits each)

2 sectors (256 Kbits, 32768 bytes each)

256 pages (256 bytes each).

Each page can be individually programmed (bits are programmed from 1 to 0). The device is

sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.

Table 3.

Memory organization

Sector

Address range

1

0

08000h

00000h

0FFFFh

07FFFh

16/52

M25P05-A

Memory organization

Figure 6.

Block diagram

HOLD

W

High voltage

generator

Control logic

S

C

D

Q

I/O shift register

Status

register

Address register

and counter

256 byte

data buffer

0FFFFh

Size of the

read-only

memory area

08000h

00000h

000FFh

256 bytes (page size)

X decoder

AI05759

17/52

Instructions

M25P05-A

6

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

Chip Select (S) must be driven High after the last bit of the instruction sequence has been

shifted in.

In the case of a read data bytes (READ), read data bytes at higher speed (Fast_Read), read

identification (RDID), read status register (RDSR) or release from deep power-down, and

read electronic signature (RES) instruction, the shifted-in instruction sequence is followed

by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a page program (PP), sector erase (SE), bulk erase (BE), write status register

(WRSR), write enable (WREN), write disable (WRDI) or deep power-down (DP) instruction,

Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is

rejected, and is not executed. That is, Chip Select (S) must driven High when the number of

clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a write status register cycle, program cycle

or erase cycle are ignored, and the internal write status register cycle, program cycle or

erase cycle continues unaffected.

18/52

M25P05-A

Instructions

Table 4.

Instruction set

Description

One-byteinstruction Address Dummy

Data

Instruction

code

bytes

WREN

WRDI

Write enable

0000 0110

0000 0100

1001 1111

0000 0101

0000 0001

0000 0011

06h

04h

9Fh

05h

01h

03h

0

3

0

Write disable

RDID⁽¹⁾

RDSR

WRSR

READ

Read identification

Read status register

Write status register

Read data bytes

1 to 3

1 to ∞

1

1 to ∞

Read data bytes at higher

speed

FAST_READ

0000 1011

0Bh

3

1

1 to ∞

PP

SE

BE

DP

Page program

Sector erase

Bulk erase

0000 0010

1101 1000

1100 0111

1011 1001

02h

D8h

C7h

B9h

3

0

1 to 256

0

Deep power-down

Release from deep power-

down, and read electronic

signature

0

3

0

1 to ∞

RES

1010 1011

ABh

Release from deep power-

down

0

1. The read identification (RDID) instruction is available only in products with process technology code X and

Y (see application note AN1995).

6.1

Write enable (WREN)

The write enable (WREN) instruction (Figure 7) sets the write enable latch (WEL) bit.

The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase

(SE), bulk erase (BE) and write status register (WRSR) instruction.

The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 7.

Write enable (WREN) instruction sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI02281E

19/52

Instructions

M25P05-A

6.2

Write disable (WRDI)

The write disable (WRDI) instruction (Figure 8) resets the write enable latch (WEL) bit.

The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The write enable latch (WEL) bit is reset under the following conditions:

■

Power-up

■

Write disable (WRDI) instruction completion

Write status register (WRSR) instruction completion

Page program (PP) instruction completion

Sector erase (SE) instruction completion

Bulk erase (BE) instruction completion.

Figure 8.

Write disable (WRDI) instruction sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI03750D

20/52

M25P05-A

Instructions

6.3

Read identification (RDID)

The read identification (RDID) instruction is available in products with process technology

code X and Y.

The read identification (RDID) instruction allows the 8-bit manufacturer identification to be

read, followed by two bytes of device identification. The manufacturer identification is

assigned by JEDEC, and has the value 20h for Numonyx. The device identification is

assigned by the device manufacturer, and indicates the memory type in the first byte (20h),

and the memory capacity of the device in the second byte (10h).

Any read identification (RDID) instruction while an erase or program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The read identification (RDID) instruction should not be issued while the device is in deep

power-down mode.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. This is followed by the 24-bit device identification, stored in

the memory, being shifted out on Serial Data output (Q), each bit being shifted out during

the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 9.

The read identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the standby power mode. Once in

the standby power mode, the device waits to be selected, so that it can receive, decode and

execute instructions.

Table 5.

Read identification (RDID) data-out sequence

Device identification

Manufacturer identification

Memory type

Memory capacity

20h

10h

Figure 9.

Read identification (RDID) instruction sequence and data-out sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

C

D

Instruction

Manufacturer identification

Device identification

High Impedance

Q

15 14 13

MSB

3

2

1

0

MSB

AI06809b

21/52

Instructions

M25P05-A

6.4

Read status register (RDSR)

The read status register (RDSR) instruction allows the status register to be read. The status

register may be read at any time, even while a program, erase or write status register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

write in progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the status register continuously, as shown in Figure 10.

Table 6.

Status register format

b7

b0

SRWD

0

BP1

BP0

WEL

WIP

Status register write protect

Block protect bits

Write enable latch bit

Write in progress bit

The status and control bits of the status register are as follows:

6.4.1

6.4.2

6.4.3

WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

register, program or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to

‘0’ no such cycle is in progress.

WEL bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch. When

set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is

reset and no write status register, program or erase instruction is accepted.

BP1, BP0 bits

The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against program and erase instructions. These bits are written with the

write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0)

bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes protected

against page program (PP) and sector erase (SE) instructions. The block protect (BP1,

BP0) bits can be written provided that the hardware protected mode has not been set. The

bulk erase (BE) instruction is executed if, and only if, both block protect (BP1, BP0) bits are

0.

6.4.4

SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The status register write disable (SRWD) bit and write protect (W) signal

allow the device to be put in the hardware protected mode (when the status register write

disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the non-

volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write

status register (WRSR) instruction is no longer accepted for execution.

22/52

M25P05-A

Instructions

Figure 10. Read status register (RDSR) instruction sequence and data-out sequence

S

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C

D

Instruction

Status register out

High Impedance

Q

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

AI02031E

6.5

Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

register. Before it can be accepted, a write enable (WREN) instruction must previously have

been executed. After the write enable (WREN) instruction has been decoded and executed,

the device sets the write enable latch (WEL).

The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data input (D).

The instruction sequence is shown in Figure 11.

The write status register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

status register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.

If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed write status register cycle (whose duration is t ) is initiated.

W

While the write status register cycle is in progress, the status register may still be read to

check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during

the self-timed write status register cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the write enable latch (WEL) is reset.

The write status register (WRSR) instruction allows the user to change the values of the

block protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,

as defined in Table 2. The write status register (WRSR) instruction also allows the user to

set or reset the status register write disable (SRWD) bit in accordance with the Write Protect

(W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow

the device to be put in the hardware protected mode (HPM). The write status register

(WRSR) instruction is not executed once the hardware protected mode (HPM) is entered.

The protection features of the device are summarized in Table 7.

When the status register write disable (SRWD) bit of the status register is 0 (its initial

delivery state), it is possible to write to the status register provided that the write enable latch

(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the

whether Write Protect (W) is driven High or Low.

23/52

Instructions

M25P05-A

When the status register write disable (SRWD) bit of the status register is set to ‘1’, two

cases need to be considered, depending on the state of Write Protect (W):

■

If Write Protect (W) is driven High, it is possible to write to the status register provided

that the write enable latch (WEL) bit has previously been set by a write enable (WREN)

instruction

■

If Write Protect (W) is driven Low, it is not possible to write to the status register even if

the write enable latch (WEL) bit has previously been set by a write enable (WREN)

instruction (attempts to write to the status register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the block protect (BP1, BP0) bits of the status register, are

also hardware protected against data modification.

Regardless of the order of the two events, the hardware protected mode (HPM) can be

entered:

■

by setting the status register write disable (SRWD) bit after driving Write Protect (W)

Low

■

or by driving Write Protect (W) Low after setting the status register write disable

(SRWD) bit.

The only way to exit the hardware protected mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can

never be activated, and only the software protected mode (SPM), using the block protect

(BP1, BP0) bits of the status register, can be used.

Figure 11. Write status register (WRSR) instruction sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

C

Instruction

Status

register in

7

6

5

4

3

2

0

1

D

Q

High Impedance

MSB

AI02282D

24/52

M25P05-A

Instructions

Table 7.

Protection modes

Memory content

W

signal

SRWD

bit

Write protection of the status

Mode

Protected

area⁽¹⁾

Unprotected

area⁽¹⁾

register

1

0

Status register is writable (if the

WREN instruction has set the WEL

bit).

Protected

against page

program, sector program and

erase and bulk sector erase

Ready to

accept page

Software

protected

(SPM)

The values in the SRWD, BP1 and

BP0 bits can be changed

1

erase

instructions

Protected

against page

program, sector program and

erase and bulk sector erase

erase

Ready to

accept page

Status register is hardware write

protected.

Hardware

protected

(HPM)

0

1

The values in the SRWD BP1 and

BP0 bits cannot be changed

instructions

1. As defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Table 2.

25/52

Instructions

M25P05-A

6.6

Read data bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the read

data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum

frequency f , during the falling edge of Serial Clock (C).

R

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single read data bytes (READ) instruction.

There is no address roll-over; when the highest address (0FFFFh) is reached, the

instruction should be terminated.

The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any read data bytes (READ)

instruction, while an erase, program or write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 12. Read data bytes (READ) instruction sequence and data-out sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-bit address

23 22 21

MSB

3

2

1

0

D

Q

Data out 1

Data out 2

High Impedance

2

7

6

5

4

3

1

7

0

MSB

AI03748D

1. Address bits A23 to A16 must be set to 00h.

26/52

M25P05-A

Instructions

6.7

Read data bytes at higher speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the read

data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit

being shifted out, at a maximum frequency f , during the falling edge of Serial Clock (C).

C

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.

There is no address roll-over; when the highest address (0FFFFh) is reached, the

instruction should be terminated.

The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip

Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read

data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle

is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

C

Instruction

24-bit address

23 22 21

3

2

1

0

D

Q

High Impedance

S

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

C

Dummy byte

7

6

5

4

3

2

0

1

D

Q

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

MSB

AI04006

1. Address bits A23 to A16 must be set to 00h.

27/52

Instructions

M25P05-A

6.8

Page program (PP)

The page program (PP) instruction allows bytes to be programmed in the memory (changing

bits from 1 to 0). Before it can be accepted, a write enable (WREN) instruction must

previously have been executed. After the write enable (WREN) instruction has been

decoded, the device sets the write enable latch (WEL).

The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, three address bytes and at least one data byte on Serial Data input (D). If

the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Table 14: Instruction

times).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the page program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose

duration is t ) is initiated. While the page program cycle is in progress, the status register

PP

may be read to check the value of the write in progress (WIP) bit. The write in progress

(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the write enable latch (WEL) bit is

reset.

A page program (PP) instruction applied to a page which is protected by the block protect

(BP1, BP0) bits (see Table 3. and Table 2.) is not executed.

28/52

M25P05-A

Instructions

Figure 14. Page program (PP) instruction sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

C

D

Instruction

24-bit address

Data byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

MSB

S

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

C

D

Data byte 2

Data byte 3

Data byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

MSB

AI04082B

1. Address bits A23 to A16 must be set to 00h.

29/52

Instructions

M25P05-A

6.9

Sector erase (SE)

The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data input (D). Any address inside the

sector (see Table 3) is a valid address for the sector erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed sector erase cycle (whose duration is t ) is

SE

initiated. While the sector erase cycle is in progress, the status register may be read to

check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during

the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the write enable latch (WEL) bit is reset.

A sector erase (SE) instruction applied to a page which is protected by the block protect

(BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 15. Sector erase (SE) instruction sequence

S

0

1

2

3

4

5

6

7

8

9

29 30 31

C

D

Instruction

24-bit address

23 22

MSB

2

0

1

AI03751D

1. Address bits A23 to A16 must be set to 00h.

30/52

M25P05-A

Instructions

6.10

Bulk erase (BE)

The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write

enable (WREN) instruction must previously have been executed. After the write enable

(WREN) instruction has been decoded, the device sets the write enable latch (WEL).

The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed bulk erase cycle (whose duration is t ) is initiated. While the

BE

bulk erase cycle is in progress, the status register may be read to check the value of the

write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk

erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the write enable latch (WEL) bit is reset.

The bulk erase (BE) instruction is executed only if both block protect (BP1, BP0) bits are 0.

The bulk erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 16. Bulk erase (BE) instruction sequence

S

0

1

2

3

4

5

6

7

C

D

Instruction

AI03752D

31/52

Instructions

M25P05-A

6.11

Deep power-down (DP)

Executing the deep power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the deep power-down mode). It can also be used as a software

protection mechanism, while the device is not in active use, as in this mode, the device

ignores all write, program and erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in standby mode (if

there is no internal cycle currently in progress). But this mode is not the deep power-down

mode. The deep power-down mode can only be entered by executing the deep power-down

(DP) instruction, subsequently reducing the standby current (from I

to I

, as specified

CC1

CC2

in Table 13).

To take the device out of deep power-down mode, the release from deep power-down and

read electronic signature (RES) instruction must be issued. No other instruction must be

issued while the device is in deep power-down mode.

The release from deep power-down and read electronic signature (RES) instruction, and the

read identification (RDID) instruction also allow the electronic signature of the device to be

output on Serial Data output (Q).

The deep power-down mode automatically stops at power-down, and the device always

powers-up in the standby mode.

The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of t before the supply current is reduced

DP

to I

and the deep power-down mode is entered.

CC2

Any deep power-down (DP) instruction, while an erase, program or write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep power-down (DP) instruction sequence

S

t_DP

0

1

2

3

4

5

6

7

C

D

Instruction

Standby mode

Deep power-down mode

AI03753D

32/52

M25P05-A

Instructions

6.12

Release from deep power-down and read electronic

signature (RES)

To take the device out of deep power-down mode, the release from deep power-down and

read electronic signature (RES) instruction must be issued. No other instruction must be

issued while the device is in deep power-down mode.

The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic

signature, whose value for the M25P05-A is 05h.

Except while an erase, program or write status register cycle is in progress, the release from

deep power-down and read electronic signature (RES) instruction always provides access

to the 8-bit electronic signature of the device, and can be applied even if the deep power-

down mode has not been entered.

Any release from deep power-down and read electronic signature (RES) instruction while an

erase, program or write status register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge

of Serial Clock (C). Then, the 8-bit electronic signature, stored in the memory, is shifted out

on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 18.

The release from deep power-down and read electronic signature (RES) instruction is

terminated by driving Chip Select (S) High after the electronic signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is

driven Low, cause the electronic signature to be output repeatedly.

When Chip Select (S) is driven High, the device is put in the standby power mode. If the

device was not previously in the deep power-down mode, the transition to the standby power

mode is immediate. If the device was previously in the deep power-down mode, though, the

transition to the standby power mode is delayed by t

, and Chip Select (S) must remain

RES2

High for at least t

(max), as specified in Table 15. Once in the standby power mode, the

RES2

device waits to be selected, so that it can receive, decode and execute instructions.

Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,

but before the whole of the 8-bit electronic signature has been transmitted for the first time

(as shown in Figure 19), still ensures that the device is put into standby power mode. If the

device was not previously in the deep power-down mode, the transition to the standby power

mode is immediate. If the device was previously in the deep power-down mode, though, the

transition to the standby power mode is delayed by t

, and Chip Select (S) must remain

RES1

High for at least t

(max), as specified in Table 15. Once in the standby power mode, the

RES1

device waits to be selected, so that it can receive, decode and execute instructions.

33/52

Instructions

M25P05-A

Figure 18. Release from deep power-down and read electronic signature (RES)

instruction sequence and data-out sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

C

t

Instruction

3 dummy bytes

RES2

23 22 21

MSB

3

2

1

0

D

Q

Electronic signature Out

High Impedance

7

6

5

4

3

2

0

1

MSB

Deep power-down mode

Standby mode

AI04047C

1. The value of the 8-bit electronic signature, for the M25P05-A, is 05h.

Figure 19. Release from deep power-down (RES) instruction sequence

S

t

RES1

0

1

2

3

4

5

6

7

C

D

Instruction

High Impedance

Q

Deep power-down mode

Standby mode

AI04078B

34/52

M25P05-A

Power-up and power-down

7

Power-up and power-down

At power-up and power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on V ) until V reaches the correct value:

CC

■

V

(min) at power-up, and then for a further delay of t

at power-down

CC

SS

VSL

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during power-up, a power on reset

(POR) circuit is included. The logic inside the device is held reset while V is less than the

CC

power on reset (POR) threshold voltage, V – all operations are disabled, and the device

WI

does not respond to any instruction.

Moreover, the device ignores all write enable (WREN), page program (PP), sector erase

(SE), bulk erase (BE) and write status register (WRSR) instructions until a time delay of

t

has elapsed after the moment that V rises above the V threshold. However, the

PUW

CC WI

correct operation of the device is not guaranteed if, by this time, V is still below V (min).

CC

No write status register, program or erase instructions should be sent until the later of:

■

t

after V passed the V threshold

CC WI

PUW

VSL

after V passed the V (min) level

CC

These values are specified in Table 8.

If the delay, t

, has elapsed, after V has risen above V (min), the device can be

VSL

CC

selected for read instructions even if the t

delay is not yet fully elapsed.

PUW

At power-up, the device is in the following state:

■

The device is in the standby mode (not the deep power-down mode)

The write enable latch (WEL) bit is reset

The write in progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.

CC

Each device in a system should have the V rail decoupled by a suitable capacitor close to

CC

the package pins (generally, this capacitor is of the order of 100 nF).

At power-down, when V drops from the operating voltage, to below the power on reset

CC

(POR) threshold voltage, V , all operations are disabled and the device does not respond

WI

to any instruction (the designer needs to be aware that if a power-down occurs while a write,

program or erase cycle is in progress, some data corruption can result).

35/52

Initial delivery state

M25P05-A

Figure 20. Power-up timing

V

CC

V

(max)

CC

Program, erase and write commands are rejected by the device

Chip selection not allowed

V

(min)

CC

tVSL

Read access allowed

Device fully

accessible

Reset state

of the

device

V

WI

tPUW

time

AI04009C

Table 8.

Symbol

Power-up timing and V threshold

WI

Parameter

Min

Max

Unit

(1)

t_VSL

V_CC(min) to S low

10

1

µs

ms

V

(1)

t_PUW

Time delay to Write instruction

Write inhibit voltage

10

2

(1)

V_WI

1

1. These parameters are characterized only.

8

Initial delivery state

The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte

contains FFh). The status register contains 00h (all status register bits are 0).

36/52

M25P05-A

Maximum ratings

9

Maximum ratings

Stressing the device above the rating listed in Table 9: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 9.

Symbol

Absolute maximum ratings

Parameter

Min

Max

Unit

T_STG

T_LEAD

V_IO

Storage temperature

–65

150

see⁽¹⁾

V_CC+ 0.6

4.0

°C

V

Lead temperature during soldering

Input and output voltage (with respect to ground)

Supply voltage

–0.6

V_CC

V

Electrostatic discharge voltage (human body

model)⁽²⁾

V_ESD

–2000

2000

V

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances

(RoHS) 2002/95/EU.

2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

37/52

DC and AC parameters

M25P05-A

10

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Table 10. Operating conditions

Symbol

Parameter

Min

Max

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature

2.3⁽¹⁾

–40

3.6

85

V

°C

1. Only in products with process technology code Y. In products with process technology code X, V_CC(min) is

2.7 V.

(1)

Table 11. AC measurement conditions

Symbol

Parameter

Min

Max

Unit

C_L

Load capacitance

30

pF

ns

V

Input rise and fall times

5

Input pulse voltages

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

V_CC/ 2

Input timing reference voltages

Output timing reference voltages

V

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC measurement I/O waveform

Input levels

Input and output

timing reference levels

0.8V

CC

0.7V

CC

0.3V

CC

0.5V

0.2V

CC

AI07455

(1)

Table 12. Capacitance

Symbol

Parameter

Test condition

Min

Max

Unit

C_OUT

C_IN

Output capacitance (Q)

V_OUT= 0 V

V_IN= 0 V

8

6

pF

Input capacitance (other pins)

1. Sampled only, not 100% tested, at T_A= 25 °C and a frequency of 25 MHz.

38/52

M25P05-A

DC and AC parameters

Table 13. DC characteristics

Test condition (in addition to

Symbol

Parameter

Min

Max

Unit

those in Table 10.)

I_LI

Input leakage current

Output leakage current

Standby current

± 2

50

5

µA

I_LO

I_CC1

I_CC2

S = V_CC, V_IN= V_SSor V_CC

Deep power-down current

C = 0.1V_CC/ 0.9.V_CCat 50 MHz,

Q = open

8

4

mA

I_CC3

Operating current (READ)

C = 0.1V_CC/ 0.9.V_CCat 25 MHz,

Q = open

I_CC4

I_CC5

I_CC6

I_CC7

V_IL

Operating current (PP)

Operating current (WRSR)

Operating current (SE)

Operating current (BE)

Input low voltage

S = V_CC

15

mA

V

15

– 0.5

0.3V_CC

V_IH

Input high voltage

0.7V_CCV_CC+0.4

0.4

V

V_OL

V_OH

Output low voltage

I_OL= 1.6 mA

V

Output high voltage

I_OH= –100 µA

V_CC–0.2

V

Table 14. Instruction times

Test conditions specified in Table 10 and Table 11.

Symbol

Alt.

Parameter

Min

Typ

Max

Unit

t_W

Write status register cycle time

Page program cycle time (256 bytes)

Page program cycle time (n bytes)

Sector erase cycle time

5

1.4

15

ms

(1)

t_PP

5

ms

0.4+n*1/256⁽²⁾

t_SE

t_BE

0.65

3

6

s

Bulk erase cycle time

0.85

1. When using the page program (PP) instruction to program consecutive bytes, optimized timings are

obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤

256).

2. t_PP=2µs+8µs*[int(n-1)/2+1]+4µs*[int(n-1)/2]+2µs, only in products with process technology code X and Y.

39/52

DC and AC parameters

M25P05-A

Max Unit

Table 15. AC characteristics (25 MHz operation)

Test conditions specified in Table 10 and Table 11.

Symbol Alt.

Parameter

Clock frequency for the following instructions:

Min

Typ

f_C

f_R

f_CFAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDSR, WRSR

D.C.

25

20

MHz

Clock frequency for read instructions

t_CLHClock high time

D.C.

18

0.1

10

5

MHz

ns

(1)

t_CH

(1)

t_CL

t_CLLClock low time

ns

Clock rise time⁽³⁾(peak to peak)

Clock fall time⁽³⁾(peak to peak)

t_CSSS active setup time (relative to C)

S not active hold time (relative to C)

t_DSUData in setup time

V/ns

ns

(2)

t_CLCH

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

ns

t_DHData in hold time

5

ns

S active hold time (relative to C)

S not active setup time (relative to C)

t_CSHS deselect time

10

100

ns

(2)

t_SHQZ

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_DISOutput disable time

15

ns

t_VClock Low to Output Valid

t_HOOutput hold time

ns

0

ns

HOLD setup time (relative to C)

HOLD hold time (relative to C)

HOLD setup time (relative to C)

HOLD hold time (relative to C)

t_LZHOLD to Output Low-Z

t_HZHOLD to Output High-Z

Write protect setup time

10

ns

(2)

t_HHQX

15

20

ns

(2)

t_HLQZ

t_WHSL

t_SHWL

ns

(4)

20

ns

Write protect hold time

100

ns

(2)

t_DP

S High to deep power-down mode

3

µs

S High to standby mode without electronic signature

read

(2)

t_RES1

µs

S High to standby mode with electronic signature

read

t_RES2

1.8

1. t_CH+ t_CLmust be greater than or equal to 1/ f_C.

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

40/52

M25P05-A

DC and AC parameters

Table 16. AC characteristics (40 MHz operation)

40 MHz available for products marked since week 20 of 2004, only⁽¹⁾

Test conditions specified in Table 10. and Table 11.

Symbol Alt.

Parameter

Min Typ Max Unit

Clock frequency for the following instructions:

f_CFAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDSR, WRSR

f_C

f_R

D.C.

40 MHz

Clock frequency for read instructions

t_CLHClock high time

D.C.

11

0.1

5

20 MHz

(2)

t_CH

ns

(2)

t_CL

t_CLLClock low time

(3)

t_CLCH

t_CHCL

Clock rise time⁽⁴⁾(peak to peak)

Clock fall time⁽⁴⁾(peak to peak)

t_CSSS active setup time (relative to C)

S not active hold time (relative to C)

t_DSUData in setup time

V/ns

ns

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

5

ns

2

ns

t_DHData in hold time

5

ns

S active hold time (relative to C)

S not active setup time (relative to C)

t_CSHS deselect time

5

ns

5

ns

100

ns

(3)

t_SHQZ

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_DISOutput disable time

9

ns

µs

t_VClock Low to Output Valid

t_HOOutput hold time

0

5

HOLD setup time (relative to C)

HOLD hold time (relative to C)

HOLD setup time (relative to C)

HOLD hold time (relative to C)

t_LZHOLD to Output Low-Z

t_HZHOLD to Output High-Z

Write protect setup time

(3)

t_HHQX

9

(3)

t_HLQZ

t_WHSL

t_SHWL

(5)

(1)

20

Write protect hold time

100

(3)

t_DP

S High to deep power-down mode

3

S High to standby mode without electronic signature

read

(3)

t_RES1

t_RES2

µs

S High to standby mode with electronic signature read

1.8

1. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

2. t_CH+ t_CLmust be greater than or equal to 1/ f_C.

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Details of how to find the date of marking are given in application note, AN1995.

41/52

DC and AC parameters

M25P05-A

Table 17. AC characteristics (50 MHz operation)

50 MHz available only in products with process technology code Y⁽¹⁾⁽²⁾

Test conditions specified in Table 10 and Table 11.

Symbol

Alt.

Parameter

Min Typ

Max Unit

Clock frequency⁽¹⁾for the following instructions: FAST_READ,

PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR

f_C

f_R

f_C

D.C.

50

25

MHz

Clock frequency for read instructions

D.C.

9

MHz

ns

(3)

t_CH

t_CLHClock high time

t_CLLClock low time

(3)

t_CL

9

ns

(4)

t_CLCH

Clock rise time⁽⁵⁾(peak to peak)

0.1

5

V/ns

ns

(4)

t_CHCL

Clock fall time⁽⁵⁾(peak to peak)

t_CSSS active setup time (relative to C)

S not active hold time (relative to C)

t_DSUData in setup time

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

5

ns

2

ns

t_DHData in hold time

5

ns

S active hold time (relative to C)

S not active setup time (relative to C)

t_CSHS deselect time

5

ns

5

ns

100

ns

(4)

t_SHQZ

t_DISOutput disable time

8

ns

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

t_V

t_HOOutput hold time

HOLD setup time (relative to C)

Clock Low to Output Valid

ns

0

5

ns

HOLD hold time (relative to C)

HOLD setup time (relative to C)

ns

HOLD hold time (relative to C)

ns

(4)

t_HHQX

t_LZHOLD to Output Low-Z

8

ns

(4)

t_HLQZ

t_HZHOLD to Output High-Z

ns

(6)

t_WHSL

Write protect setup time

20

ns

(6)

t_SHWL

Write protect hold time

100

ns

(4)

t_DP

S High to deep power-down mode

S High to standby mode without electronic signature read

S High to standby mode with electronic signature read

3

µs

(4)

t_RES1

30

µs

(4)

t_RES2

µs

1. Details of how to find the process on the device marking are given in application note AN1995.

2. 50 MHz operation is also available in products with process technology code X, but with a reduced supply voltage range

(2.7 to 3.6 V).

3. t_CH+ t_CLmust be greater than or equal to 1/ f_C.

4. Value guaranteed by characterization, not 100% tested in production.

5. Expressed as a slew-rate.

6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

42/52

M25P05-A

DC and AC parameters

Figure 22. Serial input timing

tSHSL

tSHCH

tCHCL

S

tCHSL

tSLCH

tCHSH

C

tDVCH

tCHDX

tCLCH

MSB IN

LSB IN

D

Q

High Impedance

AI01447C

Figure 23. Write protect setup and hold timing during WRSR when SRWD =1

W

tSHWL

tWHSL

S

C

D

High Impedance

Q

AI07439

43/52

DC and AC parameters

M25P05-A

Figure 24. Hold timing

S

C

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

tHHQX

Q

D

HOLD

AI02032

Figure 25. Output timing

S

tCH

C

tCLQV

tCL

tSHQZ

tCLQX

LSB OUT

Q

tQLQH

tQHQL

ADDR

.LSB IN

D

AI01449e

44/52

M25P05-A

Package mechanical

11

Package mechanical

In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label.

Figure 26. SO8N – 8 lead plastic small outline, 150 mils body width, package outline

h x 45˚

A2

A

c

ccc

b

e

0.25 mm

D

GAUGE PLANE

k

8

1

E1

E

L

A1

L1

SO-A

1. Drawing is not to scale.

Table 18. SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data

millimeters

inches

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

b

1.75

0.25

0.069

0.010

0.10

1.25

0.28

0.17

0.004

0.049

0.011

0.007

0.48

0.23

0.10

5.00

6.20

4.00

–

0.019

0.009

0.004

0.197

0.244

0.157

–

c

ccc

D

4.90

6.00

3.90

1.27

4.80

5.80

3.80

–

0.193

0.236

0.154

0.050

0.189

0.228

0.150

–

E

E1

e

h

0.25

0°

0.50

8°

0.010

0°

0.020

8°

k

L

0.40

1.27

0.016

0.050

L1

1.04

0.041

45/52

Package mechanical

M25P05-A

Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package outline

A

D

aaa C A

R1

D1

B

E

E1

E2

A2

e

b

2x

0.10 C

B

D2

0.10 C

A

θ

L

ddd

C

A

A1 A3

70-ME

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 19. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

A3

b

0.85

0.80

0.00

1.00

0.05

0.033

0.031

0.000

0.039

0.002

0.65

0.20

0.40

6.00

5.75

3.40

5.00

4.75

4.00

1.27

0.10

0.60

0.026

0.008

0.016

0.236

0.226

0.134

0.197

0.187

0.157

0.050

0.004

0.024

0.35

3.20

0.48

3.60

0.014

0.126

0.019

0.142

D

D1

D2

E

E1

E2

e

3.80

–

4.30

–

0.150

–

0.169

–

R1

L

0.00

0.50

0.000

0.020

0.75

12°

0.029

12°

Q

aaa

bbb

ddd

0.15

0.10

0.05

0.006

0.004

0.002

46/52

M25P05-A

Package mechanical

Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline

D

8

5

c

E1

E

1

4

α

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

1. Drawing is not to scale.

Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.20

0.15

1.05

0.30

0.20

0.10

3.10

–

0.047

0.006

0.041

0.012

0.008

0.004

0.122

–

0.05

0.80

0.19

0.09

0.002

0.031

0.007

0.003

1.00

0.039

c

CP

D

3.00

0.65

6.40

4.40

0.60

1.00

2.90

–

0.118

0.026

0.252

0.173

0.024

0.039

0.114

–

e

E

6.20

4.30

0.45

6.60

4.50

0.75

0.244

0.169

0.018

0.260

0.177

0.029

E1

L

L1

α

0°

8

8°

0°

8

8°

N

47/52

Package mechanical

M25P05-A

Figure 29. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

2 x 3 mm package outline

e

b

D

L1

L3

E

E2

L

A

D2

ddd

A1

UFDFPN-01

1. Drawing is not to scale.

Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

2 x 3 mm package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

b⁽¹⁾

D

0.55

0.02

0.25

2.00

1.60

0.45

0.00

0.20

1.90

1.50

0.60

0.05

0.30

2.10

1.70

0.08

3.10

0.30

–

0.022

0.001

0.010

0.079

0.063

0.018

0.000

0.008

0.075

0.059

0.024

0.002

0.012

0.083

0.067

0.003

0.122

0.012

–

D2

ddd⁽²⁾

E

3.00

0.20

0.50

0.45

2.90

0.10

–

0.118

0.008

0.020

0.018

0.114

0.004

–

E2

e

L

0.40

0.50

0.15

0.016

0.020

0.006

L1

L3

0.30

0.012

1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

48/52

M25P05-A

Ordering information

12

Ordering information

Table 22. Ordering information scheme

Example:

M25P05-A

V MN 6 T

P

Device type

M25P

Device function

05-A = 512 Kbits (64 Kbit x8)

Operating voltage

V = V_CC= 2.3 to 3.6 V

Package

MN = SO8 (150 mil width)

MP = VFQFPN8 (MLP8)

DW = TSSOP8⁽¹⁾

MB = UFDFPN8 (MLP8)

Temperature range

6 = –40 to 85 °C

Option

blank = standard packing

T = tape & reel packing

Plating technology

P or G = ECOPACK® (RoHS compliant)

1. The TSSOP8 package is available in products with process technology code X and Y (details of how to

find the process on the device marking are given in application note AN1995).

Note:

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest Numonyx sales office.

49/52

Revision history

M25P05-A

13

Revision history

Table 23. Document revision history

Date

Revision

Changes

25-Feb-2001

1.0

Initial release.

Clarification of descriptions of entering Standby Power mode from Deep

Power-down mode, and of terminating an instruction sequence or data-

out sequence.

11-Apr-2002

12-Sep-2002

1.1

1.2

VFQFPN8 package (MLP8) added.

Typical Page Program time improved. Write Protect setup and hold times

specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware

Protection mode again immediately after.

13-Dec-2002

24-Nov-2003

1.3

2

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

40 MHz AC characteristics table included as well as 25 MHz. I_CC3(max),

t_SE(typ) and t_BE(typ) values improved. Change of naming for VDFPN8

package

Devices with process technology code X added (Read identification

(RDID) and Table 17: AC characteristics (50 MHz operation)) added.

TSSOP8 package added.

Notes 1 and 2 removed from Table 22: Ordering information scheme and

Note 1 added.

13-Jan-2005

01-Apr-2005

3

4

Note 1 to Table 9: Absolute maximum ratings changed, note 2 and T_LEAD

values removed.

Small text changes.

Frequency test condition modified for I_CC3in Table 13: DC characteristics.

Read identification (RDID), Deep power-down (DP) and Release from

deep power-down and read electronic signature (RES) instructions and

Active power, standby power and deep power-down modes paragraph

clarified.

SO8 package specifications updated (see Figure 26. and Table 18).

Updated Page Program (PP) instructions in Page programming, Page

program (PP) and Instruction times.

01-Aug-2005

06-Jul-2006

5

6

Packages are fully ECOPACK® compliant. SO8N and VFQFPN8 package

specifications updated (see Section 11: Package mechanical).

Figure 3: Bus master and memory devices on the SPI bus updated and

Note 2 added. T_LEADremoved from Section Table 9.: Absolute maximum

ratings. Small text changes.

VCC supply voltage and VSS ground descriptions added. Figure 3: Bus

master and memory devices on the SPI bus updated, note 2 removed

replaced by explanatory paragraph.

19-Dec-2006

7

WIP bit behavior at power-up specified in Section 7: Power-up and power-

down. T_LEADadded and V_IOmax modified in Table 9: Absolute maximum

ratings. VFQFPN8 and SO8N packages updated (see Section 11:

Package mechanical).

50/52

M25P05-A

Revision history

Table 23. Document revision history (continued)

Date

Revision

Changes

Removed ‘low voltage’ from the title. Small text changes.

Changed note below Table 12: Capacitance.

Changed the minimum value for V_CC(from 2.7 to 2.3 V).

UFDFPN8 package (MLP8) added.

07-Aug-2007

8

Frequency test condition modified for I_CC3in Table 13: DC characteristics.

t_SE(typ), t_BE(typ) and t_PP(typ) values improved in Table 14: Instruction

times.

Changed maximum value for f_Rin Table 17: AC characteristics (50 MHz

operation).

10-Oct-2007

10-Dec-2007

9

Added the reference to a new process technology (code Y).

Applied Numonyx branding.

10

Updated Table 3: Bus master and memory devices on the SPI bus.

Modified the code for UFDFPN8 package from ‘ZW’ to ‘MB’.

18-Apr-2008

11

Minor text changes.

51/52

M25P05-A

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

52/52


型号：	M25P05-AVMN6G
厂家：	NUMONYX B.V
描述：	512 Kbit, serial Flash memory, 50 MHz SPI bus interface 512千位，串行闪存， 50MHz的SPI总线接口闪存存储内存集成电路光电二极管时钟
文件：	总52页 (文件大小：1092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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