M25P05-VMN6 [NUMONYX]
Flash, 64KX8, PDSO8, 0.150 INCH, PLASTIC, SO-8;
| 型号： | M25P05-VMN6 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 64KX8, PDSO8, 0.150 INCH, PLASTIC, SO-8 光电二极管 |
| 文件： | 总32页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25P05
512 Kbit, Low Voltage, Serial Flash Memory
With 20 MHz SPI Bus Interface
NOT FOR NEW DESIGN
FEATURES SUMMARY
This device is now designated as “Not for New De-
sign”. Please use the M25P05-A in all future de-
signs (as described in application note AN1511).
Figure 1. Packages
■ 512 Kbit of Flash Memory
■ Page Program (up to 128 Bytes) in 3 ms
(typical)
■ Sector Erase (256 Kbit) in 1 s (typical)
■ Bulk Erase (512 Kbit) in 2 s (typical)
■ 2.7 V to 3.6 V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 20 MHz Clock Rate (maximum)
■ Deep Power-down Mode 1 µA (typical)
■ Electronic Signature
8
1
SO8 (MN)
150 mil width
■ More than 100,000 Erase/Program Cycles per
Sector
■ More than 20 Year Data Retention
February 2002
1/32
This is information on a product still in production but not recommended for new designs.
M25P05
SUMMARY DESCRIPTION
The M25P05 is a 512 Kbit (64K x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
Figure 3. SO Connections
The memory can be programmed 1 to 128 bytes at
a time, using the Page Program instruction.
The memory is organized as 2 sectors, each con-
taining 256 pages. Each page is 128 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 512 pages, or 65536 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
M25P05
S
Q
1
2
3
4
8
V
CC
HOLD
7
6
W
C
D
V
5
SS
AI04038
Figure 2. Logic Diagram
V
CC
D
C
S
Q
M25P05
W
HOLD
V
SS
AI04037
Table 1. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
D
Q
S
W
HOLD
V
Supply Voltage
Ground
CC
V
SS
2/32
M25P05
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip Select (S) Low enables the device, placing it
in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP1
and BP0 bits of the Status Register).
3/32
M25P05
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI03746C
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL
0
CPHA
0
C
1
1
C
D or Q
MSB
LSB
AI01438
4/32
M25P05
OPERATING FEATURES
Page Programming
Erase, Write Status Register). The device then
goes in to the Stand-by Power mode. The device
consumption drops to I
.
CC1
To program one data byte, two instructions are re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
internal Program cycle (of duration t ).
consumption drops further to I
. The device re-
PP
CC2
mains in this mode until another specific instruc-
tion (the Release from Deep Power-down Mode
and Read Electronic Signature (RES) instruction)
is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertant Write, Program or Erase
instructions.
To spread this overhead, the Page Program (PP)
instruction allows up to 128 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction.
Status Register
The Status Register contains a number of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instruc-
tions.
Polling During a Write, Program or Erase Cycle
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (t , t , t , or t ). The Write In
W
PP SE
BE
WEL bit. The Write Enable Latch (WEL) bit indi-
Progress (WIP) bit is provided in the Status Regis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Active Power, Stand-by Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode.
When Chip Select (S) is High, the device is dis-
abled, but could remain in the Active Power mode
until all internal cycles have completed (Program,
5/32
M25P05
Table 2. Protected Area Sizes
Status Register
Content
Memory Content
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
0
1
1
0
1
0
1
none
All sectors (Sectors 0 and 1)
No protection against Page Program (PP) and Sector Erase (SE)
All sectors (Sectors 0 and 1) protected against Bulk Erase (BE)
All sectors (Sectors 0 and 1)
none
– Write Status Register (WRSR) instruction
completion
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P05 boasts the
following data protection mechanisms:
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
■ The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
■ Power-On Reset and an internal timer (t
)
PUW
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
■ The Write Protect (W) signal, in co-operation
with the Status Register Write Disable (SRWD)
bit, allows the Block Protect (BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be
write-protected. This is the Hardware Protected
Mode (HPM).
■ Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
■ All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
■ In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
– Power-up
– Write Disable (WRDI) instruction completion
Figure 6. Hold Condition Activation
C
HOLD
Active
Hold
Active
Hold
Active
AI02029C
6/32
M25P05
the rising edge does not coincide with Serial Clock
(C) being Low, the Hold condition ends when Se-
rial Clock (C) next goes Low. (This is shown in Fig-
ure 6).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in Fig-
ure 6).
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts
when Serial Clock (C) next goes Low. Similarly, if
7/32
M25P05
MEMORY ORGANIZATION
The memory is organized as:
■ 65536 bytes (8 bits each)
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
■ 2 sectors (256 Kbits, 32768 bytes each)
■ 512 pages (128 bytes each).
Table 3. Memory Organization
Sector
Address Range
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
1
0
08000h
0FFFFh
07FFFh
00000h
Figure 7. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
128 Byte
Data Buffer
0FFFFh
08000h
00000h
0007Fh
128 Bytes (Page Size)
X Decoder
AI04039
8/32
M25P05
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
At the end of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) or Write Status Register
(WRSR) instruction, Chip Select (S) must be driv-
en High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number
of clock pulses after Chip Select (S) being driven
Low is an exact multiple of eight.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
The instruction set is listed in Table 4.
Depending on the instruction, the one-byte in-
struction code is followed by address bytes, or by
data bytes, or by both or none. Chip Select (S)
must be driven High after the last bit of the instruc-
tion sequence has been shifted in.
Table 4. Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
PP
Description
One-byte Instruction Code
0000 0110
Write Enable
Write Disable
0000 0100
Read Status Register
Write Status Register
Read Data Bytes
Page Program
0000 0101
0000 0001
0000 0011
0000 0010
SE
Sector Erase
1101 1000
BE
Bulk Erase
1100 0111
DP
Deep Power-down
1011 1001
RES
Release from Deep Power-down, and Read Electronic Signature
1010 1011
9/32
M25P05
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281D
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750C
– Power-up
– Write Disable (WRDI) instruction completion
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9)
resets the Write Enable Latch (WEL) bit.
– Write Status Register (WRSR) instruction com-
pletion
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
10/32
M25P05
Figure 10. Read Status Register (RDSR) Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031C
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruction is accepted.
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 10.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. When both of
the Block Protect (BP1, BP0) bits are set to 1, the
whole memory is protected against Page Program
(PP) and Sector Erase (SE) instructions. The Bulk
Erase (BE) instruction is executed if, and only if,
both Block Protect (BP1, BP0) bits are 0. This is
summarized in Table 2. The Block Protect (BP1,
BP0) bits can be written provided that the Hard-
ware Protected mode has not been set.
Table 5. Status Register Format
b7
b0
SRWD
0
0
0
BP1 BP0 WEL WIP
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
Note: 1. SRWD, BP1 and BP0 are non-volatile read and write bits.
2. WEL and WIP are volatile read-only bits (WEL is set and
reset by specific instructions; WIP is automatically set
and reset by the internal logic of the device).
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Process (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
11/32
M25P05
Figure 11. Write Status Register (WRSR) Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282C
(whose duration is t ) is initiated. While the Write
W
Write Status Register (WRSR)
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complet-
ed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2. The Write Status Register (WRSR) in-
struction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in ac-
cordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
12/32
M25P05
Table 6. Protection Modes
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
1
1
Protected Area
Unprotected Area
1
0
0
0
Status Register is
Writable (if the WREN
Software instruction has set the
Protected WEL bit)
Protected against Page
Program and Sector
Erase
Ready to accept Page
Program and Sector
Erase instructions
(SPM)
The values in the BP1
and BP0 bits can be
changed
1
0
1
1
Status Register is
Hardware Hardware write protected
Protected The values in the BP1
Protected against Page
Program and Sector
Erase
Ready to accept Page
Program and Sector
Erase instructions
(HPM)
and BP0 bits cannot be
changed
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
(Attempts to write to the Status Register are re-
The protection features of the device are summa-
rized in Table 6.
jected, and are not accepted for execution). As
a consequence, all the data bytes in the memo-
ry area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Reg-
ister, are also hardware protected against data
modification.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
– If Write Protect (W) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
– If Write Protect (W) is driven Low, it is not pos-
sible to write to the Status Register even if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
– or by driving Write Protect (W) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
13/32
M25P05
Figure 12. Read Data Bytes (READ) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748C
Note: 1. Address bits A23 to A16 must be set to 00h.
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
There is no address roll-over; when the highest
address (0FFFFh) is reached, the instruction
should be terminated.
Read Data Bytes (READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
a maximum frequency f , during the falling edge of
R
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location.
The address is automatically incremented to the
14/32
M25P05
Figure 13. Page Program (PP) Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 128
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI03749C
Note: 1. Address bits A23 to A16 must be set to 00h.
data bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 128 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes (of which the
most significant byte, A23-A16, must be 00h) and
at least one data byte on Serial Data Input (D). If
the 7 least significant address bits (A6-A0) are not
all zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are pro-
grammed from the start address of the same page
(the one whose 7 least significant address bits
(A6-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration of the sequence.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is t
)
PP
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. When the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP0, BP1)
bits (see Table 2) is not executed.
The instruction sequence is shown in Figure 13.
If more than 128 bytes are sent to the device, pre-
viously latched data are discarded and the last 128
15/32
M25P05
Figure 14. Sector Erase (SE) Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751C
Note: 1. Address bits A23 to A16 must be set to 00h.
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
ration is t ) is initiated. While the Sector Erase cy-
SE
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see Table 2) is not executed.
The instruction sequence is shown in Figure 14.
16/32
M25P05
Figure 15. Bulk Erase (BE) Sequence
S
C
D
0
1
2
3
4
5
6
7
Instruction
AI03752C
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Erase cycle (whose duration is
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
t
) is initiated. While the Bulk Erase cycle is in
BE
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
both Block Protect (BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more,
sectors are protected.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
17/32
M25P05
Figure 16. Deep Power-down (DP) Sequence
S
t
DP
0
1
2
3
4
5
6
7
C
D
Instruction
Stand-by Mode
Deep Power-down Mode
AI03753C
ture of the device to be output on Serial Data Out-
put (Q).
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
to reduce the standby current (from I
to I
,
CC1
CC2
driven High, it requires a delay of t
before the
DP
as specified in Table 13).
supply current is reduced to I
and the Deep
CC2
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
18/32
M25P05
Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Sequence
S
C
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Electronic Signature Out
High Impedance
7
6
5
4
3
2
0
1
MSB
Deep Power-down Mode
Stand-by Mode
AI03755C
value for the M25P05 is 10h. This can be read us-
ing the Release from Deep Power-down and Read
Electronic Signature (RES) instruction.
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode. The instruction can also be used to
read, on Serial Data Output (Q), the 8-bit Electron-
ic Signature of the device.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by a
dummy 3-byte address (A23-A0), each bit being
latched-in on Serial Data Input (D) during the rising
edge of Serial Clock (C). Then, the 8-bit Electronic
Signature, stored in the memory, is shifted out on
Serial Data Output (Q), each bit being shifted out
during the falling edge of Serial Clock (C).
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the
Electronic Signature of the device, and can be ap-
plied even if the Deep Power-down mode has not
been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The instruction sequence is shown in Figure 17.
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
Once Chip Select (S) is driven High, the device is
put in the Standby mode. The device waits to be
selected, so that it can receive, decode and exe-
cute instructions.
This instruction serves a second purpose. The de-
vice features an 8-bit Electronic Signature, whose
19/32
M25P05
Figure 18. Release from Deep Power-down (RES) Sequence
S
t
RES
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Stand-by Mode
AI03754C
ure 18), still insures that the device is taken out of
the Deep Power-down mode, but incurs a delay
Driving Chip Select (S) High after the 8-bit instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in Fig-
(t
) before the device is put in Standby mode.
Chip Select (S) must remain High for at least
(max), as specified in Table 14.
RES
t
RES
20/32
M25P05
POWER-UP, POWER-DOWN AND DELIVERY STATE
Moreover, the device ignores all Page Program
(PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instructions until a
Power-up
At Power-up, the device must not be selected (that
time delay of t
has elapsed after the moment
PUW
is Chip Select (S) must follow the voltage supplied
on until the supply voltage reaches
(min), and a further t delay has elapsed.
that V
rises above the V threshold. However,
CC
WI
V
)
CC
the correct operation of the device is not
guaranteed if, by this time, V is still below
V
CC
VSL
CC
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset
(POR) circuit is included. The logic inside the
device is held reset while V is less than the POR
threshold value, V – all operations are disabled,
and the device will not respond to any instruction.
Similarly, when V
V
(min). No Write Status Register, Program or
CC
Erase instructions should be sent until the later of:
– t
– t
after V passed the V threshold
CC WI
PUW
VSL
CC
afterV passed the V (min) level
WI
CC
CC
These values are specified in Table 7.
drops from the operating
CC
voltage, to below the POR threshold value, V , all
operations are disabled and the device will not
respond to any instruction.
No instructions (including Read, Write Status
Register, Program or Erase instructions) should
WI
At Power-up, the device is in the following state:
– The device is in the Standby mode (not the
Deep Power-down mode).
– The Write Enable Latch (WEL) bit is reset.
be sent to the device until a time delay of t
after
VSL
V
has risen above the V (min) level.
CC
CC
Figure 19. Power-up Timing
V
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009B
Table 7. Power-Up Timing and V Threshold
WI
Symbol
Parameter
Min.
Max.
Unit
1
V
(min) to S low
10
µs
ms
V
tVSL
CC
1
Time delay to Write instruction
Write Inhibit Voltage
15
tPUW
1
1.5
2.5
VWI
Note: 1. These parameters are characterized only.
21/32
M25P05
INITIAL DELIVERY STATE
Power-down
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V ) until V
correct value:
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
reaches the
CC
CC
– V (min) at Power-up
CC
Table 8. Initial Status Register Format
– V at Power-down
SS
b7
0
b0
0
A simple pull-up resistor on Chip Select (S) can be
used to insure safe and proper Power-up and
Power-down.
0
0
0
0
0
0
22/32
M25P05
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
150
235
4.0
Unit
°C
°C
V
T
STG
Storage Temperature
–65
1
TLEAD
VIO
Lead Temperature during Soldering (20 seconds max.)
Input and Output Voltage (with respect to Ground)
Supply Voltage
–0.6
–0.6
V
4.0
V
CC
2
VESD
–2000
2000
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
23/32
M25P05
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 10. Operating Conditions
Symbol
Parameter
Min.
2.7
Max.
3.6
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 11. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
5
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 20. AC Measurement I/O Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825
Table 12. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
Input Capacitance (other pins)
V
8
6
OUT
CIN
V
IN
= 0V
pF
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 20 MHz.
A
24/32
M25P05
Table 13. DC Characteristics
Test Condition
(in addition to those in Table 10)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
50
5
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down Current
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open
ICC3
Operating Current (READ)
3
mA
ICC4
ICC5
ICC6
ICC7
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
S = VCC
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
mA
V
15
15
0.3VCC
VCC+1
– 0.5
VIH
0.7VCC
Input High Voltage
V
Output Low Voltage
IOL = 1.6 mA
0.4
V
VOL
VOH
I
OH = –100 µA
VCC–0.2
Output High Voltage
V
25/32
M25P05
Table 14. AC Characteristics
Test conditions specified in Table 10 and Table 11
Symbol
Alt.
Parameter
Min.
D.C.
10
Max.
Unit
MHz
ns
f
f
C
Clock Frequency
20
C
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Clock High Time
SLCH
CSS
t
10
ns
CHSL
1
t
22
ns
t
CLH
CH
1
t
Clock Low Time
22
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CLL
CL
t
t
Data In Setup Time
DVCH
DSU
t
t
Data In Hold Time
5
CHDX
DH
t
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
10
10
50
CHSH
t
SHCH
t
t
CSH
SHSL
2
t
Output Disable Time
20
20
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
t
t
HO
0
CLQX
t
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
10
10
10
10
HLCH
t
CHHH
t
HHCH
t
CHHL
2
t
20
20
t
LZ
HHQX
2
t
HOLD to Output High-Z
ns
µs
µs
t
HZ
HLQZ
2
S High to Deep Power-down Mode
S High to Standby Mode
1.6
1.6
t
DP
2
t
RES
t
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Bulk Erase Cycle Time
5
5
2
4
ms
ms
s
W
t
PP
t
SE
t
BE
s
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
26/32
M25P05
Figure 21. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 22. Hold Timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD
AI02032
27/32
M25P05
Figure 23. Output Timing
S
C
tCH
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
AI01449C
28/32
M25P05
PACKAGE MECHANICAL
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
C
A
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
29/32
M25P05
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M25P05
–
V
MN
6
T
Device Type
M25P
Device Function
05 = 512 Kbit (64K x 8)
Operating Voltage
V = V = 2.7 to 3.6V
CC
Package
MN = SO8 (150 mil width)
Temperature Range
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
30/32
M25P05
REVISION HISTORY
Table 16. Document Revision History
Date
Description of Revision
09-Feb-2001 1.0
26-Mar-2001 1.1
12-Apr-2001 1.2
25-May-2001 1.3
Document written
Correction to descriptions on Hold condition and Power up: no parameters changed
Descriptions of Page Programming made more precise
Serial Paged Flash Memory renamed as Serial Flash Memory
Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes;
Release from Power-down and Read Electronic Signature (RES); Power-up
Repositioning of several tables and illustrations without changing their contents
Power-up timing illustration; SO8W package removed
11-Sep-2001 1.4
25-Feb-2002 1.5
Changes to tables: Abs Max Ratings/V ; DC Characteristics/V
IO
IL
Product is “Not for New Design”
31/32
M25P05
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong -
India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
www.st.com
32/32
相关型号：
M25P10-A
512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface
STMICROELECTR
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