M25P64-VME6TPA [NUMONYX]
Flash Memory,;型号: | M25P64-VME6TPA |
厂家: | NUMONYX B.V |
描述: | Flash Memory, 时钟 光电二极管 内存集成电路 |
文件: | 总54页 (文件大小:1079K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M25P64
64 Mbit, low voltage, Serial Flash memory
with 75 MHz SPI bus interface
Features
64 Mbit of Flash memory
2.7 V to 3.6 V single supply voltage
SPI bus compatible serial interface
75 MHz clock rate (maximum)
VDFPN8 (ME)
8 × 6 mm (MLP8)
Page Program (up to 256 Bytes)
– in 1.4 ms (typical)
– in 0.35 ms (typical with VPP = 9 V)
Sector Erase (512 Kbit)
Bulk Erase (64 Mbit)
Electronic Signatures
– JEDEC standard two-Byte signature
(2017h)
SO16 (MF)
300 mils width
– RES instruction, one-Byte, signature (16h),
for backward compatibility
– Unique ID code (UID) with 16 bytes
readonly: available upon customer request
Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
More than 100 000 Erase/Program cycles per
sector
More than 20-year data retention
Packages
– RoHS compliant
Automotive certified parts available
May 2009
Rev 9
1/54
www.numonyx.com
1
Contents
M25P64
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10
V
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
6.2
6.3
6.4
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/54
M25P64
Contents
6.4.2
6.4.3
6.4.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
6.6
6.7
6.8
6.9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 31
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11 Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
9
10
11
12
13
3/54
List of tables
M25P64
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC characteristics process technology T9HX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AC characteristics, T9HX parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
Table 19.
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20.
Table 21.
4/54
M25P64
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 26
Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 27
Figure 12. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence . . . 31
Figure 15. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . 36
Figure 19. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 46
Figure 23. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 49
5/54
Description
M25P64
1
Description
The M25P64 is a 64 Mbit (8M x 8) Serial Flash Memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus instructions allowing clock
frequency up to 75 MHz.(1)
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
An enhanced Fast Program/Erase mode is available to speed up operations in factory
environment. The device enters this mode whenever the VPPH voltage is applied to the Write
Protect/Enhanced Program Supply Voltage pin (W/VPP).(2)
The memory is organized as 128 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 32768 pages, or
8388608 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P64 in Lead-free and
RoHS compliant packages.
Note:
Important: This datasheet details the functionality of the M25P64 devices, based on the
previous process or based on the current T9HX process (available since March 2008). The
new device in T9HX is backward compatible with the old one and it includes these additional
features:
- improved max frequency (Fast Read) to 75 MHz
- UID/CFD protection feature
1. 75 MHz operation is available only for process technology T9HX devices, identified by process identification
digit "4" in the device marking.
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
6/54
M25P64
Description
Figure 1. Logic diagram
V
CC
D
C
S
Q
M25P64
W/V
PP
HOLD
V
SS
AI07485B
Table 1.
Signal names
Signal name
Function
Direction
Input
C
Serial Clock
D
Serial Data Input
Serial Data Output
Chip Select
Input
Output
Input
Input
Input
Q
S
W/VPP
HOLD
VCC
VSS
Write Protect/Enhanced Program Supply Voltage
Hold
Supply Voltage
Ground
Figure 2. VDFPN connections
M25P64
S
1
8
7
6
5
V
CC
HOLD
Q
2
3
4
W/V
C
D
PP
V
SS
AI08595B
1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally, to VSS
and must not be allowed to be connected to any other voltage or signal line on the PCB.
,
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
7/54
Description
M25P64
Figure 3. SO connections
M25P64
HOLD
1
16
15
14
13
12
11
10
9
C
V
2
3
4
5
6
7
8
D
CC
DU
DU
DU
DU
S
DU
DU
DU
DU
V
SS
Q
W/V
PP
AI07486C
1. DU = Don’t Use
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
8/54
M25P64
Signal description
2
Signal description
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3
2.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the
device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
9/54
Signal description
M25P64
2.6
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control
input. This input signal is used to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the values in the BP2, BP1 and BP0
bits of the Status Register).
If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must
be stable until the Program/Erase algorithm is completed.(1)
2.7
2.8
VCC supply voltage
VCC is the supply voltage.
VSS ground
VSS is the reference for the VCC supply voltage.
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
10/54
M25P64
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus master and memory devices on the SPI bus
V
V
SS
CC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
V
V
V
CC
C
Q
D
C
Q
D
C Q D
CC
CC
V
V
V
SS
SS
SS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
W/V
HOLD
S
W/V
HOLD
S
W/V
HOLD
PP
PP
PP
AI13792
1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the Serial Data Output (Q) line at
a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure
that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
11/54
SPI modes
M25P64
Example: Cp = 50 pF, that is R*Cp = 5 μs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 μs.
Figure 5. SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
12/54
M25P64
Operating features
4
Operating features
4.1
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)
and Table 16: AC characteristics).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
Fast Program/Erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device
enters the Fast Program/Erase mode during the Page Program, Sector Erase, or Bulk
Erase(1) instruction whenever a voltage equal to VPPH is applied to the W/VPP pin.
The use of the Fast Program/Erase mode requires specific operating conditions in addition
to the normal ones (VCC must be within the normal operating range):
the voltage applied to the W/VPP pin must be equal to VPPH (see Table 10)
ambient temperature, TA must be 25°C ±10°C,
the cumulated time during which W/VPP is at VPPH should be less than 80 hours
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
13/54
Operating features
M25P64
4.5
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1
.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
14/54
M25P64
Operating features
4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P64 features the following data protection mechanisms:
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertant changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
Table 2.
Protected area sizes
Status Register
content
Memory content
BP2 BP1 BP0
Protected area
Unprotected area
Bit
Bit
Bit
0
0
0
0
0
1
0
1
0
none
Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125)
All sectors(1) (128 sectors: 0 to 127)
Upper 32nd (4 sectors: 124 to 127)
Lower 31/32nds (124 sectors: 0 to 123)
Lower 15/16ths (120 sectors: 0 to 119)
Upper sixteenth (8 sectors: 120 to
127)
0
1
1
1
0
0
1
0
1
Lower seven-eighths (112 sectors: 0 to
111)
Upper eighth (16 sectors: 112 to 127)
Upper quarter (32 sectors: 96 to 127)
Lower three-quarters (96 sectors: 0 to
95)
1
1
1
1
0
1
Upper half (64 sectors: 64 to 127)
All sectors (128 sectors: 0 to 127)
Lower half (64 sectors: 0 to 63)
none
1. The device is ready to accept a Bulk Erase instruction, if and only if, all Block Protect (BP2, BP1, BP0) are
0.
15/54
Operating features
M25P64
4.8
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 6).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 6. Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
AI02029D
16/54
M25P64
Memory organization
5
Memory organization
The memory is organized as:
8388608 bytes (8 bits each)
128 sectors (512 Kbits, 65536 bytes each)
32768 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 7. Block diagram
HOLD
High Voltage
Generator
W/V
Control Logic
PP
S
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
7FFFFFh
Size of the
read-only
memory area
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI08520B
17/54
Memory organization
Table 3.
M25P64
Memory organization
Sector
Address range
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
7F0000h
7E0000h
7D0000h
7C0000h
7B0000h
7A0000h
790000h
780000h
770000h
760000h
750000h
740000h
730000h
720000h
710000h
700000h
6F0000h
6E0000h
6D0000h
6C0000h
6B0000h
6A0000h
690000h
680000h
670000h
660000h
650000h
640000h
630000h
620000h
610000h
600000h
5F0000h
5E0000h
5D0000h
7FFFFFh
7EFFFFh
7DFFFFh
7CFFFFh
7BFFFFh
7AFFFFh
79FFFFh
78FFFFh
77FFFFh
76FFFFh
75FFFFh
74FFFFh
73FFFFh
72FFFFh
71FFFFh
70FFFFh
6FFFFFh
6EFFFFh
6DFFFFh
6CFFFFh
6BFFFFh
6AFFFFh
69FFFFh
68FFFFh
67FFFFh
66FFFFh
65FFFFh
64FFFFh
63FFFFh
62FFFFh
61FFFFh
60FFFFh
5FFFFFh
5EFFFFh
5DFFFFh
98
97
96
95
94
93
18/54
M25P64
Memory organization
Table 3.
Memory organization (continued)
Sector
Address range
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
5C0000h
5B0000h
5A0000h
590000h
580000h
570000h
560000h
550000h
540000h
530000h
520000h
510000h
500000h
4F0000h
4E0000h
4D0000h
4C0000h
4B0000h
4A0000h
490000h
480000h
470000h
460000h
450000h
440000h
430000h
420000h
410000h
400000h
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
5CFFFFh
5BFFFFh
5AFFFFh
59FFFFh
58FFFFh
57FFFFh
56FFFFh
55FFFFh
54FFFFh
53FFFFh
52FFFFh
51FFFFh
50FFFFh
4FFFFFh
4EFFFFh
4DFFFFh
4CFFFFh
4BFFFFh
4AFFFFh
49FFFFh
48FFFFh
47FFFFh
46FFFFh
45FFFFh
44FFFFh
43FFFFh
42FFFFh
41FFFFh
40FFFFh
3FFFFFh
3EFFFFh
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
19/54
Memory organization
Table 3.
M25P64
Memory organization (continued)
Sector
Address range
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
33FFFFh
32FFFFh
31FFFFh
30FFFFh
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
20/54
M25P64
Memory organization
Table 3.
Memory organization (continued)
Sector
Address range
22
21
20
19
18
17
16
15
14
13
12
11
10
9
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
8
7
6
5
4
3
2
1
0
21/54
Instructions
M25P64
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR), Read Identification (RDID) or Read Electronic Signature
(RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (S) must driven High when the number of clock pulses after
Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 4.
Instruction set
One-byte instruction Address
Dummy
bytes
Data
bytes
Instruction
Description
code
bytes
WREN
WRDI
RDID
Write Enable
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
06h
04h
9Fh
05h
01h
03h
0
0
0
0
0
3
0
0
0
0
0
0
0
0
Write Disable
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
1 to 3
1 to ∞
1
RDSR
WRSR
READ
1 to ∞
Read Data Bytes at
Higher Speed
FAST_READ
PP
0000 1011
0000 0010
0Bh
02h
3
3
1
0
1 to ∞
1 to
256
Page Program
SE
BE
Sector Erase
1101 1000
1100 0111
1010 1011
D8h
C7h
ABh
3
0
0
0
0
3
0
0
Bulk Erase
RES
Read Electronic Signature
1 to ∞
22/54
M25P64
Instructions
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8. Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
23/54
Instructions
M25P64
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
24/54
M25P64
Instructions
6.3
Read Identification (RDID)
The read identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A unique ID code (UID) (17 bytes, of which 16 available upon customer request).(1)
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx.
The device identification is assigned by the device manufacturer, and indicates the memory
type in the first byte (20h), and the memory capacity of the device in the second byte (17h).
The UID contains the length of the following data in the first byte (set to 10h) and 16 bytes of
the optional customized factory data (CFD) content. The CFD bytes are read-only and can
be programmed with customers data upon their demand. If the customers do not make
requests, the devices are shipped with all the CFD bytes programmed to zero (00h).
Any read identification (RDID) instruction while an erase or program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The read identification (RDID) instruction should not be issued while the device is in deep
power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
serial data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The read identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output. When Chip Select (S) is driven High, the device is put in the
standby power mode. Once in the standby power mode, the device waits to be selected so
that it can receive, decode, and execute instructions.
Table 5.
Read identification (RDID) data-out sequence
Device identification
UID
Manufacturer identification
Memory type
20h
Memory capacity
CFD length
CFD content
20h
17h
10h
16 bytes
1. The UID feature is available only for process technology T9HX devices, identified by process identification digit
"4" in the device marking.
25/54
Instructions
M25P64
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
28 29 30 31
C
Instruction
DQ0
Manufacturer identification
Device identification
UID
High Impedance
DQ1
15 14 13
MSB
3
2
1
0
MSB
MSB
AI06809d
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 11.
Table 6.
Status Register format
b7
b0
SRWD
0
0
BP2
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
The status and control bits of the Status Register are as follows:
6.4.1
6.4.2
6.4.3
26/54
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
M25P64
Instructions
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
27/54
Instructions
M25P64
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write
Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the Hardware Protected
Mode (HPM) is entered.
Table 7.
Protection modes
Memory content
W/VPP SRWD
Write Protection of the
Status Register
Mode
signal
bit
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
Software
Protected
(SPM)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
instructions
1
1
Status Register is
Hardware write protected
Hardwar
e
Protected
(HPM)
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
0
1
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
The protection features of the device are summarized in Table 7.
28/54
M25P64
Instructions
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect/ (W/VPP) High.
If Write Protect/ (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
29/54
Instructions
M25P64
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748D
1. Address bit A23 is Don’t Care.
30/54
M25P64
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
1. Address bit A23 is Don’t Care.
31/54
Instructions
M25P64
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Table 16: AC
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
32/54
M25P64
Instructions
Figure 15. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04082B
33/54
Instructions
M25P64
6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 16. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
1. Address bit A23 is Don’t Care.
34/54
M25P64
Instructions
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Instruction
AI03752D
35/54
Instructions
M25P64
6.11
Read Electronic Signature (RES)
The instruction is used to read, on Serial Data Output (Q), the old-style 8-bit Electronic
Signature, whose value for the M25P64 is 16h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic
Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic
Signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic
Signature, and the Read Identifier (RDID) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is
shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 18.
The Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S)
High after the Electronic Signature has been read at least once. Sending additional clock
cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic
Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time,
still ensures that the device is put into Standby Power mode. Once in the Standby Power
mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Figure 18. Read Electronic Signature (RES) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
C
Instruction
3 Dummy Bytes
23 22 21
MSB
3
2
1
0
D
Q
Electronic Signature Out
High Impedance
7
6
5
4
3
2
0
1
MSB
AI04047C
1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h.
36/54
M25P64
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
V
CC(min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during Power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
tPUW after VCC passed the VWI threshold
VSL after VCC passed the VCC(min) level
t
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
The device is in the Standby Power mode
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.).
Power up sequencing for Fast program/erase mode: VCC should attain VCCMIN before VPPH
is applied.
37/54
Power-up and Power-down
M25P64
Figure 19. Power-up timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
Table 8.
Power-Up timing and VWI threshold
Parameter
Symbol
Min.
Max.
Unit
(1)
tVSL
VCC(min) to S low
30
1
μs
ms
V
(1)
tPUW
Time delay to Write instruction
Write Inhibit Voltage
10
(1)
VWI
1.5
2.5
1. These parameters are characterized only.
38/54
M25P64
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the Numonyx SURE Program and other relevant quality
documents.
Table 9.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TSTG
Storage Temperature
–65
150
°C
°C
TLEAD
Lead Temperature during Soldering
See note (1)
VCC
–0.5
+
VIO
Input and Output Voltage (with respect to Ground)
V
0.6
VCC
VPP
Supply Voltage
–0.2
–0.2
4.0
V
V
V
Fast Program/Erase Voltage(2)
10.0
VESD
Electrostatic Discharge Voltage (Human Body model) (3)
–2000
2000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly) and the European
directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices,
identified by process identification digit "4" in the device marking.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1 = 1500 Ω, R2 = 500 Ω).
39/54
DC and AC parameters
M25P64
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 10. Operating conditions
Symbol
Parameter
Min.
Typ
Max. Unit
VCC
Supply Voltage
2.7
3.6
9.5
V
V
Supply Voltage on W/VPP pin for Fast Program/Erase
mode (1)
VPPH
8.5
TA
TA
Ambient Operating Temperature (grade 6)(2)
Ambient Operating Temperature (grade 3)(3)
–40
–40
85
°C
°C
125
Ambient Operating Temperature for Fast
Program/Erase mode
TAVPP
15
25
35
°C
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices,
identified by process identification digit "4" in the device marking.
2. "Autograde 6 and Standard parts (grade 6) are tested to 85 °C, but the Autograde 6 will follow the HRCF.
3. Autograde 3 is tested to 125 °C.
Table 11.
Data Retention and Endurance
Parameter
Condition
Min.
Max.
Unit
Program / erase cycles Grade 3, Autograde 6, Grade 6 100,000
Cycles per sector
years
Data retention
at 55°C
20
Table 12. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
CL
Load Capacitance
30
pF
ns
V
Input Rise and Fall Times
5
Input Pulse Voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC / 2
Input Timing Reference Voltages
Output Timing Reference Voltages
V
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
40/54
M25P64
DC and AC parameters
Figure 20. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
CC
0.3V
CC
0.5V
0.2V
CC
AI07455
Table 13. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
CIN
Output Capacitance (Q)
VOUT = 0 V
VIN = 0 V
8
6
pF
pF
Input Capacitance (other pins)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 20 MHz.
Table 14. DC characteristics
Test condition
Symbol
Parameter
(in addition to those in
Min.
Max.
Unit
Table 10)
ILI
ILO
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
μA
μA
μA
ICC1
S = VCC, VIN = VSS or VCC
100
C = 0.1VCC / 0.9.VCC at 50 MHz,
Q = open
8
4
mA
mA
ICC3
Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open
ICC4
ICC5
ICC6
ICC7
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
S = VCC
S = VCC
S = VCC
S = VCC
15
20
20
20
mA
mA
mA
mA
Operating current for Fast
Program/Erase mode
ICCPP
S = VCC, VPP = VPPH
20
mA
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
– 0.5
0.3VCC
V
V
V
V
0.7VCC VCC+0.2
0.4
VOL
VOH
IOL = 1.6 mA
IOH = –100 μA
VCC–0.2
41/54
DC and AC parameters
Table 15. DC characteristics process technology T9HX (1)
M25P64
Unit
Test condition (in addition
Symbol
Parameter
Min
Max
to those in Table 10)
ILI
Input leakage current
Output leakage current
Standby current
± 2
± 2
50
μA
μA
μA
μA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Deep Power-down current
10
C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open
12
4
mA
mA
ICC3
Operating current (READ)
C = 0.1VCC / 0.9VCC at
33 MHz, DQ1 = open
ICC4
ICC5
ICC6
VIL
Operating current (PP)
Operating current (WRSR)
Operating current (SE)
Input low voltage
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
V
15
– 0.5
0.3VCC
VIH
Input high voltage
0.7VCC VCC+0.4
V
VOL
VOH
Output low voltage
IOL = 1.6 mA
0.4
V
Output high voltage
IOH = –100 μA
VCC–0.2
V
1. Technology T9HX devices are identified by process identification digit "4" in the device marking.
42/54
M25P64
DC and AC parameters
Table 16. AC characteristics
Test conditions specified in Table 10 and Table 12
Symbol Alt.
Parameter
Min.
Typ.
Max. Unit
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR
fC
fR
fC
D.C.
50
20
MHz
Clock Frequency for READ instructions
D.C.
9
MHz
ns
(1)
tCH
tCLH Clock High Time
tCLL Clock Low Time
(1)
tCL
9
ns
(2)
(2)
tCLCH
tCHCL
Clock Rise Time(3) (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
Clock Fall Time(3) (peak to peak)
tCSS S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
tDSU Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
5
ns
2
ns
tDH Data In Hold Time
5
ns
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
tCSH S Deselect Time
5
ns
5
ns
100
ns
(2)
tSHQZ
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tDIS Output Disable Time
8
8
ns
tV Clock Low to Output Valid
tHO Output Hold Time
ns
0
5
5
5
5
ns
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
tLZ HOLD to Output Low-Z
tHZ HOLD to Output High-Z
Write Protect Setup Time
ns
ns
ns
ns
(2)
tHHQX
tHLQZ
tWHSL
tSHWL
8
8
ns
(2)
(4)
(4)
ns
20
ns
Write Protect Hold Time
100
ns
(6)
tVPPHSL
tW
Enhanced Program Supply Voltage High to Chip Select Low 200
Write Status Register Cycle Time
ns
5
15
5
ms
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.4
ms
(5)
tPP
0.4+ n*1/256
Page Program Cycle Time (VPP = VPPH) (256 Bytes)
Sector Erase Cycle Time
0.35
1
ms
s
3
tSE
Sector Erase Cycle Time (VPP = VPPH
Bulk Erase Cycle Time
)
0.5
68
35
s
160
160
s
tBE
Bulk Erase Cycle Time (VPP = VPPH
)
s
1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256).
6.
VPPH should be kept at a valid level until the program/erase operation is completed and result (success or failure) is known.
43/54
DC and AC parameters
M25P64
Table 17. AC characteristics, T9HX parts (page 1 of 2) (1)
Test conditions specified in Table 10 and Table 12
Symbol
Alt.
Parameter
Min
Typ(2)
Max
Unit
Clock frequency for the following instructions:
FAST_READ, SE, BE, WREN, WRDI, RDID,
RDSR, WRSR, PP
fC
fC
D.C.
75
33
MHz
fR
Clock frequency for read instructions
D.C.
6
MHz
ns
(3)
tCH
tCLH Clock High time
tCLL Clock Low time
(2)
tCL
6
ns
(4)
tCLCH
Clock rise time(5) (peak to peak)
0.1
0.1
5
V/ns
V/ns
ns
(3)
tCHCL
Clock fall time(4) (peak to peak)
tCSS S active setup time (relative to C)
S not active hold time (relative to C)
tDSU Data in setup time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
5
ns
2
ns
tDH Data in hold time
5
ns
S active hold time (relative to C)
S not active setup time (relative to C)
tCSH S deselect time
5
ns
5
ns
80
ns
(3)
tSHQZ
tDIS Output disable time
8
8
6
ns
Clock Low to Output valid under 30 pF
ns
tCLQV
tV
Clock Low to Output valid under 10 pF
ns
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO Output hold time
0
5
5
5
5
ns
HOLD setup time (relative to C)
HOLD hold time (relative to C)
HOLD setup time (relative to C)
HOLD hold time (relative to C)
tLZ HOLD to Output Low-Z
tHZ HOLD to Output High-Z
Write protect setup time
ns
ns
ns
ns
(3)
tHHQX
8
8
ns
(3)
tHLQZ
ns
(6)
tWHSL
20
ns
(5)
tSHWL
Write protect hold time
100
ns
Enhanced program supply voltage High
(VPPH) to Chip Select Low
(7)
tVPPHSL
200
ns
(3)
tRDP
tW
S High to standby mode
30
15
μs
Write status register cycle time
Page program cycle time (256 bytes)
Page program cycle time (n bytes)
1.3
0.8
ms
(8)
tPP
5
ms
int(n/8) × 0.025(9)
44/54
M25P64
DC and AC parameters
Table 17. AC characteristics, T9HX parts (page 2 of 2) (1)
Test conditions specified in Table 10 and Table 12
Parameter Min
Symbol
Alt.
Typ(2)
Max
Unit
tSE
tBE
Sector erase cycle time
Bulk erase cycle time
0.7
68
3
s
s
160
1. Technology T9HX devices are identified by process identification digit "4" in the device marking.
2. Typical values given for TA = 25° C.
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
7.
V
PPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is
known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
8. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
9. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 21. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
45/54
DC and AC parameters
M25P64
Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1
W/V
PP
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439b
Figure 23. Hold timing
S
tHLCH
tCHHL
tHLQZ
tHHCH
C
tCHHH
tHHQX
Q
D
HOLD
AI02032
46/54
M25P64
DC and AC parameters
Figure 24. Output timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR
LSB IN
D
AI01449e
Figure 25. VPPH timing
End of PP, SE or BE
(identified by WPI polling)
S
C
D
PP, SE, BE
VPPH
W/VPP
ai12092
tVPPHSL
47/54
Package mechanical
M25P64
11
Package mechanical
Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline
D
E
E2
e
b
D2
A
L
K
L1
ddd
A1
VDFPN-02
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 18. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
b
0.85
1.00
0.05
0.48
0.0335
0.0394
0.0020
0.0189
0.00
0.35
0.0000
0.0138
0.40
8.00
5.16
0.0157
0.3150
0.2031
D
(1)
D2
ddd
E
0.05
0.0020
6.00
4.80
1.27
0.2362
0.1890
0.0500
E2
e
–
–
–
–
K
0.82
0.45
0.0323
0.0177
L
0.50
0.60
0.15
0.0197
0.0236
0.0059
L1
N
8
8
1. D2 Max must not exceed (D – K – 2 × L).
48/54
M25P64
Package mechanical
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
D
h x 45˚
C
16
9
E
H
1
8
θ
A2
A
A1
L
ddd
B
e
SO-H
1. Drawing is not to scale.
Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
B
2.35
0.10
0.33
0.23
10.10
7.40
–
2.65
0.30
0.51
0.32
10.50
7.60
–
0.093
0.004
0.013
0.009
0.398
0.291
–
0.104
0.012
0.020
0.013
0.413
0.299
–
C
D
E
e
1.27
0.050
H
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.030
0.050
8°
h
L
θ
ddd
0.10
0.004
49/54
Part numbering
M25P64
12
Part numbering
Table 20. Ordering information scheme
Example:
M25P64
–
V
MF
6
T
P
B
A
Device Type
M25P = Serial Flash memory for Code Storage
Device Function
64 = 64 Mbit (8M x 8)
Operating Voltage
V = VCC = 2.7 V to 3.6 V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8 × 6 mm (MLP8)(1)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow.
3 = Automotive temperature range, –40 to 125 °C.(1)
Device tested with high reliability certified flow.(2)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = RoHS compliant
Lithography(3)
B = 110nm, Fab.2 Diffusion Plant
Automotive Grade
A = Automotive, –40 to 85 °C.
Device tested with high reliability certified flow(4)
blank = standard -40 to 85 °C device
1. Please contact your nearest Numonyx Sales Office for Automotive Package options availability.
2. Numonyx strongly recommends the use of the Automotive Grade devices (AutoGrade 6 and Grade 3) for use in an
automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask
your nearest Numonyx sales office for a copy.
3. The lithography digit is present only in the automotive parts ordering scheme.
4. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive envirnoment. The High
Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest Numonyx sales
office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
50/54
M25P64
Part numbering
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
51/54
Revision history
M25P64
13
Revision history
Table 21. Document revision history
Date
Revision
Changes
28-Apr-2003
15-May-2003
20-Jun-2003
18-Jul-2003
02-Sep-2003
0.1
0.2
0.3
0.4
0.5
Target Specification Document written in brief form
Target Specification Document written in full
8x6 MLP8 and SO16(300 mil) packages added
tPP, tSE and tBE revised
Voltage supply range changed
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added
19-Sep-2003
17-Dec-2003
15-Nov-2004
0.6
0.7
1.0
Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package
removed.
Document status promoted from Target Specification to Preliminary Data.
8x6 MLP8 package added. Minor wording changes.
Deep Power-Down mode removed from datasheet (Figure 18: Read
Electronic Signature (RES) instruction sequence and data-out sequence
modified and tRES1 and tRES2 removed from Table 16: AC
characteristics). SO16 Wide package specifications updated. End timing
line of tSHQZ modified in Figure 24: Output timing. Figures moved below
the corresponding instructions in the Instructions section.
24-Feb-2005
2.0
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP) and Table 16: AC characteristics.
Fast Program/Erase mode added and Power-up specified for Fast
Program/Erase mode in Power-up and Power-down section. W pin
changed to W/VPP. (see Write Protect/Enhanced Program supply voltage
(W/VPP) description). Note 2 inserted below Figure 26 Blank option
removed under Plating Technology.
23-Dec-2005
3.0
tVPPHSL added to Table 16: AC characteristics and Figure 25: VPPH
timing inserted.
All packages are RoHS compliant.
Document status promoted from Preliminary Data to full Datasheet
status.
VDFPN8 (MLP8) package specifications updated (see Section 11:
Package mechanical).
16-Feb-2006
07-Sep-2006
4.0
5
Figure 4: Bus master and memory devices on the SPI bus modified.
ICC1 maximum value updated in Table 14: DC characteristics.
Hardware Write Protection feature added to Features on page 1.
VCC supply voltage and VSS ground descriptions added.
Figure 4: Bus master and memory devices on the SPI bus updated and
explanatory paragraph added.
19-Jan-2007
6
At Power-up The Write In Progress (WIP) bit is reset.
VIO max modified and TLEAD added in Table 9: Absolute maximum
ratings. Small text changes.
Note 1 added to Table 18: VDFPN8 (MLP8) 8-lead Very thin Dual Flat
Package No lead, 8 × 6 mm, package mechanical data.
52/54
M25P64
Revision history
Table 21. Document revision history
Date
Revision
Changes
10-Dec-2007
7
Applied Numonyx branding.
To provide support for the Automotive market, added the following:
– Automotive bullet to cover page;
30-Oct-2008
22-May-2009
8
9
– Grade 3 and grade 6 information to Table 10.: Operating conditions;
– Table 11.: Data Retention and Endurance
– Automotive information to Table 20.: Ordering information scheme.
Added a lithography note to Table 20.: Ordering information scheme;
Added information supporting 75 MHz.
53/54
M25P64
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Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
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by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
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