M28W320BB90ZB1中文资料_数据手册_规格书

M28W320BT

M28W320BB

32 Mbit (2Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V = 2.7V to 3.6V Core Power Supply

DD

– V

= 1.65V to 3.3V for Input/Output

DDQ

FBGA

– V = 12V for fast Program (optional)

PP

■ ACCESS TIME: 70, 85, 90,100ns

■ PROGRAMMING TIME

– 10µs typical

TFBGA47 (ZB)

8 x 6 ball array

– Double Word Programming Option

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■ BLOCK PROTECTION on TWO PARAMETER

TSOP48 (N)

12 x 20mm

BLOCKS

– WP for Block Protection

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W320BT: 88BCh

– Bottom Device Code, M28W320BB: 88BDh

November 2001

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M28W320BT, M28W320BB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DD

Supply Voltage (1.65V to V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDQ

DD

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PP

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Memory Blocks Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M28W320BT, M28W320BB

Table 6. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

V

PP

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26

Figure 13. TFBGA47 - 8 x 6 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . 27

Table 17. TFBGA47 - 8 x 6 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . . . . . . 27

Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 28

Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 28

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/43

M28W320BT, M28W320BB

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21. Top Boot Block Addresses, M28W320BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22. Bottom Boot Block Addresses, M28W320BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 41

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 42

Table 29. Write State Machine Current/Next. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4/43

M28W320BT, M28W320BB

SUMMARY DESCRIPTION

The M28W320B is a 32 Mbit (2 Mbit x 16) non-vol-

atile Flash memory that can be erased electrically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 to 3.6V)

Figure 2. Logic Diagram

V

DD DDQ PP

supply. V

allows to drive the I/O pin down to

DDQ

21

16

1.65V. An optional 12V V power supply is pro-

PP

vided to speed up customer programming.

A0-A20

The device features an asymmetrical blocked ar-

chitecture. The M28W320B has an array of 71

blocks: 8 Parameter Blocks of 4 KWord and 63

Main Blocks of 32 KWord. M28W320BT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W320BB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

DQ0-DQ15

W

E

M28W320BT

M28W320BB

G

RP

WP

Parameter blocks 0 and 1 can be protected from

accidental programming or erasure. Each block

can be erased separately. Erase can be suspend-

ed in order to perform either read or program in

any other block and then resumed. Program can

be suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles.

V

SS

AI03822

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

Table 1. Signal Names

A0-A20

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

E

G

Output Enable

Write Enable

Reset

The memory is offered in TSOP48 (10 X 20mm),

and TFBGA47 (0.75mm pitch) packages and is

supplied with all the bits erased (set to ’1’).

W

RP

WP

Write Protect

Core Power Supply

V

DD

Power Supply for

Input/Output

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

V

PP

Ground

SS

5/43

M28W320BT, M28W320BB

Figure 3. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

V

DDQ

SS

DQ15

DQ7

DQ14

DQ6

A8

DQ13

DQ5

NC

A20

W

DQ12

DQ4

RP

12

13

37

36

V

M28W320BT

M28W320BB

DD

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

PP

WP

A19

A18

A17

A7

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI04383

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M28W320BT, M28W320BB

Figure 4. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

A18

A20

DQ2

DQ3

A19

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

A12

A9

A6

A3

DQ11

DQ12

DQ4

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI03823

7/43

M28W320BT, M28W320BB

Figure 5. Block Addresses

M28W320BT

M28W320BB

Top Boot Block Addresses

Bottom Boot Block Addresses

1FFFFF

4 KWords

1FF000

1FFFFF

32 KWords

1F8000

1F7FFF

Total of 8

4 KWord Blocks

1F0000

Total of 63

32 KWord Blocks

1F8FFF

4 KWords

1F8000

1F7FFF

32 KWords

1F0000

00FFFF

32 KWords

4 KWords

008000

007FFF

Total of 63

007000

32 KWord Blocks

Total of 8

00FFFF

4 KWord Blocks

32 KWords

008000

007FFF

000FFF

000000

32 KWords

4 KWords

000000

AI04382

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

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M28W320BT, M28W320BB

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

mal operation. Exiting reset mode the device

enters read array mode, but a negative transition

of Chip Enable or a change of the address is re-

quired to ensure valid data outputs.

V

Supply Voltage (2.7V to 3.6V). V

pro-

DD

vides the power supply to the internal core of the

memory device. It is the main power supply for all

operations (Read, Program and Erase).

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or data to be programmed during a Write Bus op-

eration.

V

Supply Voltage (1.65V to V ). V

DDQ DD DDQ

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

from V . V

can be tied to V

or can use a

DD

DDQ

DD

separate supply.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

V

Program Supply Voltage. V

is both a

PP

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage V

at V and Reset is at V the device is in active

and the

IL

IH

DD

mode. When Chip Enable is at V the memory is

Program Supply Voltage V

any order.

can be applied in

IH

PP

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

If V is kept in a low voltage range (0V to 3.6V)

PP

V

is seen as a control input. In this case a volt-

PP

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable, E, or Write En-

able, W, whichever occurs first.

age lower than V

against program or erase, while V

gives an absolute protection

PPLK

> V

en-

PP1

PP

ables these functions (see Table 11, DC Charac-

teristics for the relevant values). V is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

PP

If V is in the range 11.4V to 12.6V it acts as a

PP

Write Protect (WP). Write Protect is an input to

protect or unprotect the two lockable parameter

power supply pin. In this condition V

must be

PP

stable until the Program/Erase algorithm is com-

pleted (see Table 13 and 14).

blocks. When Write Protect is at V , the lockable

IL

blocks are protected and Program or Erase oper-

ations are not possible. When Write Protect is at

V

Ground. V is the reference for all voltage

SS

V , the lockable blocks are unprotected and can

IH

measurements.

be programmed or erased (refer to Table 4, Mem-

ory Blocks Protection Truth).

Note: Each device in a system should have

V

and V decoupled with a 0.1µF ca-

DD, DDQ PP

Reset (RP). The Reset input provides a hard-

pacitor close to the pin. See Figure 7, AC Mea-

surement Load Circuit. The PCB trace widths

ware reset of the memory. When Reset is at V ,

IL

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

should be sufficient to carry the required V

Program and Erase currents.

PP

mized. When Reset is at V , the device is in nor-

IH

9/43

M28W320BT, M28W320BB

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Bus Operations, for a summary.

See Figures 9 and 10, Write AC Waveforms, and

Tables 13 and 14, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

pedance when the Output Enable is at V .

IH

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at V and the device is in

IH

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

able must be at V in order to perform a read op-

IL

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 8, Read Mode AC Waveforms, and Table

12, Read AC Characteristics, for details of when

the output becomes valid.

V

during a program or erase operation, the de-

IH

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity, even if Chip Enable is low, V , and the supply

IL

Read mode is the default state of the device when

exiting Reset or after power-up.

current is reduced to I

puts will still output data.

. The data Inputs/Out-

DD1

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

Reset. During Reset mode, when Output Enable

is low, V , the memory is deselected and the out-

IL

puts are high impedance. The memory is in Reset

and Write Enable are at V with Output Enable at

mode when Reset is at V . The power consump-

IL

V . Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

IH

able inputs. If Reset is pulled to V during a Pro-

SS

gram or Erase, this operation is aborted and the

memory content is no longer valid.

Table 2. Bus Operations

V

Operation

Read

E

G

W

RP

WP

X

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

IH

Don't Care

V or V

DD

IL

IH

V

IH

Write

X

IL

PPH

V

IH

Output Disable

Standby

Reset

X

Don't Care

IH

V

IH

X

Hi-Z

IH

V

X

Hi-Z

IL

Note: X = V or V , V = 12V ± 5%.

PPH

IL

IH

10/43

M28W320BT, M28W320BB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time, to monitor

the progress of an operation, or the Program/

Erase states. See Appendix D, Table 29, Write

State Machine Current/Next, for a summary of the

Command Interface.

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device.

One Bus Write cycle is required to issue the Read

Query Command. Once the command is issued

subsequent Bus Read operations read from the

Common Flash Interface Memory Area. See Ap-

pendix B, Common Flash Interface, Tables 23, 24,

25, 26, 27 and 28 for details on the information

contained in the Common Flash Interface memory

area.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

DD

LKO

Block Erase Command

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 3, Commands,

in conjunction with the text descriptions below.

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Read Memory Array command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

Read Status Register Command

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register, at any address, until another

command is issued. See Table 7, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Erase aborts if Reset turns to V . As data integrity

IL

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will only ac-

cept the Read Status Register command and the

Program/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 6, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 19, Erase Flowchart and

Pseudo Code, for the flowchart for using the Erase

command.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes.

Program Command

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer or the Device Code depending

on the levels of A0. The Manufacturer Code is out-

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program command.

■ The first bus cycle sets up the Program

put when the address line A0 is at V , the Device

IL

command.

Code is output when A0 is at V . Addresses A1-

IH

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

A7 must be kept to V , other addresses are ig-

IL

nored. The codes are output on DQ0-DQ7 with

DQ8-DQ15 at 00h. (see Table 4)

11/43

M28W320BT, M28W320BB

commands will be ignored. Typical Program times

are given in Table 6, Program, Erase Times and

Program/Erase Endurance Cycles.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program command will also be accepted. Only

the blocks not being erased may be read or pro-

grammed correctly.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 16, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to V . Program/Erase is aborted if

IH

ed when V is not at V

. The command can be

but the result is not

PPH

PP

PPH

Reset turns to V .

IL

executed if V is below V

PP

guaranteed.

See Appendix C, Figure 18, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

20, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program command.

■ The second bus cycle latches the Address and

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendix C, Figure 18, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 20, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Resume com-

mand.

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V . As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 17, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Block Protection

Two parameter/lockable blocks (blocks #0 and #1)

can be protected against Program or Erase oper-

ations. Unprotected blocks can be programmed or

erased.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

To protect the two lockable blocks set Write Pro-

tect to V . When V is below V all blocks are

IL

PP

PPLK

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

protected. Any attempt to Program or Erase pro-

tected blocks will abort, the data in the block will

not be changed and the Status Register outputs

the error.

Table 5, Memory Blocks Protection Truth Table,

defines the protection methods.

12/43

M28W320BT, M28W320BB

Table 3. Commands

Commands

Bus Write Operations

No. of

Cycles

1st Cycle

2nd Cycle

Addr

3nd Cycle

Addr

Bus

Op.

Bus

Op.

Bus

Op.

Addr Data

Data

Read

Addr

Read Memory Array

Read Status Register

1+

Write

X

FFh

70h

Data

Read

Status

Register

X

Signature

Read Electronic Signature

Read CFI Query

Erase

1+

2

Write

X

90h

98h

20h

Signature

Query

D0h

Read

(2)

Addr

CFI Addr

Read

Write

Block

Addr

40h or

10h

Data

Input

Program

2

3

Write

X

Write

Addr

Data

Input

Data

Input

(3)

30h

Addr 1

Write

Addr 2

Double Word Program

Clear Status Register

1

Write

X

50h

B0h

D0h

Program/Erase Suspend

Program/Erase Resume

Note: 1. X = Don't Care.

2. A0=V outputs Manufacturer code, A0=V outputs Device code. Address A7-A1 must be V .

IL

IH

IL

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 4. Read Electronic Signature

Code

Device

E

G

W

A0

A1-A7

A8-A20

DQ0-DQ7

DQ8-DQ15

Manufacture.

Code

V

IH

V

Don't Care

20h

00h

IL

V

M28W320CT

M28W320CB

Don't Care

BCh

BDh

88h

IL

IH

IL

Device Code

V

IH

V

IH

IL

Note:

RP = V .

IH

Table 5. Memory Blocks Protection Truth Table

Lockable Blocks

(blocks #0 and #1)

(1)

Other Blocks

V

RP

WP

PP

V

X

V

X

Protected

IL

V

IH

IL

(2)

V

IH

V

Unprotected

V

or V

IL

DD

PPH

V

IH

V

IH

Unprotected

or V

Note: 1. X = Don't Care

2. V must also be greater than the Program Voltage Lock Out V

.

PPLK

PP

13/43

M28W320BT, M28W320BB

Table 6. Program, Erase Times and Program/Erase Endurance Cycles

M28W320B

Parameter

Unit

Test Conditions

Min

Max

200

5

Typ

10

V

= V

DD

Word Program

µs

PP

V

= 12V ±5%

= V

Double Word Program

Main Block Program

10

µs

PP

0.16

0.32

0.02

0.04

1

s

PP

V

5

s

PP

DD

V

= 12V ±5%

= V

4

s

PP

Parameter Block Program

Main Block Erase

V

4

s

PP

DD

= 12V ±5%

= V

10

s

PP

V

1

s

PP

DD

= 12V ±5%

= V

0.8

s

PP

Parameter Block Erase

V

PP

DD

Program/Erase Cycles (per Block)

100,000

cycles

14/43

M28W320BT, M28W320BB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to the Read Status Register Command section.

To output the contents, the Status Register is

latched on the falling edge of the Chip Enable or

Output Enable signals, and can be read until Chip

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Enable or Output Enable returns to V . Either

IH

Chip Enable or Output Enable must be toggled to

update the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

The bits in the Status Register are summarized in

Table 7, Status Register Bits. Refer to Table 7 in

conjunction with the following text descriptions.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

V

Status (Bit 3). The V

Status bit can be

PP

used to identify an invalid voltage on the V pin

PP

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

PP

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

cur if V becomes invalid during an operation.

PP

When the V Status bit is Low (set to ‘0’), the volt-

PP

age on the V pin was sampled at a valid voltage;

PP

when the V Status bit is High (set to ‘1’), the V

PP

pin has a voltage that is below the V

Lockout

PP

Voltage, V

, the memory is protected and Pro-

PPLK

gram and Erase operations cannot be performed.

Once set High, the V Status bit can only be reset

PP

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit (set to ‘1’) indicates that an Erase

operation has been suspended or is going to be

suspended.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit (set to ‘1’) indicates that a Pro-

gram operation has been suspended or is going to

be suspended.

The Program Suspend Status should only be con-

sidered valid when the Program/Erase Controller

Status bit is High (Program/Erase Controller inac-

tive). Bit 2 is set within 5µs of the Program/Erase

Suspend command being issued therefore the

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

memory may still complete the operation rather

than

entering

the

Suspend

mode.

15/43

M28W320BT, M28W320BB

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a protected block.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a protected block.

Table 7. Status Register Bits

Bit

Name

Logic Level

Definition

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

PP

Status

V

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level '1' is High, '0' is Low.

16/43

M28W320BT, M28W320BB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–55

–0.6

Max

85

(1)

T

°C

V

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

T

125

155

BIAS

T

STG

V

+0.6

IO

DDQ

V

, V

DDQ

4.1

13

V

DD

V

Program Voltage

V

PP

Note: 1. Depends on range.

17/43

M28W320BT, M28W320BB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 9,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 9. Operating and AC Measurement Conditions

M28W320BT, M28W320BB

70

85

90

100

Parameter

Units

Min

Max

Min

Max

Min

Max

Min

Max

V

Supply Voltage

2.7

3.6

2.7

3.6

2.7

3.6

2.7

3.6

V

DD

2.7

3.3

85

2.7

3.3

85

2.7

3.3

85

1.65

– 40

3.3

85

Supply Voltage (V

≤ V

)

DDQ

DD

Ambient Operating Temperature

– 40

°C

pF

ns

V

Load Capacitance (C )

50

L

Input Rise and Fall Times

Input Pulse Voltages

5

0 to V

DDQ

Input and Output Timing Ref.

Voltages

V

/2

V

DDQ

/2

V

DDQ

/2

V

DDQ

/2

V

DDQ

Figure 6. AC Measurement I/O Waveform

Figure 7. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DDQ

V

0V

DD

25kΩ

AI00610

DEVICE

UNDER

TEST

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI00609C

L

Table 10. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

IN

V

IN

= 0V

C

V

OUT

12

pF

OUT

Note: Sampled only, not 100% tested.

18/43

M28W320BT, M28W320BB

Table 11. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V≤ V ≤ V

LI

IN

DDQ

I

0V≤ V

≤V

±10

20

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

10

15

mA

DD

SS

IH

E = V

± 0.2V,

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

50

20

50

400

µA

DD1

RP = V

± 0.2V

DDQ

Supply Current

(Reset)

I

RP = V ± 0.2V

15

10

5

DD2

SS

Program in progress

mA

µA

V

PP

= 12V ± 5%

I

Supply Current (Program)

Supply Current (Erase)

DD3

Program in progress

= V

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

DD4

Erase in progress

= V

5

V

PP

DD

E = V

± 0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

DD5

Erase suspended

Program Current

(Read or Stand-by)

I

V

> V

µA

PP

DD

Program Current

(Read or Stand-by)

I

V

≤ V

5

µA

PP1

DD

I

RP = V ± 0.2V

Program Current (Reset)

PP2

SS

Program in progress

10

mA

V

PP

= 12V ± 5%

I

Program Current (Program)

PP3

Program in progress

= V

5

10

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

V

PP

DD

–0.5

0.4

0.8

V

Input Low Voltage

Input High Voltage

IL

V

≥ 2.7V

DDQ

V

–0.4

V

+0.4

DDQ

V

IH

V

0.7 V

+0.4

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

Output Low Voltage

Output High Voltage

0.1

V

OL

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

–0.1

OH

DDQ

V

DDQ

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

1.65

3.6

PP1

Program Voltage

(Program or Erase

operations)

V

11.4

12.6

V

PPH

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

Supply Voltage (Program

DD

V

LKO

and Erase lock-out)

19/43

M28W320BT, M28W320BB

Figure 8. Read AC Waveforms

tAVAV

VALID

A0-A20

E

tAVQV

tAXQX

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQV

tGHQX

tGHQZ

tGLQX

VALID

DQ0-DQ15

OUTPUTS

ENABLED

ADDR. VALID

CHIP ENABLE

DATA VALID

STANDBY

AI03825b

Table 12. Read AC Characteristics

M28W320B

Symbol

Alt

Parameter

Unit

70

85

90

100

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

70

0

ns

AVAV

RC

t

ACC

Max

Min

Max

Min

Max

AVQV

(1)

t

Address Transition to Output Transition

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

0

t

OH

AXQX

EHQX

EHQZ

(1)

(2)

(1)

(2)

(1)

t

0

20

70

0

ns

t

20

85

0

25

90

0

30

100

0

HZ

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

LZ

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

0

t

OH

GHQX

t

20

0

20

0

25

30

0

30

35

0

t

DF

OE

GHQZ

t

Max

Min

t

GLQV

GLQX

t

OLZ

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

20/43

M28W320BT, M28W320BB

Figure 9. Write AC Waveforms, Write Enable Controlled

21/43

M28W320BT, M28W320BB

Table 13. Write AC Characteristics, Write Enable Controlled

M28W320B

Symbol

Alt

Parameter

Unit

70

45

0

85

45

0

90

50

0

100

50

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

50

DVWH

t

0

ELWL

t

70

85

90

100

ELQV

(1,2)

Output Valid to V Low

0

t

PP

QVVPL

t

Output Valid to Write Protect Low

QVWPL

(1)

t

V

High to Write Enable High

Min

200

0

200

0

200

0

200

0

ns

t

VPS

PP

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

WHDX

WHEH

AH

DH

CH

t

0

t

25

20

25

45

25

20

25

45

30

50

30

50

WHEL

WHGL

t

WHWL

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

22/43

M28W320BT, M28W320BB

Figure 10. Write AC Waveforms, Chip Enable Controlled

23/43

M28W320BT, M28W320BB

Table 14. Write AC Characteristics, Chip Enable Controlled

M28W320B

Symbol

Alt

Parameter

Unit

70

45

0

85

45

0

90

50

0

100

50

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

DH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

EHAX

t

0

EHDX

t

CPH

25

0

25

0

30

0

30

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

45

70

45

85

50

90

50

100

ELEH

t

ELQV

(1,2)

Output Valid to V Low

0

t

PP

QVVPL

t

Data Valid to Write Protect Low

QVWPL

(1)

t

V

High to Chip Enable High

PP

200

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

Min

0

ns

WLEL

t

45

50

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

24/43

M28W320BT, M28W320BB

Figure 11. Power-Up and Reset AC Waveforms

W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI03453b

Table 15. Power-Up and Reset AC Characteristics

M28W320B

Symbol

Parameter

Test Condition

Unit

70

85

90

100

During

Program

and Erase

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip

Enable Low, Output Enable Low

t

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

25/43

M28W320BT, M28W320BB

PACKAGE MECHANICAL

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

mm

inches

Symbol

Typ

Min

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Min

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.4764

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.4685

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0279

5°

α

N

48

CP

0.10

0.0039

26/43

M28W320BT, M28W320BB

Figure 13. TFBGA47 - 8 x 6 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

SE

E

E1

e

BALL "A1"

ddd

e

b

A2

A

A1

BGA-Z16

Drawing is not to scale.

Table 17. TFBGA47 - 8 x 6 ball array, 0.75 mm pitch, Package Mechanical Data

mm

Min

inch

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.200

0.0079

1.000

0.0394

0.400

6.390

5.250

0.350

6.290

–

0.450

0.0157

0.2516

0.2067

0.0138

0.2476

–

0.0177

D

6.490

0.2555

D1

ddd

e

–

0.100

0.0039

0.750

10.500

3.750

0.570

3.375

0.375

–

0.0295

0.4134

0.1476

0.0224

0.1329

0.0148

–

E

10.400

10.600

0.4094

0.4173

E1

FD

FE

SD

SE

–

27/43

M28W320BT, M28W320BB

Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI03295

Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI03296

28/43

M28W320BT, M28W320BB

PART NUMBERING

Table 18. Ordering Information Scheme

Example:

M28W320BT

90

N

6

T

Device Type

M28

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.65V or 2.7V

DD

DDQ

Device Function

320B = 32 Mbit (x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

85 = 85 ns

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA47: 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Table 19. Daisy Chain Ordering Scheme

Example:

M28W320B

-ZB T

Device Type

M28W320B

Daisy Chain

-ZB = TFBGA47: 0.75 mm pitch

Option

T = Tape & Reel Packing

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc...) or for further information on any aspect of this device, please contact

the ST Sales Office nearest to you.

29/43

M28W320BT, M28W320BB

REVISION HISTORY

Table 20. Document Revision History

Date

Version

-01

Revision Details

January 2001

06-Mar-2001

First Issue

-02

Document type : from Preliminary Data to Data Sheet

70ns Speed Class added

10-May-2001

29-May-2001

-03

-04

Completely rewritten and restructured, 85ns speed class added.

Corrections to CFI data and Block Address Table.

V

DDQ

Maximum changed to 3.3V

31-Oct-2001

-05

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 3)

description clarified (Table 13)

t

WHEL

30/43

M28W320BT, M28W320BB

APPENDIX A. BLOCK ADDRESS TABLES

Table 21. Top Boot Block Addresses,

M28W320BT

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

32

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F00000-F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

Size

(KWord)

#

Address Range

0

4

1FF000-1FFFFF

1FE000-1FEFFF

1FD000-1FDFFF

1FC000-1FCFFF

1FB000-1FBFFF

1FA000-1FAFFF

1F9000-1F9FFF

1F8000-1F8FFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

31/43

M28W320BT, M28W320BB

Table 22. Bottom Boot Block Addresses,

M28W320BB

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

4

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

007000-007FFF

006000-006FFF

005000-005FFF

004000-004FFF

003000-003FFF

002000-002FFF

001000-001FFF

000000-000FFF

Size

#

Address Range

(KWord)

32

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

8

7

6

4

5

4

3

4

2

4

1

4

0

4

32/43

M28W320BT, M28W320BB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 23, 24,

25, 26, 27 and 28 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 28, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 23. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 24. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

Reserved

ST

88BCh

88BDh

Top

Bottom

01h

02h-0Fh

10h

reserved

0051h

0052h

0059h

0003h

0000h

Query Unique ASCII String "QRY"

“Q”

“R”

“Y”

11h

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID

code defining a specific algorithm

Intel

Compatible

14h

offset = P =

0035h

15h

Address for Primary Algorithm extended Query table

P=35h

NA

16h

17h

18h

0000h

Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported (note: 0000h means none exists)

value = A =

0000h

19h

1Ah

Address for Alternate Algorithm extended Query table

note: 0000h means none exists

NA

0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

33/43

M28W320BT, M28W320BB

Table 25. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0027h

2.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

3.6V

11.4V

12.6V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1 s

Typical timeout per single word program = 2 µs

n

Typical timeout for Double Word Program = 2 µs

n

Typical timeout per individual block erase = 2 ms

n

NA

Typical timeout for full chip erase = 2 ms

n

512µs

8 s

Maximum timeout for word program = 2 times typical

n

Maximum timeout for Double Word Program = 2 times typical

n

Maximum timeout per individual block erase = 2 times typical

n

NA

Maximum timeout for chip erase = 2 times typical

34/43

M28W320BT, M28W320BB

Table 26. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0016h

4MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async

Flash Device Interface Code description

2Ah

2Bh

0002h

0000h

n

4

2

Maximum number of bytes in multi-byte program or page = 2

2Ch

0002h

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Dh

2Eh

003Eh

0000h

Region 1 Information

Number of identical-size erase block = 003Eh+1

63

64KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8KByte

63

31h

32h

003Eh

0000h

Region 2 Information

Number of identical-size erase block = 003Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64KByte

35/43

M28W320BT, M28W320BB

Table 27. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0006h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

Chip Erase supported

Erase Suspend supported

Program Suspend

Lock/Unlock supported

Queued Erase supported

(1 = Yes, 0 = No)

No

Yes

No

bit 31 to 5 Reserved; undefined bits are ‘0’

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

NA

(P+A)h = 3Fh

(P+B)h = 40h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+C)h = 41h

(P+D)h = 42h

(P+E)h

0030h

00C0h

0000h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

12V

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Reserved

Note: 1. See Table 24, offset 15h for P pointer definition.

Table 28. Security Code Area

Offset

81h

Data

XXXX

Description

82h

64 bits unique device number.

83h

84h

36/43

M28W320BT, M28W320BB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 16. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

Program

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

37/43

M28W320BT, M28W320BB

Figure 17. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03539b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

38/43

M28W320BT, M28W320BB

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI03540b

39/43

M28W320BT, M28W320BB

Figure 19. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

40/43

M28W320BT, M28W320BB

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

Write 70h

Read Status

Register

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

Write D0h

Write FFh

Read Data

}

Erase Continues

}

AI03549b

41/43

M28W320BT, M28W320BB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 29. Write State Machine Current/Next

Command Input (and Next State)

Data

When

Read

Program/ Program/

Erase Erase

Suspend Resume

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(10/40h)

Erase

Confirm

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read

Elect.Sg.

(90h)

(B0h)

(D0h)

Read

Array

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

“1”

Array

Read Array

Read

Status

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

Status

Read Array

Read

Elect.Sg.

Electronic

Signature

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

Program

Setup

Status

Program (Command input = Data to be Programmed)

Program

Suspend

to Read

Status

Program

(continue)

“0”

“1”

Status

Program (continue)

Program

Suspend

to Read

Status

Program

Suspend

to Read

Array

Program

Program Program Program

Program Suspend to

Read Array

Program Suspend Program Suspend Suspend Suspend

(continue) to Read (continue) to Read

Status

Array

to Read

Array

to Read

Elect.Sg.

Array

Status

Program

Suspend

to Read

Array

Program

Suspend

to Read

Array

Program

Program Program Program

Program Suspend to

Read Array

Program Suspend Program Suspend Suspend Suspend

(continue) to Read (continue) to Read

to Read

Array

to Read

Elect.Sg.

Array

Status

Program

Suspend

to Read

Elect.Sg.

Program

Program Program Program

Electronic Suspend

Signature

Program Suspend to

Read Array

Program Suspend Program Suspend Suspend Suspend

(continue) to Read (continue) to Read

to Read

Array

to Read

Array

to Read

Elect.Sg.

Array

Status

Program

(complete)

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

“1”

Status

Read Array

Erase

Command

Error

Erase

Setup

Erase

(continue)

Erase

(continue)

Status

Erase Command Error

Erase

Cmd.

Error

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

“0”

“1”

Status

Read Array

Erase

Suspend

to Read

Status

Erase

(continue)

Erase (continue)

Erase

Erase (continue)

Erase

Suspend

to Read

Status

Erase

Suspend Program

to Read

Array

Erase

Suspend

Erase

Suspend

Erase

Suspend Suspend Suspend

“1”

Status

Array

Setup

to Read (continue) to Read (continue) to Read

Array

to Read

Array

to Read

Elect.Sg.

Array

Status

Erase

Suspend

to Read

Array

Erase

Suspend Program

to Read

Array

Erase

Suspend

Erase

Suspend

Erase

Suspend Suspend Suspend

Setup

to Read (continue) to Read (continue) to Read

Array

to Read

Array

to Read

Elect.Sg.

Array

Status

Erase

Suspend

to Read

Elect.Sg.

Electronic Suspend Program

Suspend

Erase

Suspend

Erase

Suspend Suspend Suspend

“1”

Signature

to Read

Array

Setup

to Read (continue) to Read (continue) to Read

Array

to Read

Array

to Read

Elect.Sg.

Array

Status

Erase

(complete)

Read

Array

Program

Setup

Erase

Setup

Read

Status

Read

Array

Read

Elect.Sg.

Status

Read Array

Note: Elect.Sg. = Electronic Signature.

42/43

M28W320BT, M28W320BB

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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43/43

型号	制造商	描述	价格	文档
M28W320BB90ZB1T	STMICROELECTRONICS	32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory	获取价格
M28W320BB90ZB6	NUMONYX	2MX16 FLASH 3V PROM, 90ns, PBGA47, 6.39 X 10.50 MM, 0.75 MM PITCH, TFBGA-47	获取价格
M28W320BB90ZB6T	STMICROELECTRONICS	32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory	获取价格
M28W320BT	STMICROELECTRONICS	32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory	获取价格
M28W320BT100N1	NUMONYX	2MX16 FLASH 3V PROM, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48	获取价格
M28W320BT100N1T	STMICROELECTRONICS	32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory	获取价格
M28W320BT100N1T	NUMONYX	Flash, 2MX16, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48	获取价格
M28W320BT100N6	NUMONYX	Flash, 2MX16, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48	获取价格
M28W320BT100N6T	STMICROELECTRONICS	32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory	获取价格
M28W320BT100N6T	NUMONYX	Flash, 2MX16, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48	获取价格

M28W320BB90ZB1

M28W320BB90ZB1 概述

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