M29DW640F90ZE6_技术文档

M29DW640F

64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block)

3V Supply Flash Memory

Feature summary

■ Supply voltage

– V_CC= 2.7V to 3.6V for Program, Erase and

Read

– V_PP=12V for Fast Program (optional)

■ Asynchronous Page Read mode

– Page Width 8 Words

– Page Access 25, 30ns

– Random Access 60, 70ns

TSOP48 (N)

12 x 20mm

■ Programming time

– 10µs per Byte/Word typical

– 4 Words / 8 Bytes at-a-time Program

FBGA

■ Memory blocks

– Quadruple Bank Memory Array:

8Mbit+24Mbit+24Mbit+8Mbit

TFBGA48 (ZE)

6 x 8 mm

– Parameter Blocks (at both Top and Bottom)

■ Dual operations

– While Program or Erase in a group of

banks (from 1 to 3), Read in any of the

other banks

■ Low power consumption

– Standby and Automatic Standby

■ 100,000 Program/Erase cycles per block

■ Program/Erase Suspend and Resume

■ Electronic Signature

– Read from any Block during Program

Suspend

– Manufacturer Code: 0020h

– Device Code: 227Eh + 2202h + 2201

■ ECOPACK^®packages available

– Read and Program another Block during

Erase Suspend

■ Unlock Bypass Program command

– Faster Production/Batch Programming

■ V_PP/WP pin for Fast Program and Write Protect

■ Temporary Block Unprotection mode

■ Common Flash Interface

– 64 bit Security Code

■ Extended Memory Block

– Extra block used as security block or to

store additional information

December 2007

Rev 4

1/74

www.numonyx.com

1

Contents

M29DW640F

Contents

1

2

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 13

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V

/Write Protect (V WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PP/

PP

Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.12

2.13

V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CC

SS

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1

3.2

3.3

3.4

3.5

3.6

Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6.1

3.6.2

Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4

Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.1

4.1.2

4.1.3

Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/74

M29DW640F

Contents

4.1.4

4.1.5

4.1.6

4.1.7

4.1.8

4.1.9

Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

4.2.8

Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3

Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1

4.3.2

4.3.3

Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 29

5

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1

Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.1

5.1.2

5.1.3

5.1.4

Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6

Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 36

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7

8

9

10

3/74

Contents

M29DW640F

Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

C.1

C.2

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

D.1

D.2

Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4/74

M29DW640F

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Bus operations, BYTE = V_{IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19}

Bus operations, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Commands, 16-bit mode, BYTE = V_{IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29}

Commands, 8-bit mode, BYTE = V_{IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30}

Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 31

Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Dual operations allowed in same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Toggle and Alternative Toggle Bits AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 52

TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 53

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Extended Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Programmer technique bus operations, BYTE = V_IHor V_{IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68}

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

5/74

List of figures

M29DW640F

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10. Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 11. Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 13. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 14. Toggle and Alternative Toggle Bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . 49

Figure 15. Toggle and Alternative Toggle Bits mechanism, Output Enable controlled . . . . . . . . . . . . 49

Figure 16. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 52

Figure 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 53

Figure 20. Programmer Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 21. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 22. In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 23. In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6/74

M29DW640F

Summary description

1

Summary description

The M29DW640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,

erased and reprogrammed. These operations can be performed using a single low voltage

(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.

The device features an asymmetrical block architecture, with 16 parameter and 126 main

blocks, divided into four Banks, A, B, C and D, providing multiple Bank operations. While

programming or erasing is underway in one group of banks (from 1 to 3), reading can be

conducted in any of the other banks. The bank architecture is summarized in Table 2. Eight

of the Parameter Blocks are at the top of the memory address space, and eight are at the

bottom.

The M29DW640F has one extra 256 Byte block (Extended Block) that can be accessed

using a dedicated command. The Extended Block can be protected and so is useful for

storing security information. However the protection is irreversible, once protected the

protection cannot be undone.

Each block can be erased independently, so it is possible to preserve valid data while old

data is erased. The blocks can be protected to prevent accidental Program or Erase

commands from modifying the memory. Program and Erase commands are written to the

Command Interface of the memory. An on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by taking care of all of the special

operations that are required to update the memory contents. The end of a program or erase

operation can be detected and any error conditions identified. The command set required to

control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the

memory. They allow simple connection to most microprocessors, often without additional

logic.

The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch)

packages.

In order to meet environmental requirements, Numonyx also offers the in ECOPACK^®

packages. ECOPACK packages are Lead-free. The category of second Level Interconnect

is marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97. The maximum ratings related to soldering conditions are also marked on the inner

box label.

The memory is supplied with all the bits erased (set to ’1’).

7/74

Summary description

Figure 1.

M29DW640F

Logic diagram

V

/WP

CC PP

22

15

A0-A21

DQ0-DQ14

DQ15A–1

W

E

M29DW640F

G

RB

RP

BYTE

V

SS

AI11247

Table 1.

Signal names

Address Inputs

A0-A21

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

DQ15A–1

Data Input/Output or Address Input

Chip Enable

E

G

Output Enable

W

Write Enable

RP

RB

BYTE

V_CC

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply voltage

V_PP/WP

V_PP/Write Protect

V_SS

NC

Ground

Not Connected Internally

8/74

M29DW640F

Figure 2.

Summary description

TSOP connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

A20

W

DQ12

DQ4

RP

12

13

37

36

V

CC

M29DW640F

A21

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

/WP

RB

A18

A17

A7

PP

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI11248

9/74

Summary description

Figure 3.

M29DW640F

TFBGA48 connections (top view through package)

1

2

3

4

5

6

RB

W

RP

A21

A

B

A3

A4

A7

A17

A6

A9

A8

A13

A12

V

/WP

PP

A2

A1

A0

E

A18

A10

A14

C

D

A5

A20

A19

A11

A15

DQ2

DQ5

DQ0

DQ8

DQ9

DQ1

DQ7

DQ14

DQ13

DQ6

A16

E

F

BYTE

DQ10

DQ11

DQ3

DQ12

DQ15

A–1

G

V

G

H

CC

V

DQ4

V

SS

AI11

1. Balls are shorted together via the substrate but not connected to the die.

Table 2.

Bank

Bank architecture

Parameter Blocks

Main Blocks

Bank

Size

No. of Blocks

Block Size

No. of Blocks

Block Size

A

B

C

D

8 Mbit

24 Mbit

8 Mbit

8

—

8

8KByte/ 4 KWord

15

48

15

64KByte/ 32 KWord

—

8KByte/ 4 KWord

10/74

M29DW640F

Figure 4.

Summary description

Block addresses (x8)

(x8)

Address lines A21-A0, DQ15A-1

000000h

001FFFh

400000h

40FFFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

Total of 8

Parameter

Blocks

Total of 48

Main Blocks

Bank C

00E000h

6F0000h

8 KByte or

4 KWord

64 KByte or

32 KWord

00FFFFh

010000h

6FFFFFh

700000h

Bank A

64 KByte or

32 KWord

64 KByte or

32 KWord

01FFFFh

0F0000h

70FFFFh

7E0000h

Total of 15

Main Blocks

Total of 15

Main Blocks

64 KByte or

32 KWord

64 KByte or

32 KWord

0FFFFFh

100000h

7EFFFFh

7F0000h

Bank D

64 KByte or

32 KWord

8 KByte or

4 KWord

10FFFFh

7F1FFFh

Total of 48

Main Blocks

Total of 8

Parameter

Blocks

Bank B

3F0000h

3FFFFFh

7FE000h

7FFFFFh

64 KByte or

32 KWord

8 KByte or

4 KWord

AI06880

1. Also see Appendix A, Table 24 for a full listing of the Block addresses.

11/74

Summary description

M29DW640F

Figure 5.

Block addresses (x16)

(x16)

Address lines A21-A0

000000h

000FFFh

200000h

207FFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

Total of 8

Parameter

Total of 48

Main Blocks

Bank C

Blocks

007000h

378000h

8 KByte or

4 KWord

64 KByte or

32 KWord

007FFFh

008000h

37FFFFh

380000h

Bank A

64 KByte or

32 KWord

64 KByte or

32 KWord

00FFFFh

078000h

387FFFh

3F0000h

Total of 15

Main Blocks

Total of 15

Main Blocks

64 KByte or

32 KWord

64 KByte or

32 KWord

07FFFFh

080000h

3F7FFFh

3F8000h

Bank D

64 KByte or

32 KWord

8 KByte or

4 KWord

087FFFh

3F8FFFh

Total of 48

Main Blocks

Total of 8

Parameter

Blocks

Bank B

1F8000h

1FFFFFh

3FF000h

3FFFFFh

64 KByte or

32 KWord

8 KByte or

4 KWord

AI05555

1. Also see Appendix A, Table 24 for a full listing of the Block addresses.

12/74

M29DW640F

Signal descriptions

2

Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

2.2

2.3

Address Inputs (A0-A21)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.

During Bus Write operations they represent the commands sent to the Command Interface

of the internal state machine.

Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

when BYTE is High, V_IH. When BYTE is Low, V_IL, these pins are not used and are high

impedance. During Bus Write operations the Command Register does not use these bits.

When reading the Status Register these bits should be ignored.

2.4

Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, V_IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).

When BYTE is Low, V_IL, this pin behaves as an address pin; DQ15A–1 Low will select the

LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text

consider references to the Data Input/Output to include this pin when BYTE is High and

references to the Address Inputs to include this pin when BYTE is Low except when stated

explicitly otherwise.

2.5

2.6

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, V_IH, all other pins are ignored.

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

13/74

Signal descriptions

M29DW640F

2.7

2.8

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

V /Write Protect (V /WP)

PP

The V_PP/Write Protect pin provides two functions. The V_PPfunction allows the memory to

use an external high voltage power supply to reduce the time required for Program

operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word

(2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write

Protect function provides a hardware method of protecting the four outermost boot blocks

(two at the top, and two at the bottom of the address space).

When V_PP/Write Protect is Low, V_IL, the memory protects the four outermost boot blocks;

Program and Erase operations in these blocks are ignored while V_PP/Write Protect is Low,

even when RP is at V_ID.

When V_PP/Write Protect is High, V_IH, the memory reverts to the previous protection status

of the four outermost boot blocks (two at the top, and two at the bottom of the address

space). Program and Erase operations can now modify the data in these blocks unless the

blocks are protected using Block Protection.

Applying V_PPHto the V_PP/WP pin will temporarily unprotect any block previously protected

(including the four outermost parameter blocks) using a High Voltage Block Protection

technique (In-System or Programmer technique). See Table 3: Hardware protection for

details.

When V_PP/Write Protect is raised to V_PPthe memory automatically enters the Unlock

Bypass mode. When V_PP/Write Protect returns to V_IHor V_ILnormal operation resumes.

During Unlock Bypass Program operations the memory draws I_PPfrom the pin to supply the

programming circuits. See the description of the Unlock Bypass command in the Command

Interface section. The transitions from V_IHto V_PPand from V_PPto V_IHmust be slower than

t_VHVPP, see Figure 17.

Never raise V_PP/Write Protect to V_PPfrom any mode except Read mode, otherwise the

memory may be left in an indeterminate state.

The V_PP/Write Protect pin must not be left floating or unconnected or the device may

become unreliable. A 0.1µF capacitor should be connected between the V_PP/Write Protect

pin and the V_SSGround pin to decouple the current surges from the power supply. The PCB

track widths must be sufficient to carry the currents required during Unlock Bypass Program,

I_PP.

Table 3.

V_PP/WP

Hardware protection

RP

Function

4 outermost parameter blocks protected from Program/Erase

operations

V_IH

V_IL

V_ID

All blocks temporarily unprotected except the 4 outermost blocks

All blocks temporarily unprotected

V_IHor V_ID

V_PPH

V_IHor V_ID

All blocks temporarily unprotected

14/74

M29DW640F

Signal descriptions

2.9

Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

Note that if V_PP/WP is at V_IL, then the four outermost boot blocks will remain protected even

if RP is at V_ID.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V_IL, for at

least t_PLPX. After Reset/Block Temporary Unprotect goes High, V_IH, the memory will be

ready for Bus Read and Bus Write operations after t_PHELor t_RHEL, whichever occurs last.

See the Ready/Busy Output section, Table 20 and Figure 16: Reset/Block Temporary

Unprotect AC waveforms.

Holding RP at V_IDwill temporarily unprotect the protected Blocks in the memory. Program

and Erase operations on all blocks will be possible. The transition from V_IHto V_IDmust be

slower than t_PHPHH

.

2.10

Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is

performing a Program or Erase operation. During Program or Erase operations Ready/Busy

is Low, V_OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and

Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy

becomes high-impedance. See Table 20 and Figure 16: Reset/Block Temporary Unprotect

AC waveforms.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.11

Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus

modes of the memory. When Byte/Word Organization Select is Low, V_IL, the memory is in

x8 mode, when it is High, V_IH, the memory is in x16 mode.

2.12

V

Supply Voltage

CC

V_CCprovides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V_CCSupply Voltage is less than the Lockout

voltage, V_LKO. This prevents Bus Write operations from accidentally damaging the data

during power up, power down and power surges. If the Program/Erase Controller is

programming or erasing during this time then the operation aborts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the V_CCSupply Voltage pin and the V_SS

Ground pin to decouple the current surges from the power supply. The PCB track widths

must be sufficient to carry the currents required during Program and Erase operations, I_CC3

.

15/74

Signal descriptions

M29DW640F

2.13

V

Ground

SS

V_SSis the reference for all voltage measurements. The device features two V_SSpins both of

which must be connected to the system ground.

16/74

M29DW640F

Bus operations

3

Bus operations

There are five standard bus operations that control the device. These are Bus Read

(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.

Using the multiple bank architecture of the M29DW640F, while programming or erasing is

underway in one group of banks (from 1 to 3), reading can be conducted in any of the other

banks. Write operations are only allowed in one bank at a time.

See Table 4 and Table 5, Bus operations, for a summary. Typically glitches of less than 5ns

on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect

bus operations.

3.1

Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface. To speed up the read operation the memory array can be read in Page mode

where data is internally read and stored in a page buffer. The Page has a size of 8 Words

and is addressed by the address inputs A0-A2.

A valid Bus Read operation involves setting the desired address on the Address Inputs,

applying a Low signal, V_IL, to Chip Enable and Output Enable and keeping Write Enable

High, V_IH. The Data Inputs/Outputs will output the value, see Figure 10: Random Read AC

waveforms, Figure 11: Page Read AC waveforms, and Table 16: Read AC characteristics,

for details of when the output becomes valid.

3.2

Bus Write

Bus Write operations write to the Command Interface. A valid Bus Write operation begins by

setting the desired address on the Address Inputs. The Address Inputs are latched by the

Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V_IH,

during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC waveforms,

and Table 17 and Table 18, Write AC characteristics, for details of the timing requirements.

3.3

3.4

Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V_IH.

Standby

When Chip Enable is High, V_IH, the memory enters Standby mode and the Data

Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to

the Standby Supply Current, I_CC2, Chip Enable should be held within V_CC0.2V. For the

Standby current level see Table 15: DC characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply Current, I_CC3, for Program or Erase operations until the operation completes.

17/74

Bus operations

M29DW640F

3.5

Automatic Standby

If CMOS levels (V_CC0.2V) are used to drive the bus and the bus is inactive for 300ns or

more the memory enters Automatic Standby where the internal Supply Current is reduced to

the Standby Supply Current, I_CC2. The Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

3.6

Special bus operations

Additional bus operations can be performed to read the Electronic Signature and also to

apply and remove Block Protection. These bus operations are intended for use by

programming equipment and are not usually used in applications. They require V_IDto be

applied to some pins.

3.6.1

3.6.2

Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read

to identify the memory. These codes can be read by applying the signals listed in Table 4

and Table 5, Bus operations.

Block Protect and Chip Unprotect

Groups of blocks can be protected against accidental Program or Erase. The Protection

Groups are shown in Appendix A, Table 24: Block addresses The whole chip can be

unprotected to allow the data inside the blocks to be changed.

The V_PP/Write Protect pin can be used to protect the four outermost boot blocks. When

V

_PP/Write Protect is at V_ILthe four outermost boot blocks are protected and remain

protected regardless of the Block Protection Status or the Reset/Block Temporary

Unprotect pin status.

Block Protect and Chip Unprotect operations are described in Appendix D.

18/74

M29DW640F

Table 4.

Bus operations

(1)

Bus operations, BYTE = V_IL

Address Inputs

A2 A1 A0

Cell address

Data Inputs/Outputs

Operation

E

G

W

A21-

A12

Others, DQ14

DQ15A-1 -DQ8

A3

DQ7-DQ0

Bus Read

V_ILV_ILV_IH

V_ILV_IHV_IL

Hi-Z

Data Output

Data Input

Hi-Z

Bus Write

Command address

Output Disable

Standby

X

V_IHV_IH

X

V_IH

X

Hi-Z

Read Manufacturer

Code

V_ILV_ILV_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

Hi-Z

20h

7Eh

02h

01h

Read Device Code

(Cycle 1)

Bank

addrs

Read Device Code

(Cycle 2)

Hi-Z

A6 = V_IL

A9 = V_ID,

others =X

Read Device Code

(Cycle 3)

Hi-Z

Extended Block

Indicator Bit

80h (factory locked)

00h (not locked)

Bank

A

V_ILV_ILV_IH

V_IL

V_IH

V_IL

Hi-Z

(DQ7)

01h (protected)

Block Protection

Verification

Block

addrs

V_ILV_ILV_IH

00h (unprotected)

1. X = V or V

.

IH

IL

19/74

Bus operations

M29DW640F

(1)

Table 5.

Bus operations, BYTE = V_IH

Address Inputs

A2 A1 A0

Cell address

Data Inputs/Outputs

DQ15A-1, DQ14-DQ0

Operation

E

G

W

A21-

A12

A3

Others

Bus Read

Bus Write

Output Disable

Standby

V_ILV_ILV_IH

V_ILV_IHV_IL

Data Output

Data Input

Hi-Z

Command address

X

V_IHV_IH

X

V_IH

X

Hi-Z

Read Manufacturer

Code

V_ILV_ILV_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

0020h

227Eh

2202h

2201h

Read Device Code

(Cycle 1)

Bank

addrs

Read Device Code

(Cycle 2)

A6 = V_IL

A9 = V_ID,

others =X

Read Device Code

(Cycle 3)

Extended Block

Indicator Bit

0080h (factory locked)

0000h (not locked)

Bank

A

V_ILV_ILV_IH

V_IL

V_IH

V_IL

(DQ7)

0001h (protected)

Block Protection

Verification

Block

addrs

V_ILV_ILV_IH

0000h (unprotected)

1. X = V or V

.

IH

IL

20/74

M29DW640F

Command interface

4

Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations. Failure to observe a

valid sequence of Bus Write operations will result in the memory returning to Read mode.

The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-

bit or 8-bit mode. See either Table 6, or Table 7, depending on the configuration that is being

used, for a summary of the commands.

4.1

Standard commands

4.1.1

Read/Reset command

The Read/Reset command returns the memory to its Read mode. It also resets the errors in

the Status Register. Either one or three Bus Write operations can be used to issue the

Read/Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a

program or erase operation, to return the device to read mode. If the Read/Reset command

is issued during the timeout of a Block erase operation then the memory will take up to 10µs

to abort. During the abort period no valid data can be read from the memory. The

Read/Reset command will not abort an Erase operation when issued while in Erase

Suspend.

4.1.2

Auto Select command

The Auto Select command is used to read the Manufacturer Code and Device Code, the

Block Protection Status and the Extended Block Indicator. It can be addressed to either

Bank. Three consecutive Bus Write operations are required to issue the Auto Select

command. The final Write cycle must be addressed to one of the Banks. Once the Auto

Select command is issued Bus Read operations to the Bank where the command was

issued output the Auto Select data. Bus Read operations to the other Bank will output the

contents of the memory array. The memory remains in Auto Select mode until a Read/Reset

or CFI Query command is issued. This command must be issued addressing the same

Bank, as was given when entering Auto Select Mode.

In Auto Select mode the Manufacturer Code can be read using a read operation, A6 and A3

to A0 each held at V_IL, and A21-A19 set to the Bank Address. The other address bits may

be set to either V_ILor V_IH.

The Device Codes can be read using a read operation, A6 held at V_IL, A3 to A0 each held at

the levels given in Table 4 and Table 5, and A21-A19 set to the Bank Address. The other

address bits may be set to either V_ILor V_IH.

The Block Protection Status of each block can be read using a read operation, A6 A3 A2 A0

each held at V_IL, A1 held at V_IH, and A21-A19 set to the Bank Address, and A18-A12

specifying the address of the block inside the Bank. The other address bits may be set to

either V_ILor V_IH. If the addressed block is protected then 01h is output on Data

Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

21/74

Command interface

M29DW640F

The Extended Block Status of the Extended Block can be read using a read operation, A6,

A3 and A2, at V_IL, A0 and A1, at V_IH, and A21-A19 set to Bank Address A. The other bits

may be set to either V_ILor V_IH(Don't Care). If the Extended Block is "Factory Locked" then

80h is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output.

4.1.3

Read CFI Query command

The Read CFI Query Command is used to put the addressed bank in Read CFI Query

mode. Once in Read CFI Query mode Bus Read operations to the same bank will output

data from the Common Flash Interface (CFI) Memory Area. If the read operations are to a

different bank from the one specified in the command then the read operations will output

the contents of the memory array and not the CFI data.

One Bus Write cycle is required to issue the Read CFI Query Command. Care must be

taken to issue the command to one of the banks (A21-A19) along with the address shown in

Table 4 and Table 5 (A-1, A0-A10). Once the command is issued subsequent Bus Read

operations in the same bank (A21-A19) to the addresses shown in Appendix B (A7-A0), will

read from the Common Flash Interface Memory Area.

This command is valid only when the device is in the Read Array or Autoselected mode. To

enter Read CFI query mode from Auto Select mode, the Read CFI Query command must

be issued to the same bank address as the Auto Select command, otherwise the device will

not enter Read CFI Query mode.

The Read/Reset command must be issued to return the device to the previous mode (the

Read Array mode or Autoselected mode). A second Read/Reset command would be

needed if the device is to be put in the Read Array mode from Autoselected mode.

See Appendix B, Table 25, Table 26, Table 27, Table 28, Table 29 and Table 30 for details on

the information contained in the Common Flash Interface (CFI) memory area.

4.1.4

Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations

are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all

of the blocks are protected the Chip Erase operation appears to start but will terminate

within about 100µs, leaving the data unchanged. No error condition is given when protected

blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase

Suspend command. It is not possible to issue any command to abort the operation. Typical

chip erase times are given in Table 8. All Bus Read operations during the Chip Erase

operation will output the Status Register on the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and

return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All

previous data is lost.

22/74

M29DW640F

Command interface

4.1.5

Block Erase command

The Block Erase command can be used to erase a list of one or more blocks in one or more

Banks. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the

selected blocks is lost.

Six Bus Write operations are required to select the first block in the list. Each additional

block in the list can be selected by repeating the sixth Bus Write operation using the address

of the additional block. The Block Erase operation starts the Program/Erase Controller after

a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any more blocks. Each additional block must

therefore be selected within 50µs of the last block. The 50µs timer restarts when an

additional block is selected. After the sixth Bus Write operation a Bus Read operation within

the same Bank will output the Status Register. See the Status Register section for details on

how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks

are erased. If all of the selected blocks are protected the Block Erase operation appears to

start but will terminate within about 100µs, leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase

Suspend command and the Read/Reset command which is only accepted during the 50µs

time-out period. Typical block erase times are given in Table 8.

After the Erase operation has started all Bus Read operations to the Banks being erased will

output the Status Register on the Data Inputs/Outputs. See the section on the Status

Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs Bus Read operations to the Banks

where the command was issued will continue to output the Status Register. A Read/Reset

command must be issued to reset the error condition and return to Read mode.

4.1.6

Erase Suspend command

The Erase Suspend command may be used to temporarily suspend a Block or multiple

Block Erase operation. One Bus Write operation specifying the Bank Address of one of the

Blocks being erased is required to issue the command. Issuing the Erase Suspend

command returns the whole device to Read mode.

The Program/Erase Controller will suspend within the Erase Suspend Latency time (see

Table 8 for value) of the Erase Suspend Command being issued. Once the Program/Erase

Controller has stopped the memory will be set to Read mode and the Erase will be

suspended. If the Erase Suspend command is issued during the period when the memory is

waiting for an additional block (before the Program/Erase Controller starts) then the Erase is

suspended immediately and will start immediately when the Erase Resume Command is

issued. It is not possible to select any further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. If any

attempt is made to program in a protected block or in the suspended block then the Program

command is ignored and the data remains unchanged. The Status Register is not read and

no error condition is given. Reading from blocks that are being erased will output the Status

Register.

23/74

Command interface

M29DW640F

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands

during an Erase Suspend. The Read/Reset command must be issued to return the device to

Read Array mode before the Resume command will be accepted.

During Erase Suspend a Bus Read operation to the Extended Block will output the

Extended Block data. Once in the Extended Block mode, the Exit Extended Block command

must be issued before the erase operation can be resumed.

4.1.7

4.1.8

Erase Resume command

The Erase Resume command is used to restart the Program/Erase Controller after an

Erase Suspend. The command must include the Bank Address of the Erase-Suspended

Bank, otherwise the Program/Erase Controller is not restarted.

The device must be in Read Array mode before the Resume command will be accepted. An

Erase can be suspended and resumed more than once.

Program Suspend command

The Program Suspend command allows the system to interrupt a program operation so that

data can be read from any block. When the Program Suspend command is issued during a

program operation, the device suspends the program operation within the Program Suspend

Latency time (see Table 8 for value) and updates the Status Register bits. The Bank

Addresses of the Block being programmed must be specified in the Program Suspend

command.

After the program operation has been suspended, the system can read array data from any

address. However, data read from Program-Suspended addresses is not valid.

The Program Suspend command may also be issued during a program operation while an

erase is suspended. In this case, data may be read from any addresses not in Erase

Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time

Program area), the user must use the proper command sequences to enter and exit this

region.

The system may also issue the Auto Select command sequence when the device is in the

Program Suspend mode. The system can read as many Auto Select codes as required.

When the device exits the Auto Select mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See Auto Select command sequence for

more information.

4.1.9

Program Resume command

After the Program Resume command is issued, the device reverts to programming. The

controller can determine the status of the program operation using the DQ7 or DQ6 status

bits, just as in the standard program operation. See Write Operation Status for more

information.

The system must write the Program Resume command, specifying the Bank addresses of

the Program-Suspended Block, to exit the Program Suspend mode and to continue the

programming operation.

Further issuing of the Resume command is ignored. Another Program Suspend command

can be written after the device has resumed programming.

24/74

M29DW640F

Command interface

4.1.10

Program command

The Program command can be used to program a value to one address in the memory array

at a time. The command requires four Bus Write operations, the final Write operation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

Programming can be suspended and then resumed by issuing a Program Suspend

command and a Program Resume command, respectively (see Section 4.1.8: Program

Suspend command and Section 4.1.9: Program Resume command).

If the address falls in a protected block then the Program command is ignored, the data

remains unchanged. The Status Register is never read and no error condition is given.

After programming has started, Bus Read operations in the Bank being programmed output

the Status Register content, while Bus Read operations to the other Bank output the

contents of the memory array. See the section on the Status Register for more details.

Typical program times are given in Table 8.

After the program operation has completed the memory will return to the Read mode, unless

an error has occurred. When an error occurs Bus Read operations to the Bank where the

command was issued will continue to output the Status Register. A Read/Reset command

must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.2

Fast Program commands

There are five Fast Program commands available to improve the programming throughput,

by writing several adjacent Words or Bytes in parallel.

When V_PPHis applied to the V_PP/Write Protect pin the memory automatically enters the Fast

Program mode. The user can then choose to issue any of the Fast Program commands.

Care must be taken because applying a V_PPHto the V_PP/WP pin will temporarily unprotect

any protected block. Fast programming should not be attempted when V_PPis not at V_PPH

.

4.2.1

Double Word Program command

This is used to write two adjacent Words in x16 mode, in parallel. The addresses of the two

Words must differ only in A0.

Three bus write cycles are necessary to issue the command.

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Word to be written.

3. The third bus cycle latches the Address and the Data of the second Word to be written

and starts the Program/Erase Controller.

25/74

Command interface

M29DW640F

4.2.2

Quadruple Word Program command

This is used to write a page of four adjacent Words, in x16 mode, in parallel. The addresses

of the four Words must differ only in A1 and A0.

Five bus write cycles are necessary to issue the command.

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Word to be written.

3. The third bus cycle latches the Address and the Data of the second Word to be written.

4. The fourth bus cycle latches the Address and the Data of the third Word to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Word to be written

and starts the Program/Erase Controller.

4.2.3

Double Byte Program command

This is used to write two adjacent Bytes in x8 mode, in parallel. The addresses of the two

Bytes must differ only in DQ15A-1.

Three bus write cycles are necessary to issue the command.

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written

and starts the Program/Erase Controller.

4.2.4

Quadruple Byte Program command

This is used to write four adjacent Bytes in x8 mode, in parallel. The addresses of the four

Bytes must differ only in A0, DQ15A-1.

Five bus write cycles are necessary to issue the command.

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written and

starts the Program/Erase Controller.

26/74

M29DW640F

Command interface

4.2.5

Octuple Byte Program command

This is used to write eight adjacent Bytes, in x8 mode, in parallel. The addresses of the eight

Bytes must differ only in A1, A0 and DQ15A-1.

Nine bus write cycles are necessary to issue the command.

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.

6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.

7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.

8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be

written.

9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written

and starts the Program/Erase Controller.

Only one bank can be programmed at any one time. The other bank must be in Read mode

or Erase Suspend.

After programming has started, Bus Read operations in the Bank being programmed output

the Status Register content, while Bus Read operations to the other Bank output the

contents of the memory array.

Programming can be suspended and then resumed by issuing a Program Suspend

command and a Program Resume command, respectively. (See Section 4.1.8: Program

Suspend command and Section 4.1.9: Program Resume command)

After the program operation has completed the memory will return to the Read mode, unless

an error has occurred. When an error occurs Bus Read operations to the Bank where the

command was issued will continue to output the Status Register. A Read/Reset command

must be issued to reset the error condition and return to Read mode.

Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’

to ’1’.

Typical Program times are given in Table 8: Program, Erase times and Program, Erase

Endurance cycles.

4.2.6

Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory faster than with the standard program commands. When

the cycle time to the device is long, considerable time saving can be made by using these

commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode.

The Unlock Bypass Program command can then be issued to program addresses within the

bank, or the Unlock Bypass Reset command can be issued to return the bank to Read

mode. In Unlock Bypass mode the memory can be read as if in Read mode.

27/74

Command interface

M29DW640F

When V_PPis applied to the V_PP/Write Protect pin the memory automatically enters the

Unlock Bypass mode and the Unlock Bypass Program command can be issued

immediately.

4.2.7

Unlock Bypass Program command

The Unlock Bypass Program command can be used to program one address in the memory

array at a time. The command requires two Bus Write operations, the final write operation

latches the address and data in the internal state machine and starts the Program/Erase

Controller.

The Program operation using the Unlock Bypass Program command behaves identically to

the Program operation using the Program command. The operation cannot be aborted, a

Bus Read operation to the Bank where the command was issued outputs the Status

Register. See the Program command for details on the behavior.

4.2.8

Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from

Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass

Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

4.3

Block Protection commands

4.3.1

Enter Extended Block command

The M29DW640F has one extra 256-Byte block (Extended Block) that can only be accessed

using the Enter Extended Block command. Three Bus write cycles are required to issue the

Extended Block command. Once the command has been issued the device enters

Extended Block mode where all Bus Read or Program operations to the 000000h-00007Fh

(Word) or 000000h-0000FFh (Byte) addresses access the Extended Block. The Extended

Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In

Extended Block mode only array cell locations (Bank A) with the same addresses as the

Extended Block (000000h-00007Fh (Word) or 000000h-0000FFh (Byte)) are not accessible.

In Extended Block mode dual operations are allowed and the Extended Block physically

belongs to Bank A.

When in Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume

commands are not allowed.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be

undone.

4.3.2

Exit Extended Block command

The Exit Extended Block command is used to exit from the Extended Block mode and return

the device to Read mode. Four Bus Write operations are required to issue the command.

28/74

M29DW640F

Command interface

4.3.3

Block Protect and Chip Unprotect commands

Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are

shown in Appendix A, Table 24: Block addresses. The whole chip can be unprotected to allow the data

inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix D.

Table 6.

Commands, 16-bit mode, BYTE = V_IH

Bus Write operations⁽¹⁾

3rd 4th

Add Data Add Data Add Data Add Data Add Data Add Data

Command

1st

2nd

5th

6th

1

3

X

F0

Read/Reset

Auto Select

555

AA 2AA

55

X

F0

90

A0

(BKA)

555

3

555

AA 2AA

Program

4

3

2

6

555

X

555

PA

PD

Double Word Program

Quadruple Word Program

Unlock Bypass

50

56

PA0 PD0 PA1 PD1

PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

AA 2AA

55

PD

00

55

555

20

Unlock Bypass Program

Unlock Bypass Reset

Chip Erase

A0

90

PA

X

555

AA 2AA

B0

555

80

555

AA 2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase/Program Suspend

Erase/Program Resume

1

BKA

30

(BKA)

55

Read CFI Query⁽²⁾

1

98

Enter Extended Block

Exit Extended Block

3

4

555

AA 2AA

55

555

88

90

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the

table are in hexadecimal.

2. Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t

Care, however for the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations

must be addressed to the same bank.

29/74

Command interface

M29DW640F

Table 7.

Commands, 8-bit mode, BYTE = V_IL

Bus Write operations⁽¹⁾

1st

2nd

3rd

4th

5th

6th

7th

8th

9th

Command

1

3

X

F0

Read/Reset

AAA AA 555 55

X

F0

90

(BKA)

AAA

Auto Select

Program

3

4

AAA AA 555 55 AAA A0 PA PD

AAA 50 PA0 PD1 PA1 PD1

Double

Byte

Program

3

5

Quadruple

Byte

AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

Program

Octuple

Byte

Program

5

3

2

AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7

AAA AA 555 55 AAA 20

Unlock

Bypass

Unlock

Bypass

Program

X

A0 PA PD

Unlock

Bypass

Reset

2

6

90

X

00

Chip Erase

AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase/

Program

Suspend

1

BKA B0

Erase/

Program

Resume

1

3

BKA 30

Read CFI

Query⁽²⁾

(BKA)

98

AA

Enter

Extended

Block

AAA AA 555 55 AAA 88

AAA AA 555 55 AAA 90

Exit

Extended

Block

4

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

2. Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t Care, however for

the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations must be addressed to the same bank.

30/74

M29DW640F

Table 8.

Command interface

Program, Erase times and Program, Erase Endurance cycles

Parameter

Min

Typ⁽¹⁾⁽²⁾

Max⁽²⁾

Unit

Chip Erase

80

400⁽³⁾

6⁽⁴⁾

s

Block Erase (64 KBytes)

0.8

s

µs

Erase Suspend latency time

50⁽⁴⁾

200⁽³⁾

400⁽³⁾

200⁽³⁾

100⁽³⁾

50⁽³⁾

4

Byte Program (1, 2, 4 or 8 at-a-time)

Word Program (1, 2 or 4 at-a-time)

Chip Program (Byte by Byte)

10

80

40

20

10

µs

s

Chip Program (Word by Word)

Chip Program (quadruple Byte or double Word)

Chip Program (octuple Byte or quadruple Word)

Program Suspend latency time

Program/Erase cycles (per Block)

Data Retention

s

µs

100,000

20

cycles

years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

31/74

Status register

M29DW640F

5

Status register

The M29DW640F has one Status Register. The Status Register provides information on the

current or previous Program or Erase operations executed in each bank. The various bits

convey information and errors on the operation. Bus Read operations from any address

within the Bank, always read the Status Register during Program and Erase operations. It is

also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summarized in Table 9: Status Register Bits.

5.1

Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the

Program/Erase Controller has suspended the Erase operation.

Figure 6: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid

Address is the address being programmed or an address within the block being erased.

5.1.1

Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Toggle

Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address. After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block

being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure 7: Toggle flowchart, gives an example of how to use the Data Toggle Bit. Figure 14

and Figure 15 describe Toggle Bit timing waveform.

32/74

M29DW640F

Status register

5.1.2

Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The

Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the

correct data to the memory. If the Error Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit is output on DQ5 when the Status Register

is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to

do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.

One of the Erase commands must be used to set all the bits in a block or in the whole

memory from ’0’ to ’1’.

5.1.3

5.1.4

Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation

during a Block Erase command. Once the Program/Erase Controller starts erasing the

Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit

is set to ’0’ and additional blocks to be erased may be written to the Command Interface.

The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during

Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is

read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,

etc., with successive Bus Read operations from addresses within the blocks being erased. A

protected block is treated the same as a block not being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read operations from addresses within the blocks being erased. Bus Read

operations to addresses within blocks not being erased will output the memory cell data as if

in Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses

within blocks that have not erased correctly. The Alternative Toggle Bit does not change if

the addressed block has erased correctly.

Figure 14 and Figure 15 describe Alternative Toggle Bit timing waveform.

33/74

Status register

M29DW640F

Table 9.

Status Register Bits

Operation

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Program

Bank address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

Bank address

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Bank address

Any address

DQ7

Toggle

1

0

–

1

0

1

–

Hi-Z

0

1

Toggle

Erasing block

Toggle

Block Erase before

timeout

Non-Erasing block

Erasing block

Toggle

No Toggle

Toggle

0

Toggle

Hi-Z

0

Block Erase

Erase Suspend

Erase Error

Non-Erasing block

Erasing block

Toggle

No Toggle

Toggle

No Toggle

Hi-Z

0

Non-Erasing block

Good Block address

Faulty Block address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

0

1. Unspecified data bits should be ignored.

1. Figure 14 and Figure 15 describe Toggle and Alternative Toggle Bits timing waveforms.

Figure 6.

Data Polling flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

=

YES

DATA

NO

DQ5 = 1

YES

READ DQ7

at VALID ADDRESS

DQ7

=

YES

DATA

NO

FAIL

PASS

AI07760

34/74

M29DW640F

Figure 7.

Status register

Toggle flowchart

START

READ DQ6

ADDRESS = BA

READ

DQ5 & DQ6

ADDRESS = BA

DQ6

=

NO

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

ADDRESS = BA

DQ6

=

NO

TOGGLE

YES

FAIL

PASS

AI08929b

1. BA = Address of Bank being Programmed or Erased.

35/74

Dual operations and multiple bank architecture

M29DW640F

6

Dual operations and multiple bank architecture

The Multiple Bank Architecture of the M29DW640F gives greater flexibility for software developers to split

the code and data spaces within the memory array. The Dual Operations feature simplifies the software

management of the device by allowing code to be executed from one bank while another bank is being

programmed or erased.

The Dual Operations feature means that while programming or erasing in one bank, read operations are

possible in another bank with zero latency.

Only one bank at a time is allowed to be in program or erase mode. However, certain commands can

cross bank boundaries, which means that during an operation only the banks that are not concerned with

the cross bank operation are available for dual operations. For example, if a Block Erase command is

issued to erase blocks in both Bank A and Bank B, then only Banks C or D are available for read

operations while the erase is being executed.

If a read operation is required in a bank, which is programming or erasing, the program or erase

operation can be suspended.

Also if the suspended operation was erase then a program command can be issued to another block, so

the device can have one block in Erase Suspend mode, one programming and other banks in read mode.

By using a combination of these features, read operations are possible at any moment in the device.

Table 10 and Table 11 show the dual operations possible in other banks and in the same bank. Note that

only the commonly used commands are represented in these tables.

Table 10. Dual operations allowed in other banks

Commands allowed in another bank⁽¹⁾

Status of bank⁽¹⁾

Read

Status

Read

CFI

Query

Program/ Program/

Erase Erase

Suspend Resume

Auto

Read

Array

Program Erase

Select

Register⁽²⁾

Idle

Yes

Yes⁽³⁾

No

Yes

No

Yes

No

Yes

–

Yes

–

Yes⁽³⁾

No

–

Yes⁽⁴⁾

No

Programming

Erasing

No

–

No

Program Suspended

Erase Suspended

No

Yes

No

Yes

No

Yes⁽⁵⁾

Yes⁽⁶⁾

No

–

1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the operation

are available for dual operations.

2. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.

3. Only after a program or erase operation in that bank.

4. Only after a Program or Erase Suspend command in that bank.

5. Only a Program Resume is allowed if the bank was previously in Program Suspend mode.

6. Only an Erase Resume is allowed if the bank was previously in Erase Suspend mode.

36/74

M29DW640F

Dual operations and multiple bank architecture

Table 11. Dual operations allowed in same bank

Commands allowed in same bank

Read

CFI

Query

Program/ Program/

Auto

Status of bank

Read ReadStatus

Array

Program

Erase

Register⁽¹⁾

Select

Suspend Resume

Idle

Yes

No

Yes

No

Yes

No

Yes

–

Yes

–

Yes⁽²⁾

Yes⁽⁴⁾

Yes⁽⁵⁾

Yes⁽³⁾

Programming

Erasing

–

No

Program

Suspended

Yes⁽⁶⁾

No

Yes

No

–

Yes

Erase Suspended

Yes⁽⁷⁾

Yes⁽⁶⁾

No

1. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.

2. Only after a program or erase operation in that bank.

3. Only after a Program or Erase Suspend command in that bank.

4. Only a Program Suspend.

5. Only an Erase suspend.

6. Not allowed in the Block or Word that is being erased or programmed.

7. The Status Register can be read by addressing the block being erase suspended.

37/74

Maximum ratings

M29DW640F

7

Maximum ratings

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions

for extended periods may affect device reliability. These are stress ratings only and

operation of the device at these or any other conditions above those indicated in the

Operating sections of this specification is not implied. Refer also to the Numonyx SURE

Program and other relevant quality documents.

Table 12. Absolute maximum ratings

Symbol

Parameter

Temperature Under Bias

Min

Max

Unit

T_BIAS

T_STG

V_IO

–50

–65

125

150

°C

V

Storage Temperature

Input or Output voltage ⁽¹⁾⁽²⁾

Supply voltage

–0.6

V_CC+0.6

4

V_CC

V_ID

V

Identification voltage

Program voltage

13.5

V

(3)

V_PP

13.5

V

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

3.

V

must not remain at 12V for more than a total of 80hrs.

PP

38/74

M29DW640F

DC and AC parameters

8

DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 13: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Table 13. Operating and AC measurement conditions

M29DW640F

Parameter

60

70

Unit

Min

Max

Min

Max

V

_CCSupply voltage

2.7

3.6

85

2.7

3.6

85

V

°C

pF

ns

V

Ambient Operating Temperature

Load capacitance (C_L)

–40

30

Input Rise and Fall times

10

Input pulse voltages

0 to V_CC

_CC/2

0 to V_CC

V_CC/2

Input and Output Timing Ref. voltages

V

Figure 8.

AC measurement I/O waveform

V

CC

0V

V

/2

CC

AI05557

39/74

DC and AC parameters

Figure 9. AC measurement Load Circuit

M29DW640F

V

CC

PP

CC

25kΩ

DEVICE

UNDER

TEST

C

L

0.1µF

C

includes JIG capacitance

L

AI05558

Table 14. Device capacitance⁽¹⁾

Symbol

Parameter

Test condition

Min

Max

Unit

C_IN

Input capacitance

Output capacitance

V_IN= 0V

6

pF

C_OUT

V_OUT= 0V

12

1. Sampled only, not 100% tested.

40/74

M29DW640F

DC and AC parameters

Table 15. DC characteristics

Symbol

Parameter

Test condition

Min

Max

Unit

I_LI

Input Leakage Current

Output Leakage Current

0V ≤V_IN≤V_CC

1

µA

I_LO

0V ≤V_OUT≤V_CC

E = V_IL, G = V_IH,

f = 6MHz

(1)

I

Supply Current (Read)

10

100

20

mA

µA

CC1

E = V_CC0.2V,

RP = V_CC0.2V

I_CC2

Supply Current (Standby)

V

_PP/WP =

mA

Supply Current

(Program/Erase)

Program/Erase

Controller active

(1)(2)

V_ILor V_IH

I_CC3

V

_PP/WP = V_PP

20

0.8

mA

V

V_IL

Input Low voltage

Input High voltage

–0.5

V_IH

0.7V_CC

V_CC+0.3

V

Voltage for V /WP Program

Acceleration

PP

V_PP

V_CC= 2.7V 10%

11.5

12.5

V

Current for V /WP Program

Acceleration

PP

I_PP

V_CC=2.7V 10%

15

mA

V_OL

V_OH

V_ID

Output Low voltage

Output High voltage

Identification voltage

I_OL= 1.8mA

0.45

V

I_OH= –100µA

V_CC–0.4

11.5

12.5

2.3

Program/Erase Lockout supply

voltage

V_LKO

1.8

V

1. In Dual operations the Supply Current will be the sum of I

2. Sampled only, not 100% tested.

(read) and I

(program/erase).

CC3

CC1

41/74

DC and AC parameters

M29DW640F

Figure 10. Random Read AC waveforms

tAVAV

VALID

A0-A21/

A–1

tAVQV

tAXQX

tEHQX

E

tELQV

tELQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05559

42/74

M29DW640F

Figure 11. Page Read AC waveforms

DC and AC parameters

43/74

DC and AC parameters

M29DW640F

Table 16. Read AC characteristics

M29DW640F

Symbol

Alt

Parameter

Test condition

Unit

60

70

E = V_IL,

Min

t_AVAV

t_AVQV

t_AVQV1

t_RC

Address Valid to Next Address Valid

Address Valid to Output Valid

60

70

ns

G = V_IL

E = V_IL,

Max

t_ACC

60

25

70

25

G = V_IL

E = V_IL,

Max

t_PAGE

t_FLQZ

Address Valid to Output Valid (Page)

BYTE Low to Output Hi-Z

G = V_IL

t_BLQZ

t_BHQV

Max

25

30

0

25

30

0

ns

t_FHQVBYTE High to Output valid

(1)

t_ELQX

t_LZ

t_HZ

t_CE

Chip Enable Low to Output Transition

G = V_IL

Min

Max

(1)

t_EHQZ

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

25

60

25

70

t_ELQV

t_ELBL

t_ELBH

t_EHQX

t_GHQX

t_ELFL

t_ELFH

Chip Enable to BYTE Low or High

Max

Min

5

0

5

0

ns

Chip Enable, Output Enable or

Address Transition to Output Transition

t_OH

t_AXQX

Output Enable Low to Output

Transition

(1)

t_GLQX

t_OLZ

E = V_IL

t_GLQV

t_OE

t_DF

Output Enable Low to Output Valid

Output Enable High to Output Hi-Z

E = V_IL

Max

25

ns

(1)

t_GHQZ

1. Sampled only, not 100% tested.

44/74

M29DW640F

DC and AC parameters

Figure 12. Write AC waveforms, Write Enable controlled

tAVAV

A0-A21/

VALID

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05560

45/74

DC and AC parameters

M29DW640F

Table 17. Write AC characteristics, Write Enable controlled

M29DW640F

Symbol

Alt

Parameter

Unit

60

70

t_AVAV

t_AVWL

t_DVWH

t_ELWL

t_WC

t_AS

t_DS

t_CS

Address Valid to Next Address Valid

Address Valid to Write Enable Low

Input Valid to Write Enable High

Min

Max

60

0

70

0

ns

µs

ns

45

0

45

0

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

V_CCHigh to Chip Enable Low

t_GHWL

t_VCHEL

t_WLWH

t_WHDX

t_WHEH

t_WHWL

t_WLAX

t_WHGL

0

t_VCS

t_WP

50

45

0

50

45

0

Write Enable Low to Write Enable High

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable High to Output Enable Low

Program/Erase Valid to RB Low

t_DH

t_CH

0

t_WPH

t_AH

t_OEH

t_BUSY

30

45

0

30

45

0

(1)

t_WHRL

30

1. Sampled only, not 100% tested.

46/74

M29DW640F

DC and AC parameters

Figure 13. Write AC waveforms, Chip Enable controlled

tAVAV

A0-A21/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI05561

47/74

DC and AC parameters

M29DW640F

Table 18. Write AC characteristics, Chip Enable controlled

M29DW640F

Symbol

Alt

Parameter

Unit

60

70

t_AVAV

t_AVEL

t_DVEH

t_ELEH

t_ELAX

t_EHDX

t_EHWH

t_EHEL

t_EHGL

t_WC

t_AS

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

Input Valid to Chip Enable High

Min

Max

Min

60

0

70

0

ns

µs

ns

t_DS

45

0

45

0

t_CP

Chip Enable Low to Chip Enable High

Chip Enable Low to Address Transition

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Program/Erase Valid to RB Low

t_AH

t_DH

t_WH

t_CPH

t_OEH

t_BUSY

0

30

0

30

0

(1)

t_EHRL

30

0

30

0

t_GHEL

t_VCHWL

t_WLEL

Output Enable High Chip Enable Low

V_CCHigh to Write Enable Low

t_VCS

t_WS

50

0

50

0

Write Enable Low to Chip Enable Low

1. Sampled only, not 100% tested.

48/74

M29DW640F

DC and AC parameters

Figure 14. Toggle and Alternative Toggle Bits mechanism, Chip Enable controlled

Address Outside the Bank

Being Programmed or Erased

Address in the Bank

Being Programmed or Erased

Address Outside the Bank

Being Programmed or Erased

A0-A21

A-1

tAXEL

E

G

tELQV

Toggle/

Alternative Toggle Bit

Toggle/

Alternative Toggle Bit

Data

DQ2⁽¹⁾/DQ6⁽²⁾

Read Operation outside the Bank

Being Programmed or Erased

Read Operation in the Bank

Being Programmed or Erased

Read Operation Outside the Bank

Being Programmed or Erased

AI08914d

1. The Toggle Bit is output on DQ6.

2. The Alternative Toggle Bit is output on DQ2.

3. Refer to Table 16: Read AC characteristics for t

value.

ELQV

Figure 15. Toggle and Alternative Toggle Bits mechanism, Output Enable controlled

Address Outside the Bank

Being Programmed or Erased

Address in the Bank

Being Programmed or Erased

Address Outside the Bank

Being Programmed or Erased

A0-A21

A-1

tAXGL

G

E

tGLQV

Toggle/

Alternative Toggle Bit

Toggle/

Alternative Toggle Bit

Data

DQ2⁽¹⁾/DQ6⁽²⁾

Read Operation outside the Bank

Being Programmed or Erased

Read Operation in the Bank

Being Programmed or Erased

Read Operation Outside the Bank

Being Programmed or Erased

AI08915d

1. The Toggle Bit is output on DQ6.

4. The Alternative Toggle Bit is output on DQ2.

5. Refer to Table 16: Read AC characteristics for t

value.

GLQV

49/74

DC and AC parameters

M29DW640F

Unit

Table 19. Toggle and Alternative Toggle Bits AC characteristics

Symbol

Alt

Parameter

60

70

t_AXEL

t_AXGL

Address Transition to Chip Enable Low

Address Transition to Output Enable Low

Min

10

ns

Figure 16. Reset/Block Temporary Unprotect AC waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPHPHH

tPLPX

RP

tPLYH

AI02931B

Figure 17. Accelerated Program Timing waveforms

V

PP

V

/WP

PP

V

or V

IH

IL

tVHVPP

AI05563

50/74

M29DW640F

DC and AC parameters

Table 20. Reset/Block Temporary Unprotect AC characteristics

M29DW640F

Unit

Symbol

Alt

Parameter

60

70

(1)

t_PHWL

RP High to Write Enable Low, Chip Enable

Low, Output Enable Low

t_PHEL

t_RH

Min

50

ns

(1)

t_PHGL

(1)

t_RHWL

RB High to Write Enable Low, Chip Enable

Low, Output Enable Low

(1)

t_RHEL

t_RB

0

(1)

t_RHGL

t_PLPX

t_PLYH

t_RP

RP Pulse Width

Min

Max

Min

500

20

500

20

ns

µs

ns

t_READYRP Low to Read Mode

(1)

t_PHPHH

t_VIDR

RP Rise Time to V_ID

500

250

500

250

(1)

t_VHVPP

V_PPRise and Fall Time

1. Sampled only, not 100% tested.

51/74

Package mechanical

M29DW640F

9

Package mechanical

Figure 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

1. Drawing is not to scale.

Table 21. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

B

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3°

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3°

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

α

0°

5°

0°

5°

52/74

M29DW640F

Package mechanical

Figure 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

1. Drawing is not to scale.

Table 22. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

53/74

Part numbering

M29DW640F

10

Part numbering

Table 23. Ordering information scheme

Example:

M29DW640F

70

N

1

T

Device Type

M29

Architecture

D = Dual or Multiple Bank

Operating Voltage

W = V_CC= 2.7 to 3.6V

Device Function

640F = 64 Mbit (x8/x16), Boot Block, 8+24+24+8 partitioning, 0.13µm technology

Speed

60 = 60ns

70 = 70ns

Package

N = TSOP48: 12 x 20 mm

ZE = TFBGA48 6 x 8mm, 0.8 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Note:

This product is also available with the Extended Block factory locked. For further details and

ordering information contact your nearest Numonyx sales office.

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect

of this device, please contact your nearest Numonyx Sales Office.

54/74

M29DW640F

Block addresses

Appendix A

Block addresses

Table 24. Block addresses

(KBytes/

Block

Protection Block

Group

(x8)

(x16)

KWords)

0

1

8/4

Protection Group

000000h-001FFFh⁽¹⁾

002000h-003FFFh⁽¹⁾

004000h-005FFFh⁽¹⁾

006000h-007FFFh⁽¹⁾

008000h-009FFFh⁽¹⁾

00A000h-00BFFFh⁽¹⁾

00C000h-00DFFFh⁽¹⁾

00E000h-00FFFFh⁽¹⁾

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

000000h–000FFFh⁽¹⁾

001000h–001FFFh⁽¹⁾

002000h–002FFFh⁽¹⁾

003000h–003FFFh⁽¹⁾

004000h–004FFFh⁽¹⁾

005000h–005FFFh⁽¹⁾

006000h–006FFFh⁽¹⁾

007000h–007FFFh⁽¹⁾

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

2

8/4

3

8/4

4

8/4

5

8/4

6

8/4

7

8/4

8

64/32

9

Protection Group

10

11

12

13

14

15

16

17

18

19

20

21

22

Protection Group

55/74

Block addresses

M29DW640F

Table 24. Block addresses (continued)

(KBytes/

KWords)

Protection Block

Group

Block

(x8)

(x16)

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

64/32

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

Protection Group

56/74

M29DW640F

Block addresses

(x16)

Table 24. Block addresses (continued)

(KBytes/

KWords)

Protection Block

Group

Block

(x8)

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

64/32

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h–40FFFFh

410000h–41FFFFh

420000h–42FFFFh

430000h–43FFFFh

440000h–44FFFFh

450000h–45FFFFh

460000h–46FFFFh

470000h–47FFFFh

480000h–48FFFFh

490000h–49FFFFh

4A0000h–4AFFFFh

4B0000h–4BFFFFh

4C0000h–4CFFFFh

4D0000h–4DFFFFh

4E0000h–4EFFFFh

4F0000h–4FFFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

Protection Group

57/74

Block addresses

M29DW640F

Table 24. Block addresses (continued)

(KBytes/

KWords)

Protection Block

Group

Block

(x8)

(x16)

87

88

64/32

500000h–50FFFFh

510000h–51FFFFh

520000h–52FFFFh

530000h–53FFFFh

540000h–54FFFFh

550000h–55FFFFh

560000h–56FFFFh

570000h–57FFFFh

580000h–58FFFFh

590000h–59FFFFh

5A0000h–5AFFFFh

5B0000h–5BFFFFh

5C0000h–5CFFFFh

5D0000h–5DFFFFh

5E0000h–5EFFFFh

5F0000h–5FFFFFh

600000h–60FFFFh

610000h–61FFFFh

620000h–62FFFFh

630000h–63FFFFh

640000h–64FFFFh

650000h–65FFFFh

660000h–66FFFFh

670000h–67FFFFh

680000h–68FFFFh

690000h–69FFFFh

6A0000h–6AFFFFh

6B0000h–6BFFFFh

6C0000h–6CFFFFh

6D0000h–6DFFFFh

6E0000h–6EFFFFh

6F0000h–6FFFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

Protection Group

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

58/74

M29DW640F

Block addresses

(x16)

Table 24. Block addresses (continued)

(KBytes/

KWords)

Protection Block

Group

Block

(x8)

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

64/32

8/4

700000h–70FFFFh

710000h–71FFFFh

720000h–72FFFFh

730000h–73FFFFh

740000h–74FFFFh

750000h–75FFFFh

760000h–76FFFFh

770000h–77FFFFh

780000h–78FFFFh

790000h–79FFFFh

7A0000h–7AFFFFh

7B0000h–7BFFFFh

7C0000h–7CFFFFh

7D0000h–7DFFFFh

7E0000h–7EFFFFh

7F0000h–7F1FFFh

7F2000h–7F3FFFh

7F4000h–7F5FFFh

7F6000h–7F7FFFh

7F8000h–7F9FFFh

7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

Protection Group

8/4

1. Used as Extended Block addresses in Extended Block mode.

59/74

Common Flash Interface (CFI)

M29DW640F

Appendix B

Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from

the Flash memory device. It allows a system software to query the device to determine various electrical

and timing parameters, density information and functions supported by the memory. The system can

interface easily with the device, enabling the software to upgrade itself when necessary.

When the Read CFI Query command is issued the addressed bank enters Read CFI Query mode and

read operations in the same bank (A21-A19) output the CFI data. Table 25, Table 26, Table 27, Table 28,

Table 29 and Table 30 show the addresses (A-1, A0-A10) used to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is written

(see Table 30: Security Code Area). This area can be accessed only in Read mode by the final user. It is

impossible to change the security number after it has been written by Numonyx.

Table 25. Query structure overview

Address

Sub-section name

Description

x16

x8

10h

1Bh

27h

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

61h

80h

C2h

Security Code Area

64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

Table 26. CFI Query Identification String

Address

Data

Description

Value

x16

x8

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

“Q”

"R"

"Y"

0052h Query Unique ASCII String "QRY"

0059h

0002h

AMD

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

Compatible

0000h

0040h

Address for Primary Algorithm extended Query table (see Table 29)

0000h

P = 40h

NA

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported

0000h

Address for Alternate Algorithm extended Query table

0000h

NA

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

60/74

M29DW640F

Common Flash Interface (CFI)

Table 27. CFI Query System Interface Information

Address

Data

Description

Value

x16

x8

V_CCLogic Supply Minimum Program/Erase voltage

1Bh

36h

0027h

0036h

00B5h

00C5h

bit 7 to 4 BCD value in volts

2.7V

3.6V

bit 3 to 0 BCD value in 100 mV

V_CCLogic Supply Maximum Program/Erase voltage

1Ch

1Dh

1Eh

38h

3Ah

3Ch

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV

V_PP[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

11.5V

12.5V

bit 3 to 0 BCD value in 100 mV

V_PP[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

1Fh

20h

21h

22h

23h

24h

25h

26h

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0004h

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

Typical timeout per single Byte/Word program = 2ⁿµs

Typical timeout for minimum size write buffer program = 2ⁿµs

Typical timeout per individual block erase = 2ⁿms

16µs

NA

1s

Typical timeout for full Chip Erase = 2ⁿms

NA

Maximum timeout for Byte/Word program = 2ⁿtimes typical

Maximum timeout for write buffer program = 2ⁿtimes typical

Maximum timeout per individual block erase = 2ⁿtimes typical

Maximum timeout for Chip Erase = 2ⁿtimes typical

256 µs

NA

8s

NA

61/74

Common Flash Interface (CFI)

M29DW640F

Table 28. Device Geometry Definition

Address

Data

Description

Value

x16

x8

27h

4Eh

0017h

Device Size = 2ⁿin number of Bytes

8 MBytes

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0003h

0000h

Maximum number of Bytes in multi-Byte program or page = 2ⁿ

8

Number of Erase Block Regions⁽¹⁾. It specifies the number of

regions containing contiguous Erase Blocks of the same size.

2Ch

58h

0003h

3

8

2Dh

2Eh

5Ah

5Ch

0007h

0000h

Erase Block Region 1 Information

Number of Erase Blocks of identical size = 0007h+1

2Fh

30h

5Eh

60h

0020h

0000h

Erase Block Region 1 Information

8 KBytes

126

Block size in Region 1 = 0020h * 256 Byte

31h

32h

62h

64h

007Dh

0000h

Erase Block Region 2 Information

Number of Erase Blocks of identical size = 007Dh+1

33h

34h

66h

68h

0000h

0001h

Erase Block Region 2 Information

64 KBytes

8

Block size in Region 2 = 0100h * 256 Byte

35h

36h

6Ah

6Ch

0007h

0000h

Erase Block Region 3 information

Number of Erase Blocks of identical size = 0007h + 1

37h

38h

6Eh

70h

0020h

0000h

Erase Block Region 3 information

8 KBytes

Block size in region 3 = 0020h * 256 Bytes

1. Erase Block Region 1 corresponds to addresses 000000h to 007FFFh; Erase block Region 2 corresponds to addresses

008000h to 3F7FFFh and Erase Block Region 3 corresponds to addresses 3F8000h to 3FFFFFh.

62/74

M29DW640F

Common Flash Interface (CFI)

Table 29. Primary Algorithm-specific Extended Query table

Address

Data

Description

Value

x16

x8

40h

41h

42h

43h

44h

80h

82h

84h

86h

88h

0050h

"P"

0052h Primary Algorithm extended Query table unique ASCII string “PRI”

0049h

"R"

"I"

0031h Major version number, ASCII

0033h Minor version number, ASCII

"1"

"3"

Address Sensitive Unlock (bits 1 to 0)

0000h 00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

45h

8Ah

Yes

Erase Suspend

46h

47h

48h

8Ch

8Eh

90h

0002h

2

1

00 = not supported, 01 = Read only, 02 = Read and Write

Block Protection

0001h

00 = not supported, x = number of sectors in per group

Temporary Block Unprotect

0001h

Yes

00 = not supported, 01 = supported

Block Protect /Unprotect

0005h 04 = M29W400B

05=

49h

92h

5

Simultaneous Operations,

0077h

4Ah

4Bh

4Ch

94h

96h

98h

119

No

x = number of blocks (excluding Bank A)

0000h Burst Mode, 00 = not supported, 01 = supported

Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page

0002h

Word

Yes

V_PPSupply Minimum Program/Erase voltage

4Dh

4Eh

9Ah

9Ch

00B5h bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

11.5V

12.5V

V_PPSupply Maximum Program/Erase voltage

00C5h bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

00h = uniform device

01h = 8 x8 KByte Blocks, Top and Bottom Boot with Write Protect

4Fh

9Eh

0001h

T/B

02h = Bottom boot device

03h = Top Boot Device

04h = Both Top and Bottom

50h

57h

A0h

AEh

0001h Program Suspend, 00 = not supported, 01 = supported

Yes

4

Bank Organization, 00 = data at 4Ah is zero

0004h

X = number of banks

63/74

Common Flash Interface (CFI)

M29DW640F

Value

Table 29. Primary Algorithm-specific Extended Query table

Address

Data

Description

x16

x8

Bank A information

58h

B0h

0017h

0030h

0017h

23

48

23

X = number of blocks in Bank A

Bank B information

59h

5Ah

5Bh

B2h

B4h

B6h

X = number of blocks in Bank B

Bank C information

X = number of blocks in Bank C

Bank D information

X = number of blocks in Bank D

Table 30. Security Code Area

Address

Data

Description

x16

x8

61h

62h

63h

64h

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

64/74

M29DW640F

Extended Memory Block

Appendix C

Extended Memory Block

The has an extra block, the Extended Block, that can be accessed using a dedicated

command.

This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a

security block (to provide a permanent security identification number) or to store additional

information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated

by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be

changed. When set to ‘1’, it indicates that the device is factory locked and the Extended

Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the

Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is

another security feature which ensures that a customer lockable device cannot be used

instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific

procedure must be followed to read it. See “Extended Block Indicator Bit” in Table 4: Bus

operations, BYTE = V_ILand Table 5: Bus operations, BYTE = V_IH, respectively, for details of

how to read bit DQ7.

The Extended Block can only be accessed when the device is in Extended Block mode. For

details of how the Extended Block mode is entered and exited, refer to Section 4.3: Block

Protection commands and Section 4.3.2: Exit Extended Block command, and to Table 6:

Commands, 16-bit mode, BYTE = V_IHand Table 7: Commands, 8-bit mode, BYTE = V_IL,

respectively.

C.1

C.2

Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is

written to the Extended Block address space (see Table 31: Extended Block address and

data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to

‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the

Extended Block but care must be taken because the protection of the Extended Block is not

reversible.

There are two ways of protecting the Extended Block:

●

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the In-System Technique with RP either at V_IHor at V_ID(refer to Appendix D,

Figure 22: In-System Equipment Group Protect flowchart and Figure 23: In-System

Equipment Chip Unprotect flowchart, for a detailed explanation of the technique).

●

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the Programmer Technique (refer to Appendix D, Figure 20: Programmer

Equipment Group Protect flowchart and Figure 21: Programmer Equipment Chip

Unprotect flowchart, for a detailed explanation of the technique).

65/74

Extended Memory Block

M29DW640F

Once the Extended Block is programmed and protected, the Exit Extended Block command must be

issued to exit the Extended Block mode and return the device to Read mode.

Table 31. Extended Block address and data

Address⁽¹⁾

Data

Device

Customer

Lockable

x8

x16

Factory Locked

000000h-00000Fh

000010h-00007Fh

000000h-000007h Random Number

SecurityIdentification

Number

Determined

by Customer

000008h-00003Fh

ESN⁽²⁾

000080h-0000FFh 000040h-00007Fh

Unavailable

1. See Table 24: Block addresses.

2. ENS = Electronic Serial Number.

66/74

M29DW640F

Block protection

Appendix D

Block protection

Block protection can be used to prevent any operation from modifying the data stored in the

memory. The blocks are protected in groups, refer to Appendix A, Table 24 for details of the

Protection Groups. Once protected, Program and Erase operations within the protected

group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the

Programmer technique, the In-System technique and Temporary Unprotection. Temporary

Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is

described in the Signal Descriptions section.

To protect the Extended Block issue the Enter Extended Block command and then use

either the Programmer or In-System technique. Once protected issue the Exit Extended

Block command to return to read mode. The Extended Block protection is irreversible, once

protected the protection cannot be undone.

D.1

Programmer technique

The Programmer technique uses high (V_ID) voltage levels on some of the bus pins. These

cannot be achieved using a standard microprocessor bus, therefore the technique is

recommended only for use in Programming Equipment.

To protect a group of blocks follow the flowchart in Figure 20: Programmer Equipment Group

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all groups can be unprotected at the same time. To unprotect the chip follow Figure 21:

Programmer Equipment Chip Unprotect flowchart. Table 32: Programmer technique bus

operations, BYTE = V_IHor V_IL, gives a summary of each operation.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possible. Do not abort the procedure before

reaching the end. Chip Unprotect can take several seconds and a user message should be

provided to show that the operation is progressing.

D.2

In-System technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary

Unprotect pin, RP ⁽¹⁾. This can be achieved without violating the maximum ratings of the

components on the microprocessor bus, therefore this technique is suitable for use after the

memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure 22: In-System Equipment Group

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all the groups can be unprotected at the same time. To unprotect the chip follow

Figure 23: In-System Equipment Chip Unprotect flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possible. Do not allow the microprocessor to

service interrupts that will upset the timing and do not abort the procedure before reaching

the end. Chip Unprotect can take several seconds and a user message should be provided

to show that the operation is progressing.

67/74

Block protection

Note:

M29DW640F

RP can be either at V_IHor at V_IDwhen using the In-System Technique to protect the

Extended Block.

Table 32. Programmer technique bus operations, BYTE = V_IHor V_IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A21

A9 = V_ID, A12-A21 Block Address

Others = X

Block (Group)

Protect⁽¹⁾

V_IL

V_IDV_ILPulse

X

A9 = V_ID, A12 = V_IH, A15 = V_IH

Others = X

Chip Unprotect

V_IDV_IDV_ILPulse

A0 = V_IL, A1 = V_IH, A2 = V_IL, A3 = V_IL,

A6 = V_IL, A9 = V_ID,

Pass = xx01h

Retry = xx00h.

Block (Group)

Protect Verify

V_IL

V_IH

A12-A21 Block address

Others = X

A0 = V_IL, A1 = V_IH, A2 = V_IL, A3 = V_IL,

A6 = V_IH, A9 = V_ID,

Pass = xx00h

Block (Group)

Unprotect Verify

V_IL

V_IH

A12-A21 Block address

Retry = xx01h.

Others = X

1. Block Protection Groups are shown in Appendix D, Table 24.

68/74

M29DW640F

Block protection

Figure 20. Programmer Equipment Group Protect flowchart

START

ADDRESS =

GROUP ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V , A1 = V

A0, A2, A3, A6 = V

IH

IL

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

NO

++n

= 25

DATA = 01h

YES

A9 = V

IH

A9 = V

E, G = V

IH

E, G = V

IH

PASS

FAIL

AI07756

1. Block Protection Groups are shown in Appendix D, Table 24.

69/74

Block protection

M29DW640F

Figure 21. Programmer Equipment Chip Unprotect flowchart

START

PROTECT ALL

GROUPS

n = 0

CURRENT GROUP = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT

GROUP ADDRESS

A0, A2, A3 = V

A1, A6 = V

IH

IL

E = V

IL

Wait 4µs

INCREMENT

CURRENT GROUP

G = V

IL

Wait 60ns

Read DATA

NO

YES

DATA = 00h

NO

++n

= 1000

LAST

GROUP

NO

YES

A9 = V

IH

E, G = V

IH

E, G = V

IH

FAIL

PASS

AI07757

1. Block Protection Groups are shown in Appendix D, Table 24.

70/74

M29DW640F

Block protection

Figure 22. In-System Equipment Group Protect flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V A1 = V

IL,

IH

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V A1 = V

IL,

Wait 100µs

WRITE 40h

IH

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V A1 = V

IL,

IH

Wait 4µs

READ DATA

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V A1 = V

IL,

IH

NO

DATA = 01h

YES

NO

++n

RP = V

IH

= 25

YES

RP = V

ISSUE READ/RESET

COMMAND

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI07758

1. Block Protection Groups are shown in Appendix D, Table 24.

2. RP can be either at V or at V when using the In-System Technique to protect the Extended Block.

IH

ID

71/74

Block protection

M29DW640F

Figure 23. In-System Equipment Chip Unprotect flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3, A6 = V A1 = V

IL,

IH

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3 = V A1, A6 = V

IL,

IH

Wait 10ms

WRITE 40h

ADDRESS =

CURRENT GROUP ADDRESS

A0, A2, A3 = V A1, A6 = V

IL,

IH

Wait 4µs

INCREMENT

CURRENT GROUP

READ DATA

ADDRESS =

CURRENT GROUP ADDRESS

A0, A2, A3 = V A1, A6 = V

IL,

IH

NO

YES

DATA = 00h

NO

++n

LAST

NO

= 1000

GROUP

YES

RP = V

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

FAIL

PASS

AI07759

1. Block Protection Groups are shown in Appendix D, Table 24.

72/74

M29DW640F

Revision history

Table 33. Document revision history

Date

Revision

Changes

02-Dec-2005

1.0

First issue.

DQ7 changed to DQ7 for Program, Program During Erase

Suspend and Program Error in Table 9: Status Register Bits.

10-Mar-2006

2.0

Converted to new template.

Updated address values in Table 31: Extended Block address and

data.

23-Aug-2006

10-Dec-2007

3

4

Amended data in Table 28: Device Geometry Definition

Applied Numonyx branding.

73/74

M29DW640F

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

74/74


型号：	M29DW640F90ZE6
厂家：	NUMONYX B.V
描述：	64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory 64兆位（8MB X8或X16 4Mb的，多行，页，引导块） 3V供应闪存闪存
文件：	总74页 (文件大小：1481K)
中文：	中文翻译
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M29DW640F90ZE6 [NUMONYX]

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