M29F200BB50MT3 [NUMONYX]
Flash, 128KX16, 50ns, PDSO44, 0.500 INCH, PLASTIC, SO-44;型号: | M29F200BB50MT3 |
厂家: | NUMONYX B.V |
描述: | Flash, 128KX16, 50ns, PDSO44, 0.500 INCH, PLASTIC, SO-44 光电二极管 |
文件: | 总29页 (文件大小:583K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M29F200BT
M29F200BB
2 Mbit (256Kb x8 or 128Kb x16, Boot Block)
Single Supply Flash Memory
FEATURES SUMMARY
■
SINGLE 5V±10% SUPPLY VOLTAGE for
Figure 1. Packages
PROGRAM, ERASE and READ
OPERATIONS
■
■
ACCESS TIME: 45, 50, 70, 90ns
PROGRAMMING TIME
–
8µs per Byte/Word typical
■ 7 MEMORY BLOCKS
–
–
1 Boot Block (Top or Bottom Location)
2 Parameter and 4 Main Blocks
TSOP48 (N)
12 x 20mm
■ PROGRAM/ERASE CONTROLLER
–
–
Embedded Byte/Word Program algorithm
Embedded Multi-Block/Chip Erase
algorithm
–
–
Status Register Polling and Toggle Bits
Ready/Busy Output Pin
44
■ ERASE SUSPEND and RESUME MODES
–
Read and Program another Block during
Erase Suspend
1
■ UNLOCK BYPASS PROGRAM COMMAND
Faster Production/Batch Programming
SO44 (MT)
–
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
–
Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
–
Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
–
–
–
Manufacturer Code: 0020h
Top Device Code M29F200BT: 00D3h
Bottom Device CodeM29F200BB: 00D4h
■
ECOPACK® PACKAGES AVAILABLE
September 2005
1/29
M29F200BT, M29F200BB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/29
M29F200BT, M29F200BB
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute Maximum Ratings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Capacitance (TA = 25 °C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C). . . . . . . . . . . . . . . . . 19
Table 12. Read AC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C). . . . . . . . . . . . 20
Figure 9. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)21
Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)22
Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)23
Figure 12.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 24
Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 24
Figure 14.SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . 25
Table 17. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/29
M29F200BT, M29F200BB
Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Top Boot Block Addresses, M29F200BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. Bottom Boot Block Addresses, M29F200BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4/29
M29F200BT, M29F200BB
SUMMARY DESCRIPTION
The M29F200B is a 2 Mbit (256Kb x8 or 128Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
M29F200B is fully backward compatible with the
M29F200.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Table 1. Signal Names
A0-A16
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
RB
BYTE
V
CC
V
Ground
SS
The blocks in the memory are asymmetrically ar-
ranged, see Tables 19 and 20, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
NC
Not Connected Internally
Figure 2. Logic Diagram
V
CC
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
17
15
A0-A16
DQ0-DQ14
W
E
DQ15A–1
BYTE
RB
M29F200BT
M29F200BB
In order to meet environmental requirements, ST
offers the M29F200B in ECOPACK® packages.
G
RP
ECOPACK packages are Lead-free. The category
of second Level Interconnect is marked on the
package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum rat-
ings related to soldering conditions are also
marked on the inner box label.
V
SS
AI02912
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
5/29
M29F200BT, M29F200BB
Figure 3. SO Connections
Figure 4. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
BYTE
2
W
V
SS
3
A8
DQ15A–1
4
A9
DQ7
5
A10
A11
A12
A13
A14
A15
A16
BYTE
DQ14
DQ6
6
7
A8
DQ13
DQ5
8
NC
NC
W
9
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
21
22
M29F200BT
M29F200BB
RP
NC
NC
RB
NC
NC
A7
12
13
37
36
V
M29F200BT
M29F200BB
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
V
SS
DQ15A–1
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
A6
DQ2
A5
DQ10
DQ3
DQ12
DQ4
A4
A3
V
E
SS
DQ11
V
CC
A2
AI02914
A1
24
25
A0
AI02913
6/29
M29F200BT, M29F200BB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
High, VIH, the memory will be ready for Bus Read
and Bus Write operations after tPHEL or tRHEL
,
whichever occurs last. See the Ready/Busy Out-
put section, Table 15., Reset/Block Temporary
Unprotect AC Characteristics (TA = 0 to 70 °C, –
40 to 85 °C or –40 to 125 °C) and Figure
12., Reset/Block Temporary Unprotect AC Wave-
forms, for more details.
Address Inputs (A0-A16). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
tPHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15., Reset/
Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
and Figure 12., Reset/Block Temporary Unprotect
AC Waveforms.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-
1). When BYTE is High, VIH, this pin behaves as
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, VIL, the memory is in 8-bit mode, when
it is High, VIH, the memory is in 16-bit mode.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block temporary unprotect goes
7/29
M29F200BT, M29F200BB
supply. The PCB track widths must be sufficient to
carry the currents required during program and
Vss Ground. The VSS Ground is the reference
for all voltage measurements.
erase operations, ICC4
.
8/29
M29F200BT, M29F200BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
When Chip Enable is at VIH the Supply Current is
reduced to the TTL Standby Supply Current, ICC2
.
To further reduce the Supply Current to the CMOS
Standby Supply Current, ICC3, Chip Enable should
be held within VCC ± 0.2V. For Standby current
levels see Table 11., DC Characteristics (TA = 0 to
70°C, –40 to 85°C or –40 to 125°C).
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC4, for Program or Erase operations un-
til the operation completes.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 9., Read Mode AC Waveforms,
and Table 12., Read AC Characteristics (TA = 0 to
70°C, –40 to 85°C or –40 to 125°C), for details of
when the output becomes valid.
Automatic Standby. If CMOS levels (VCC
±
0.2V) are used to drive the bus and the bus is in-
active for 150ns or more the memory enters Auto-
matic Standby where the internal Supply Current
is reduced to the CMOS Standby Supply Current,
I
CC3. The Data Inputs/Outputs will still output data
if a Bus Read operation is in progress.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
9/29
M29F200BT, M29F200BB
Table 2. Bus Operations, BYTE = VIL
Data Inputs/Outputs
Address Inputs
DQ15A–1, A0-A16
Operation
E
G
W
DQ14-DQ8
DQ7-DQ0
Data Output
Data Input
Hi-Z
V
IL
V
V
IH
Bus Read
Cell Address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
X
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
Hi-Z
Hi-Z
20h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
D3h (M29F200BT)
D4h (M29F200BB)
IH
IL
ID
V
V
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
Table 3. Bus Operations, BYTE = VIH
Address Inputs
A0-A16
Data Inputs/Outputs
Operation
Bus Read
E
G
W
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
V
IL
V
V
IH
Cell Address
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
X
IH
V
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
0020h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
00D3h (M29F200BT)
00D4h (M29F200BB)
IH
IL
ID
V
V
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
IL
.
IH
10/29
M29F200BT, M29F200BB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6.. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take up to 10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH. The
Device Code for the M29F200BT is 00D3h and for
the M29F200BB is 00D4h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A16 specifying the address of
the block. The other address bits may be set to ei-
ther VIL or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
11/29
M29F200BT, M29F200BB
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 6.. All Bus Read opera-
tions during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6.. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being is-
sued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register. It
is also possible to enter the Auto Select mode: the
memory will behave as in the Auto Select mode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
12/29
M29F200BT, M29F200BB
Table 4. Commands, 16-bit mode, BYTE = VIH
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
2
2
6
X
F0
AA
AA
AA
AA
A0
90
Read/Reset
555
555
555
555
X
2AA
2AA
2AA
2AA
PA
55
55
55
55
PD
00
55
55
X
F0
90
A0
20
Auto Select
555
555
555
Program
PA
PD
Unlock Bypass
Unlock Bypass Program
Unlock Bypass Reset
Chip Erase
X
X
555
AA
AA
B0
30
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
1
1
X
X
13/29
M29F200BT, M29F200BB
Table 5. Commands, 8-bit mode, BYTE = VIL
Bus Write Operations
3rd 4th
1st
2nd
5th
6th
Command
Dat
a
Addr Data Addr Data Addr Data Addr
Addr Data Addr Data
1
3
3
X
F0
AA
AA
(4)
Read/Reset
AAA
AAA
555
555
555
555
PA
55
55
55
55
PD
00
55
55
X
F0
90
A0
20
(5)
AAA
AAA
AAA
Auto Select
(6)
4
3
2
2
6
AAA
AAA
X
AA
AA
A0
90
PA
PD
Program
(7)
Unlock Bypass
(6)
Unlock Bypass Program
(8)
X
X
Unlock Bypass Reset
(6)
AAA
AA
AA
B0
30
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
BA
10
30
Chip Erase
(6)
6+ AAA
Block Erase
(9)
1
1
X
X
Erase Suspend
(10)
Erase Resume
Note: 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
2. All values in the table are in hexadecimal.
3. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
4. After a Read/Reset command, read the memory as normal until another command is issued.
5. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
6. After a Program, Unlock Bypass Program, Chip Erase, or Block Erase command, read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until the Timeout Bit is set.
7. After the Unlock Bypass command, issue Unlock Bypass Program or Unlock Bypass Reset commands.
8. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
9. After the Erase Suspend command, read non-erasing memory blocks as normal, issue Auto Select and Program commands on
non-erasing blocks as normal.
10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/Erase Con-
troller completes and the memory returns to Read Mode.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
Typical after
(1)
Parameter
Min
Max
Unit
Typ
(1)
100k W/E Cycles
Chip Erase (All bits in the memory set to ‘0’)
Chip Erase
0.8
0.8
2.5
0.6
8
s
2.5
0.6
8
10
4
s
Block Erase (64 Kbytes)
s
Program (Byte or Word)
150
9
µs
Chip Program (Byte by Byte)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
2.3
1.2
2.3
1.2
s
s
4.5
100,000
cycles
Note: T = 25°C, V = 5V.
A
CC
14/29
M29F200BT, M29F200BB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7., Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 5., Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ‘1’. In both cases, a succes-
sive Bus Read operation will show the bit is still ’0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 6., Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
15/29
M29F200BT, M29F200BB
Table 7. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: Unspecified data bits should be ignored.
Figure 5. Data Polling Flowchart
Figure 6. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
YES
DQ6
NO
TOGGLE
DATA
=
NO
FAIL
YES
FAIL
PASS
PASS
AI03598
AI01370B
16/29
M29F200BT, M29F200BB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
°C
Ambient Operating Temperature (Temperature Range Option 1)
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
Temperature Under Bias
0 to 70
T
A
–40 to 85
–40 to 125
–50 to 125
–65 to 150
°C
°C
T
°C
BIAS
T
Storage Temperature
°C
STG
(2)
Input or Output Voltage
Supply Voltage
–0.6 to 6
–0.6 to 6
V
V
V
V
IO
V
CC
V
Identification Voltage
–0.6 to 13.5
ID
Note: 1. Except for the Operating Temperature Range, stresses above those listed in the Table 8., Absolute Maximum Ratings (1) may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
17/29
M29F200BT, M29F200BB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Parameter
M29F200B
45 / 50
High Speed
30pF
70 / 90
Standard
100pF
AC Test Conditions
Load Capacitance (C )
L
Input Rise and Fall Times
≤10ns
≤10ns
Input Pulse Voltages
0 to 3V
1.5V
0.45 to 2.4V
0.8V and 2.0V
Input and Output Timing Ref. Voltages
Table 10. Capacitance (TA = 25 °C, f = 1 MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
pF
C
V
IN
= 0V
= 0V
6
IN
C
V
OUT
12
pF
OUT
Note: Sampled only, not 100% tested.
Figure 7. AC Testing Input Output Waveform
Figure 8. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
L
Standard
C
2.4V
2.0V
0.8V
0.45V
AI01275B
C
includes JIG capacitance
AI03027
L
18/29
M29F200BT, M29F200BB
Table 11. DC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
(2)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
Typ
I
LI
0V ≤V ≤V
IN
CC
I
0V ≤V ≤V
OUT CC
±1
µA
LO
E = V , G = V ,
IL
IH
I
Supply Current (Read)
6
20
1
mA
mA
µA
CC1
f = 6MHz
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC2
IH
E = V ±0.2V,
CC
I
30
100
CC3
RP = V ±0.2V
CC
Program/Erase
Controller active
(1)
Supply Current (Program/Erase)
20
mA
I
CC4
V
Input Low Voltage
–0.5
2
0.8
V
V
IL
V
V
V
+0.5
Input High Voltage
IH
CC
I
= 5.8mA
= –2.5mA
= –100µA
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
Identification Voltage
Identification Current
0.45
V
OL
OL
I
I
2.4
V
OH
V
OH
V
–0.4
V
CC
OH
V
11.5
12.5
100
V
ID
I
ID
A9 = V
µA
ID
Program/Erase Lockout Supply
Voltage
(1)
3.2
4.2
V
V
LKO
Note: 1. Sampled only, not 100% tested.
2. T = 25°C, V = 5V.
A
CC
19/29
M29F200BT, M29F200BB
Table 12. Read AC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F200B
50
Symbol
Alt
Parameter
Test Condition
Unit
45
70 / 90
E = V ,
Address Valid to Next Address
Valid
IL
t
t
Min
45
50
50
70
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
Max
45
70
AVQV
G = V
G = V
G = V
E = V
IL
Chip Enable Low to Output
Transition
(1)
t
Min
Max
Min
0
45
0
0
50
0
0
70
0
ns
ns
ns
t
t
LZ
IL
ELQX
t
Chip Enable Low to Output Valid
t
CE
IL
ELQV
Output Enable Low to Output
Transition
(1)
t
OLZ
IL
IL
GLQX
t
t
E = V
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Max
Max
25
15
30
18
30
20
ns
ns
GLQV
OE
(1)
(1)
t
G = V
t
t
HZ
IL
IL
EHQZ
t
E = V
Output Enable High to Output Hi-Z
Max
Min
15
0
18
0
20
0
ns
ns
DF
GHQZ
t
Chip Enable, Output Enable or
Address Transition to Output
Transition
EHQX
t
t
GHQX
OH
t
AXQX
t
t
ELBL
ELFL
Chip Enable to BYTE Low or High
Max
5
5
5
ns
t
t
t
t
ELBH
ELFH
t
BYTE Low to Output Hi-Z
BYTE High to Output Valid
Max
Max
15
30
15
30
20
30
ns
ns
BLQZ
FLQZ
t
BHQV
FHQV
Note: 1. Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms
tAVAV
VALID
A0-A16/
A–1
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI02915
20/29
M29F200BT, M29F200BB
Table 13. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Unit
Symbol
Alt
Parameter
45
45
0
50
50
0
70 / 90
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
ELWL
t
t
40
25
0
40
25
0
45
30
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
WHDX
t
0
0
0
WHEH
t
t
WPH
20
0
20
0
20
0
WHWL
t
t
AS
AVWL
t
t
40
0
40
0
45
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
0
WHGL
(1)
t
Program/Erase Valid to RB Low
Max
Min
30
50
30
50
30
50
ns
µs
t
BUSY
WHRL
t
t
V
CC
High to Chip Enable Low
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 10. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A16/
VALID
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01991
21/29
M29F200BT, M29F200BB
Table 14. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Symbol
Alt
Parameter
Unit
45
45
0
50
50
0
70 / 90
t
t
WC
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
WS
WLEL
t
t
40
25
0
40
25
0
45
30
0
ELEH
CP
DS
DH
t
t
t
DVEH
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
t
t
WH
0
0
0
EHWH
t
t
20
0
20
0
20
0
EHEL
CPH
t
t
AS
AVEL
t
t
40
0
40
0
45
0
ELAX
AH
t
GHEL
t
t
0
0
0
EHGL
OEH
(1)
t
Program/Erase Valid to RB Low
Max
Min
30
50
30
50
30
50
ns
µs
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 11. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A16/
VALID
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01992
22/29
M29F200BT, M29F200BB
Table 15. Reset/Block Temporary Unprotect AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M29F200B
Unit
Symbol
Alt
Parameter
45
50
70 / 90
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
t
t
Min
Min
50
50
50
ns
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
t
0
0
0
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
Max
Min
500
10
500
10
500
10
ns
µs
ns
PLPX
RP
(1)
t
RP Low to Read Mode
t
READY
PLYH
(1)
t
RP Rise Time to V
500
500
500
t
VIDR
ID
PHPHH
Note: 1. Sampled only, not 100% tested.
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI02931
23/29
M29F200BT, M29F200BB
PACKAGE MECHANICAL
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
Note: Drawing is not to scale.
Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.100
12.100
20.200
18.500
–
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.0106
0.0083
0.0039
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0
5
0
5
24/29
M29F200BT, M29F200BB
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
D
44
23
c
E1 E
θ
1
22
A1
L
A2
A
L1
ddd
b
e
SO-F
Note: 1. Drawing is not to scale.
Table 17. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.00
0.118
0.10
2.69
0.004
0.106
2.56
0.35
2.79
0.50
0.28
28.63
0.10
16.28
12.73
–
0.101
0.014
0.007
1.117
0.110
0.020
0.011
1.127
0.004
0.641
0.501
–
c
0.18
D
28.50
28.37
1.122
ddd
E
16.03
12.60
1.27
15.77
12.47
–
0.631
0.496
0.050
0.031
0.068
0.621
0.491
–
E1
e
L
0.79
L1
Θ
1.73
8
8
N
44
44
25/29
M29F200BT, M29F200BB
PART NUMBERING
Table 18. Ordering Information Scheme
Example:
M29F200BB
50
N
1
T
Device Type
M29
Operating Voltage
F = V = 5V ± 10%
CC
Device Function
200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45 ns
(1)
50 = 50 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
MT = SO44 500mm width
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Note: 1. 50ns speed devices are only available in M29F200BB in Temperature Range option 3.
The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts,
otherwise devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
26/29
M29F200BT, M29F200BB
APPENDIX A. BLOCK ADDRESSES
Table 19. Top Boot Block Addresses,
M29F200BT
Table 20. Bottom Boot Block Addresses,
M29F200BB
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
#
6
5
4
3
2
1
0
16
8
3C000h-3FFFFh
3A000h-3BFFFh
38000h-39FFFh
30000h-37FFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
1E000h-1FFFFh
1D000h-1DFFFh
1C000h-1CFFFh
18000h-1BFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
6
5
4
3
2
1
0
64
64
64
32
8
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
8
32
64
64
64
8
16
27/29
M29F200BT, M29F200BB
REVISION HISTORY
Table 21. Document Revision History
Date
Version
Revision Details
July 1999
1.0
First Issue
Chip Erase Max. specification added (Table 6)
Block Erase Max. specification added (Table 6)
Program Max. specification added (Table 6)
Chip Program Max. specification added (Table 6)
10/08/99
07/28/00
2.0
3.0
4.0
I
and I
Typ. specification added (Table 11)
CC1
CC3
I
Test Condition changed (Table 11)
CC3
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 5.)
Data Toggle Flowchart diagram change (Figure 6.)
Document restructured.
Table 18., Ordering Information Scheme: standard package added and ECOPACK version
added for both standard package and Tape & Reel packing. Note: 1. modified.
55ns speed class replaced by 50ns.
19-Sep-2005
TSOP48 mechanical data updated, and SO44 525mm body width changed to SO44
500mm body width.
28/29
M29F200BT, M29F200BB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
29/29
相关型号:
©2020 ICPDF网 联系我们和版权申明