M29F400BT45MT3T [NUMONYX]
Flash, 256KX16, 45ns, PDSO44, 0.500 INCH, PLASTIC, SOP-44;
| 型号： | M29F400BT45MT3T |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 256KX16, 45ns, PDSO44, 0.500 INCH, PLASTIC, SOP-44 光电二极管 |
| 文件： | 总40页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29F400BT
M29F400BB
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
single supply Flash memory
Feature summary
■ Single 5V±10% supply voltage for program,
erase and read operations
■ Access time: 45ns
■ Programming time
– 8µs per Byte/Word typical
TSOP48 (N)
12 x 20mm
■ 11 memory blocks
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 8 Main Blocks
■ Program/erase controller
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase
algorithm
44
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
1
■ Erase Suspend and Resume modes
SO44 (MT)
– Read and Program another Block during
Erase Suspend
■ Unlock Bypass Program command
■ Electronic signature
– Faster Production/Batch Programming
– Manufacturer Code: 0020h
■ Temporary block unprotection mode
– Top Device Code M29F400BT: 00D5h
– Bottom Device Code M29F400BB: 00D6h
■ Low power consumption
– Standby and Automatic Standby
®
■ ECOPACK packages available
■ 100,000 program/erase cycles per block
■ 20-year data retention
– Defectivity below 1 ppm/year
July 2006
Rev 3
1/40
www.st.com
1
Contents
M29F400BT, M29F400BB
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data input/output or address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Byte/Word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.12
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1
3.6.2
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 14
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
4.4
4.5
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/40
M29F400BT, M29F400BB
Contents
4.6
4.7
4.8
4.9
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11 Read/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12 Auto Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Program, Unlock Bypass Program, Chip Erase, Block Erase . . . . . . . . . 20
4.14 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.15 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.17 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
5.2
5.3
5.4
5.5
Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 27
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
8
9
10
Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
List of tables
M29F400BT, M29F400BB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus operations, BYTE = V
Bus operations, BYTE = V
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Commands, 16-bit mode, BYTE = V
Commands, 8-bit mode, BYTE = V
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program/ Erase times endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data. . . . 35
SO44 - 44 lead Plastic Small Outline, 500 mils body width, package mechanical data . . . 36
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Top boot block addresses, M29F400BT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Bottom boot block addresses, M29F400BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4/40
M29F400BT, M29F400BB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC testing input output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 35
Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package outline. . . . . . . . . . . 36
5/40
Summary description
M29F400BT, M29F400BB
1
Summary description
The M29F400B is a 4 Mbit (512Kb x8 or 256Kb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single 5V supply.
On power-up the memory defaults to its Read mode where it can be read in the same way
as a ROM or EPROM. The M29F400B is fully backward compatible with the M29F400.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Tables Table 19. and Table 20.,
Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks.
The 16 Kbyte Boot Block can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and
the remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with
all the bits erased (set to ’1’).
®
In order to meet environmental requirements, ST offers the M29F400B in ECOPACK
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6/40
M29F400BT, M29F400BB
Summary description
Figure 1.
Logic diagram
V
CC
18
15
A0-A17
DQ0-DQ14
W
E
DQ15A–1
BYTE
RB
M29F400BT
M29F400BB
G
RP
V
SS
AI02904
Table 1.
Signal names
Address Inputs
A0-A17
DQ0-DQ7
Data Inputs/Outputs
Data Inputs/Outputs
DQ8-DQ14
DQ15A–1
E
Data Input/Output or Address Input
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
RB
BYTE
VCC
VSS
NC
Ground
Not Connected Internally
7/40
Summary description
Figure 2.
M29F400BT, M29F400BB
TSOP connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
A8
DQ13
DQ5
NC
NC
W
DQ12
DQ4
RP
NC
NC
RB
NC
A17
A7
12
13
37
36
V
M29F400BT
M29F400BB
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A6
A5
A4
A3
V
E
SS
A2
A1
24
25
A0
AI02905
8/40
M29F400BT, M29F400BB
Summary description
Figure 3.
SO connections
NC
RB
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
2
W
3
A8
4
A9
5
A10
A11
A12
A13
A14
A15
A16
BYTE
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M29F400BT
M29F400BB
V
V
SS
DQ15A–1
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
DQ11
V
CC
AI02906
9/40
Signal descriptions
M29F400BT, M29F400BB
2
Signal descriptions
See Figure Figure 1., Logic Diagram, and Table Table 1., Signal Names, for a brief overview
of the signals connected to this device.
2.1
2.2
2.3
Address inputs (A0-A17)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
Data inputs/outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the Command
Interface of the internal state machine.
Data inputs/outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, V . When BYTE is Low, V , these pins are not used and are
IH
IL
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
2.4
Data input/output or address input (DQ15A-1)
When BYTE is High, V , this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
IH
When BYTE is Low, V , this pin behaves as an address pin; DQ15A–1 Low will select the
IL
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
2.5
2.6
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V , all other pins are ignored.
IH
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
10/40
M29F400BT, M29F400BB
Signal descriptions
2.7
2.8
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V , for at
IL
least t
. After Reset/Block Temporary Unprotect goes High, V , the memory will be
PLPX
IH
ready for Bus Read and Bus Write operations after t
or t
, whichever occurs last.
RHEL
PHEL
See the Ready/Busy Output section, Table Table 15. and Figure Figure 11.,
Reset/Temporary Unprotect AC Characteristics for more details.
Holding RP at V will temporarily unprotect the protected Blocks in the memory. Program
ID
and Erase operations on all blocks will be possible. The transition from V to V must be
IH
ID
slower than t
.
PHPHH
2.9
Ready/Busy output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the memory
array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table Table 15. and Figure Figure 11., Reset/Temporary
Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy is Low, V . Ready/Busy will remain Low
OL
during Read/Reset commands or Hardware Resets until the memory is ready to enter Read
mode.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.10
Byte/Word organization select (BYTE)
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Select is Low, V , the memory is in 8-
IL
bit mode, when it is High, V , the memory is in 16-bit mode.
IH
11/40
Signal descriptions
M29F400BT, M29F400BB
2.11
VCC supply voltage
The V Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
CC
The Command Interface is disabled when the V Supply Voltage is less than the Lockout
CC
Voltage, V
. This prevents Bus Write operations from accidentally damaging the data
LKO
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the V Supply Voltage pin and the V
CC
SS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, I
.
CC4
2.12
VSS ground
The V Ground is the reference for all voltage measurements.
SS
12/40
M29F400BT, M29F400BB
Bus operations
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Tables Table 2. and Table 3.,
Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write
IL
Enable High, V . The Data Inputs/Outputs will output the value, see Figure Figure 8., Read
IH
Mode AC Waveforms, and Table Table 12., Read AC Characteristics, for details of when the
output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V ,
IH
during the whole Bus Write operation. See Figures Figure 9. and Figure 10., Write AC
Waveforms, and Tables Table 13. and Table 14., Write AC Characteristics, for details of the
timing requirements.
3.3
3.4
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V .
IH
Standby
When Chip Enable is High, V , the Data Inputs/Outputs pins are placed in the high-
IH
impedance state and the Supply Current is reduced to the Standby level.
When Chip Enable is at V the Supply Current is reduced to the TTL Standby Supply
IH
Current, I
. To further reduce the Supply Current to the CMOS Standby Supply Current,
CC2
I
, Chip Enable should be held within V ± 0.2V. For Standby current levels see Table
CC3
CC
Table 11., DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
, for Program or Erase operations until the operation completes.
CC4
13/40
Bus operations
M29F400BT, M29F400BB
3.5
Automatic Standby
If CMOS levels (V ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
CC
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the CMOS Standby Supply Current, I
Bus Read operation is in progress.
. The Data Inputs/Outputs will still output data if a
CC3
3.6
Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V to be
ID
applied to some pins.
3.6.1
3.6.2
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Tables
Table 2. and Table 3., Bus Operations.
Block Protection and Blocks Unprotection
Each block can be separately protected against accidental Program or Erase. Protected
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. For further information refer to
Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
(1)
Table 2.
Bus operations, BYTE = V
IL
Data Inputs/Outputs
Address Inputs
Operation
E
G
W
DQ15A–1, A0-A17
DQ14-DQ8
DQ7-DQ0
Bus Read
Bus Write
Output Disable
Standby
VIL
VIL
X
VIL
VIH
VIH Cell Address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Output
Data Input
Hi-Z
VIL Command Address
VIH VIH
X
X
VIH
X
X
Hi-Z
Read Manufacturer
Code
A0 = VIL, A1 = VIL, A9
= VID, Others VIL or VIH
VIL
VIL
VIL
VIH
Hi-Z
Hi-Z
20h
A0 = VIH, A1 = VIL, A9
= VID, Others VIL or VIH
D5h (M29F400BT)
D6h (M29F400BB)
Read Device Code
VIL
VIH
1. X = VIL or VIH
.
14/40
M29F400BT, M29F400BB
Table 3.
Bus operations
(1)
Bus operations, BYTE = V
IH
Address Inputs
A0-A17
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
Bus Read
VIL
VIL
X
VIL
VIH
VIH
X
VIH Cell Address
Data Output
Data Input
Hi-Z
Bus Write
VIL Command Address
Output Disable
Standby
VIH
X
X
X
VIH
Hi-Z
Read Manufacturer
Code
A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or VIH
VIL
VIL
VIL
VIL
VIH
VIH
0020h
A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
00D5h (M29F400BT)
00D6h (M29F400BB)
Read Device Code
1. X = VIL or VIH
.
15/40
Command interface
M29F400BT, M29F400BB
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode. See either Table Table 4., or Table 5., depending on the configuration that
is being used, for a summary of the commands.
4.1
4.2
Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus
Write operations can be used to issue the Read/Reset command.
If the Read/Reset command is issued during a Block Erase operation or following a
Programming or Erase error then the memory will take upto 10µs to abort. During the abort
period no valid data can be read from the memory. Issuing a Read/Reset command during a
Block Erase operation will leave invalid data in the memory.
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits may be set to either V or V . The
IL
IL
IL
IH
Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = V and A1 = V . The
IH
IL
other address bits may be set to either V or V . The Device Code for the M29F400BT is
IL
IH
00D5h and for the M29F400BB is 00D6h.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= V , A1 = V , and A12-A17 specifying the address of the block. The other address bits
IL
IH
may be set to either V or V . If the addressed block is protected then 01h is output on
IL
IH
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
16/40
M29F400BT, M29F400BB
Command interface
4.3
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table Table 8.. Bus Read operations during the program operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more
details.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4
4.5
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.
See the Program command for details on the behavior.
4.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command.
17/40
Command interface
M29F400BT, M29F400BB
4.7
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table Table 8.. All
Bus Read operations during the Chip Erase operation will output the Status Register on the
Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.8
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register for details on how
to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend and Read/Reset commands. Typical block erase times are given in Table Table 8..
All Bus Read operations during the Block Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
18/40
M29F400BT, M29F400BB
Command interface
4.9
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command
being issued. Once the Program/Erase Controller has stopped the memory will be set to
Read mode and the Erase will be suspended. If the Erase Suspend command is issued
during the period when the memory is waiting for an additional block (before the
Program/Erase Controller starts) then the Erase is suspended immediately and will start
immediately when the Erase Resume Command is issued. It will not be possible to select
any further blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. Reading
from blocks that are being erased will output the Status Register. It is also possible to enter
the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until
a Read/Reset command returns the memory to Erase Suspend mode.
4.10
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.
Table 4.
Commands, 16-bit mode, BYTE = V
IH
Bus Write operations
3rd 4th
Command
1st
2nd
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
F0
1
3
3
4
3
X
Read/Reset
555 AA 2AA 55
555 AA 2AA 55
555 AA 2AA 55
555 AA 2AA 55
X
F0
90
Auto Select
Program
555
555 A0
PA
PD
Unlock Bypass
555
20
Unlock Bypass
Program
2
X
X
A0
90
PA
X
PD
00
Unlock Bypass
Reset
2
6
Chip Erase
555 AA 2AA 55
555
555
80
80
555 AA 2AA 55
555 AA 2AA 55
555
BA
10
30
Block Erase
6+ 555 AA 2AA 55
Erase Suspend
Erase Resume
1
1
X
X
B0
30
19/40
Command interface
Table 5.
M29F400BT, M29F400BB
(1) (2)
Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
3rd 4th
Command
1st
2nd
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
F0
1
3
3
4
3
X
Read/Reset
AAA AA
AAA AA
AAA AA
AAA AA
555
555
555
555
55
X
F0
Auto Select
Program
55 AAA 90
55 AAA A0
55 AAA 20
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
X
A0
90
PA
X
PD
00
Unlock Bypass
Reset
2
6
Chip Erase
AAA AA
555
555
55 AAA 80 AAA AA 555
55 AAA 80 AAA AA 555
55 AAA 10
55 BA 30
Block Erase
6+ AAA AA
Erase Suspend
Erase Resume
1
1
X
X
B0
30
1. X = Don’t Care, PA = Program Address, PD = Program Data, BA = Any address in the Block.
2. All values are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands;
A11-A17, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is V or
IL
DQ15 when BYTE is V .
IH
4.11
Read/Reset
After a Read/Reset command, read the memory as normal until another command is
issued.
4.12
4.13
Auto Select
After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase
After these commands read the Status Register until the Program/Erase Controller
completes and the memory returns to Read Mode. Add additional Blocks during Block
Erase Command with additional Bus Write Operations until Timeout Bit is set.
20/40
M29F400BT, M29F400BB
Command interface
4.14
4.15
4.16
4.17
Unlock Bypass
After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset
commands.
Unlock Bypass Reset
After the Unlock Bypass Reset command read the memory as normal until another
command is issued.
Erase Suspend
After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto
Select and Program commands on non-erasing blocks as normal.
Erase Resume
After the Erase Resume command the suspended Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to
Read Mode.
21/40
Status Register
M29F400BT, M29F400BB
5
Status Register
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.
The bits in the Status Register are summarized in Table Table 6., Status Register Bits.
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure Figure 4., Data Polling Flowchart, gives an example of how to use the Data Polling
Bit. A Valid Address is the address being programmed or an address within the block being
erased.
5.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure Figure 5., Data Toggle Flowchart, gives an example of how to use the Data Toggle
Bit.
22/40
M29F400BT, M29F400BB
Status Register
5.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to
do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will
show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block
or in the whole memory from ’0’ to ’1’.
5.4
5.5
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
Once the operation completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
23/40
Status Register
M29F400BT, M29F400BB
(1)
Table 6.
Status Register bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
Program During
Erase Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
1
0
0
0
0
0
–
1
0
0
1
1
–
0
0
0
0
0
0
0
0
0
0
0
Toggle
Erasing Block
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
No Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
No Toggle
No
Toggle
Erasing Block
1
0
–
Toggle
1
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
1
0
0
0
0
Toggle
Toggle
1
1
1
1
No Toggle
Toggle
1. Unspecified data bits should be ignored.
Figure 4.
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
= 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI03598
24/40
M29F400BT, M29F400BB
Figure 5.
Status Register
Data toggle flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ6
=
NO
TOGGLE
YES
NO
DQ5
= 1
YES
READ DQ6
TWICE
DQ6
=
NO
TOGGLE
YES
FAIL
PASS
AI01370B
25/40
Maximum rating
M29F400BT, M29F400BB
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 7.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Ambient Operating Temperature (Temperature Range
Option 1)
0 to 70
°C
Ambient Operating Temperature (Temperature Range
Option 6)
TA
–40 to 85
°C
°C
Ambient Operating Temperature (Temperature Range
Option 3)
–40 to 125
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
–50 to 125
–65 to 150
–0.6 to 6
°C
°C
V
(1)
VIO
VCC
VID
–0.6 to 6
V
Identification Voltage
–0.6 to 13.5
V
1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
26/40
M29F400BT, M29F400BB
Program and erase times and endurance cycles
7
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are
shown in Table 8. Exact erase times may change depending on the memory array condition.
(1)
Table 8.
Program/ Erase times endurance cycles
Typical after
Parameter
Min
Typ(2) 100k W/E Cycles Max Unit
(2)
Chip Erase (All bits in the memory set to ‘0’)
Chip Erase
1.5
5
1.5
5
s
20
4
s
Block Erase (64 Kbytes)
0.6
8
0.6
8
s
Program (Byte or Word)
150
18
9
µs
Chip Program (Byte by Byte)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
4.5
2.3
4.5
2.3
s
s
100,000
cycles
1.
TA = 0 to 70°C, –40 to 85°C or –40 to 125°C
2. TA = 25°C, VCC = 5V.
27/40
DC and AC parameters
M29F400BT, M29F400BB
8
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 9: AC measurement conditions. Designers should check that the operating conditions
in their circuit match the operating conditions when relying on the quoted parameters.
Table 9.
AC measurement conditions
Parameter
M29F400B
45 / 55
70 / 90
AC Test Conditions
High Speed
30pF
Standard
100pF
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
≤10ns
≤10ns
0 to 3V
1.5V
0.45 to 2.4V
0.8V and 2.0V
Input and Output Timing Ref. Voltages
Figure 6.
AC testing input output waveform
High Speed
3V
1.5V
0V
Standard
2.4V
2.0V
0.8V
0.45V
AI01275B
28/40
M29F400BT, M29F400BB
Figure 7.
DC and AC parameters
AC testing load circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
C
L
C
includes JIG capacitance
AI03027
L
(1) (2)
Table 10. Capacitance
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
6
pF
pF
COUT
VOUT = 0V
12
1. TA = 25 °C, f = 1 MHz
2. Sampled only, not 100% tested.
29/40
DC and AC parameters
M29F400BT, M29F400BB
(1)
Table 11. DC characteristics
Symbol
Parameter
Test Condition
Min
Typ(2)
Max
Unit
ILI
Input Leakage Current
Output Leakage Current
0V ≤VIN ≤VCC
±1
±1
µA
µA
ILO
0V ≤VOUT ≤VCC
E = VIL, G = VIH, f =
6MHz
ICC1
ICC2
ICC3
Supply Current (Read)
7
20
1
mA
mA
µA
Supply Current (Standby)
TTL
E = VIH
E = VCC ±0.2V,
RP = VCC ±0.2V
Supply Current (Standby)
CMOS
30
100
20
Supply Current
(Program/Erase)
Program/Erase
Controller active
(3)
ICC4
mA
VIL
VIH
VOL
Input Low Voltage
–0.5
2
0.8
VCC +0.5
0.45
V
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage TTL
IOL = 5.8mA
IOH = –2.5mA
2.4
VCC –0.4
11.5
VOH
Output High Voltage
CMOS
IOH = –100µA
A9 = VID
V
VID
IID
Identification Voltage
Identification Current
12.5
100
V
µA
Program/Erase Lockout
Supply Voltage
(3)
VLKO
3.2
4.2
V
1.
TA = 0 to 70°C, –40 to 85°C or –40 to 125°C
2. TA = 25 °C, VCC = 5V.
3. Sampled only, not 100% tested.
30/40
M29F400BT, M29F400BB
Figure 8.
DC and AC parameters
Read mode AC waveforms
tAVAV
VALID
A0-A17/
A–1
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGHQX
tGHQZ
tGLQV
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI02907
(1)
Table 12. Read AC characteristics
M29F400B
Test
Symbol Alt Parameter
Unit
Condition
45
55
70 / 90
Address Valid to Next Address
Valid
E = VIL,
G = VIL
tAVAV
tAVQV
tRC
Min
45
55
70
70
ns
ns
E = VIL,
G = VIL
tACC Address Valid to Output Valid
Max 45
55
Chip Enable Low to Output
Transition
(2)
tELQX
tLZ
G = VIL Min
G = VIL Max 45
E = VIL Min
0
0
55
0
0
70
0
ns
ns
ns
tELQV
tCE Chip Enable Low to Output Valid
Output Enable Low to Output
Transition
(2)
tGLQX
tOLZ
0
tGLQV
tOE Output Enable Low to Output Valid E = VIL Max 25
tHZ Chip Enable High to Output Hi-Z G = VIL Max 15
30
18
18
30
20
20
ns
ns
ns
(2)
tEHQZ
(2)
tGHQZ
tDF Output Enable High to Output Hi-Z E = VIL Max 15
tEHQX
tGHQX
tAXQX
Chip Enable, Output Enable or
tOH Address Transition to Output
Transition
Min
0
5
0
5
0
5
ns
ns
tELBL
tELBH
tELFL
Chip Enable to BYTE Low or High
tELFH
Max
tBLQZ
tFLQZ BYTE Low to Output Hi-Z
Max 15
Max 30
15
30
20
30
ns
ns
tBHQV tFHQV BYTE High to Output Valid
1. TA = 0 to 70°C, –40 to 85°C or –40 to 125°C
2. Sampled only, not 100% tested.
31/40
DC and AC parameters
Figure 9.
M29F400BT, M29F400BB
Write AC waveforms, Write Enable controlled
tAVAV
VALID
A0-A17/
A–1
tWLAX
tAVWL
tWHEH
tWHGL
E
tELWL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01869C
(1)
Table 13. Write AC characteristics, Write Enable controlled
M29F400B
Unit
Symbol
Alt
Parameter
45
55
70 / 90
tAVAV
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tWHGL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
45
0
55
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
40
25
0
40
25
0
45
30
0
tDS
tDH
tCH
Input Valid to Write Enable High
Write Enable High to Input Transition
Write Enable High to Chip Enable High
0
0
0
tWPH Write Enable High to Write Enable Low
20
0
20
0
20
0
tAS
tAH
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
40
0
40
0
45
0
tOEH Write Enable High to Output Enable Low
tBUSY Program/Erase Valid to RB Low
tVCS VCC High to Chip Enable Low
0
0
0
(2)
tWHRL
30
50
30
50
30
50
tVCHEL
1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C
2. Sampled only, not 100% tested.
32/40
M29F400BT, M29F400BB
DC and AC parameters
Figure 10. Write AC waveforms, Chip Enable controlled
tAVAV
VALID
A0-A17/
A–1
tELAX
tAVEL
tEHWH
tEHGL
W
G
E
tWLEL
tGHEL
tELEH
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01870C
(1)
Table 14. Write AC characteristics, Chip Enable controlled
M29F400B
Unit
Symbol
Alt
Parameter
45
55
70 / 90
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tELAX
tGHEL
tEHGL
tWC Address Valid to Next Address Valid
tWS Write Enable Low to Chip Enable Low
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
45
0
55
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tCP
tDS
tDH
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
40
25
0
40
25
0
45
30
0
Chip Enable High to Input Transition
tWH Chip Enable High to Write Enable High
tCPH Chip Enable High to Chip Enable Low
0
0
0
20
0
20
0
20
0
tAS
tAH
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
40
0
40
0
45
0
tOEH Chip Enable High to Output Enable Low
tBUSY Program/Erase Valid to RB Low
tVCS VCC High to Write Enable Low
0
0
0
(2)
tEHRL
30
50
30
50
30
50
tVCHWL
1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C
2. Sampled only, not 100% tested.
33/40
DC and AC parameters
M29F400BT, M29F400BB
Figure 11. Reset/Block Temporary Unprotect AC waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
RP
tRHWL, tRHEL, tRHGL
tPLPX
tPHPHH
tPLYH
AI02931
(1)
Table 15. Reset/Block Temporary Unprotect AC characteristics
M29F400B
55 70 / 90
Symbol
Alt
Parameter
Unit
ns
45
(2)
tPHWL
RP High to Write Enable Low, Chip
Enable Low, Output Enable Low
tPHEL
tRH
Min
Min
50
50
0
50
0
(2)
tPHGL
(2)
tRHWL
RB High to Write Enable Low, Chip
Enable Low, Output Enable Low
(2)
tRHEL
tRB
0
ns
(2)
tRHGL
tPLPX
tRP
RP Pulse Width
Min
Max
Min
500
10
500
10
500
10
ns
µs
ns
(2)
tPLYH
tREADY RP Low to Read Mode
tVIDR RP Rise Time to VID
(2)
tPHPHH
500
500
500
1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C
2. Sampled only, not 100% tested.
34/40
M29F400BT, M29F400BB
Package mechanical
9
Package mechanical
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.100
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0039
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0°
5°
0°
5°
35/40
Package mechanical
M29F400BT, M29F400BB
Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package
outline
D
44
23
c
E1 E
θ
1
22
A1
L
A2
A
L1
ddd
b
e
SO-F
1. Drawing is not to scale.
Table 17. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.00
0.118
0.10
2.69
0.004
0.106
2.56
0.35
2.79
0.50
0.28
28.63
0.10
16.28
12.73
–
0.101
0.014
0.007
1.117
0.110
0.020
0.011
1.127
0.004
0.641
0.501
–
c
0.18
D
28.50
28.37
1.122
ddd
E
16.03
12.60
1.27
15.77
12.47
–
0.631
0.496
0.050
0.031
0.068
0.621
0.491
–
E1
e
L
0.79
L1
Θ
1.73
8°
8°
N
44
44
36/40
M29F400BT, M29F400BB
Part numbering
10
Part numbering
Table 18. Ordering information scheme
Example:
M29F400BB
55 N 1
T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
400B = 4 Mbit (512Kb x8 or 256Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
MT = SO44
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Note:
The last two characters of the ordering code may be replaced by a letter code for
preprogrammed parts, otherwise devices are shipped from the factory with the memory
content bits erased to ‘1’.
For a list of available options (Speed, Package, etc...) or for further information on any
aspect of this device, please contact the ST Sales Office nearest to you.
37/40
Block address tables
M29F400BT, M29F400BB
Appendix A
Block address tables
Table 19. Top boot block addresses, M29F400BT
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
10
9
8
7
6
5
4
3
2
1
0
16
8
7C000h-7FFFFh
7A000h-7BFFFh
78000h-79FFFh
70000h-77FFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
3E000h-3FFFFh
3D000h-3DFFFh
3C000h-3CFFFh
38000h-3BFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
8
32
64
64
64
64
64
64
64
Table 20. Bottom boot block addresses, M29F400BB
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
10
9
8
7
6
5
4
3
2
1
0
64
64
64
64
64
64
64
32
8
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
8
16
38/40
M29F400BT, M29F400BB
Revision history
Revision history
Table 21. Document revision history
Date
Revision
Changes
July 1999
First Issue
Chip Erase Max. specification added (Table Table 8.)
Block Erase Max. specification added (Table Table 8.)
Program Max. specification added (Table Table 8.)
Chip Program Max. specification added (Table Table 8.)
ICC1 and ICC3 Typ. specification added (Table Table 11.)
09/21/99
10/04/99
07/28/00
I
CC3 Test Condition change (Table Table 11.)
New document template
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
1.1
Data Polling Flowchart diagram change (Figure Figure 4.)
Data Toggle Flowchart diagram change (Figure Figure 5.)
Table 18. Ordering Information Scheme: standard package added
and ECOPACK version added for both standard package and Tape &
Reel packing.
19-Sep-2005
20-Jul-2006
2.0
3
TSOP48 Mechanical Data updated. SO44 525mm width changed to
500mm width.
Document converted to new ST template. Small text changes.
Figure 12: TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm,
package outline updated.
39/40
M29F400BT, M29F400BB
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