M29W064FB70N3E [NUMONYX]
64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory; 64兆位（ 8兆比特×8或4兆位×16 ，网页，引导块） 3 V电源闪存
| 型号： | M29W064FB70N3E |
| 厂家： | 
NUMONYX B.V |
| 描述： | 64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory |
| 文件： | 总69页 (文件大小：1265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W064FT
M29W064FB
64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block)
3 V supply Flash memory
Preliminary Data
Features
■ Supply voltage
– V = 2.7 V to 3.6 V for program, erase,
CC
read
– V =12 V for fast program (optional)
PP
■ Asynchronous random/page read
– Page width: 4 words
– Page access: 25 ns
– Random access: 60, 70 ns
■ Programming time
TSOP48 (N)
12 x 20 mm
– 10 µs per byte/word typical
– 4 words/8 bytes program
■ 135 memory blocks
– 1 boot block and 7 parameter blocks,
8 Kbytes each (top or bottom location)
■ 100,000 program/erase cycles per block
■ Extended memory block
– 127 main blocks, 64 Kbytes each
■ Program/erase controller
– Extra block used as security block or to
store additional information
– Embedded byte/word program algorithms
■ Program/erase suspend and resume
■ Low power consumption
– Read from any block during program
suspend
– Standby and automatic standby
– Read and program another block during
erase suspend
■ Electronic signature
– Manufacturer code: 0020h
■ Unlock Bypass Program command
■ Automotive device grade 3
– Faster production/batch programming
– Temperature: -40 to 125 °C
■ V /WP pin for fast program and write protect
– Automotive grade certified (AEC-Q100)
PP
®
■ Temporary block unprotection mode
■ ECOPACK packages
■ Common Flash interface
– 64-bit security code
Table 1.
Device summary
Root part number
Device code
M29W064FT
M29W064FB
22EDh
22FDh
March 2008
Rev 2
1/69
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.numonyx.com
1
Contents
M29W064FT, M29W064FB
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data input/output or address input (DQ15A–1) . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP/write protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/block temporary unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 Ready/busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.11 Byte/word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.12
2.13
V
CC supply voltage (2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
3.5
3.6
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6.1
3.6.2
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block protect and chip unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1
4.1.2
4.1.3
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/69
M29W064FT, M29W064FB
Contents
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3
Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.1
4.3.2
4.3.3
Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 25
5
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
5.2
5.3
5.4
5.5
Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
7
8
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3/69
Contents
M29W064FT, M29W064FB
Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
C.1
C.2
Factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
D.1
D.2
Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4/69
M29W064FT, M29W064FB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4.
Bus operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IL
Table 5.
Bus operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IH
Table 6.
Table 7.
Commands, 16-bit mode, BYTE = V
Commands, 8-bit mode, BYTE = V
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 8.
Table 9.
Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 28
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset/block temporary unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data . . . . 43
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Top boot block addresses, M29W064FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bottom boot block addresses, M29W064FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Programmer technique bus operations, BYTE = V or V
IH
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5/69
List of figures
M29W064FT, M29W064FB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Write AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Reset/block temporary unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, top view package outline . . . . . 43
Figure 14. Programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 15. Programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 16. In-system equipment group protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17. In-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6/69
M29W064FT, M29W064FB
Description
1
Description
The M29W064F is a 64 Mbit (8 Mbit x 8 or 4 Mbit x 16) non-volatile memory that can be
read, erased and reprogrammed. These operations can be performed using a single low
voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its read mode.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Blocks can be protected in units of 256 Kbytes
(generally groups of four 64 Kbyte blocks), to prevent accidental program or erase
commands from modifying the memory. Program and erase commands are written to the
command interface of the memory. An on-chip program/erase controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
The device features an asymmetrical blocked architecture. The device has an array of 135
blocks:
●
8 parameters blocks of 8 Kbytes each (or 4 Kwords each)
127 main blocks of 64 Kbytes each (or 32 Kwords each)
●
M29W064FT has the parameter blocks at the top of the memory address space while the
M29W064FB locates the parameter blocks starting from the bottom.
The M29W064F has an extra block, the extended block, of 128 words in x 16 mode or of
256 bytes in x 8 mode that can be accessed using a dedicated command. The extended
block can be protected and so is useful for storing security information. However the
protection is not reversible, once protected the protection cannot be undone.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The V /WP signal is used to enable faster programming of the device, enabling multiple
PP
word/byte programming. If this signal is held at V , the boot block, and its adjacent
SS
parameter block, are protected from program and erase operations.
The device supports asynchronous random read and page read from all blocks of the
memory array.
The memories are offered in TSOP48 (12 x 20 mm) package.
7/69
Description
M29W064FT, M29W064FB
Figure 1.
Logic diagram
V
V
/WP
CC PP
22
15
A0-A21
DQ0-DQ14
W
E
DQ15A–1
BYTE
RB
M29W064FT
M29W064FB
G
RP
V
SS
AI11250b
Table 2.
Signal names
Name
Description
Direction
A0-A21
DQ0-DQ7
DQ8-DQ14
Address inputs
Inputs
I/O
Data inputs/outputs
Data inputs/outputs
I/O
DQ15A–1 (or DQ15) Data input/output or address input (or data input/output)
I/O
E
G
Chip Enable
Input
Input
Input
Input
Output
Input
Supply
Supply
–
Output Enable
W
Write Enable
RP
Reset/block temporary unprotect
Ready/busy output
RB
BYTE
VCC
VPP/WP
VSS
NC
Byte/word organization select
Supply voltage
Supply voltage for fast program (optional) or write protect
Ground
Not connected internally
–
8/69
M29W064FT, M29W064FB
Figure 2. TSOP connections
Description
A15
A14
A13
A12
A11
A10
A9
1
48
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A19
A20
W
DQ12
DQ4
M29W064FT
M29W064FB
RP
A21
/WP
RB
A18
A17
A7
12
13
37
36
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
PP
A6
A5
A4
A3
V
E
SS
A2
A1
24
25
A0
AI11251b
9/69
Signal descriptions
M29W064FT, M29W064FB
2
Signal descriptions
See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals
connected to this device.
2.1
2.2
2.3
Address inputs (A0-A21)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
Data inputs/outputs (DQ0-DQ7)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the program/erase controller.
Data inputs/outputs (DQ8-DQ14)
The data I/O outputs the data stored at the selected address during a bus read operation
when BYTE is High, V . When BYTE is Low, V , these pins are not used and are high
IH
IL
impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
2.4
Data input/output or address input (DQ15A–1)
When BYTE is High, V , this pin behaves as a data input/output pin (as DQ8-DQ14). When
IH
BYTE is Low, V , this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
IL
the addressed word, DQ15A–1 High will select the MSB. Throughout the text consider
references to the Data input/output to include this pin when BYTE is High and references to
the address inputs to include this pin when BYTE is Low except when stated explicitly
otherwise.
2.5
2.6
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing bus read and bus write operations to be
performed. When Chip Enable is High, V , all other pins are ignored.
IH
Output Enable (G)
The Output Enable, G, controls the bus read operation of the memory.
10/69
M29W064FT, M29W064FB
Signal descriptions
2.7
2.8
Write Enable (W)
The Write Enable, W, controls the bus write operation of the memory’s command interface.
VPP/write protect (VPP/WP)
The V /write protect pin provides two functions. The V function allows the memory to
PP
PP
use an external high voltage power supply to reduce the time required for unlock bypass
program operations. The write protect function provides a hardware method of protecting
the two outermost boot blocks. The V /write protect pin must not be left floating or
PP
unconnected.
When V /write protect is Low, V , the memory protects the two outermost boot blocks;
PP
IL
program and erase operations in this block are ignored while V /Write Protect is Low, even
PP
when RP is at V .
ID
When V /write protect is High, V , the memory reverts to the previous protection status of
PP
IH
the two outermost boot blocks. Program and erase operations can now modify the data in
the two outermost boot blocks unless the block is protected using block protection.
Applying V
to the V /WP pin will temporarily unprotect any block previously protected
PP
PPH
(including the two outermost parameter blocks) using a high voltage block protection
technique (in-system or programmer technique). See Table 3: Hardware protection for
details.
When V /write protect is raised to V the memory automatically enters the unlock bypass
PP
PP
mode. When V /write protect returns to V or V normal operation resumes. During
PP
IH
IL
unlock bypass program operations the memory draws I from the pin to supply the
PP
programming circuits. See the description of the Unlock Bypass command in Section 4:
Command interface. The transitions from V to V and from V to V must be slower
IH
PP
PP
IH
than t
, see Figure 12: Accelerated program timing waveforms.
VHVPP
Never raise V /Write Protect to V from any mode except read mode, otherwise the
PP
PP
memory may be left in an indeterminate state.
A 0.1 µF capacitor should be connected between the V /write protect pin and the V
PP
SS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during unlock bypass program, I .
PP
Table 3.
VPP/WP
Hardware protection
RP
Function
VIH
VID
VID
2 outermost parameter blocks protected from program/erase operations
All blocks temporarily unprotected except the 2 outermost blocks
All blocks temporarily unprotected
VIL
VIH or VID
VPPH
VIH or VID All blocks temporarily unprotected
11/69
Signal descriptions
M29W064FT, M29W064FB
2.9
Reset/block temporary unprotect (RP)
The reset/block temporary unprotect pin can be used to apply a hardware reset to the
memory or to temporarily unprotect all blocks that have been protected.
Note that if V /WP is at V , then the two outermost boot blocks will remain protected even
PP
IL
if RP is at V .
ID
A hardware reset is achieved by holding reset/block temporary unprotect Low, V , for at
IL
least t
. After reset/block temporary unprotect goes High, V , the memory will be ready
PLPX
IH
for bus read and bus write operations after t
or t
, whichever occurs last. See
PHEL
RHEL
Section 2.10: Ready/busy output (RB), Table 17: Reset/block temporary unprotect AC
characteristics and Figure 11: Reset/block temporary unprotect AC waveforms, for more
details.
Holding RP at V will temporarily unprotect the protected blocks in the memory. Program
ID
and erase operations on all blocks will be possible. The transition from V to V must be
IH
ID
slower than t
.
PHPHH
2.10
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, V . Ready/busy is high-impedance during read mode, Auto select mode and erase
OL
suspend mode.
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See Table 17: Reset/block temporary unprotect AC
characteristics and Figure 11: Reset/block temporary unprotect AC waveforms, for more
details.
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/word organization select (BYTE)
The byte/word organization select pin is used to switch between the x 8 and x 16 bus modes
of the memory. When byte/word organization select is Low, V , the memory is in x 8 mode,
IL
when it is High, V , the memory is in x 16 mode.
IH
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M29W064FT, M29W064FB
Signal descriptions
2.12
VCC supply voltage (2.7 V to 3.6 V)
V
provides the power supply for all operations (read, program and erase).
CC
The command interface is disabled when the V supply voltage is less than the lockout
CC
voltage, V
. This prevents bus write operations from accidentally damaging the data
LKO
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1 µF capacitor should be connected between the V supply voltage pin and the V
CC
SS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, I
.
CC3
2.13
VSS ground
V
is the reference for all voltage measurements. The device features two V pins which
SS
SS
must be both connected to the system ground.
13/69
Bus operations
M29W064FT, M29W064FB
3
Bus operations
There are five standard bus operations that control the device. These are bus read, bus
write, output disable, standby and automatic standby. See Table 4: Bus operations, BYTE =
V and Table 5: Bus operations, BYTE = V , for a summary. Typically glitches of less than
IL
IH
5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1
3.2
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. A valid bus read operation involves setting the desired address on the address
inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write
Enable High, V . The data inputs/outputs will output the value, see Figure 7: Read mode
AC waveforms, and Table 14: Read AC characteristics, for details of when the output
IL
IH
becomes valid.
Bus write
Bus write operations write to the command interface. To speed up the read operation the
memory array can be read in page mode where data is internally read and stored in a page
buffer. The page has a size of 4 words and is addressed by the address inputs A0-A1.
A valid bus write operation begins by setting the desired address on the address inputs. The
address inputs are latched by the command interface on the falling edge of Chip Enable or
Write Enable, whichever occurs last. The data inputs/outputs are latched by the command
interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output
Enable must remain High, V , during the whole bus write operation. See Figure 9: Write AC
IH
waveforms, write enable controlled, Figure 10: Write AC waveforms, chip enable controlled,
and Table 15: Write AC characteristics, write enable controlled and Table 16: Write AC
characteristics, chip enable controlled, for details of the timing requirements.
3.3
3.4
Output disable
The data inputs/outputs are in the high impedance state when Output Enable is High, V .
IH
Standby
When Chip Enable is High, V , the memory enters standby mode and the data
IH
inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to
the standby supply current, I
, Chip Enable should be held within V
0.2 V. For the
CC2
CC
standby current level see Table 13: DC characteristics.
During program or erase operations the memory will continue to use the program/erase
supply current, I , for program or erase operations until the operation completes.
CC3
14/69
M29W064FT, M29W064FB
Bus operations
3.5
Automatic standby
If CMOS levels (V
0.2 V) are used to drive the bus and the bus is inactive for 300 ns or
CC
more the memory enters automatic standby where the internal supply current is reduced to
the standby supply current, I
operation is in progress.
. The data inputs/outputs will still output data if a bus read
CC2
3.6
Special bus operations
Additional bus operations can be performed to read the electronic signature and also to
apply and remove block protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V to be
ID
applied to some pins.
3.6.1
3.6.2
Electronic signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 4:
Bus operations, BYTE = V and Table 5: Bus operations, BYTE = V .
IL
IH
Block protect and chip unprotect
Groups of blocks can be protected against accidental program or erase. The protection
groups are shown in Appendix A: Block addresses, Table 20 and Table 21. The whole chip
can be unprotected to allow the data inside the blocks to be changed.
The V /write protect pin can be used to protect the two outermost boot blocks. When
PP
V
/write protect is at V the two outermost boot blocks are protected and remain
PP
IL
protected regardless of the block protection status or the reset/block temporary unprotect
pin status.
Block protect and chip unprotect operations are described in Appendix D: Block protection.
15/69
Bus operations
M29W064FT, M29W064FB
Data inputs/outputs
(1)
Table 4.
Bus operations, BYTE = V
IL
Address inputs
DQ15A–1, A0-A21
Operation
E
G
W
DQ14-DQ8
DQ7-DQ0
Bus read
VIL VIL VIH Cell address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data output
Data input
Hi-Z
Bus write
VIL VIH VIL Command address
Output disable
Standby
X
VIH VIH
X
X
VIH
X
X
Hi-Z
A0-A3 = VIL, A6 = VIL,
A9 = VID, Others VIL or VIH
Read manufacturer code VIL VIL VIH
Hi-Z
Hi-Z
20h
A0 = VIH, A1-A3 = VIL,
VIL VIL VIH A6 = VIL, A9 = VID,
EDh (M29W064FT)
FDh (M29W064FB)
Read device code
Others VIL or VIH
A0 -A1 = VIH, A2-A3 = VIL,
VIL VIL VIH A6 = VIL, A9 = VID,
80h (factory locked)
Read extended memory
block verify code
Hi-Z
Hi-Z
00h (customer lockable)
Others VIL or VIH
A0, A2, A3, A6 = VIL,
A1 = VIH, A9 = VID,
A12-A21 = Block address,
Others VIL or VIH
01h (protected)
Read block protection
status
VIL VIL VIH
00h (unprotected)
1. X = VIL or VIH
.
(1)
Bus operations, BYTE = V
IH
Table 5.
Address inputs
A0-A21
Data inputs/outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
Bus read
VIL
VIL
X
VIL
VIH
VIH
X
VIH Cell address
VIL Command address
Data output
Data input
Hi-Z
Bus write
Output disable
Standby
VIH
X
X
X
VIH
Hi-Z
A0-A3 = VIL, A6 = VIL,
A9 = VID, others VIL or VIH
Read manufacturer code
Read device code
VIL
VIL
VIL
VIL
VIH
VIH
0020h
22EDh (M29W064FT)
22FDh (M29W064FB)
A0 = VIH, A1-A3= VIL, A6 = VIL,
A9 = VID, Others VIL or VIH
A0-A1 = VIH, A2-A3= VIL,
VIH A6 = VIL, A9 = VID,
others VIL or VIH
80h (factory locked)
Read extended memory
block verify code
VIL
VIL
00h (customer lockable)
A0, A2, A3, A6 = VIL, A1 = VIH,
A9 = VID,
0001h (protected)
Read block protection
status
VIL
VIL
VIH
A12-A21 = Block address,
0000h (unprotected)
others VIL or VIH
1. X = VIL or VIH
.
16/69
M29W064FT, M29W064FB
Command interface
4
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. Failure to observe a
valid sequence of bus write operations will result in the memory returning to read mode. The
long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode. See either Table 6, or Table 7, depending on the configuration that is being
used, for a summary of the commands.
4.1
Standard commands
4.1.1
Read/Reset command
The Read/Reset command returns the memory to its read mode. It also resets the errors in
the status register. Either one or three bus write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between bus write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a block erase operation then the memory will take up to 10 µs
to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an erase operation when issued while in erase
suspend.
4.1.2
Auto Select command
The Auto Select command is used to read the manufacturer code, the device code, the
block protection status and the extended memory block verify code. Three consecutive bus
write operations are required to issue the Auto Select command. Once the Auto Select
command is issued the memory remains in auto select mode until a Read/Reset command
is issued. Read CFI Query and Read/Reset commands are accepted in auto select mode,
all other commands are ignored.
In auto select mode, the manufacturer code and the device code can be read by using a bus
read operation with addresses and control signals set as shown in Table 4: Bus operations,
BYTE = V and Table 5: Bus operations, BYTE = V , except for A9 that is ‘don’t care’.
IL
IH
The block protection status of each block can be read using a bus read operation with
addresses and control signals set as shown in Table 4: Bus operations, BYTE = V and
IL
Table 5: Bus operations, BYTE = V , except for A9 that is ‘don’t care’. If the addressed
IH
block is protected then 01h is output on data inputs/outputs DQ0-DQ7, otherwise 00h is
output (in 8-bit mode).
The protection status of the extended memory block, or extended memory block verify
code, can be read using a bus read operation with addresses and control signals set as
shown in Table 4: Bus operations, BYTE = V and Table 5: Bus operations, BYTE = V ,
IL
IH
except for A9 that is ‘don’t care’. If the extended block is factory locked then 80h is output on
data input/outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).
17/69
Command interface
M29W064FT, M29W064FB
4.1.3
Read CFI Query command
The Read CFI Query command is used to read data from the common Flash interface (CFI)
memory area. This command is valid when the device is in the read array mode, or when the
device is in auto selected mode.
One bus write cycle is required to issue the Read CFI Query command. Once the command
is issued subsequent bus read operations read from the common Flash Interface memory
area.
The Read/Reset command must be issued to return the device to the previous mode (the
read array mode or autoselected mode). A second Read/Reset command would be needed
if the device is to be put in the read array mode from autoselected mode.
See Appendix B: Common Flash interface (CFI), Tables 22, 23, 24, 25, 26 and 27 for details
on the information contained in the common Flash interface (CFI) memory area.
4.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six bus write operations are
required to issue the Chip Erase command and start the program/erase controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the chip erase operation appears to start but will terminate within
about 100 µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 8: Program, erase times and program, erase endurance
cycles. All bus read operations during the chip erase operation will output the status register
on the data inputs/outputs. See the section on the status register for more details.
After the chip erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
18/69
M29W064FT, M29W064FB
Command interface
4.1.5
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six bus write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth bus write operation using the address of the additional
block. The block erase operation starts the program/erase controller about 50 µs after the
last bus write operation. Once the program/erase controller starts it is not possible to select
any more blocks. Each additional block must therefore be selected within 50 µs of the last
block. The 50 µs timer restarts when an additional block is selected. The status register can
be read after the sixth bus write operation. See the status register section for details on how
to identify if the program/erase controller has started the block erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the block erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the block erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 8: Program, erase times
and program, erase endurance cycles. All bus read operations during the block erase
operation will output the status register on the data inputs/outputs. See the section on the
status register for more details.
After the block erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Block Erase command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
4.1.6
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to read mode. The command requires one bus write
operation.
The program/erase controller will suspend within the erase suspend latency time of the
Erase Suspend command being issued. Once the program/erase controller has stopped the
memory will be set to read mode and the erase will be suspended. If the Erase Suspend
command is issued during the period when the memory is waiting for an additional block
(before the program/erase controller starts) then the erase is suspended immediately and
will start immediately when the Erase Resume command is issued. It is not possible to
select any further blocks to erase after the erase resume.
During erase suspend it is possible to read and program cells in blocks that are not being
erased; both read and program operations behave as normal on these blocks. If any attempt
is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The status register is not read and
no error condition is given. Reading from blocks that are being erased will output the status
register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an erase suspend. The Read/Reset command must be issued to return the device to
read array mode before the Resume command will be accepted.
19/69
Command interface
M29W064FT, M29W064FB
4.1.7
Erase Resume command
The Erase Resume command must be used to restart the program/erase controller after an
erase suspend. The device must be in read array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.
4.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the program suspend
latency time (see Table 8: Program, erase times and program, erase endurance cycles for
value) and updates the status register bits.
After the program operation has been suspended, the system can read array data from any
address. However, data read from program-suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in erase
suspend or program suspend. if a read is needed from the extended block area (one-time
program area), the user must use the proper command sequences to enter and exit this
region.
The system may also issue the Auto Select command sequence when the device is in the
program suspend mode. The system can read as many auto select codes as required.
When the device exits the auto select mode, the device reverts to the program suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
4.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See write operation status for more
information.
The system must write the Program Resume command, to exit the program suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
20/69
M29W064FT, M29W064FB
Command interface
4.1.10
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four bus write operations, the final write operation latches
the address and data, and starts the program/erase controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 4.1.8: Program
Suspend command and Section 4.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The status register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 8: Program, erase times and program, erase endurance cycles. Bus read operations
during the program operation will output the status register on the data inputs/outputs. See
the section on the status register for more details.
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs the memory will continue to output the status
register. A Read/Reset command must be issued to reset the error condition and return to
read mode.
Note that the Program command cannot change a bit set to ’0’ back to ’1’. One of the erase
commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
21/69
Command interface
M29W064FT, M29W064FB
4.2
Fast program commands
There are four fast program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple
Byte Program commands are available for x 8 operations, while the Double, Quadruple
Word Program commands are available for x 16 operations.
Fast program commands can be suspended and then resumed by issuing a Program
Suspend command and a Program Resume command, respectively (see Section 4.1.8:
Program Suspend command and Section 4.1.9: Program Resume command).
When V
is applied to the V /write protect pin the memory automatically enters the fast
PP
PPH
program mode. The user can then choose to issue any of the fast program commands. Care
must be taken because applying a V
protected block.
to the V /WP pin will temporarily unprotect any
PPH
PP
4.2.1
4.2.2
Double Byte Program command
The Double Byte Program command is used to write a page of two adjacent bytes in
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to
issue the Double Byte Program command.
1. The first bus cycle sets up the Double Byte Program command
2. The second bus cycle latches the address and the data of the first byte to be written
3. The third bus cycle latches the address and the data of the second byte to be written.
Quadruple Byte Program command
The Quadruple Byte Program command is used to write a page of four adjacent bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple Byte Program command.
1. The first bus cycle sets up the Quadruple Byte Program command
2. The second bus cycle latches the Address and the data of the first byte to be written
3. The third bus cycle latches the address and the data of the second byte to be written
4. The fourth bus cycle latches the address and the data of the third byte to be written
5. The fifth bus cycle latches the address and the data of the fourth byte to be written and
starts the program/erase controller.
22/69
M29W064FT, M29W064FB
Command interface
4.2.3
Octuple Byte Program command
This is used to write eight adjacent bytes, in x 8 mode, simultaneously. The addresses of the
eight bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command:
1. The first bus cycle sets up the command
2. The second bus cycle latches the address and the data of the first byte to be written
3. The third bus cycle latches the address and the data of the second byte to be written
4. The fourth bus cycle latches the address and the data of the third byte to be written
5. The fifth bus cycle latches the address and the data of the fourth byte to be written
6. The sixth bus cycle latches the address and the data of the fifth byte to be written
7. The seventh bus cycle latches the address and the data of the sixth byte to be written
8. The eighth bus cycle latches the address and the data of the seventh byte to be written.
9. The ninth bus cycle latches the address and the data of the eighth byte to be written
and starts the program/erase controller.
4.2.4
Double Word Program command
The Double Word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command:
●
●
●
The first bus cycle sets up the Quadruple Word Program command.
The second bus cycle latches the address and the data of the first word to be written
The third bus cycle latches the address and the data of the second word to be written
and starts the program/erase controller.
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs bus read operations will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
Note that the fast program commands cannot change a bit set to ’0’ back to ’1’. One of the
erase commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical program times are given in Table 8: Program, erase times and program, erase
endurance cycles.
23/69
Command interface
M29W064FT, M29W064FB
4.2.5
Quadruple Word Program command
This is used to write a page of four adjacent words (or 8 adjacent bytes), in x 16 mode,
simultaneously. The addresses of the four words must differ only in A1 and A0.
Five bus write cycles are necessary to issue the command:
●
●
●
●
●
The first bus cycle sets up the command
The second bus cycle latches the address and the data of the first word to be written
The third bus cycle latches the address and the data of the second word to be written
The fourth bus cycle latches the address and the data of the third word to be written
The fifth bus cycle latches the address and the data of the fourth word to be written and
starts the program/erase controller.
4.2.6
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three bus write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in read mode.
When V is applied to the V /write protect pin the memory automatically enters the
PP
PP
unlock bypass mode and the Unlock Bypass Program command can be issued immediately.
4.2.7
Unlock Bypass Program command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the cycle time to the device is long, considerable
time saving can be made by using these commands. Three bus write operations are
required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in read mode.
The memory offers accelerated program operations through the V /write protect pin. When
PP
the system asserts V on the V /write protect pin, the memory automatically enters the
PP
PP
unlock bypass mode. The system may then write the two-cycle unlock bypass program
command sequence. The memory uses the higher voltage on the V /write protect pin, to
PP
accelerate the unlock bypass program operation.
Never raise V /write protect to V from any mode except read mode, otherwise the
PP
PP
memory may be left in an indeterminate state.
4.2.8
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to read/reset mode from Unlock
bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from unlock bypass mode.
24/69
M29W064FT, M29W064FB
Command interface
4.3
Block Protection commands
4.3.1
Enter Extended Block command
The device has an extra 256-byte block (extended block) that can only be accessed using
the Enter Extended Block command. Three bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters extended
block mode where all bus read or write operations to the boot block addresses access the
extended block. The extended block (with the same address as the boot blocks) cannot be
erased, and can be treated as one-time programmable (OTP) memory. In extended block
mode the boot blocks are not accessible.
To exit from the extended block mode the Exit Extended Block command must be issued.
The extended block can be protected, however once protected the protection cannot be
undone.
4.3.2
4.3.3
Exit Extended Block command
The Exit Extended Block command is used to exit from the extended block mode and return
the device to read mode. Four bus write operations are required to issue the command.
Block Protect and Chip Unprotect commands
Groups of blocks can be protected against accidental program or erase. The Protection
groups are shown in Appendix A: Block addresses, Table 20: Top boot block addresses,
M29W064FT and Table 21: Bottom boot block addresses, M29W064FB. The whole chip can
be unprotected to allow the data inside the blocks to be changed.
Block protect and chip unprotect operations are described in Appendix D: Block protection.
25/69
Command interface
M29W064FT, M29W064FB
(1)
Table 6.
Commands, 16-bit mode, BYTE = V
IH
Bus write operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
50
Read/Reset
555
555
555
555
2AA
2AA
2AA
55
55
55
X
F0
90
A0
Auto Select
555
555
Program
PA
PD
Double Word Program
PA0 PD0 PA1 PD1
PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Quadruple Word
Program
5
3
2
555
555
X
56
AA
A0
Unlock Bypass
2AA
PA
55
555
20
Unlock Bypass
Program
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Program/Erase
Suspend
1
1
X
X
B0
30
Program/Erase
Resume
Read CFI Query
1
3
4
55
98
AA
AA
Enter Extended Block
Exit Extended Block
555
555
2AA
2AA
55
55
555
555
88
90
X
00
1. X don’t care, PA program address, PD program data, BA any address in the block. All values in the table are in
hexadecimal. The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14
and DQ15 are don’t care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH
.
26/69
M29W064FT, M29W064FB
Command interface
Table 7.
Commands, 8-bit mode, BYTE = V
IL
Bus write operations(1)
4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data
F0
3 AAA AA 555 55
Command
1st
2nd
3rd
7th
8th
9th
1
X
Read/Reset
X
F0
Auto Select
Program
3 AAA AA 555 55 AAA 90
4 AAA AA 555 55 AAA A0 PA PD
Double Byte
Program
3 AAA 50 PA0 PD0 PA1 PD1
Quadruple
Byte Program
5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Octuple Byte
Program
9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
2
X
A0 PA PD
Program
Unlock Bypass
Reset
2
X
90
X
00
Chip Erase
Block Erase
6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Program/Erase
Suspend
1
1
1
X
X
B0
30
Program/Erase
Resume
Read CFI
Query
AA 98
Enter
Extended
Block
3 AAA AA 555 55 AAA 88
4 AAA AA 555 55 AAA 90
Exit Extended
Block
X
00
1. X don’t care, PA program address, PD program data, BA any address in the block. All values in the table are in
hexadecimal. The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14
and DQ15 are don’t care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
27/69
Command interface
M29W064FT, M29W064FB
Table 8.
Program, erase times and program, erase endurance cycles
Parameter
Min
Typ(1)(2)
Max(2)
Unit
Chip Erase
80
400(3)
6(4)
s
s
Block Erase (64 Kbytes)
0.8
Erase Suspend latency time
50(4)
200(3)
200(3)
200(3)
200(3)
400(3)
200(3)
100(3)
50(3)
4
µs
µs
µs
µs
µs
s
Program (byte or word)
10
10
10
10
80
40
20
10
Double Byte
Double Word /Quadruple Byte Program
Quadruple Word / Octuple Byte Program
Chip Program (byte by byte)
Chip Program (word by word)
Chip Program (Double Word/Quadruple Byte Program)
Chip Program (Quadruple Word/Octuple Byte Program)
Program Suspend latency time
Program/Erase cycles (per block)
Data retention
s
s
s
µs
cycles
years
100,000
20
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC
.
28/69
M29W064FT, M29W064FB
Status register
5
Status register
Bus read operations from any address always read the status register during program and
erase operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in Table 9: Status register bits.
5.1
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations from the address just programmed output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from a ’0’ to a ’1’ when the
program/erase controller has suspended the erase operation.
Figure 3: Data polling flowchart, gives an example of how to use the data polling bit. A valid
address is the address being programmed or an address within the block being erased.
5.2
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During program and erase operations the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the operation
the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
Figure 4: Toggle flowchart, gives an example of how to use the toggle bit.
29/69
Status register
M29W064FT, M29W064FB
5.3
Error bit (DQ5)
The error bit can be used to identify errors detected by the program/erase controller. The
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the
correct data to the memory. If the error bit is set a Read/Reset command must be issued
before other commands are issued. The error bit is output on DQ5 when the status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One
of the erase commands must be used to set all the bits in a block or in the whole memory
from ’0’ to ’1’.
5.4
5.5
Erase timer bit (DQ3)
The erase timer bit can be used to identify the start of program/erase controller operation
during a Block Erase command. Once the program/erase controller starts erasing the erase
timer bit is set to ’1’. Before the program/erase controller starts the erase timer bit is set to ’0’
and additional blocks to be erased may be written to the command interface. The erase
timer bit is output on DQ3 when the status register is read.
Alternative toggle bit (DQ2)
The alternative toggle bit can be used to monitor the program/erase controller during erase
operations. The alternative toggle bit is output on DQ2 when the status register is read.
During chip erase and block erase operations the toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive bus read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to read mode.
During erase suspend the alternative toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive bus read operations from addresses within the blocks being erased. Bus read
operations to addresses within blocks not being erased will output the memory cell data as if
in read mode.
After an erase operation that causes the error bit to be set the alternative toggle bit can be
used to identify which block or blocks have caused the error. The alternative toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive bus read operations from addresses within
blocks that have not erased correctly. The alternative toggle bit does not change if the
addressed block has erased correctly.
30/69
M29W064FT, M29W064FB
Status register
(1)
Table 9.
Status register bits
Operation
Address
DQ7
DQ6
DQ5 DQ3
DQ2
RB
Program
Any address
DQ7
Toggle
0
0
–
–
–
0
Program during erase
suspend
Any address
DQ7
Toggle
–
0
Program error
Chip erase
Any address
Any address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
Hi-Z
0
0
0
0
0
0
1
Toggle
Erasing block
Toggle
Toggle
0
Block erase before
timeout
Non-erasing block
Erasing block
Toggle
No Toggle
Toggle
0
Toggle
0
Block erase
Erase suspend
Erase error
Non-erasing block
Erasing block
Toggle
No Toggle
Toggle
0
No Toggle
Hi-Z
Hi-Z
Non-erasing block
Good block address
Faulty block address
Data read as normal
0
0
Toggle
Toggle
1
1
1
1
No Toggle Hi-Z
Toggle
Hi-Z
1. Unspecified data bits should be ignored.
Figure 3.
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO
DQ5
= 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
FAIL
PASS
AI90194
31/69
Status register
Figure 4.
M29W064FT, M29W064FB
Toggle flowchart
START
READ DQ6
READ
DQ5 & DQ6
DQ6
=
NO
TOGGLE
YES
NO
DQ5
= 1
YES
READ DQ6
TWICE
DQ6
=
NO
TOGGLE
YES
FAIL
PASS
AI90195B
32/69
M29W064FT, M29W064FB
Maximum rating
6
Maximum rating
Stressing the device above the rating listed in Table 10: Absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 10. Absolute maximum ratings
Symbol
Parameter
Temperature under bias
Min
Max
Unit
TBIAS
TSTG
VIO
–50
–65
125
150
°C
°C
V
Storage temperature
Input or output voltage(1)(2)
Supply voltage
–0.6
–0.6
–0.6
–0.6
VCC + 0.6
4
VCC
VID
V
Identification voltage
Program voltage
13.5
V
(3)
VPP
13.5
V
1. Minimum voltage may undershoot to –2 V during transition and for less than 20 ns during transitions.
2. Maximum voltage may overshoot to VCC +2 V during transition and for less than 20 ns during transitions.
3. VPP must not remain at 12 V for more than a total of 80 hrs.
33/69
DC and AC parameters
M29W064FT, M29W064FB
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 11. Operating and AC measurement conditions
M29W064FT, M29W064FB
Parameter
Unit
Min
Max
VCC supply voltage
2.7
3.6
85
V
°C
pF
ns
V
Ambient operating temperature
Load capacitance (CL)
–40
30
Input rise and fall times
10
Input pulse voltages
0 to VCC
VCC/2
Input and output timing ref. voltages
V
Figure 5.
AC measurement I/O waveform
V
CC
V
/2
CC
0 V
AI05557
Figure 6.
AC measurement load circuit
V
V
V
CC
PP
CC
25kΩ
DEVICE
UNDER
TEST
25kΩ
C
L
0.1µF
0.1µF
C
includes JIG capacitance
L
AI05558
34/69
M29W064FT, M29W064FB
DC and AC parameters
Table 12. Device capacitance
Symbol
Parameter
Test condition
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V
6
pF
pF
COUT
Output capacitance
VOUT = 0 V
12
1. Sampled only, not 100% tested.
Table 13. DC characteristics
Symbol
Parameter
Test condition
Min
Max
Unit
ILI
Input leakage current
Output leakage current
0 V ≤VIN ≤VCC
1
1
µA
µA
ILO
0 V ≤VOUT ≤VCC
E = VIL, G = VIH,
f = 6 MHz
ICC1
Supply current (read)
10
100
20
mA
µA
E = VCC 0.2 V,
RP = VCC 0.2 V
ICC2
Supply current (standby)
V
PP/WP =
mA
Supply current
(program/erase)
Program/erase
controller active
VIL or VIH
ICC3
VPP/WP = VPP
20
mA
V
VIL
VIH
Input low voltage
Input high voltage
–0.5
0.8
0.7VCC VCC + 0.3
V
Voltage for VPP/WP
program acceleration
VPP
IPP
V
CC = 2.7 V 10%
11.5
12.5
V
Current for VPP/WP
program acceleration
VCC = 2.7 V 10%
15
mA
VOL
VOH
VID
Output low voltage
Output high voltage
Identification voltage
IOL = 1.8 mA
0.45
V
V
V
IOH = –100 µA
VCC–0.4
11.5
12.5
2.3
Program/erase lockout
supply voltage
(1)
VLKO
1.8
V
1. Sampled only, not 100% tested.
35/69
DC and AC parameters
M29W064FT, M29W064FB
Figure 7.
Read mode AC waveforms
tAVAV
VALID
A0-A20/
A–1
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
Figure 8.
Page read AC waveforms
A2-A21
A0-A1
VALID ADDRESS
VALID
VALID
tAVQV
VALID
VALID
E
tELQV
tEHQX
tEHQZ
G
tGHQX
tGHQZ
tGLQV
tAVQV1
VALID
DATA
DQ0-DQ15
VALID DATA
VALID DATA
VALID DATA
AI11553
36/69
M29W064FT, M29W064FB
DC and AC parameters
M29W064FT,
Table 14. Read AC characteristics
M29W064FB
Symbol
Alt
Parameter
Test condition
Unit
60
70
E = VIL,
G = VIL
tAVAV
tAVQV
tAVQV1
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
Min
60
70
ns
ns
ns
E = VIL,
G = VIL
Max
Max
60
25
70
25
E = VIL,
G = VIL
tPAGE Address Valid to Output Valid (Page)
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
G = VIL
G = VIL
E = VIL
E = VIL
G = VIL
E = VIL
Min
Max
Min
0
0
ns
ns
ns
ns
ns
ns
tELQV
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
tOE Output Enable Low to Output Valid
tHZ Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
60
0
70
0
(1)
tGLQX
tGLQV
Max
Max
Max
25
25
25
25
25
25
(1)
tEHQZ
(1)
tGHQZ
tEHQX
tGHQX
tAXQX
Chip Enable, Output Enable or Address
Transition to Output Transition
tOH
Min
0
5
0
5
ns
ns
tELBL
tELBH
tBLQZ
tBHQV
tELFL
Chip Enable to BYTE Low or High
tELFH
Max
tFLQZ BYTE Low to Output Hi-Z
tFHQV BYTE High to Output Valid
Max
Max
25
30
25
30
ns
ns
1. Sampled only, not 100% tested.
37/69
DC and AC parameters
Figure 9. Write AC waveforms, write enable controlled
M29W064FT, M29W064FB
tAVAV
VALID
A0-A20/
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI05560
38/69
M29W064FT, M29W064FB
DC and AC parameters
M29W064FT,
Table 15. Write AC characteristics, write enable controlled
M29W064FB
Symbol
Alt
Parameter
Unit
60
70
tAVAV
tELWL
tWC
tCS
tWP
tDS
tDH
tCH
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
60
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tWHGL
45
45
0
45
45
0
Write Enable High to Input Transition
Write Enable High to Chip Enable High
0
0
tWPH Write Enable High to Write Enable Low
30
0
30
0
tAS
tAH
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
45
0
45
0
tOEH Write Enable High to Output Enable Low
tBUSY Program/Erase Valid to RB Low
tVCS VCC High to Chip Enable Low
0
0
(1)
tWHRL
30
50
30
50
tVCHEL
1. Sampled only, not 100% tested.
39/69
DC and AC parameters
M29W064FT, M29W064FB
Figure 10. Write AC waveforms, chip enable controlled
tAVAV
A0-A20/
VALID
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI05561
40/69
M29W064FT, M29W064FB
DC and AC parameters
Table 16. Write AC characteristics, chip enable controlled
M29W064FT, M29W064FB
Symbol
Alt
Parameter
Unit
60
70
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tELAX
tGHEL
tEHGL
tWC Address Valid to Next Address Valid
tWS Write Enable Low to Chip Enable Low
tCP Chip Enable Low to Chip Enable High
tDS Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
60
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
45
45
0
45
45
0
tDH Chip Enable High to Input Transition
tWH Chip Enable High to Write Enable High
tCPH Chip Enable High to Chip Enable Low
0
0
30
0
30
0
tAS
Address Valid to Chip Enable Low
tAH Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
45
0
45
0
tOEH Chip Enable High to Output Enable Low
tBUSY Program/Erase Valid to RB Low
tVCS VCC High to Write Enable Low
0
0
(1)
tEHRL
30
50
30
50
tVCHWL
1. Sampled only, not 100% tested.
Figure 11. Reset/block temporary unprotect AC waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI02931B
41/69
DC and AC parameters
M29W064FT, M29W064FB
Figure 12. Accelerated program timing waveforms
V
PP
V
/WP
PP
V
or V
IH
IL
tVHVPP
tVHVPP
AI05563
Table 17. Reset/block temporary unprotect AC characteristics
M29W064FT,
Unit
Symbol
Alt
Parameter
M29W064FB
(1)
tPHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
tPHEL
tRH
Min
50
0
ns
ns
(1)
tPHGL
(1)
tRHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
(1)
tRHEL
tRB
Min
(1)
tRHGL
tPLPX
tPLYH
tRP
RP pulse width
Min
Max
Min
Min
500
50
ns
µs
ns
ns
tREADY RP Low to read mode
(1)
tPHPHH
tVIDR
RP rise time to VID
500
250
(1)
tVHVPP
VPP rise and fall time
1. Sampled only, not 100% tested.
42/69
M29W064FT, M29W064FB
Package mechanical
8
Package mechanical
®
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK
packages. ECOPACK packages are lead-free. The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 13. TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, top view package
outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 18. TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package
mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
1.20
0.15
1.05
0.27
0.21
0.10
12.10
20.20
18.50
–
0.047
0.006
0.041
0.011
0.008
0.004
0.476
0.795
0.728
–
0.10
1.00
0.22
0.05
0.95
0.17
0.10
0.004
0.039
0.009
0.002
0.037
0.007
0.004
C
CP
D1
E
12.00
20.00
18.40
0.50
0.60
0.80
3°
11.90
19.80
18.30
–
0.472
0.787
0.724
0.020
0.024
0.031
3°
0.468
0.779
0.720
–
E1
e
L
0.50
0.70
0.020
0.028
L1
α
0°
5°
0°
5°
43/69
Ordering information
M29W064FT, M29W064FB
9
Ordering information
Table 19. Ordering information scheme
Example:
M29W064FB
70
N
3
F
Device type
M29
Operating voltage
W = VCC = 2.7 to 3.6 V
Device function
064F = 64 Mbit (x 8 / x 16), boot block
Array matrix
T = Top boot
B = Bottom boot
Speed
60 = 60 ns
70 = 70 ns
Package
N = TSOP48: 12 x 20 mm
Temperature range
3 = automotive grade certified(1), −40 to 125 °C
Option
E = ECOPACK package, standard packing
F = ECOPACK package, tape & reel packing
1. Qualified and characterized according to AEC Q100 & Q003 or equivalent, advanced screening according
to AEC Q001 & Q002 or equivalent.
Note:
This product is also available with the extended block factory locked. For further details and
ordering information contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to ‘1’. For a list of
available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest Numonyx sales office.
44/69
M29W064FT, M29W064FB
Block addresses
Appendix A
Block addresses
Table 20. Top boot block addresses, M29W064FT
Block
Kbytes/Kwords
Protection block group
(x 8)
(x 16)
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh(1)
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
000000h–007FFFh(1)
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
1
Protection group
2
3
4
5
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
45/69
Block addresses
M29W064FT, M29W064FB
(x 16)
Table 20. Top boot block addresses, M29W064FT (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
46/69
M29W064FT, M29W064FB
Block addresses
(x 16)
Table 20. Top boot block addresses, M29W064FT (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–287FFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2F7FFFh
2F8000h–2FFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
47/69
Block addresses
M29W064FT, M29W064FB
(x 16)
Table 20. Top boot block addresses, M29W064FT (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
96
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
97
Protection group
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
48/69
M29W064FT, M29W064FB
Block addresses
(x 16)
Table 20. Top boot block addresses, M29W064FT (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
124
125
126
127
128
129
130
131
132
133
134
64/32
64/32
64/32
8/4
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
8/4
8/4
Protection group
8/4
8/4
8/4
8/4
8/4
1. Used as the extended block addresses in extended block mode.
49/69
Block addresses
M29W064FT, M29W064FB
(x 16)
Table 21. Bottom boot block addresses, M29W064FB
Block
Kbytes/Kwords
Protection block group
(x 8)
0
8/4
000000h-001FFFh(1)
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
000000h–000FFFh(1)
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
1
8/4
2
8/4
3
8/4
4
8/4
5
8/4
Protection group
6
8/4
7
8/4
8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
50/69
M29W064FT, M29W064FB
Block addresses
(x 16)
Table 21. Bottom boot block addresses, M29W064FB (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
51/69
Block addresses
M29W064FT, M29W064FB
(x 16)
Table 21. Bottom boot block addresses, M29W064FB (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–287FFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
52/69
M29W064FT, M29W064FB
Block addresses
(x 16)
Table 21. Bottom boot block addresses, M29W064FB (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
99
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2F7FFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
53/69
Block addresses
M29W064FT, M29W064FB
(x 16)
Table 21. Bottom boot block addresses, M29W064FB (continued)
Block
Kbytes/Kwords
Protection block group
(x 8)
131
132
133
134
64/32
64/32
64/32
64/32
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7FFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
Protection group
1. Used as the extended block addresses in extended block mode.
54/69
M29W064FT, M29W064FB
Common Flash interface (CFI)
Appendix B
Common Flash interface (CFI)
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query command is issued the device enters CFI query mode and the data
structure is read from the memory. Tables 22, 23, 24, 25, 26, and 27, show the addresses
used to retrieve the data.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Table 27: Security code area). This area can be accessed only in read mode
by the final user. It is impossible to change the security number after it has been written by
Numonyx.
(1)
Table 22. Query structure overview
Address
Sub-section name
Description
x 16
x 8
10h
1Bh
27h
20h CFI query identification string
36h System interface information
4Eh Device geometry definition
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Primary algorithm-specific extended
query table
Additional information specific to the
primary algorithm (optional)
40h
61h
80h
C2h Security code area
64-bit unique device number
1. Query data are always presented on the lowest order data outputs.
55/69
Common Flash interface (CFI)
M29W064FT, M29W064FB
(1)
Table 23. CFI query identification string
Address
Data
Description
Value
x 16
x 8
10h
11h
12h
13h
14h
20h 0051h
‘Q’
‘R’
‘Y’
22h 0052h Query unique ASCII string ‘QRY’
24h 0059h
26h 0002h
Primary algorithm command set and control interface ID code
16-bit ID code defining a specific algorithm
AMD
compatible
28h 0000h
15h 2Ah 0040h
16h 2Ch 0000h
17h 2Eh 0000h
Address for primary algorithm extended query table (see
Table 26)
P = 40h
NA
Alternate vendor command set and control interface ID code
second vendor - specified algorithm supported
18h
19h
30h 0000h
32h 0000h
Address for alternate algorithm extended query table
NA
1Ah 34h 0000h
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Table 24. CFI query system interface information
Address
Data
Description
Value
2.7 V
x 16 x 8
VCC logic supply minimum program/erase voltage
1Bh 36h 0027h bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
VCC logic supply maximum program/erase voltage
1Ch 38h 0036h bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6 V
VPP [programming] supply minimum program/erase voltage
1Dh 3Ah 00B5h bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5 V
12.5 V
VPP [programming] supply maximum program/erase voltage
1Eh 3Ch 00C5h bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs
20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs
21h 42h 000Ah Typical timeout per individual block erase = 2n ms
22h 44h 0000h Typical timeout for full chip erase = 2n ms
16 µs
NA
1 s
NA
23h 46h 0004h Maximum timeout for byte/word program = 2n times typical
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical
256 µs
NA
8 s
NA
56/69
M29W064FT, M29W064FB
Common Flash interface (CFI)
(1)
Table 25. Device geometry definition
Address
Data
Description
Value
x 16
x 8
27h
4Eh
0017h Device size = 2n in number of bytes
8 Mbytes
28h
29h
50h
52h
0002h
x 8, x 16
Async.
Flash device interface code description
0000h
2Ah
2Bh
54h
56h
0004h
Maximum number of bytes in multi-byte program or page = 2n 16 bytes
0000h
Number of erase block regions. It specifies the number of
regions containing contiguous erase blocks of the same size.
2Ch
58h
0002h
2
2Dh
2Eh
5Ah
5Ch
0007h Region 1 information
8
0000h Number of erase blocks of identical size = 0007h+1
2Fh
30h
5Eh
60h
0020h Region 1 information
8 Kbytes
127
0000h Block size in region 1 = 0020h * 256 byte
31h
32h
62h
64h
007Eh Region 2 information
0000h Number of erase blocks of identical size= 007Eh+1
33h
34h
66h
68h
0000h Region 2 information
64 Kbytes
0001h Block size in region 2 = 0100h * 256 byte
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h Region 3 information
0000h Number of erase blocks of identical size=007Fh+1
0000h Region 3 information
0
0
0000h Block size in region 3 = 0000h * 256 bytes
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h Region 4 information
0000h Number of erase blocks of identical size=007Fh+1
0000h Region 4 information
0
0
0000h Block size in region 4 = 0000h * 256 bytes
1. For bottom boot devices, erase block region 1 is located from address 000000h to 007FFFh and erase
block region 2 from address 008000h to 3FFFFFh.
For top boot devices, erase block region 1 is located from address 000000h to 3F7FFFh and erase block
region 2 from address 3F8000h to 3FFFFFh.
57/69
Common Flash interface (CFI)
M29W064FT, M29W064FB
Table 26. Primary algorithm-specific extended query table
Address
Data
Description
Value
x 16
x 8
40h
41h
42h
43h
44h
80h 0050h
82h 0052h
84h 0049h
‘P’
Primary algorithm extended query table unique ASCII string
‘PRI’
‘R’
‘I’
86h 0031h Major version number, ASCII
88h 0033h Minor version number, ASCII
‘1’
‘3’
Address sensitive unlock (bits 1 to 0)
8Ah 0000h 00h = required, 01h = not required
Silicon revision number (bits 7 to 2)
45h
Yes
Erase suspend
8Ch 0002h
46h
47h
48h
49h
2
4
00h = not supported, 01h = read only, 02 = read and write
Block protection
8Eh 0004h
90h 0001h
92h 0004h
00h = not supported, x = number of blocks per protection group
Temporary block unprotect
Yes
04
00h = not supported, 01h = supported
Block protect /unprotect
04 = M29W064F
4Ah
4Bh
94h 0000h Simultaneous operations, 00h = not supported
96h 0000h Burst mode: 00h = not supported, 01h = supported
No
No
Page mode: 00h = not supported, 01h = 4 page word, 02h = 8
4Ch
98h 0001h
page word
Yes
VPP supply minimum program/erase voltage
4Dh
9Ah 00B5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5 V
VPP supply maximum program/erase voltage
4Eh
4Fh
50h
9Ch 00C5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5 V
–
Top/bottom boot block flag
0002h
9Eh
02h = bottom boot device
03h = top boot device
0003h
Program suspend
A0h 0001h 00h = not supported
01h = supported
Supported
58/69
M29W064FT, M29W064FB
Common Flash interface (CFI)
Description
Table 27. Security code area
Address
Data
x 16
x 8
61h
62h
63h
64h
C3h, C2h
C5h, C4h
C7h, C6h
C9h, C8h
XXXX
XXXX
XXXX
XXXX
64 bit: unique device number
59/69
Extended memory block
M29W064FT, M29W064FB
Appendix C
Extended memory block
The M29W064F has an extra block, the extended block, that can be accessed using a
dedicated command.
This extended block is 128 words in x 16 mode and 256 bytes in x 8 mode. It is used as a
security block to provide a permanent security identification number) or to store additional
information.
The extended block is either factory locked or customer lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed.
When set to ‘1’, it indicates that the device is factory locked and the extended block is
protected. When set to ‘0’, it indicates that the device is customer lockable and the extended
block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security
feature which ensures that a customer lockable device cannot be used instead of a factory
locked one.
Bit DQ7 is the most significant bit in the extended block verify code and a specific procedure
must be followed to read it. See ‘extended memory block verify code’ in Table 4: Bus
operations, BYTE = V and Table 5: Bus operations, BYTE = V , for details of how to read
IL
IH
bit DQ7.
The extended block can only be accessed when the device is in extended block mode. For
details of how the extended block mode is entered and exited, refer to the Section 4.3.1:
Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to
Table 6 and Table 7: Commands, 8-bit mode, BYTE = V .
IL
C.1
C.2
Factory locked extended block
In devices where the extended block is factory locked, the security identification number is
written to the extended block address space (see Table 28: Extended block address and
data) in the factory. The DQ7 bit is set to ‘1’ and the extended block cannot be unprotected.
Customer lockable extended block
A device where the extended block is customer lockable is delivered with the DQ7 bit set to
‘0’ and the extended block unprotected. It is up to the customer to program and protect the
extended block but care must be taken because the protection of the extended block is not
reversible.
There are two ways of protecting the extended block:
●
Issue the Enter Extended Block command to place the device in extended block mode,
then use the in-system technique with RP either at V or at V (refer to Appendix D,
IH
ID
Section D.2: In-system technique and to the corresponding flowcharts, Figure 16 and
Figure 17, for a detailed explanation of the technique)
●
Issue the Enter Extended Block command to place the device in extended block mode,
then use the programmer technique (refer to Appendix D, Section D.1: Programmer
technique and to the corresponding flowcharts, Figure 14 and Figure 15, for a detailed
explanation of the technique).
Once the extended block is programmed and protected, the Exit Extended Block command
must be issued to exit the extended block mode and return the device to read mode.
60/69
M29W064FT, M29W064FB
Extended memory block
Table 28. Extended block address and data
Address
Data
x 8
000000h-00007Fh 000000h-00003Fh Security identification number
000080h-0000FFh 000040h-00007Fh Unavailable
x 16
Factory locked
Customer lockable
Determined by customer
61/69
Block protection
M29W064FT, M29W064FB
Appendix D
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the
memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 20
and Table 21 for details of the protection groups. Once protected, program and erase
operations within the protected group fail to change the data.
There are three techniques that can be used to control block protection, these are the
programmer technique, the in-system technique and temporary unprotection. Temporary
unprotection is controlled by the reset/block temporary unprotection pin, RP; this is
described in the Section 2: Signal descriptions.
D.1
Programmer technique
The programmer technique uses high (V ) voltage levels on some of the bus pins. These
ID
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in programming equipment.
To protect a group of blocks follow the flowchart in Figure 14: Programmer equipment group
protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all groups can be unprotected at the same time. To unprotect the chip follow Figure 15:
Programmer equipment chip unprotect flowchart. Table 29: Programmer technique bus
operations, BYTE = V or V , gives a summary of each operation.
IH
IL
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
D.2
In-system technique
The in-system technique requires a high voltage level on the reset/blocks temporary
unprotect pin, RP. This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
memory has been fitted to the system.
To protect a group of blocks follow the flowchart in Figure 16: In-system equipment group
protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all the groups can be unprotected at the same time. To unprotect the chip follow
Figure 17: In-system equipment chip unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
Note:
RP can be either at V or at V when using the in-system technique to protect the extended
IH ID
block.
62/69
M29W064FT, M29W064FB
Block protection
Table 29. Programmer technique bus operations, BYTE = V or V
IH
IL
Address inputs
Data inputs/outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
A0-A21
A9 = VID, A12-A21 = block address,
others = X
Block (group)
protect(1)
VIL VID VIL pulse
VID VID VIL pulse
X
A9 = VID, A12 = VIH, A15 = VIH
others = X
Chip unprotect
X
A0, A2, A3 = VIL, A1 = VIH, A6 = VIL,
A9 = VID, A12-A21 = block address
Pass = XX01h
Retry = XX00h
Block (group)
protection verify
VIL VIL
VIH
others = X
A0, A2, A3 = VIL, A1 = VIH, A6 = VIH,
A9 = VID, A12-A21 = block address
Retry = XX01h
Pass = XX00h
Block (group)
unprotection verify
VIL VIL
VIH
others = X
1. Block protection groups are shown in Appendix A, tables 20 and 21.
63/69
Block protection
M29W064FT, M29W064FB
Figure 14. Programmer equipment group protect flowchart
START
ADDRESS = GROUP ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
IH
,
A0, A2, A3 = V , A1 =V
,
IL
IH
A6 =V A9 = VID, Others = X
IL,
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
IH
E, G = V
IH
YES
PASS
A9 = V
IH
E, G = V
IH
AI11555
FAIL
1. Block protection groups are shown in Appendix A, tables 20 and 21.
64/69
M29W064FT, M29W064FB
Figure 15. Programmer equipment chip unprotect flowchart
Block protection
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = V , A1 =V
,
IL
IH
A9 = VID, Others = X
A6 =V
IH,
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT GROUP
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
GROUP
NO
NO
++n
= 1000
YES
YES
A9 = V
A9 = V
E, G = V
IH
IH
E, G = V
IH
IH
FAIL
PASS
AI11556b
1. Block protection groups are shown in Appendix A, tables 20 and 21.
65/69
Block protection
Figure 16. In-system equipment group protect flowchart
M29W064FT, M29W064FB
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = V , A1 = V
IL
IH
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = V , A1 = V
IL
Wait 100µs
WRITE 40h
IH
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = V , A1 = V
IL
IH
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = V , A1 = V
IL
IH
DATA
NO
=
01h
YES
RP = V
++n
= 25
NO
IH
YES
RP = V
ISSUE READ/RESET
COMMAND
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI11563
1. Block protection groups are shown in Appendix A, tables 20 and 21.
2. RP can be either at VIH or at VID when using the in-system technique to protect the extended block.
66/69
M29W064FT, M29W064FB
Figure 17. In-system equipment chip unprotect flowchart
Block protection
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3, A6 = V , A1 = V
IL
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3 = V , A1, A6 = V
IL
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = V , A1, A6 = V
IL
IH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = V , A1, A6 = V
IL
IH
DATA
=
00h
NO
YES
++n
= 1000
NO
NO
LAST
GROUP
YES
YES
RP = V
IH
RP = V
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI11564
1. Block protection groups are shown in Appendix A, tables 20 and 21.
67/69
Revision history
M29W064FT, M29W064FB
10
Revision history
Table 30. Document revision history
Date
Revision
Changes
18-Mar-2008
27-Mar-2008
1
2
Initial release.
Applied Numonyx branding.
68/69
M29W064FT, M29W064FB
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
69/69
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64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory
NUMONYX
M29W064FT90N3E
64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory
NUMONYX
M29W064FT90N3F
64 Mbit (8 Mbit x 8 or 4 Mbit x 16, page, boot block) 3 V supply Flash memory
NUMONYX
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