M36W0R6040T3ZAQE [NUMONYX]

64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP; 64兆位（ 4兆】 16 ，多个银行，爆裂），闪存和16兆（ 1兆】 16 ）或32兆比特（ 2兆比特X16 ） PSRAM的MCP


型号：	M36W0R6040T3ZAQE
厂家：	NUMONYX B.V
描述：	64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP 64兆位（ 4兆】 16 ，多个银行，爆裂），闪存和16兆（ 1兆】 16 ）或32兆比特（ 2兆比特X16 ） PSRAM的MCP 闪存内存集成电路静态存储器
文件：	总23页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36P0R9070E0

512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory

128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package

Feature summary

FBGA

■ Multi-Chip Package

– 1 die of 512 Mbit (32Mb x 16, Multiple

Bank, Multi-Level, Burst) Flash Memory

– 1 die of 128Mbit (8Mb x16) PSRAM

■ Supply voltage

TFBGA107 (ZAC)

– V

= V

= 1.7 to 1.95V

DDQ

DDF

PPF

CCP

= 9V for fast program

■ Block locking

■ Electronic signature

– Manufacturer Code: 20h

– Device Code: 8819

– All Blocks locked at power-up

– Any combination of Blocks can be locked

with zero latency

■ ECOPACK® package available

– WP for Block Lock-Down

– Absolute Write Protection with V

= V

PPF

Flash memory

PSRAM

■ Synchronous / Asynchronous Read

– Synchronous Burst Read mode:

108MHz, 66MHz

– Asynchronous Page Read mode

– Random Access: 96ns

■ Access time: 70ns

■ User-selectable operating modes

– Asynchronous modes: Random Read, and

Write, Page Read

■ Programming time

– Synchronous modes: NOR-Flash, Full

Synchronous (Burst Read and Write)

– 4.2µs typical Word program time using

Buffer Enhanced Factory Program

command

■ Asynchronous Page Read

– Page Size: 4, 8 or 16 Words

– Subsequent Read Within Page: 20ns

■ Memory organization

– Multiple bank memory array: 64 Mbit banks

■ Burst Read

– Four Extended Flash Array (EFA) Blocks of

64 Kbits

– Fixed Length (4, 8, 16 or 32 Words) or

Continuous

■ Dual operations

– Maximum Clock Frequency: 80MHz

– program/erase in one Bank while read in

others

– No delay between read and write

operations

■ Low Power Consumption

– Active Current: < 25mA

– Standby Current: 200µA

– Deep Power-Down Current: 10µA

■ Security

■ Low Power Features

– 2112-bit user programmable OTP Cells

– 64-bit unique device number

– Partial Array Self Refresh (PASR)

– Deep Power-Down (DPD) Mode

■ 100,000 program/erase cycles per block

■ Common Flash Interface (CFI)

November 2007

Rev 3

1/23

www.numonyx.com

Contents

M36P0R9070E0

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Chip Enable input (E_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Output Enable inputs (G_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Write Enable (W_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Write Protect (WP_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.10 Flash Reset (RP_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 PSRAM Chip Enable input (E_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 PSRAM Write Enable (W_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.13 PSRAM Output Enable (G_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.14 PSRAM Upper Byte Enable (UB_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.15 PSRAM Lower Byte Enable (LB_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.16 PSRAM Configuration Register Enable (CR_P) . . . . . . . . . . . . . . . . . . . . . 11

2.17 Deep Power-Down input (DPD_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.18 V_DDFSupply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.19

2.20

_CCPSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

_DDQSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.21 V_PPFProgram Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.22 _SSGround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/23

M36P0R9070E0

Contents

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3/23

List of tables

M36P0R9070E0

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 7.

Table 8.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4/23

M36P0R9070E0

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package outline. . . . . . . . . 19

5/23

Summary description

M36P0R9070E0

Summary description

The M36P0R9070E0 combines two memory devices in one Multi-Chip Package:

●

512-Mbit Multiple Bank Flash memory (the M58PR512J).

●

128 Mbit PSRAM (the M69KB128AB).

The purpose of this document is to describe how the two memory components operate with

respect to each other. It should be read in conjunction with the M58PRxxxJ and

M69KB128AB datasheets, where all specifications required to operate the Flash memory

and PSRAM components are fully detailed. The M58PR512J and M69KB128AB datasheets

are available from www.numonyx.com.

Recommended operating conditions do not allow more than one memory to be active at the

same time.

The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits

erased (set to ‘1’).

Figure 1.

Logic diagram

CCP

DDF

PPF

DDQ

A0-A24

DQ0-DQ15

WAIT

M36P0R9070E0

DPD

AI10845

6/23

M36P0R9070E0

Summary description

Table 1.

Signal names

Address Inputs

Common Data Input/Output

A0-A24⁽¹⁾

DQ0-DQ15

V_DDQ

V_PPF

V_DDF

V_CCP

V_SS

Common Flash and PSRAM Power Supply for I/O Buffers

Flash Memory Optional Supply Voltage for Fast Program & Erase

Flash Memory Power Supply

PSRAM Power Supply

Ground

Latch Enable input

Burst Clock

WAIT

Wait Output

Not Connected Internally

Do Not Use as Internally Connected

Flash Memory

E_F

Chip Enable input

Output Enable Input

Write Enable input

Reset input

G_F

W_F

RP_F

WP_F

DPD_F

PSRAM

E_P

Write Protect input

Deep Power-Down

Chip Enable Input

G_P

Output Enable Input

W_P

Write Enable Input

CR_P

Configuration Register Enable Input

Upper Byte Enable Input

Lower Byte Enable Input

UB_P

LB_P

1. A23-A24 are Address Inputs for the Flash memory component only.

7/23

Summary description

M36P0R9070E0

Figure 2.

TFBGA connections (top view through package)

DPD

CCP

A21

A22

A11

A18

A19

A23

A24

DDF

A12

A13

A15

A17

A10

A20

A14

A16

DQ5

DQ12

DQ4

DQ2

DQ1

DQ9

DQ10

DQ3

DQ13

DQ14

WAIT

DQ7

DQ15

DQ8

DQ0

DDQ

DQ11

DQ6

DDQ

CCP

DDF

DDQ

AI11098b

8/23

M36P0R9070E0

Signal descriptions

See Figure 1., Logic diagram and Table 1., Signal names, for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A24)

Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.

Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs

select the cells in the memory array to access during Bus Read operations. During Bus

Write operations they control the commands sent to the Command Interface of the internal

state machine. The Flash memory is accessed through the Chip Enable signal (E ) and

through the Write Enable signal (W ), while the PSRAM is accessed through the Chip

Enable signal (E ) and the Write Enable signal (W ).

E Low, and E must not be Low at the same time.

2.2

Data input/output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the

data to or from the upper part of the selected address when Upper Byte Enable (UB ) is

driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the

lower part of the selected address when Lower Byte Enable (LB ) is driven Low. When both

UB and LB are disabled, the Data Inputs/ Outputs are high impedance.

2.3

2.4

Latch Enable (L)

The Latch Enable pin is common to the Flash memory and PSRAM components.

For details of how the Latch Enable signal behaves, please refer to the datasheets of the

respective memory components: M69KB128AB for the PSRAM and M58PR512J for the

Flash memory.

Clock (K)

The Clock input pin is common to the Flash memory and PSRAM components.

For details of how the Clock signal behaves, please refer to the datasheets of the respective

memory components: M69KB128AB for the PSRAM and M58PR512J for the Flash

memory.

9/23

Signal descriptions

M36P0R9070E0

2.5

Wait (WAIT)

WAIT is an output pin common to the Flash memory and PSRAM components. However the

WAIT signal does not behave in the same way for the PSRAM and the Flash memory.

For details of how it behaves, please refer to the M69KB128AB datasheet for the PSRAM

and to the M58PR512J datasheet for the Flash memory.

2.6

Flash Chip Enable input (E_F)

The Flash Chip Enable input activates the control logic, input buffers, decoders and sense

amplifiers of the Flash memory component selected. When Chip Enable is Low, V , and

Reset is High, V , the device is in active mode. When Chip Enable is at V the

corresponding Flash memory are deselected, the outputs are high impedance and the

power consumption is reduced to the standby level.

It is not allowed to have E at V and E at V at the same time. Only one memory

component can be enabled at a time.

2.7

2.8

Flash Output Enable inputs (G_F)

The Output Enable pins control the data outputs during Flash memory Bus Read

operations.

Flash Write Enable (W_F)

The Write Enable controls the Bus Write operation of the Flash memory Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.9

Flash Write Protect (WP_F)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is Low, V , Lock-Down is enabled and the protection status of the Locked-

Down blocks cannot be changed. When Write Protect is at High, V , Lock-Down is disabled

and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the

M58PR512J datasheet).

10/23

M36P0R9070E0

Signal descriptions

2.10

Flash Reset (RP_F)

The Reset input provides a hardware reset of the Flash memories. When Reset is at V , the

memory is in Reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current I

. Refer to the M58PRxxxJ datasheet, for the value

DD2

of I

. After Reset all blocks are in the Locked state and the Configuration Register is

DD2

reset. When Reset is at V , the device is in normal operation. Exiting Reset mode the

device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied

to V

(refer to the M58PRxxxJ datasheet).

RPH

2.11

2.12

PSRAM Chip Enable input (E_P)

The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted

(V ), the device is disabled, and goes automatically in low-power Standby mode or Deep

Power-down mode.

PSRAM Write Enable (W_P)

Write Enable, W , controls the Bus Write operation of the PSRAM. When asserted (V ), the

device is in Write mode and Write operations can be performed either to the configuration

registers or to the memory array.

2.13

2.14

2.15

PSRAM Output Enable (G_P)

Output Enable, G , provides a high speed tri-state control, allowing fast read/write cycles to

be achieved with the common I/O data bus.

PSRAM Upper Byte Enable (UB_P)

The Upper Byte En-able, UB , gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a Write or Read operation.

PSRAM Lower Byte Enable (LB_P)

The Lower Byte Enable, LB , gates the data on the Lower Byte Data Inputs/Outputs (DQ0-

DQ7) to or from the lower part of the selected address during a Write or Read operation.

If both LB and UB are disabled (High) during an operation, the device will disable the data

bus from receiving or transmitting data. Although the device will seem to be deselected, it

remains in an active mode as long as E remains Low.

2.16

PSRAM Configuration Register Enable (CR_P)

When this signal is driven High, V , Write operations load either the value of the Refresh

Configuration Register (RCR) or the Bus configuration register (BCR).

11/23

Signal descriptions

M36P0R9070E0

2.17

Deep Power-Down input (DPD_F)

The Deep Power-Down input is used to place the device in a Deep Power-Down

mode.When the device is in Deep Power-Down mode, the memory cannot be modified and

data is protected.

For further details on how the Deep Power-Down input signal works, please refer to the

M58PR512J datasheet.

2.18

2.19

2.20

V_DDFSupply Voltages

provides the power supply to the internal cores of the Flash memory. It is the main

DDF

power supply for all Flash memory operations (Read, Program and Erase).

V_CCPSupply Voltage

provides the power supply to the internal core of the PSRAM device. It is the main

CCP

power supply for all PSRAM operations.

V_DDQSupply Voltage

provides the power supply for the Flash memory and PSRAM I/O pins. This allows all

DDQ

Outputs to be powered independently of the Flash memory and SRAM core power supplies,

and V

CCP

DDF

2.21

V_PPFProgram Supply Voltage

is both a control input and a power supply pin for the Flash memory. The two functions

PPF

are selected by the voltage range applied to the pin.

If V is kept in a low voltage range (0V to V ) V is seen as a control input. In this

PPF

DDQ

case a voltage lower than V

gives an absolute protection against Program or Erase,

PPLK

while V

> V

enables these functions (see the M58PRxxxJ datasheet for the relevant

PPF

PP1

values). V

is only sampled at the beginning of a Program or Erase; a change in its value

PPF

after the operation has started does not have any effect and Program or Erase operations

continue.

If V

is in the range of V

it acts as a power supply pin. In this condition V

must be

PPF

PPH

PPF

stable until the Program/Erase algorithm is completed.

12/23

M36P0R9070E0

Signal descriptions

2.22

V_SSGround

is the common ground reference for all voltage measurements in the Flash (core and

I/O Buffers) and PSRAM chips. It must be connected to the system ground.

Note:

Each Flash memory device in a system should have their supply voltage (V

) and the

DDF

program supply voltage V

decoupled with a 0.1µF ceramic capacitor close to the pin

PPF

(high frequency, inherently low inductance capacitors should be as close as possible to the

package). See Figure 5., AC measurement load circuit. The PCB track widths should be

sufficient to carry the required V

program and erase currents.

PPF

13/23

Functional description

M36P0R9070E0

Functional description

The PSRAM and Flash memory components have separate power supplies but share the

same grounds. They are distinguished by two Chip Enable inputs: E for Flash and E for

the PSRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is a simultaneous read operations on the Flash memory

and the PSRAM which would result in a data bus contention. Therefore it is recommended

to put the other devices in the high impedance state when reading the selected device.

Figure 3.

Functional block diagram

PPF

DDF

DPD

A23-A24

512 Mbit

Flash

Memory

A0-A22

DQ0-DQ15

WAIT

DDQ

CCP

128Mbit

PSRAM

Ai11731

14/23

M36P0R9070E0

Table 2. Main operating modes

Functional description

(1)

A0-

DPD_FWAIT

A17 DQ0- DQ8-

A20- DQ7 DQ15

A22

Operation

E_FG_FW_FRP_F

E_PW_PG_PUB_PLB_PCR_PA19 A18

(2)

(3)

(5)

Bus Read

Bus Write

V_ILV_ILV_IHV_IHde-a⁽⁴⁾

V_ILV_IHV_ILV_IHde-a⁽⁴⁾

V_IL

Data Output

Data Input

(5)

PSRAM must be disabled

DataOutputor

Hi-Z⁽⁶⁾

Address Latch V_ILX V_IHV_IHde-a⁽⁴⁾

Output Disable V_ILV_IHV_IHV_IHde-a⁽⁴⁾Hi-Z

V_IL

Hi-Z

Standby

Reset

V_IH

V_IHde-a⁽⁴⁾Hi-Z

V_ILde-a⁽⁴⁾Hi-Z

Any PSRAM mode is allowed

Deep Power-

Down

V_IH

V_IHa⁽⁷⁾Hi-Z

Hi-Z

Output Output

Valid Valid

Word Read

V_ILV_ILV_ILV_IL

V_IHV_ILV_IHV_ILV_IL

V_ILV_ILV_IHV_IL

Valid

Lower Byte

Read

Output

High-Z

Valid

Upper Byte

Read

Output

High-Z

Valid

Input Input

Valid Valid

Word Write

V_ILV_ILV_IL

V_IHV_ILV_IL

V_ILV_IHV_IL

The Flash memory must

be disabled

Lower Byte

Write

Input

Invalid

Valid

V_IL

Low-

V_IL

Upper Byte

Write

Input

Invalid

Valid

Read CR (CR

Controlled

Method)

00(RCR)1

0(BCR)X1

(DIDR)⁽⁸⁾

BCR/RCR/

_IHV_ILV_ILV_IL

DIDR Content

V_IH

Program CR

(CR

00(RCR) BCR/

10(BCR) RCR

V_IH

High-Z

Controlled)⁽⁹⁾

Data

(8)

No Operation

V_IL

Deep Power-

Down⁽¹⁰⁾

Any Flash memory mode

is allowed

V_IH

High-Z

Hi-Z

Standby

V_IL

1. X = Don't care, de-a = de-asserted, a = asserted, CR = Configuration Register.

2. The DPD_Fsignal polarity depends on the value of the ECR14 bit.

3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.

4. If ECR15 is set to '0', the Flash memory cannot enter the Deep Power-Down mode, even if DPD_Fis asserted.

5. In the Flash memory L can be tied to V_IHif the valid address has been previously latched.

6. Depends on G_F.

7. ECR15 has to be set to ‘1’ for the Flash memory to enter Deep Power-Down.

8. A18 and A19 are used to select the BCR, RCR or DIDR registers.

9. BCR and RCR only.

10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to

‘0’, and E has to be maintained High, V_IH, during Deep Power-Down mode.

15/23

Maximum rating

M36P0R9070E0

Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 3.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

Min

Max

T_A

T_BIAS

T_STG

V_IO

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

–30

°C

–55

125

2.45

11.5

100

Input or Output Voltage

Supply Voltage

–0.2

–1.0

V_DD

V_DDQ

V_PP

Input/Output Supply Voltage

Program Voltage

I_O

Output Short Circuit Current

Time for V_PPat V_PPH

hours

t_VPPH

16/23

M36P0R9070E0

DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 4., Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Table 4.

Operating and AC measurement conditions

Flash memory

Parameter

PSRAM

Unit

Min

Max

Min

Max

V_CCPSupply Voltage

V_DDFSupply Voltage

–

1.95

1.7

–

1.95

–

1.7

8.5

–0.4

–30

_DDQSupply Voltage

V_PPFSupply Voltage (Factory environment)

_PPFSupply Voltage (Application environment)

1.95

1.7

–

1.95

–

9.5

V_DDQ+0.4

–

Ambient Operating Temperature

Load Capacitance (C_L)

–30

°C

Impedance Output (Z₀)

Output Circuit Protection Resistance (R)

Input Rise and Fall Times

Input Pulse Voltages

0 to V_DDQ

V_DDQ/2

0 to V_DDQ

V_DDQ/2

Input and Output Timing Ref. Voltages

Figure 4.

AC measurement I/O waveform

DDQ

AI06161

17/23

DC and AC parameters

Figure 5.

M36P0R9070E0

AC measurement load circuit

CCQ

DEVICE

UNDER

TEST

OUT

AI06162a

(1)

Table 5.

Symbol

Capacitance

Parameter

Test Condition

Min

Max

Unit

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V

C_OUT

V_OUT= 0V

1. Sampled only, not 100% tested.

Please refer to the M58PRxxxJ and M69KB128AB datasheets for further DC and AC

characteristic values and illustrations.

18/23

M36P0R9070E0

Package mechanical

In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®

packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

Figure 6.

TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package

outline

ddd

BALL "B1"

BGA-Z85

1. Drawing is not to scale.

19/23

Package mechanical

Table 6.

M36P0R9070E0

Stacked TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch,

package mechanical data

millimeters

inches

Min

Symbol

Typ

Min

Max

Typ

Max

1.20

0.047

0.20

0.008

0.85

0.35

8.00

6.40

0.033

0.014

0.315

0.252

0.30

7.90

0.40

8.10

0.012

0.311

0.016

0.319

ddd

0.10

0.004

0.437

11.00

8.80

0.80

1.10

0.40

10.90

11.10

0.433

0.346

0.031

0.043

0.016

0.429

20/23

M36P0R9070E0

Part numbering

Table 7.

Ordering information scheme

M36

ZAC

Example:

Device Type

M36 = Multi-Chip Package (Multiple Flash + PSRAM)

Flash 1 Architecture

P = Multi-Level, Multiple Bank, Large Buffer

Flash 2 Architecture

0 = No Die

Operating Voltage

R = V_DDF= V_CCP= V_DDQ= 1.7 to 1.95V

Flash 1 Density

9 = 512 Mbits

Flash 2 Density

0 = No Die

RAM 1 Density

7 = 128 Mbits

RAM 0 Density

0 = No Die

Parameter Blocks Location

E = Even Block Flash Memory Configuration

Product Version

0 = 90nm Flash technology, 96ns speed; PSRAM

Package

ZAC= stacked TFBGA107 C stacked footprint.

Option

Blank = Standard Packing

E = ECOPACK® Package, Standard packing

F = ECOPACK® Package, Tape & Reel packing

Note:

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this

device, please contact the Numonyx Sales Office nearest to you.

21/23

Revision history

M36P0R9070E0

Revision history

Table 8.

Date

Document revision history

Revision

Changes

28-Nov-2005

13-Jul-2006

30-Nov-2007

Initial release.

Document status promoted from Preliminary data to full Datasheet.

Document updated to latest version of M58PRxxxJ datasheet, DC

characteristics tables removed (for values refer to M58PRxxxJ and

M69KB128AB datasheets). PSRAM part replaced by M69KB128AB.

H9 ball is DU in Figure 2: TFBGA connections (top view through

package). T_STGmin and V_PPmax modified in Table 3: Absolute

maximum ratings. Table 2: Main operating modes modified.

PSRAM value for Input Rise and Fall Times filled in in Table 4:

Operating and AC measurement conditions.

Applied Numonyx branding.

22/23

M36P0R9070E0

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

23/23

M36W0R6040T3ZAQE [NUMONYX]

相关型号：

M36W0R6040T3ZAQF

M36W0R6040U4ZAME

M36W0R6040U4ZAMF

M36W0R6040U4ZSF

M36W0R604BT1

M36W0R6050B1

M36W0R6050B1

M36W0R6050B1ZAQE

M36W0R6050B1ZAQE

M36W0R6050B1ZAQF

M36W0R6050B1ZAQF

M36W0R6050B3