M36W832BE85ZA1T_技术文档

M36W832TE

M36W832BE

32 Mbit (2Mb x16, Boot Block) Flash Memory

and 8 Mbit (512Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V

= 2.7V to 3.3V

DDF

DDS

PPF

= V

= 2.7V to 3.3V

DDQF

= 12V for Fast Program (optional)

■ ACCESS TIMES: 70ns and 85ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

FBGA

– Manufacturer Code: 20h

– Top Device Code, M36W832TE: 88BAh

– Bottom Device Code, M36W832BE: 88BBh

Stacked LFBGA66 (ZA)

12 x 8mm

FLASH MEMORY

■ 32 Mbit (2Mb x16) BOOT BLOCK

– 8 x 4 KWord Parameter Blocks (Top or

Bottom Location)

■ PROGRAMMING TIME

– 10µs typical

– Double Word Programming Option

– Quadruple Word Programming Option

■ BLOCK LOCKING

SRAM

■ 8 Mbit (512Kb x 16)

■ ACCESS TIME: 70ns

– All blocks locked at Power up

– Any combination of blocks can be locked

– WPF for Block Lock-Down

■ AUTOMATIC STANDBY MODE

■ PROGRAM and ERASE SUSPEND

■ LOW V

DATA RETENTION: 1.5V

DDS

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ COMMON FLASH INTERFACE

■ SECURITY

– 128 bit user programmable OTP cells

– 64 bit unique device identifier

May 2003

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M36W832TE, M36W832BE

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A19-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Output Enable (GS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Upper Byte Enable (UBS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDF

and V

Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDQF

DDS

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PPF

SSF

and V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SSS

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . 12

SRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Flash Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Flash Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Flash Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . 20

Flash Block Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

V

Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PPF

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 16. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Flash Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19. Flash Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V . . . . . . 36

IL

Figure 15. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write . . . . . . . . . . . . . . . 38

Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low, . . . . . . . . . . . . . . . . 39

Table 21. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 21. SRAM Low V

Figure 22. SRAM Low V

Data Retention AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . 41

Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . 41

Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DDS

Table 22. SRAM Low V

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline. . 42

Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 42

Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 43

Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)44

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Top Boot Block Addresses, M36W832TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. Bottom Boot Block Addresses, M36W832BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Table 31. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX C. FLASH MEMORY FLOWCHARTS and PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . 53

Figure 26. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 27. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 32. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 33. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER

STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. Write State Machine Current/Next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 35. Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 63

5/64

M36W832TE, M36W832BE

SUMMARY DESCRIPTION

The M36W832TE is a low voltage Multiple Memo-

ry Product which combines two memory devices;

a 32 Mbit boot block Flash memory and an 8 Mbit

SRAM. Recommended operating conditions do

not allow both the Flash and the SRAM to be ac-

tive at the same time.

The memory is offered in a Stacked LFBGA66

(12x8mm, 0.8 mm pitch) package and is supplied

with all the bits erased (set to ‘1’).

Table 1. Signal Names

Address Inputs common to the Flash

and SRAM chips

A0-A18

A19-A20

Address Inputs for Flash Chip only

Data Input/Output

DQ0-DQ15

V

DDF

Flash Power Supply

V

Flash Power Supply for I/O Buffers

DDQF

Figure 2. Logic Diagram

Flash Optional Supply Voltage for Fast

Program & Erase

V

PPF

V

DDQF

DDS

V

Flash Ground

SSF

DDS

SSS

V

PPF

DDF

SRAM Power Supply

SRAM Ground

21

16

A0-A20

DQ0-DQ15

NC

Not Connected Internally

EF

GF

Flash control functions

EF

Chip Enable input

WF

GF

Output Enable input

Write Enable input

Reset input

RPF

WPF

WF

RPF

WPF

M36W832TE

M36W832BE

E1S

E2S

GS

Write Protect input

SRAM control functions

E1S, E2S

GS

Chip Enable inputs

WS

Output Enable input

Write Enable input

UBS

LBS

WS

UBS

Upper Byte Enable input

Lower Byte Enable input

LBS

V

SSS

SSF

AI90161b

6/64

M36W832TE, M36W832BE

Figure 3. LFBGA Connections (Top view through package)

7/64

M36W832TE, M36W832BE

Signal Descriptions

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

of Chip Enable or a change of the address is re-

quired to ensure valid data outputs.

SRAM Chip Enable (E1S, E2S). The Chip En-

able inputs activate the SRAM memory control

logic, input buffers and decoders. E1S at V or

IH

Address Inputs (A0-A18). Addresses

A0-A18

E2S at V deselects the memory and reduces the

IL

are common inputs for the Flash and the SRAM

components. The Address Inputs select the cells

in the memory array to access during Bus Read

operations. During Bus Write operations they con-

trol the commands sent to the Command Interface

of the internal state machine. The Flash memory is

accessed through the Chip Enable (EF) and Write

Enable (WF) signals, while the SRAM is accessed

through two Chip Enable signals (E1S and E2S)

and the Write Enable signal (WS).

Address Inputs (A19-A20). Addresses A19-A20

are inputs for the Flash component only. The

Flash memory is accessed through the Chip En-

able (EF) and Write Enable (WF) signals

power consumption to the standby level. E1S and

E2S can also be used to control writing to the

SRAM memory array, while WS remains at V It

IL.

is not allowed to set EF at V E1S at V and E2S

IL,

IL

at V at the same time.

IH

SRAM Write Enable (WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active low.

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM memory. GS is ac-

tive low.

SRAM Upper Byte Enable (UBS). The Upper

Byte Enable enables the upper bytes for SRAM

(DQ8-DQ15). UBS is active low.

SRAM Lower Byte Enable (LBS). The Lower

Byte Enable enables the lower bytes for SRAM

(DQ0-DQ7). LBS is active low.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Write Bus

operation.

Flash Chip Enable (EF). The Chip Enable input

activates the Flash memory control logic, input

buffers, decoders and sense amplifiers. When

V

Supply Voltage (2.7V to 3.3V). V

pro-

DDF

vides the power supply to the internal core of the

Flash Memory device. It is the main power supply

for all operations (Read, Program and Erase).

V

memory I/O pins and V

supply for the SRAM control pins. This allows all

Outputs to be powered independently of the Flash

core power supply, V

V

Chip Enable is at V and Reset is at V the device

IL

IH

is in active mode. When Chip Enable is at V the

IH

and V

Supply Voltage (2.7V to 3.3V).

DDS

DDQF

memory is deselected, the outputs are high imped-

ance and the power consumption is reduced to the

standby level.

Flash Output Enable (GF). The Output Enable

controls the data outputs during the Bus Read op-

eration of the Flash memory.

provides the power supply for the Flash

DDQF

provides the power

DDS

. V

can be tied to

DDF

DDQF

DDS

Flash Write Enable (WF). The Write Enable

controls the Bus Write operation of the Flash

memory’s Command Interface. The data and ad-

dress inputs are latched on the rising edge of Chip

Enable, EF, or Write Enable, WF, whichever oc-

curs first.

V

Program Supply Voltage. V

is both a

PPF

control input and a power supply pin for the Flash

memory. The two functions are selected by the

voltage range applied to the pin. The Supply Volt-

age V

and the Program Supply Voltage V

DDF

PPF

can be applied in any order.

If V is kept in a low voltage range (0V to 3.6V)

V

age lower than V

against program or erase, while V

ables these functions (see Table 15, DC Charac-

teristics for the relevant values). V is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect on Program or Erase,

however for Double or Quadruple Word Program

the results are uncertain.

Flash Write Protect (WPF). Write Protect is an

input that gives an additional hardware protection

PPF

is seen as a control input. In this case a volt-

PPF

for each block. When Write Protect is at V , the

IL

gives an absolute protection

PPLK

Lock-Down is enabled and the protection status of

the block cannot be changed. When Write Protect

> V

en-

PPF

PP1

is at V , the Lock-Down is disabled and the block

IH

PPF

can be locked or unlocked. (refer to Table 6, Read

Protection Register and Protection Register Lock).

Flash Reset (RPF). The Reset input provides a

hardware reset of the Flash memory. When Reset

is at V , the memory is in reset mode: the outputs

IL

are high impedance and the current consumption

is minimized. After Reset all blocks are in the

If V

is in the range 11.4V to 12.6V it acts as a

PPF

power supply pin. In this condition V

stable until the Program/Erase algorithm is com-

pleted (see Table 17 and 18).

must be

PPF

Locked state. When Reset is at V , the device is

IH

in normal operation. Exiting reset mode the device

enters read array mode, but a negative transition

8/64

M36W832TE, M36W832BE

V

and V

Ground. V

and V are the

SSS

pacitor close to the pin. See Figure 9, AC

Measurement Load Circuit. The PCB trace

widths should be sufficient to carry the re-

SSF

SSS

SSF

ground reference for all voltage measurements in

the Flash and SRAM chips, respectively.

quired V

program and erase currents.

PPF

Note: Each device in a system should have V

D-

, V

DF DDQF

and V

decoupled with a 0.1µF ca-

PPF

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate

power supplies and grounds and are distinguished

by three chip enable inputs: EF for the Flash mem-

ory and, E1S and E2S for the SRAM.

Recommended operating conditions do not allow

both the Flash and the SRAM to be in active mode

at the same time. The most common example is

simultaneous read operations on the Flash and

the SRAM which would result in a data bus con-

tention. Therefore it is recommended to put the

SRAM in the high impedance state when reading

the Flash and vice versa (see Table 2 Main Oper-

ation Modes for details).

Figure 4. Functional Block Diagram

V

PPF

DDQF

DDF

EF

GF

WF

RPF

Flash Memory

32 Mbit (x16)

WPF

A19-A20

A0-A18

V

SSF

V

DQ0-DQ15

DDS

E1S

E2S

GS

SRAM

8 Mbit (x16)

WS

UBS

LBS

V

SSS

AI90163

9/64

M36W832TE, M36W832BE

Table 2. Main Operation Modes

Operation

V

EF GF WF RPF WPF

Mode

E1S E2S WS GS UBS LBS DQ15-DQ8 DQ7-DQ0

PPF

V

Read

Write

X

Don’t care

or

SRAM must be disabled

Data Output

Data Input

IL

IH

V

DDF

V

IH

V

IH

IL

V

PPFH

Block

Locking

V

IL

X

Don’t care

SRAM must be disabled

X

IL

IH

Standby

Reset

X

Don’t care

Any SRAM mode is allowed

Hi-Z

IH

V

X

IL

Output

Disable

V

IH

V

IH

V

IH

X

Don’t care

Any SRAM mode is allowed

Hi-Z

IL

X

V

Data out

IH

IL

V

Read

Write

Flash must be disabled

Hi-Z

Data out

Hi-Z

IL

IH

V

IL

Data out

IH

V

X

Data in

IL

V

X

Hi-Z

Data in

Hi-Z

IH

V

IL

Data in

IH

Standby/

Power

Down

X

Hi-Z

IH

Any Flash mode is allowable

V

IL

V

IH

V

IH

X

Hi-Z

V

X

Hi-Z

IH

Data

Retention

Any Flash mode is allowable

V

X

IL

Output

Disable

V

IH

V

IH

Hi-Z

IL

IH

Note: X = V or V , V = 12V ± 5%.

PPFH

IL

IH

10/64

M36W832TE, M36W832BE

Flash Memory Component

against program or erase. All blocks are locked at

Power Up.

The Flash Memory is a 32 Mbit (2 Mbit x 16) device

that can be erased electrically at block level and

programmed in-system on a Word-by-Word basis.

These operations can be performed using a single

low voltage (2.7 to 3.6V) supply. V

drive the I/O pin down to 1.65V. An optional 12V

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

allows to

DDQF

V

power supply is provided to speed up cus-

PPF

tomer programming.

The device includes a Protection Register to in-

crease the protection of a system design. The Pro-

tection Register is divided into two segments, the

first is a 64 bit area which contains a unique device

number written by ST, while the second is a 128 bit

area, one-time-programmable by the user. The

user programmable segment can be permanently

protected. Figure 6, shows the Flash Security

Block and Protection Register Memory Map.

The device features an asymmetrical blocked ar-

chitecture with an array of 71 blocks: 8 Parameter

Blocks of 4 KWords and 63 Main Blocks of 32

KWords. The M36W832TE has the Parameter

Blocks at the top of the memory address space

while the M36W832BE locates the Parameter

Blocks starting from the bottom. The memory

maps are shown in Figure 5, Block Addresses.

The Flash Memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

When V

≤ V

all blocks are protected

PPF

PPLK

Figure 5. Flash Block Addresses

Top Boot Block Addresses

Bottom Boot Block Addresses

1FFFFF

4 KWords

1FF000

1FFFFF

32 KWords

1F8000

1F7FFF

32 KWords

1F0000

Total of 8

4 KWord Blocks

Total of 63

32 KWord Blocks

1F8FFF

4 KWords

1F8000

1F7FFF

32 KWords

1F0000

00FFFF

32 KWords

008000

007FFF

4 KWords

007000

Total of 63

32 KWord Blocks

Total of 8

00FFFF

4 KWord Blocks

32 KWords

008000

007FFF

000FFF

4 KWords

000000

32 KWords

000000

AI90164

Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.

11/64

M36W832TE, M36W832BE

Figure 6. Flash Security Block and Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

85h

84h

Unique device number

81h

(1)

Protection Register Lock

2

1

0

80h

AI90165b

Note: 1. Bit 2 of the Protection Register Lock must not be programmed to 0.

12/64

M36W832TE, M36W832BE

SRAM Component

cess time of 70ns in all conditions. The memory

operations can be performed using a single low

voltage supply, 2.7V to 3.3V, which is the same as

the Flash voltage supply.

The SRAM is an 8 Mbit asynchronous random ac-

cess memory which features a super low voltage

operation and low current consumption with an ac-

Figure 7. SRAM Block Diagram

DATA IN DRIVERS

A0-A10

512Kb x 16

RAM Array

DQ0-DQ7

2048 x 4096

DQ8-DQ15

COLUMN DECODER

UBS

WS

E2S

E1S

A11-A18

GS

LBS

E2S

POWER-DOWN

CIRCUIT

E1S

UBS

LBS

AI07964

13/64

M36W832TE, M36W832BE

OPERATING MODES

Flash Bus Operations

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Main Operation Modes, for a

summary.

See Figures 11 and 12, Flash Write AC Wave-

forms, and Tables 17 and 18, Write AC Character-

istics, for details of the timing requirements.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at V .

IH

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

when Chip Enable is at V and the device is in

IH

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

able must be at V in order to perform a read op-

IL

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 10, Flash Read Mode AC Waveforms, and

Table 16, Flash Read AC Characteristics, for de-

tails of when the output becomes valid.

V

during a program or erase operation, the de-

IH

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V , and the supply

current is reduced to I

IL

. The data Inputs/Out-

DD1

Read mode is the default state of the device when

exiting Reset or after power-up.

puts will still output data if a bus Read operation is

in progress.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

Reset. During Reset mode when Output Enable

is Low, V , the memory is deselected and the out-

IL

puts are high impedance. The memory is in Reset

and Write Enable are at V with Output Enable at

mode when Reset is at V . The power consump-

IL

V . Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

IH

able inputs. If Reset is pulled to V

during a Pro-

SSF

gram or Erase, this operation is aborted and the

memory content is no longer valid.

14/64

M36W832TE, M36W832BE

Flash Command Interface

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See Table 4, Command

Codes, for a summary of the commands and see

Appendix 31, Table 34, Write State Machine Cur-

rent/Next, for a summary of the Command Inter-

face.

Read Memory Array Command. The

Read

command returns the memory to its Read mode.

One Bus Write cycle is required to issue the Read

Memory Array command and return the memory to

Read mode. Subsequent read operations will read

the addressed location and output the data. When

a device Reset occurs, the memory defaults to

Read mode.

Read Status Register Command. The Status

Register indicates when a program or erase oper-

ation is complete and the success or failure of the

operation itself. Issue a Read Status Register

command to read the Status Register’s contents.

Subsequent Bus Read operations read the Status

Register at any address, until another command is

issued. See Table 11, Status Register Bits, for de-

tails on the definitions of the bits.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

LKO

DDF

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 3, Flash Com-

mand Codes, in conjunction with the following text

descriptions.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Read Electronic Signature Command. The

Read Electronic Signature command reads the

Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 5, 6 and 7 for

the valid address.

Table 3. Flash Command Codes

Hex Code

01h

Command

Block Lock confirm

10h

Program

20h

Erase

2Fh

Block Lock-Down confirm

30h

40h

50h

55h

56h

Double Word Program

Program

Read CFI Query Command. The Read Query

Command is used to read data from the Common

Flash Interface (CFI) Memory Area, allowing pro-

gramming equipment or applications to automati-

cally match their interface to the characteristics of

the device. One Bus Write cycle is required to is-

sue the Read Query Command. Once the com-

mand is issued subsequent Bus Read operations

read from the Common Flash Interface Memory

Area. See Appendix B, Common Flash Interface,

Tables 28, 29, 30, 31, 32 and 33 for details on the

information contained in the Common Flash Inter-

face memory area.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all the

bits within the selected block to ’1’. All previous

data in the block is lost. If the block is protected

then the Erase operation will abort, the data in the

block will not be changed and the Status Register

will output the error.

Clear Status Register

Reserved

Quadruple Word Program

Block Lock, Block Unlock, Block Lock-

Down

60h

70h

90h

98h

B0h

C0h

Read Status Register

Read Electronic Signature

Read CFI Query

Program/Erase Suspend

Protection Register Program

Program/Erase Resume, Block Unlock

confirm

D0h

FFh

Two Bus Write cycles are required to issue the

command.

Read Memory Array

■ The first bus cycle sets up the Erase command.

15/64

M36W832TE, M36W832BE

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V . As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 27, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Quadruple Word Program Command. This

feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel.The four words must differ only for the

addresses A0 and A1. Programming should not be

Erase aborts if Reset turns to V . As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

IL

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 8, Flash Program, Erase Times and

Program/Erase Endurance Cycles.

See Appendix C, Figure 30, Erase Flowchart and

Pseudo Code, for a suggested flowchart for using

the Erase command.

attempted when V_PPFis not at V

.

PPH

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple Word

Program Command.

■ The second bus cycle latches the Address and

Program Command. The memory array can be

programmed word-by-word. Two bus write cycles

are required to issue the Program Command.

the Data of the first word to be written.

■ The first bus cycle sets up the Program

command.

■ The third bus cycle latches the Address and the

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

the Data of the third word to be written.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 8, Flash Program,

Erase Times and Program/Erase Endurance Cy-

cles.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V . As data integrity

IL

Programming aborts if Reset goes to V . As data

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 28, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 26, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Clear Status Register Command. The

Clear

Double Word Program Command. This feature

is offered to improve the programming throughput,

writing a page of two adjacent words in paral-

lel.The two words must differ only for the address

A0. Programming should not be attempted when

Status Register command can be used to reset

bits 1, 3, 4 and 5 in the Status Register to ‘0’. One

bus write cycle is required to issue the Clear Sta-

tus Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

V

is not at V

.

PPF

PPH

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

Program/Erase Suspend Command. The Pro-

gram/Erase Suspend command is used to pause

a Program or Erase operation. One bus write cycle

is required to issue the Program/Erase command

and pause the Program/Erase controller.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

16/64

M36W832TE, M36W832BE

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Double Word Program, Quadruple

Word Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

Register error. The protection of the Protection

Register is not reversible.

The Protection Register Program cannot be sus-

pended.

Block Lock Command. The Block Lock com-

mand is used to lock a block and prevent Program

or Erase operations from changing the data in it.

All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

■ The second Bus Write cycle latches the block

Chip Enable to V . Program/Erase is aborted if

address.

IH

Reset turns to V .

IL

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Lock command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

Block Unlock Command. The Blocks Unlock

command is used to unlock a block, allowing the

block to be programmed or erased. Two Bus Write

cycles are required to issue the Blocks Unlock

command.

See Appendix C, Figure 29, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 31, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Suspend com-

mand.

Program/Erase Resume Command. The Pro-

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

a

Program/Erase Suspend operation has paused it.

One Bus Write cycle is required to issue the com-

mand. Once the command is issued subsequent

Bus Read operations read the Status Register.

See Appendix C, Figure 29, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 31, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Resume com-

mand.

Protection Register Program Command. The

Protection Register Program command is used to

Program the 128 bit user One-Time-Programma-

ble (OTP) segment of the Protection Register. The

segment is programmed 16 bits at a time. When

shipped all bits in the segment are set to ‘1’. The

user can only program the bits to ‘0’.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Unlock command. Refer to the “Flash

Block Locking” section, for a detailed explanation.

Block Lock-Down Command. A locked block

cannot be Programmed or Erased, or have its pro-

tection status changed when WPF is low, V .

IL

When WPF is high, V the Lock-Down function is

IH,

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

disabled and the locked blocks can be individually

unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 10 shows the protection sta-

tus after issuing a Block Lock-Down command.

The segment can be protected by programming bit

1 of the Protection Lock Register (see Figure 6,

Flash Security Block and Protection Register

Memory Map). Attempting to program a previously

protected Protection Register will result in a Status

17/64

M36W832TE, M36W832BE

Refer to the “Flash Block Locking” section for a de-

tailed explanation.

Table 4. Flash Commands

Bus Write Operations

3rd Cycle

Commands

1st Cycle

2nd Cycle

4th Cycle

5th Cycle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

Read Memory

Array

1+ Write

X

FFh

RA

X

RD

SRD

IDh

Read

Read Status

Register

70h Read

90h Read

Read Electronic

Signature

(2)

1+ Write

SA

Read CFI Query

Erase

X

98h Read QA

20h Write BA

40h

QD

2

Write

D0h

Program

2

Write

X

or

Write PA

PD

10h

Double Word

3

5

Write

X

30h Write PA1 PD1 Write PA2 PD2

(3)

Program

Quadruple Word

(6)

Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

56h

(4)

Program

Clear Status

Register

1

Write

X

50h

Program/Erase

Suspend

B0h

D0h

Program/Erase

Resume

Block Lock

2

Write

X

60h Write BA

60h Write

01h

D0h

2Fh

Block Unlock

Block Lock-Down

BA

60h Write BA

Protection

Register Program

2

Write

X

C0h Write

PRD

PRA

Note: X = Don’t Care.

1. The signature addresses are listed in Tables 5, 6 and 7.

2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

5. 55h is reserved.

6. To be characterized.

18/64

M36W832TE, M36W832BE

Table 5. Flash Read Electronic Signature

Code

Device

EF GF WF A0 A1 A2-A7

A8-A11

A12-A20 DQ0-DQ7 DQ8-DQ15

Manufacture

Code

V

IL

V

IH

V

IL

V

IL

V

0

Don’t Care

20h

00h

IL

V

M36W832TE

M36W832BE

0

Don’t Care

BAh

BBh

88h

IL

IH

IL

Device

Code

V

IL

IH

IL

Note: RPF = V

.

IH

Table 6. Flash Read Block Lock Signature

Block Status

Locked Block

EF

GF WF A0

A1 A2-A7

A8-A20

A12-A20

DQ0 DQ1 DQ2-DQ15

V

IL

V

0

Don’t Care Block Address

1

0

00h

IL

IH

IL

IH

V

IL

V

Unlocked Block

Locked-Down

Block

(1)

V

IL

V

IH

V

IL

V

IH

0

Don’t Care Block Address

1

00h

IL

X

Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section.

Table 7. Flash Read Protection Register and Lock Register

Word

EF GF WF A0-A7

A8-A20

DQ0

DQ1

DQ2

Don’t Care

DQ3-DQ7 DQ8-DQ15

OTP Prot.

data

Don’t

V

IL

V

IH

Lock

80h Don’t Care Don’t Care

Don’t Care

Care

IL

See note (1)

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don’t Care

82h Don’t Care

83h Don’t Care

84h Don’t Care

ID data

IL

ID data

85h Don’t Care OTP data

86h Don’t Care OTP data

87h Don’t Care OTP data

88h Don’t Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

19/64

M36W832TE, M36W832BE

Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles

Flash Device

Parameter

Test Conditions

Unit

Min

Typ

10

Max

200

5

V

PPF

= V

DDF

Word Program

µs

V

= 12V ±5%

= V

Double Word Program

10

µs

PPF

V

Quadruple Word Program

10

µs

(1)

s

0.16/0.08

0.32

Main Block Program

Parameter Block Program

Main Block Erase

5

s

PPF

DDF

V

= 12V ±5%

4

s

PPF

0.02/0.01

V

= V

0.04

1

4

s

PPF

DDF

V

= 12V ±5%

10

s

PPF

= V

V

1

s

DD DDF

= 12V ±5%

= V

0.4

s

PPF

Parameter Block Erase

V

PPF

DDF

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands

respectively.

20/64

M36W832TE, M36W832BE

Flash Block Locking

propriate software commands. A locked block can

be unlocked by issuing the Unlock command.

The Flash Memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

Lock-Down State. Blocks that are Locked-Down

(state (0,1,x))are protected from program and

erase operations (as for Locked blocks) but their

protection status cannot be changed using soft-

ware commands alone. A Locked or Unlocked

block can be Locked-Down by issuing the Lock-

Down command. Locked-Down blocks revert to

the Locked state when the device is reset or pow-

ered-down.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

The Lock-Down function is dependent on the WPF

■ V

PPF

≤ V

- the third level offers a complete

PPLK

input pin. When WPF=0 (V ), the blocks in the

IL

hardware protection against program and erase

on all blocks.

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WPF=1 (V ) the Lock-Down function is disabled

IH

The protection status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 10, de-

fines all of the possible protection states (WPF,

DQ1, DQ0), and Appendix C, Figure 32, shows a

flowchart for the locking operations.

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

(1,1,1) and unlocked (1,1,0) as desired while WPF

remains high. When WPF is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WPF was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

Reading a Block’s Lock Status. The lock status

of every block can be read in the Read Electronic

Signature mode of the device. To enter this mode

write 90h to the device. Subsequent reads at the

address specified in Table 6, will output the protec-

tion status of that block. The lock status is repre-

sented by DQ0 and DQ1. DQ0 indicates the Block

Lock/Unlock status and is set by the Lock com-

mand and cleared by the Unlock command. It is

also automatically set when entering Lock-Down.

DQ1 indicates the Lock-Down status and is set by

the Lock-Down command. It cannot be cleared by

software, only by a hardware reset or power-down.

Locking Operations During Erase Suspend.

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to Appendix D, Com-

mand Interface and Program/Erase Controller

State, for detailed information on which com-

mands are valid during erase suspend.

The following sections explain the operation of the

locking system.

Locked State. The default status of all blocks on

power-up or after a hardware reset is Locked

(states (0,0,1) or (1,0,1)). Locked blocks are fully

protected from any program or erase. Any pro-

gram or erase operations attempted on a locked

block will return an error in the Status Register.

The Status of a Locked block can be changed to

Unlocked or Lock-Down using the appropriate

software commands. An Unlocked block can be

Locked by issuing the Lock command.

Unlocked State. Unlocked blocks (states (0,0,0),

(1,0,0) (1,1,0)), can be programmed or erased. All

unlocked blocks return to the Locked state after a

hardware reset or when the device is powered-

down. The status of an unlocked block can be

changed to Locked or Locked-Down using the ap-

21/64

M36W832TE, M36W832BE

Table 9. Block Lock Status

Item

Address

Data

Block Lock Configuration

LOCK

Block is Unlocked

Block is Locked

DQ0=0

DQ0=1

DQ1=1

xx002

Block is Locked-Down

Table 10. Protection Status

Current

(1)

Next Lock Status

(1)

Lock Status

(WPF, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

After

WPF transition

Current State

Allowed

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.

3. A WPF transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

22/64

M36W832TE, M36W832BE

Flash Status Register

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

or Output Enable returns to V . Either Chip En-

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

IH

The bits in the Status Register are summarized in

Table 11, Status Register Bits. Refer to Table 11

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

V

Status (Bit 3). The V

Status bit can be

PPF

used to identify an invalid voltage on the V

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

PPF

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

cur if V

becomes invalid during an operation.

PPF

When the V

Status bit is Low (set to ‘0’), the

PPF

voltage on the V

voltage; when the V

PPF

‘1’), the V

pin has a voltage that is below the

PPF

V

Lockout Voltage, V

PPF

tected and Program and Erase operations cannot

be performed.

Once set High, the V

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

23/64

M36W832TE, M36W832BE

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 11. Flash Status Register Bits

Bit

Name

Logic Level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PPF

V

PPF

Status

3

2

’0’

’1’

’0’

’1’

’0’

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

24/64

M36W832TE, M36W832BE

SRAM Operations

A Write operation is initiated when E1S is at V ,

IL

E2S is at V and WS is at V . The data is latched

IH

IL

There are five standard operations that control the

SRAM component. These are Bus Read, Bus

Write, Standby/Power-down, Data Retention and

Output Disable. A summary is shown in Table 2,

Main Operation Modes

Read. Read operations are used to output the

contents of the SRAM Array.

o the falling edge of E1S, the rising edge of E2S or

the falling edge of WS, whichever occurs last. The

Write cycle is terminated on the rising edge of

E1S, the rising edge of WS or the falling edge of

E2S, whichever occurs first.

If the Output is enabled (E1S=V , E2S=V and

IL

IH

GS=V ), then WS will return the outputs to high

IL

The SRAM is in Byte Read mode whenever Write

impedance within t

of its falling edge. Care

WLQZ

Enable, WS, is at V , Output Enable, GS, is at V ,

IH

IL

must be taken to avoid bus contention in this type

of operation. The Data input must be valid for t

Chip Enable, E1S, is at V , Chip Enable, E2S, is

IL

D-

at V , and UBS or LBS is at V .

IH

IL

before the rising edge of Write Enable, for

VWH

t

The SRAM is in Word Read mode whenever Write

Enable, WS, is at V , Output Enable, GS, is at V ,

before the rising edge of E1S or for t

DVE1H

DVE2L

IH

IL

before the falling edge of E2S, whichever occurs

first, and remain valid for t , t or t

Byte Enable inputs UBS and LBS are both at V

and the two Chip Enable inputs, E1S, and E2S are

Don’t Care.

WHDX E1HAX

E2LAX

(see Table 21, Figure 17, 18, 19 and 20).

Standby/Power-Down. The SRAM component

has a chip enabled power-down feature which in-

vokes an automatic standby mode (see Table 20

and Figure 16). The SRAM is in Standby mode

whenever either Chip Enable is deasserted, E1S

Valid data will be available on the output pins after

a time of t

after the last stable address. If the

AVQV

Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (t

, t

, or t

) rath-

E1LQV E2HQV

GLQV

at V or E2S at V .

IH

IL

er than the address. Data out may be indetermi-

Data Retention. The SRAM data retention per-

formance as V goes down to V are de-

nate at t , t and t , but data lines

E1LQX E2HQX

GLQX

DDS

DR

will always be valid at t

14 and 15).

Write. Write operations are used to write data to

the SRAM. The SRAM is in Write mode whenever

WS and E1S are at V , and E2S is at V . Either

the Chip Enable inputs, E1S and E2S, or the Write

Enable input, WS, must be deasserted during ad-

dress transitions for subsequent write cycles.

(see Table 20, Figures

AVQV

scribed in Table 22, Figures 21 and 22, SRAM

Low V Data Retention AC Waveforms, E1S

DDS

Controlled and SRAM Low V

Data Retention

DDS

AC Waveforms, E2S Controlled, respectively.

Output Disable. The data outputs are high im-

IL

IH

pedance when the Output Enable, GS, is at V

IH

with Write Enable, WS, at V .

IH

25/64

M36W832TE, M36W832BE

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 12. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–55

–0.5

–0.6

–0.5

Max

85

(1)

T

°C

V

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Flash Supply Voltage

Program Voltage

T

125

150

BIAS

T

STG

V

IO

V

+0.5

DDQF

V

, V

4.1

13

V

DDF DDQF

V

PPF

V

SRAM Supply Voltage

3.6

V

DDS

Note: 1. Depends on range.

26/64

M36W832TE, M36W832BE

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 13,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

The operating and AC measurement parameters

given below (see Table 13, Operating and AC

Measurement Conditions) are those of the stand-

alone Flash and SRAM devices and some differ

from those of the stacked product.

Table 13. Operating and AC Measurement Conditions

SRAM

70

Flash Memory

70 / 85

Parameter

Units

Min

–

Max

–

Min

2.7

–

Max

3.6

–

V

Supply Voltage

V

DDF

Supply Voltage

–

DDQF

Supply Voltage

2.7

– 40

3.3

85

V

DDS

Ambient Operating Temperature

– 40

85

°C

pF

ns

V

Load Capacitance (C )

50

L

Input Rise and Fall Times

3.3

5

0 to V

DDQF

Input Pulse Voltages

DDQF

V

/2

DDQF

V

/2

DDQF

Input and Output Timing Ref. Voltages

V

Figure 8. AC Measurement I/O Waveform

Figure 9. AC Measurement Load Circuit

V

DDQF

V

DDQ

V

/2

DDQ

V

DDQF

V

0V

DDF

25kΩ

AI90166

DEVICE

UNDER

TEST

Note: V

means V

= V

DDQF DDS

DDQ

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI90167

L

Table 14. Device Capacitance

Symbol

Parameter

Test Condition

Max

12

Unit

C

IN

V

IN

= 0V, f=1 MHz

Input Capacitance

Output Capacitance

pF

C

OUT

V

OUT

16

Note: Sampled only, not 100% tested.

27/64

M36W832TE, M36W832BE

Table 15. DC Characteristics

Symbol

Parameter

Device

Test Condition

Min

Typ

Max

±2

Unit

µA

Flash &

SRAM

I

0V ≤ V ≤ V

Input Leakage Current

LI

IN

DDQF

0V ≤ V

≤ V

Flash

±10

±1

µA

OUT

DDQF,

I

Output Leakage Current

LO

≤ V

OUT

SRAM

µA

SRAM Outputs Hi-Z

EF = V ± 0.2V

DDQF

Flash

15

8

50

µA

V

= V

max

DDQF

DDF

E1S ≥ V

– 0.3V

DDS

or E2S ≤ 0.3V

≥ V – 0.3V or V ≤ 0.3V

DDS

V

IN

25

µA

f = f

(Address and Data

inputs only)

max

I

V

DD

Standby Current

DDS

SRAM

f = 0 (GS, WS, UBS and LBS)

E1S ≥ V – 0.3V

DDS

or E2S ≤ 0.3V

≥ V – 0.3V or V ≤ 0.3V

DDS

8

25

µA

V

IN

f = 0, V

= V

max

DDS

Supply Current

(Reset)

I

RPF = V

± 0.2V

Flash

15

7

50

15

µA

DDD

SSF

V

OUT

= 0mA

, CMOS levels

f = f

= 1/t

mA

max

AVAV

V

DDS

= V

max

DDS

I

Supply Current

SRAM

DD

I

= 0 mA, f = 1MHz, CMOS

Levels

OUT

1

9

2

mA

Supply Current

(Read)

I

EF = V , GF = V f = 5 MHz

IL IH,

Flash

18

10

20

DDR

Program in progress

= 12V ± 5%

5

V

PPF

Supply Current

(Program)

DDW

Program in progress

= V

10

5

V

PPF

DDF

Erase in progress

= 12V ± 5%

V

PPF

Supply Current

(Erase)

I

Flash

DDE

Erase in progress

10

V

= V

PPF

DDF

Supply Current

(Program/Erase

Suspend)

EF = V

Erase suspended

± 0.2V,

DDQF

I

15

50

µA

DDES

I

V

> V

400

5

µA

PP

PPF

DDF

Program Current

(Read or Standby)

Flash

I

≤ V

1

PP1

PPF

Program Current

(Reset)

I

RPF = V

± 0.2V

5

10

5

µA

mA

µA

PP2

SSF

Program in progress

= 12V ± 5%

1

V

PPF

Program Current

(Program)

I

Flash

PPW

Program in progress

= V

V

PPF

DDF

28/64

M36W832TE, M36W832BE

Symbol

Parameter

Device

Test Condition

Min

Typ

Max

Unit

Erase in progress

3

10

mA

V

= 12V ± 5%

PPF

Program Current

(Erase)

I

Flash

PPE

Erase in progress

= V

1

5

µA

V

PPF

DDF

Flash &

SRAM

V

= V

≥ 2.7V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.3

0.8

IL

DDQF

DDS

0.7V

V

Flash &

SRAM

DD

DDQF

+0.4

V

= V

V

IH

DDS

QF

V

= V

= V min

DDS DD

Flash &

SRAM

DDQF

V

0.1

V

OL

I

OL

= 100µA

= V

= V min

DD

Flash &

SRAM

DDQF

DDS

V

2.4

V

OH

I

= –100µA

OH

Program Voltage

(Program or Erase

operations)

V

Flash

1.65

3.6

12.6

1

V

PPL

Program Voltage

(Program or Erase

operations)

V

PPH

11.4

Program Voltage

(Program and Erase

lock-out)

V

PPLK

V

DDF

Supply Voltage

V

2

(Program and Erase

lock-out)

LKO

29/64

M36W832TE, M36W832BE

Figure 10. Flash Read Mode AC Waveforms

tAVAV

VALID

A0-A20

tAVQV

tAXQX

EF

tELQV

tELQX

tEHQX

tEHQZ

GF

tGLQV

tGHQX

tGHQZ

tGLQX

DQ0-DQ15

VALID

ADDR. VALID

CHIP ENABLE

OUTPUTS

ENABLED

DATA VALID

STANDBY

AI90168b

Table 16. Flash Read AC Characteristics

Flash Device

Symbol

Alt

Parameter

Unit

70

85

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

ns

AVAV

RC

t

ACC

Max

Min

Max

Min

Max

AVQV

(1)

t

Address Transition to Output Transition

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

0

t

OH

AXQX

(1)

t

ns

t

OH

EHQX

(1)

t

20

70

0

20

85

0

t

HZ

EHQZ

(2)

(1)

(2)

(1)

t

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

LZ

t

0

t

OH

GHQX

GHQZ

t

20

0

20

0

DF

t

Max

Min

t

OE

GLQV

GLQX

t

OLZ

Note: 1. Sampled only, not 100% tested.

2. GF may be delayed by up to t

- t

after the falling edge of EF without increasing t

.

ELQV

ELQV GLQV

30/64

M36W832TE, M36W832BE

Figure 11. Flash Write AC Waveforms, Write Enable Controlled

31/64

M36W832TE, M36W832BE

Table 17. Flash Write AC Characteristics, Write Enable Controlled

Flash Device

Symbol

Alt

Parameter

Unit

70

45

0

85

45

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

DVWH

t

ELWL

t

70

85

ELQV

(1,2)

Output Valid to V

Low

0

t

PPF

QVVPL

t

Output Valid to Write Protect Low

V High to Write Enable High

PPF

QVWPL

(1)

t

200

0

200

0

t

VPS

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

WHDX

WHEH

AH

DH

CH

t

0

t

25

20

25

45

25

20

25

45

WHEL

t

WHGL

WHWL

t

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V

< 3.6V).

PPF

32/64

M36W832TE, M36W832BE

Figure 12. Flash Write AC Waveforms, Chip Enable Controlled

33/64

M36W832TE, M36W832BE

Table 18. Flash Write AC Characteristics, Chip Enable Controlled

Flash Device

Symbol

Alt

Parameter

Unit

70

85

45

0

t

WC

Write Cycle Time

Min

70

45

0

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

DH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

EHAX

t

0

EHDX

t

CPH

25

0

25

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

45

70

45

85

ELEH

t

ELQV

(1,2)

Output Valid to V

Low

Min

0

ns

t

PPF

QVVPL

t

Data Valid to Write Protect Low

V High to Chip Enable High

PPF

QVWPL

(1)

t

200

0

200

0

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

WLEL

t

45

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V

< 3.6V).

PPF

34/64

M36W832TE, M36W832BE

Figure 13. Flash Power-Up and Reset AC Waveforms

WF,EF,GF

tPHWL

tPHEL

tPHGL

tPHEL

tPHGL

RPF

tVDHPH

tPLPH

VDDF, VDDQF

Power-Up

Reset

AI90171

Table 19. Flash Power-Up and Reset AC Characteristics

Flash Device

Symbol

Parameter

Test Condition

Unit

70

85

During

Program and

Erase

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip Enable Low,

Output Enable Low

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.

35/64

M36W832TE, M36W832BE

Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

IL

tAVAV

A0-A18

VALID

tAVQV

tAXQX

DQ0-DQ15

DATA VALID

AI90180

Note: E1S = Low, E2S = High, GS = Low, WS = High.

Figure 15. SRAM Read AC Waveforms, GS Controlled

tAVAV

A0-A18

E1S

VALID

tE1LQV

tE1HQZ

tE2LQZ

tE1LQX

tE2HQV

E2S

tE2HQX

tGLQV

tGHQZ

GS

tGLQX

DQ0-DQ15

DATA VALID

tPU

tPD

50%

V

DDS

AI07965

Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1S goes Low and E2S goes High.

Figure 16. SRAM Standby AC Waveforms

E1S

E2S

tPU

tPD

I

DD

50%

I

DDS

AI07985

36/64

M36W832TE, M36W832BE

Table 20. SRAM Read AC Characteristics

SRAM

Unit

Symbol

Alt

Parameter

Min

Max

t

Read Cycle Time

70

ns

AVAV

RC

t

ACC

Address Valid to Output Valid

70

AVQV

t

OH

Address Transition to Output Transition

10

AXQX

t

E1HQZ

t

Chip Enable 1 High to Output Hi-Z

25

70

ns

CHZ1

E2LQZ

t

E1LQV

E2HQV

Chip Enable 1 Low or Chip Enable 2 High to Output Valid

Chip Enable 1 Low to Output Transition

ACS1

t

E1LQX

t

10

CLZ1

t

E2HQX

t

OHZ

Output Enable High to Output Hi-Z

25

35

ns

GHQZ

t

Output Enable Low to Output Valid

GLQV

OE

t

OLZ

Output Enable Low to Output Transition

Chip Enable 1 High or Chip Enable 2 Low to Power Down

5

0

GLQX

(1)

70

t

PD

(1)

Chip Enable 1 Low or Chip Enable 2 High to Power Up

ns

PU

Note: 1. Sampled only. Not 100% tested.

Figure 17. SRAM Write AC Waveforms, E1 or E2S Controlled

S

tAVAV

ADDRESS VALID

A0-A18

tAVE1H

tAVE2L

tAVE1L

tAVE2H

tE1LE1H

tE1HAX

E1S

E2S

tE2HE2L

tE2LAX

tWLE1H

tWLE2L

WS

tDVE1H

tDVE2L

tE1HDZ

tE2LDZ

DQ0-DQ15

INPUT VALID

AI07966

Note: 1. DQ0-DQ15 are high impedance if GS = V

.

IH

2. If E1S or E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

37/64

M36W832TE, M36W832BE

Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write

tAVAV

A0-A18

VALID

tAVWH

tE1LWH

tE2HWH

tWHAX

E1S

E2S

tAVWL

tWLWH

WS

GS

tGHQZ

tDVWH

INPUT VALID

tWHDZ

Note 2

DQ0-DQ15

AI07967

Note: 1. DQ0-DQ15 are high impedance if GS = V

.

IH

2. If E1S or E2s and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

A0-A18

VALID

tAVWH

tE1LWH

tE2HWH

tWHAX

E1S

E2S

tAVWL

tWLWH

WS

tWHQX

tWHDZ

tWLQZ

Note 3

tDVWH

INPUT VALID

DQ0-DQ15

AI07968

Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

2. The minimum write cycle time (t ) is the sum of t and t

.

DVWH

AVAV

WLQZ

3. During this period, the I/O pins are in output mode and input signals should not be applied.

38/64

M36W832TE, M36W832BE

Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low,

tAVAV

VALID

A0-A18

tAVBH

E1S

E2S

tBLBH

tBHAX

UBS, LBS

tAVWL

WS

tBHQX

tBHDZ

tWLQZ

Note 1

tDVBH

INPUT VALID

DQ0-DQ15

AI07969

Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.

39/64

M36W832TE, M36W832BE

Table 21. SRAM Write AC Characteristics

SRAM

Symbol

Alt

Parameter

Unit

Min

Max

t

WC

Write Cycle Time

70

ns

AVAV

t

,

AVE1L

t

,

t

AS

Address Valid to Beginning of Write

0

ns

AVE2H

AVWL,

t

,

AVE1H

Address Valid to Chip Enable 1 Low or Chip Enable 2

High

t

60

AVE2L

AW

t

AVBH

t

Address Valid to Write Enable High

UBS, LBS Low to UBS, LBS High

60

ns

AVWH

AW

t

BLBH

BW

t

,

DVE1H

t

DVE2L

t

Input Valid to End of Write

30

0

ns

DW

t

DVWH

t

DVBH

,

E1HAX

t

E2LAX

End of Write to Address Change

WR

t

WHAX

t

BHAX

,

E1HDZ

t

,

E2LDZ

t

Address Transition to End of Write

Chip Enable 1 Low to End of Write

0

ns

HD

WHDZ

BHDZ

t

E1LE1H,

t

60

CW1

t

E1LWH

t

E2HE2L,

t

Chip Enable 2 High to End of Write

Output Enable High to Output Hi-Z

Write Enable High to Input Transition

Write Enable Low to Output Hi-Z

ns

CW2

t

E2HWH

t

25

20

GHQZ

GHZ

t

WHQX

t

10

50

DH

BHQX

t

WLQZ

WHZ

t

WLWH

t

Write Enable Pulse Width

ns

WLE1H

WP

t

WLE2L

40/64

M36W832TE, M36W832BE

Figure 21. SRAM Low V

Data Retention AC Waveforms, E1S Controlled

DDS

DATA RETENTION MODE

V

DDS

V

DDS (min)

>

V

1.5V

DR

tCDR

tR

E1S

>

<

0.3V and E2S 0.3V

E1S

V

-

DDS

>

or E2S

V

-0.3V

DDS

AI07970

Figure 22. SRAM Low V

Data Retention AC Waveforms, E2S Controlled

DDS

DATA RETENTION MODE

V

DDS

V

DDS (min)

>

V

1.5V

DR

tCDR

tR

<

E2S 0.3V

E2S

AI07982

Table 22. SRAM Low V

Data Retention Characteristic

DDS

Symbol

Parameter

Test Condition

Min

Typ

Max Unit

V

DDS

= 1.5V, E1S ≥ V – 0.3V,

DDS

I

V

IN

≥ V

– 0.3V or V ≤ 0.3V

DDS IN

Supply Current (Data Retention)

4

20

µA

DDDR

No input may exceed V

+ 0.3V

DDS

V

Supply Voltage (Data Retention)

Chip Disable to Power Down

Operation Recovery Time

1.5

0

3.3

V

DR

t

ns

CDR

t

R

70

Note: 1. Sampled only. Not 100% tested.

41/64

M36W832TE, M36W832BE

PACKAGE MECHANICAL

Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline

D

D2

D1

SE

b

E

E1

BALL "A1"

e

ddd

FE

FD

SD

e

A

A2

A1

BGA-Z12

Note: Drawing is not to scale.

Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data

millimeters

inches

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

b

1.400

0.0551

0.300

0.0118

1.100

0.0433

0.400

12.000

5.600

8.800

0.300

0.500

0.0157

0.4724

0.2205

0.3465

0.0118

0.0197

D

–

D1

D2

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.600

1.200

0.400

–

0.3150

0.2205

0.0315

0.0630

0.0472

0.0157

–

E1

e

FD

FE

SD

SE

42/64

M36W832TE, M36W832BE

Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

43/64

M36W832TE, M36W832BE

Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

44/64

M36W832TE, M36W832BE

PART NUMBERING

Table 24. Ordering Information Scheme

Example:

M36 W 8 32T E

70 ZA

6

T

Device Type

M36 = MMP (Flash + SRAM)

Operating Voltage

W = V

= 2.7V to 3.3V, V

= V

= 2.7V to 3.3V

DDQF

DDF

DDS

SRAM Chip Size & Organization

8 = 8 Mbit (512Kb x 16 bit)

Flash Chip Size & Organization

32T = 32 Mbit (x16), Boot Block, Top configuration

32B = 32 Mbit (x16), Boot Block, Bottom configuration

SRAM Component

E = 8Mb, 0.16µm, 70ns, 3.0V

Speed

70 = 70ns

85 = 85ns

Package

ZA = LFBGA66: 12x8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70°C

6 = –40 to 85°C

Option

T = Tape & Reel packing

S = Special Tape

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 25. Daisy Chain Ordering Scheme

Example:

M36W832TE

-ZA T

Device Type

M36W832TE

Daisy Chain

-ZA = LFBGA66: 12x8mm, 0.8mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

45/64

M36W832TE, M36W832BE

APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES

Table 26. Top Boot Block Addresses,

M36W832TE

34

32

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F00000-F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

35

Size

(KWord)

#

Address Range

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

0

4

1FF000-1FFFFF

1FE000-1FEFFF

1FD000-1FDFFF

1FC000-1FCFFF

1FB000-1FBFFF

1FA000-1FAFFF

1F9000-1F9FFF

1F8000-1F8FFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

46/64

M36W832TE, M36W832BE

Table 27. Bottom Boot Block Addresses,

M36W832BE

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

4

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

007000-007FFF

006000-006FFF

005000-005FFF

004000-004FFF

003000-003FFF

002000-002FFF

001000-001FFF

000000-000FFF

Size

#

Address Range

(KWord)

32

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

8

7

6

4

5

4

3

4

2

4

1

4

0

4

47/64

M36W832TE, M36W832BE

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 28, 29,

30, 31, 32 and 33 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 33, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 28. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 29. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

88BAh

88BBh

Top

Bottom

01h

02h-0Fh

10h

reserved Reserved

0051h

"Q"

"R"

"Y"

11h

0052h

0059h

0003h

0000h

0035h

0000h

Query Unique ASCII String "QRY"

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

14h

15h

Address for Primary Algorithm extended Query table (see Table 31)

P = 35h

NA

16h

17h

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

18h

19h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

1Ah

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

48/64

M36W832TE, M36W832BE

Table 30. CFI Query System Interface Information

Offset

Data

Description

Value

V

DDF

V

DDF

V

PPF

V

PPF

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0027h

2.7V

3.6V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

11.4V

12.6V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double/ Quadruple Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for Double/ Quadruple Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

49/64

M36W832TE, M36W832BE

Table 31. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0016h

4 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Ch

0002h

2Dh

2Eh

003Eh

0000h

Region 1 Information

Number of identical-size erase block = 003Eh+1

63

64 KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

63

31h

32h

003Eh

0000h

Region 2 Information

Number of identical-size erase block = 003Eh=1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

50/64

M36W832TE, M36W832BE

Table 32. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0066h

0000h

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Chip Erase supported

(1 = Yes, 0 = No)

Suspend Erase supported

Suspend Program supported

Legacy Lock/Unlock supported

Queued Erase supported

No

Yes

No

Instant individual block locking supported (1 = Yes, 0 = No)

No

Protection bits supported

Page mode read supported

Synchronous read supported

(1 = Yes, 0 = No)

Yes

No

bit 31 to 9 Reserved; undefined bits are ‘0’

No

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0030h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V

12V

01

DDF

bit 7 to 4

HEX value in volts

bit 3 to 0

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PPF

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

Protection Field 1: Protection Description

80h

00h

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

8 Byte

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15

Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 29, offset 15 for P pointer definition.

51/64

M36W832TE, M36W832BE

Table 33. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

128 bits: User Programmable OTP

52/64

M36W832TE, M36W832BE

APPENDIX C. FLASH MEMORY FLOWCHARTS AND PSEUDO CODES

Figure 26. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

V

Invalid

if (status_register.b3==1) /*V

error_handler ( ) ;

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

Program

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI90174b

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

53/64

M36W832TE, M36W832BE

Figure 27. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*V

error_handler ( ) ;

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI90175b

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

54/64

M36W832TE, M36W832BE

Figure 28. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write 56h

Write Address 1

& Data 1 (3)

writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*V

error_handler ( ) ;

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07950

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

55/64

M36W832TE, M36W832BE

Figure 29. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI90176b

56/64

M36W832TE, M36W832BE

Figure 30. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*V

error_handler ( ) ;

invalid error */

PPF

Error (1)

PPF

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI90177b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

57/64

M36W832TE, M36W832BE

Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI90178b

58/64

M36W832TE, M36W832BE

Figure 32. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

Write 60h

if (lock_operation==PROTECT) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNPROTECT) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Status

Register

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI90179

59/64

M36W832TE, M36W832BE

Figure 33. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

Write C0h

writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* EF or GF must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*V

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

error_handler ( ) ;

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07951

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

60/64

M36W832TE, M36W832BE

APPENDIX D. FLASH MEMORY COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER

STATE

Table 34. Write State Machine Current/Next, sheet 1 of 2

Command Input (and Next State)

Data

When

Read

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array

“1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

Status

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

Elect.Sg.

Electronic

Signature

Program

Setup

Erase

Setup

Read

“1”

“0”

“1”

Read Array

Status

Read CFI

Query

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Setup

Status

Lock Command Error

Program

Lock Command Error

Lock Cmd

Error

Erase

Setup

Read

Read Array

Status

Setup

Lock

(complete)

Program

Setup

Erase

Setup

Read

Read Array

Status

Prot. Prog.

Setup

Protection Register Program

Protection Register Program continue

Prot. Prog.

(continue)

Prot. Prog.

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

Status

Array

Status

(continue) Read Array (continue)

Program Prog. Sus Program

(continue) Read Array (continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus Prog. Sus

Read Sts Read Array

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

(continue) Read Array (continue)

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

“0”

“1”

Read Array

(continue) Read Array (continue)

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Array

Read Array

Status

Erase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

Erase

(continue)

Erase Sus

Read Sts

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Program

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Setup

Read Array (continue) Read Array (continue)

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

Erase Sus Erase Erase Sus Erase

Read Array (continue) Read Array (continue)

Erase Sus Erase Sus

Read Sts Read Array

Erase Sus

Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array (continue) Read Array (continue)

Erase Sus

Read CFI

Erase Sus

CFI

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array

Read Array (continue) Read Array (continue)

Erase

(complete)

Program

Setup

Erase

Read

Status

Read Array

Setup

Read Array

Status

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

61/64

M36W832TE, M36W832BE

Table 35. Write State Machine Current/Next, sheet 2 of 2

Command Input (and Next State)

Read CFI

Query

(98h)

Unlock

Confirm

(D0h)

Current State

Read Elect.Sg.

(90h)

Lock Setup

(60h)

Prot. Prog.

Setup (C0h)

Lock Confirm

(01h)

Lock Down

Confirm (2Fh)

Prot. Prog.

Setup

Read Array

Read Elect.Sg. Read CFI Query

Lock Setup

Read Array

Prot. Prog.

Setup

Read Status

Prot. Prog.

Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Read CFI Query Read Elect.Sg. Read CFI Query

Prot. Prog.

Setup

Read Array

Lock (complete)

Read Array

Lock Setup

Lock Command Error

Prot. Prog.

Setup

Lock Cmd Error Read Elect.Sg. Read CFI Query

Lock Setup

Prot. Prog.

Setup

Lock (complete) Read Elect.Sg. Read CFI Query

Read Array

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(continue)

Protection Register Program (continue)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Setup

Prog. Setup

Program

(continue)

Program (continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Program Suspend Read Array

Read Status

Prog. Suspend Prog. Suspend Prog. Suspend

Read Array Read Elect.Sg. Read CFI Query

Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Read CFI

Read Elect.Sg. Read CFI Query

Program

(complete)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFIQuery

Read Array

Setup

Erase

(continue)

Erase Setup

Erase Command Error

Erase

Cmd.Error

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

Setup

Erase (continue)

Erase Suspend Erase Suspend Erase Suspend

Read Ststus Read Elect.Sg. Read CFI Query

Erase

(continue)

Lock Setup

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read Array Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Erase Suspend Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read CFI Query Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase

Prot. Prog.

Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

62/64

M36W832TE, M36W832BE

REVISION HISTORY

Table 36. Document Revision History

Date

Version

Revision Details

16-Jul-2002

1.0

First Issue

Revision History moved to end of document. Flash and SRAM components updated.

Table 2, Main Operation Modes, modified.

Flash Device: “Quadruple Word Program Command” added, “Double Word Program

Command” clarified, V

Maximum changed to 3.6V, Corrections to Table 8, Flash

DDQF

Program, Erase Times and Program/Erase Endurance Cycles, Table 15, DC

Characteristicss Table and to CFI Tables 30 and 31. Security block removed.

Command Codes Table added, DQ0, DQ2, DQ3-DQ7 and DQ8-DQ15 parameters

modified for Lock in Table 7, Flash Read Protection Register and Lock Register.

70ns Speed Class added. 100ns Speed Class removed.

29-Nov-2002

2.0

SRAM device: “Data Retention” on Page 25 and SRAM read and write AC

characteristics (Figures 14, 15, 16, 17, 18, 19, 20, 21 and 22) modified. Figure 7,

SRAM Block Diagram, added.

Document promoted to full Datasheet status. Minor corrections to SRAM Block

Diagram. Input Rise and Fall Time for 70ns speed class modified in Operating and AC

Measurement Conditions Table. LFBGA Connections and Daisy Chain pin numbers

modified.

24-Mar-2003

26-May-2003

3.0

3.1

Special tape option added to ordering information scheme

63/64

M36W832TE, M36W832BE

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

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64/64


型号：	M36W832BE85ZA1T
厂家：	NUMONYX B.V
描述：	Memory Circuit, 2MX16, CMOS, PBGA66, 12 X 8 MM, 0.80 MM PITCH, LFBGA-66 静态存储器内存集成电路
文件：	总64页 (文件大小：897K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36W832BE85ZA1T [NUMONYX]

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