M39P0R9080E0ZAD [NUMONYX]
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package; 512兆位（ X16 ，多银行，多层次，突发）快闪记忆体256兆比特的低功耗SDRAM的1.8V电源，多芯片封装
| 型号： | M39P0R9080E0ZAD |
| 厂家： | 
NUMONYX B.V |
| 描述： | 512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package |
| 文件： | 总23页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M39P0R9080E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory
256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
Feature summary
■ Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
FBGA
Bank, Multi-Level, Burst) Flash memory
– 1 die of 256 Mbit (4 Banks of 4Mb x16) Low
Power Synchronous Dynamic RAM
TFBGA105 (ZAD)
■ Supply voltage
9 x 11mm
– V
– V
= V
= V
= 1.7 to 1.95V
DDQ
DDF
PPF
CCP
= 9V for fast program
■ 100,000 program/erase cycles per block
■ Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
■ Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
■ ECOPACK® package available
– WP for Block Lock-Down
– Absolute Write Protection with V
F
Flash memory
= V
SS
PPF
■ Synchronous / asynchronous read
■ Common Flash Interface (CFI)
– Synchronous Burst Read mode:
108MHz, 66MHz
LPSDRAM
– Asynchronous Page Read mode
■ 256 Mbit synchronous dynamic RAM
– Random Access: 96ns
– Organized as 4 Banks of 4 MWords, each
16 bits wide
■ Programming time
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Synchronous burst read and write
– Fixed Burst Lengths: 1, 2, 4, 8 words or Full
Page
■ Memory organization
– Burst Types: Sequential and Interleaved.
– Multiple Bank Memory Array: 64 Mbit
Banks
– Clock Frequency: 133 MHz (7.5ns speed
class)
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
– Clock Valid to Output Delay (CAS Latency):
3 at 133 MHz
■ Dual operations
■ Automatic and controlled precharge
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ Low-power features:
– Partial Array Self Refresh (PASR),
– Automatic Temperature Compensated Self
Refresh (TCSR)
■ Security
– Driver Strength (DS)
– 64-bit unique device number
– 2112-bit user programmable OTP Cells
– Deep Power-Down Mode
■ Auto Refresh and Self Refresh
November 2007
Rev 2
1/23
www.numonyx.com
1
Contents
M39P0R9080E0
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Protect input (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Deep Power-Down (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Flash memory Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.11 Flash memory Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.12 Flash memory Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13 LPSDRAM Chip Select (ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.14 LPSDRAM Column Address Strobe (CASS) . . . . . . . . . . . . . . . . . . . . . . 12
2.15 LPSDRAM Row Address Strobe (RASS) . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.16 LPSDRAM Write Enable (WS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.17 LPSDRAM Clock input (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18 LPSDRAM Clock Enable (KES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.19 LPSDRAM lower/upper data input/output mask (LDQMS/UDQMS) . . . . . 13
2.20 Flash memory VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.21 LPSDRAM VDDS supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.22
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.23 Flash memory VPPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . 13
2.24 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/23
M39P0R9080E0
Contents
5
6
7
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of tables
M39P0R9080E0
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/23
M39P0R9080E0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 20
5/23
Summary description
M39P0R9080E0
1
Summary description
The M39P0R9080E0 combines two memory devices in one Multi-Chip Package:
●
512-Mbit Multiple Bank Flash memory (the M58PR512J)
256-Mbit Low Power Synchronous DRAM (the M65KA256AF)
●
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58PR512J and
M65KA256AF datasheets, where all specifications required to operate the Flash memory
and SDRAM components are fully detailed. These datasheets are available from the
Numonyx website www.numonyx.com.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is delivered in a Stacked TFBGA105 package. In order to meet environmental
requirements, Numonyx offers the M39P0R9080E0 in ECOPACK® packages. These
packages have a Lead-free second-level interconnect. The category of Second-Level
Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
The M39P0R9080E0 is supplied with all the bits erased (set to ‘1’).
6/23
M39P0R9080E0
Figure 1.
Summary description
Logic diagram
V
V
DDS
DDF
V
V
PPF
DDQ
16
25
A0-A24
DQ0-DQ15
2
BA0-BA1
E
F
WAIT
F
G
F
W
F
RP
F
WP
F
L
F
M39P0R9080E0
K
F
DPD
F
E
S
W
S
KE
S
K
S
RAS
CAS
S
S
UDQM
S
LDQM
S
V
SS
Ai12095
7/23
Summary description
M39P0R9080E0
Table 1.
Signal names
A0-A24(1)
Address Inputs
DQ0-DQ15
VDDQ
Common Data Input/Output
Common Flash and LPSDRAM Power Supply for I/O Buffers
Flash Memory Optional Supply Voltage for Fast Program & Erase
Flash Memory Power Supply
VPPF
VDDF
LPSDRAM Power Supply
V
DDS
VSS
NC
DU
Ground
Not Connected Internally
Do Not Use as Internally Connected
Flash Memory
EF
Chip Enable input
Output Enable Input
Write Enable input
Reset input
GF
WF
RPF
WPF
Write Protect input
Latch Enable input
Burst Clock
LF
KF
WAITF
Wait Output
DPDF
Deep Power-Down
Low Power SDRAM
ES
Chip Enable Input
WS
Write Enable input
KS
LPSDRAM Clock input
KES
LPSDRAM Clock Enable input
Column Address Strobe Input
Row Address Strobe Input
Bank Select Inputs
CASS
RASS
BA0, BA1
UDQMS
LDQMS
Upper Data Input/Output Mask
Lower Data Input/Output Mask
1. A13-A24 are Address Inputs for the Flash memory component only.
8/23
M39P0R9080E0
Summary description
Figure 2.
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DU
A2
A4
A3
A6
A5
A7
A19
A18
A23
A24
A22
NC
NC
DU
A16
A15
A14
A13
A12
A11
A17
DPD
F
V
V
V
V
V
V
V
A1
SS
SS
DDS
NC
SS
DDS
SS
SS
SS
V
V
L
F
V
V
A0
NC
NC
DDF
DDF
DDS
A21
A20
WP
NC
A10
NC
W
F
F
NC
NC
NC
E
S
CAS
RAS
S
NC
A9
A8
S
KE
W
NC
E
F
RP
F
G
H
J
BA0
S
UDQM
LDQM
S
G
F
NC
NC
NC
BA1
S
S
V
V
V
V
K
S
V
V
V
WAIT
F
PPF
DQ2
DQ1
DU
DDQ
DDQ
DDF
DDF
DDQ
DDQ
V
V
V
K
F
V
V
V
SS
K
L
DQ13
DQ14
SS
SS
SS
DQ6
DQ4
SS
SS
DQ3
DQ5
DQ7
DQ8
DQ9
DQ11
DQ12
M
DQ0
NC
DQ10
NC
DQ15
DU
AI10961
9/23
Signal descriptions
M39P0R9080E0
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connect-ed to this device.
2.1
Address inputs (A0-A24)
A0-A12 are common to the Flash memory and LPSDRAM components. A13-A24 are
Address Inputs for the Flash memory component only. In the Flash memory, the Address
Inputs select the cells in the memory array to access during Bus Read operations. During
Bus Write operations they control the commands sent to the Command Interface of the
Program/Erase Controller.
In the LPSDRAM, the A0-A12 Address Inputs are used to select the row or column to be
made active. If a column is selected, only the nine least significant Address Inputs, A0-A8,
are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High
(set to ‘1’) during Read or Write, the Read or Write operation includes an Auto Precharge
cycle. If A10 is Low (set to ‘0’) during Read or Write, the Read or Write cycle does not
include an Auto Precharge cycle.
2.2
2.3
LPSDRAM Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Bank Select Address Inputs are used by the LPSDRAM to select the
bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RASS,
must be Low, V , the Column Address Strobe, CAS , and W must be High, V , when
IL
S
S
IH
selecting the addresses. The address inputs are latched on the rising edge of the clock
signal, K .
S
Data Inputs/Outputs (DQ0-DQ15)
In the Flash memory, the Data I/O output the data stored at the selected address during a
Bus Read operation or input a command or the data to be programmed during a Bus Write
operation.
In the LPSDRAM, the Data Inputs/Outputs are common to all memory components. They
output the data stored at the selected address during a Read operation, or are used to input
the data during a write operation.
2.4
Flash memory Chip Enable input (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance and the power consumption is reduced to the standby level. It is not allowed to
have EF and ES all at VIL at the same time, only one memory component should be enabled
at a time.
10/23
M39P0R9080E0
Signal descriptions
2.5
Flash memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the
memory.
2.6
Flash memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.7
2.8
Flash memory Write Protect input (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V , the Lock-Down is enabled and the protection status of the Locked-
IL
Down blocks cannot be changed. When Write Protect is at V , the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for
details).
IH
Flash memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When
Reset is at V , the memory is in reset mode: the outputs are high impedance and the
IL
current consumption is reduced to the Reset Supply Current
IDD2. Refer to the M58PRxxxJ datasheet for the value of IDD2. After Reset all blocks are in
the Locked state and the Configuration Register is reset. When Reset is at V , the device is
IH
in normal operation. Exiting reset mode the device enters asynchronous read mode, but a
negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to VRPH (refer to the M58PRxxxJ datasheet).
2.9
Flash memory Deep Power-Down (DPDF)
The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode.
When the Flash memory is in Standby mode and the Enhanced Configuration Register bit
ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the
Deep Power-Down mode.
When the device is in the Deep Power-Down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPD pin is determined by ECR14. The Deep Power-Down input is active
F
Low by default.
11/23
Signal descriptions
M39P0R9080E0
2.10
2.11
2.12
Flash memory Latch Enable (LF)
The Latch Enable input latches the address bits on its rising edge. The address latch is
transparent when Latch Enable is at V and it is inhibited when Latch Enable is at V . Latch
IL
IH
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
Flash memory Clock (KF)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V . Clock is ignored during asynchronous
IL
read and in write operations.
Flash memory Wait (WAITF)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V , Output
IH
Enable is at V , or Reset is at V . It can be configured to be active during the wait cycle or
IH
IL
one data cycle in advance.
2.13
2.14
2.15
LPSDRAM Chip Select (ES)
The Chip Select input ES activates the LPSDRAM state machine, address buffers and
decoders when driven Low, V . When ES is High, V , the device is not selected.
IL
IH
LPSDRAM Column Address Strobe (CASS)
The Column Address Strobe, CAS , is used in conjunction with Address Inputs A8-A0 and
S
BA1-BA0, to select the starting column location prior to a Read or Write.
LPSDRAM Row Address Strobe (RASS)
The Row Address Strobe, RAS , is used in conjunction with Address Inputs A11-A0 and
S
BA1-BA0, to select the starting address location prior to a Read or Write.
2.16
2.17
LPSDRAM Write Enable (WS)
The Write Enable input, W , controls writing to the LPSDRAM.
S
LPSDRAM Clock input (KS)
The Clock signal, K , is used to clock the Read and Write cycles. During normal operation,
S
the Clock Enable pin, KES, is High, V . The clock signal K can be suspended to switch the
IH
S
device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KE Low,
S
V .
IL
12/23
M39P0R9080E0
Signal descriptions
2.18
LPSDRAM Clock Enable (KES)
The Clock Enable, KE , pin is used to control the synchronizing of the signals to Clock
S
signal K . The signals are clocked when KE is High, V When KE is Low, V , the signals
S
S
IH
S
IL
are no longer clocked and data Read and Write cycles are extended. KE is also involved in
S
switching the device to the Self Refresh, Power-Down and Deep Power-Down modes.
2.19
LPSDRAM lower/upper data input/output mask
(LDQMS/UDQMS)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals
used to mask the Read or Write data. The DQM latency is two clock cycles for read
operations and there is no latency for write operations.
2.20
2.21
2.22
Flash memory VDDF supply voltage
V
provides the power supply to the internal core of the Flash memory component. It is
DDF
the main power supply for all operations (Read, Program and Erase).
LPSDRAM VDDS supply voltage
V
provides the power supply to the internal core of the LPSDRAM component. It is the
DDS
main power supply for all operations (Read and Write).
VDDQ supply voltage
VDDQ is common to the Flash memory and LPSDRAM components. It provides the power
supply to the I/O pins and enables all Outputs to be powered independently of V
for the
DDF
Flash memory, or V
separate supply.
for the LPSDRAM. V
can be tied to V
or V
, or can use a
DDS
DDQ
DDF
DDS
2.23
Flash memory VPPF Program supply voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin. If V is kept in a low voltage range (0V to V ) V is
PP
DDQ
PP
seen as a control input. In this case a voltage lower than V
gives an absolute protection
PPLK
against program or erase, while V > V
enables these functions (see the M58PRxxxJ
PP
PP1
datasheet for the relevant values). V is only sampled at the beginning of a program or
PP
erase; a change in its value after the operation has started does not have any effect and
program or erase operations continue. If V is in the range of V
it acts as a power
PP
PPH
supply pin. In this condition V must be stable until the Program/Erase algorithm is
PP
completed.
13/23
Signal descriptions
M39P0R9080E0
2.24
VSS ground
V
ground is common to the LPSDRAM and Flash memory components. It is the reference
SS
for the core supply. It must be connected to the system ground.
Each device in a system should have V ,V , V and V decoupled with a 0.1µF
PPF
Note:
DDF DDS
DDQ
ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
should be as close as possible to the package). See Figure 5: AC measurement load circuit
The PCB track widths should be sufficient to carry the required V
currents.
program and erase
PPF
14/23
M39P0R9080E0
Functional description
3
Functional description
The LPSDRAM and Flash memory components have separate power supplies but share the
same grounds. They are distinguished by two Chip Enable inputs: E for the Flash memory
F
and E for the LPSDRAM.
S
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is a simultaneous read operations on the Flash memory
and the LPSDRAM which would result in a data bus contention. Therefore it is
recommended to put the other devices in the high impedance state when reading the
selected device.
Figure 3.
Functional block diagram
V
V
PPF DDF
A13-A24
E
F
F
F
F
WP
W
512 Mbit
Flash
WAIT
F
Memory
K
A0-A12
G
F
F
RP
L
DQ0-DQ15
F
F
DPD
V
DDQ
V
DDS
BA0-BA1
E
S
W
K
S
S
256 Mbit
LPSDRAM
KE
S
S
S
CAS
RAS
UDQM
LDQM
S
S
Ai12096
V
SS
15/23
Functional description
M39P0R9080E0
(1)
Table 2.
Bus operations
Operation
Data
Output
(4)
Bus Read
Bus Write
VIL VIL VIH VIL
VIL VIH VIL VIL
VIH de-a(5)
VIH de-a(5)
(4)
Data Input
The SDRAM must be disabled
Data
Output or
Hi-Z(6)
Address
Latch
VIL X VIH VIL VIH de-a(5)
Output
Disable
VIL VIH VIH
X
VIH de-a(5) Hi-Z
Hi-Z
Hi-Z
Standby
Reset
VIH
X
X
X
X
X
X
X
VIH de-a(5) Hi-Z
VIL de-a(5) Hi-Z
Any SDRAM operation mode is allowed.
Hi-Z
Hi-Z
Deep Power-
Down
VIH
X
X
X
VIH a(7) Hi-Z
Data
Output
Burst Read
VIL VIH VIL VIH VIH
VIL VIH VIL VIL VIH
X
X
VIL V SCA BS V
The Flash memory must be
disabled
Burst Write
Self Refresh
Auto Refresh
VIL V SCA BS X Data Input
VIL VIL VIL VIH VIH VIL
VIL VIL VIL VIH VIH VIH
X
X
X
X
X
X
–
–
Power-Down
with
Precharge
VIL VIH VIH VIH
VIH VIL
X
X
X
X
VIH
X
X
X
Deep Power-
Down
VIL VIH VIH VIL VIH VIL
X
X
X
X
X
X
X
X
X
X
Any Flash memory operation mode
is allowed
Device
Deselect
VIH
X
X
X
VIH
X
X
X
X
No
Operation
VIL VIH VIH VIH VIH
X
1. X = Don't care, de-a = de-asserted, a = asserted, SCA = Start Column Address, BS = Bank Select, V = Valid.
2. The DPD signal polarity depends on the value of the ECR14 bit.
3. WAITF signal polarity is configured using the Set Configuration Register command.
4. LF can be tied to VIH if the valid address has been previously latched.
5. If ECR15 is set to '0', the device cannot enter the Deep Power-Down mode, even if DPDF is asserted.
6. Depends on GF.
7. ECR15 has to be set to ‘1’ for the device to enter Deep Power-Down.
16/23
M39P0R9080E0
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
–25
–25
85
85
°C
°C
°C
V
TBIAS
TSTG
VIO
–55
125
2.6
3.0
2.6
Input or Output Voltage
Supply Voltage
–0.5
–1.0
–0.5
–0.5
–1.0
VDDF
VDDS
VDDQ
VPPF
IO
V
LPSDRAM Supply Voltage
Input/Output Supply Voltage
Program Voltage
V
2.6
V
11.5
100
100
V
Output Short Circuit Current
Time for VPP at VPPH
mA
hours
tVPPH
17/23
DC and AC parameters
M39P0R9080E0
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and AC measurement conditions
Flash memory
Parameter(1)(2)
LPSDRAM
Min Max
Unit
Min
Max
VDDF Supply Voltage
VDDS Supply Voltage
1.7
–
1.95
–
–
–
V
V
1.7
1.7
–
1.95
1.95
–
V
DDQ Supply Voltage
VPPF Supply Voltage (Factory environment)
PPF Supply Voltage (Application environment)
1.7
8.5
–0.4
–25
1.95
9.5
V
V
V
VDDQ+0.4
85
–
–
V
Ambient Operating Temperature
Impedance Output (Z0)
–25
85
°C
Ω
pF
Ω
ns
V
50
Load Capacitance (CL)
30
30
Output Circuit Protection Resistance (R)
Input Rise and Fall Times
50
3
0.5
Input Pulse Voltages
0 to VDDQ
VDDQ/2
0.2 to 1.6
0.9
Input and Output Timing Ref. Voltages
V
1. All voltages are referenced to VSS = 0V.
2. TA = 25°C, f = 1MHz
Figure 4.
AC measurement I/O waveform
V
DDQ
0V
V
/2
DDQ
AI06161
18/23
M39P0R9080E0
Figure 5.
DC and AC parameters
AC measurement load circuit
V
/2
CCQ
R
DEVICE
UNDER
TEST
OUT
Z
0
C
L
AI06162a
(1)
Table 5.
Symbol
Capacitance
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
–
–
12
15
pF
pF
COUT
VOUT = 0V
1. Sampled only, not 100% tested.
Please refer to the M58PRxxxL and M65KA256AF datasheets for further DC and AC
characteristics values and illustrations.
19/23
Package mechanical
M39P0R9080E0
6
Package mechanical
Figure 6.
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline
D
D1
FD
e
ddd
SE
E
E1
BALL "A1"
FE
A2
e
b
A
A1
BGA-Z79
1. Drawing is not to scale.
Table 6.
Symbol
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data
millimeters
Min
inches
Min
Typ
Max
Typ
Max
A
1.20
0.047
A1
A2
b
0.20
0.008
0.80
0.35
9.00
6.40
0.031
0.014
0.354
0.252
0.30
8.90
0.40
9.10
0.012
0.350
0.016
0.358
D
D1
ddd
E
0.10
0.004
0.437
11.00
8.80
0.80
1.30
1.10
0.40
10.90
–
11.10
0.433
0.346
0.031
0.051
0.043
0.016
0.429
–
E1
e
–
–
FD
FE
SE
20/23
M39P0R9080E0
Part numbering
7
Part numbering
Table 7.
Example:
Ordering information scheme
M39 P
0
R
9
0
8
0 E
0
ZAD
E
Device Type
M39 = Multi-Chip Package (Flash + LPSDRAM)
Flash 1 Architecture
P = Multi-Level, Multiple Bank, Large Buffer
Flash 2 Architecture
0 = No Die
Operating Voltage
R = VDDF = VDDS = VDDQ = 1.7 to 1.95 V
Flash 1 Density
9 = 512 Mbits
Flash 2 Density
0 = No Die
RAM 1 Density
8 = 256 Mbit
RAM 0 Density
0 = No Die
Parameter Blocks Location
E = Even Block Flash Memory Configuration
Product Version
0 = 90nm Flash technology, 96 ns speed; LPSDRAM
Package
ZAD = stacked TFBGA105 D stacked footprint.
Option
Blank = Standard Packing
E = ECOPACK® Package, Standard packing
F = ECOPACK® Package, Tape & Reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the Numonyx Sales Office nearest to you.
21/23
Revision history
M39P0R9080E0
8
Revision history
Table 8.
Date
Document revision history
Revision
Changes
15-Dec-2005
12-Oct-2006
30-Nov-2007
0.1
Initial release.
Document status promoted from Target Specification to full
Datasheet.
Voltage ranges extended to 1.95V. Flash memory features
updated to match the data in revision 2 of the M58PRxxxJ
datasheet (random access time, programming time and VPPF
modified).
1
Table 2: Bus operations modified. VPPF max modified in
Table 3: Absolute maximum ratings. Input Pulse voltages
modified for SDRAM in Table 4: Operating and AC
measurement conditions. Flash memory and SDRAM DC
characteristics tables removed (see M58PRxxxJ and
M65KA256AF datasheets for details).
2
Applied Numonyx branding.
22/23
M39P0R9080E0
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
23/23
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