M50LPW80K5G_技术文档

M50LPW080

8 Mbit (1M x8, Uniform Block)

3V Supply Low Pin Count Flash Memory

NOT FOR NEW DESIGN

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Packages

–

V_CC= 3.0 to 3.6V for Program, Erase and

Read Operations

V_PP= 12V for Fast Program and Fast

Erase (optional)

■

TWO INTERFACES

–

Low Pin Count (LPC) Standard Interface

for embedded operation with PC

Chipsets.

–

Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility.

PLCC32 (K)

■

LOW PIN COUNT (LPC) HARDWARE

INTERFACE MODE

–

5 Signal Communication Interface

supporting Read and Write Operations

Hardware Write Protect Pins for Block

Protection

Register Based Read and Write

Protection

5 Additional General Purpose Inputs for

platform design flexibility

Synchronized with 33MHz PCI clock

■

PROGRAMMING TIME

TSOP40 (N)

10 x 20mm

–

10µs typical

Quadruple Byte Programming Option

■

16 UNIFORM 64 Kbyte MEMORY BLOCKS

PROGRAM/ERASE CONTROLLER

–

Embedded Byte Program and Block/Chip

Erase algorithms

–

Status Register Bits

■

PROGRAM and ERASE SUSPEND

–

Read other Blocks during Program/Erase

Suspend

–

Program other Blocks during Erase

Suspend

■

FOR USE in PC BIOS APPLICATIONS

ELECTRONIC SIGNATURE

–

Manufacturer Code: 20h

Device Code: 2Fh

July 2005

1/44

This is information on a product still in production but not recommended for new designs.

M50LPW080

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names (LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Memory Identification Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Low Pin Count (LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input/Output Communications (LAD0-LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Communication Frame (LFRAME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Identification Inputs (ID0-ID1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

_CCSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_PPOptional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Low Pin Count (LPC) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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M50LPW080

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. LPC Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. LPC Bus Read Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. LPC Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. LPC Bus Write Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

V

_PPStatus (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Low Pin Count Register Configuration Map ⁽¹⁾. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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M50LPW080

General Purpose Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. LPC Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. LPC Interface AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 21. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. LPC Interface Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23. LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 25. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 33

Table 27. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 34

Figure 16.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 35

Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 35

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 38

Figure 19.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 39

Figure 20.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 40

Figure 21.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 22.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 42

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M50LPW080

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 30. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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M50LPW080

SUMMARY DESCRIPTION

The M50LPW080 is a 8 Mbit (1Mb x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage (3.0 to 3.6V) supply. For

fast programming and fast erasing in production

lines an optional 12V power supply can be used to

reduce the programming and the erasing times.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected individually to prevent accidental Pro-

gram or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

Two different bus interfaces are supported by the

memory. The primary interface is the Low Pin

Count (or LPC) Standard Interface. This has been

designed to remove the need for the ISA bus in

current PC Chipsets; the M50LPW080 acts as the

PC BIOS on the Low Pin Count bus for these PC

Chipsets.

The secondary interface, the Address/Address

Multiplexed (or A/A Mux) Interface, is designed to

be compatible with current Flash Programmers for

production line programming prior to fitting to a PC

Motherboard.

The memory is offered in TSOP40 (10 x 20mm)

and PLCC32 packages and it is supplied with all

the bits erased (set to ’1’).

6/44

M50LPW080

Figure 2. Logic Diagram (LPC Interface)

Table 1. Signal Names (LPC Interface)

LAD0-LAD3

LFRAME

ID0-ID1

GPI0-GPI4

IC

Input/Output Communications

Input Communication Frame

Identification Inputs

General Purpose Inputs

Interface Configuration

Interface Reset

V

CC PP

2

5

4

LAD0-

LAD3

ID0-ID1

RP

GPI0-

GPI4

WP

INIT

CPU Reset

CLK

Clock

LFRAME

CLK

IC

TBL

M50LPW080

TBL

Top Block Lock

WP

Write Protect

Reserved for Future Use. Leave

disconnected

RFU

RP

V

Supply Voltage

CC

INIT

Optional Supply Voltage for Fast

Erase Operations

V

PP

SS

Ground

V

SS

AI04426

NC

Not Connected Internally

Table 2. Signal Names (A/A Mux Interface)

IC

Interface Configuration

Address Inputs

Figure 3. Logic Diagram (A/A Mux Interface)

A0-A10

DQ0-DQ7

Data Inputs/Outputs

Output Enable

G

V

CC PP

W

Write Enable

11

8

RC

RB

RP

Row/Column Address Select

Ready/Busy Output

Interface Reset

DQ0-DQ7

A0-A10

RC

IC

V

Supply Voltage

CC

M50LPW080

Optional Supply Voltage for Fast

Program and Fast Erase Operations

RB

V

PP

SS

G

Ground

W

NC

Not Connected Internally

RP

V

SS

AI04427

7/44

M50LPW080

Figure 4. PLCC Connections

A/A Mux

1 32

M50LPW080

17

A7

A6

GPI1

GPI0

WP

IC (V )

IL

NC

IC (V

)

IH

NC

A5

NC

A4

TBL

ID1

V

SS

CC

SS

CC

A3

9

25

A2

ID0

INIT

G

A1

RFU

LAD0

LFRAME

RFU

W

A0

RB

DQ7

DQ0

RFU

A/A Mux

AI05465

8/44

M50LPW080

Figure 5. TSOP Connections

NC

1

40

V

SS

CC

IC (V

)

IC (V )

IL

IH

CC

NC

A10

NC

RC

NC

LFRAME W

NC

INIT

RFU

G

NC

RB

NC

DQ7

DQ6

DQ5

DQ4

GPI4

NC

CLK

V

10

11

31

30

V

CC

SS

CC

SS

M50LPW080

V

PP

RP

PP

RP

NC

A9

A8

A7

A6

A5

A4

LAD3

LAD2

LAD1

LAD0

RFU

ID0

DQ3

DQ2

DQ1

DQ0

A0

NC

GPI3

GPI2

GPI1

GPI0

WP

A1

A2

TBL

20

21

ID1

A3

AI04428

Table 3. Memory Identification Input Configuration

Memory Number

ID1

ID0

A21

A20

1

V

or floating

V

or floating

1 (Boot)

1

0

IL

V

2

3

4

0

IL

IH

V

IH

V

or floating

1

V

IH

V

IH

0

9/44

M50LPW080

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on

this part. The active interface is selected before

power-up or during Reset using the Interface Con-

figuration Pin, IC.

The signals for each interface are discussed in the

Low Pin Count (LPC) Signal Descriptions section

and the Address/Address Multiplexed (A/A Mux)

Signal Descriptions section below. The supply sig-

nals are discussed in the Supply Signal Descrip-

tions section below.

(LPC) or the Address/Address Multiplexed (A/A

Mux) Interface is used. The chosen interface must

be selected before power-up or during a Reset

and, thereafter, cannot be changed. The state of

the Interface Configuration, IC, should not be

changed during operation.

To select the Low Pin Count (LPC) Interface the

Interface Configuration pin should be left to float or

driven Low, V_IL; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be

driven High, V_IH. An internal pull-down resistor is

included with a value of R_IL; there will be a leakage

current of I_LI2through each pin when pulled to V_IH;

see Table 21..

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

Reset (RP) is set Low, V_IL, the memory is in Reset

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

set High, V_IH, the memory is in normal operation.

After exiting Reset mode, the memory enters

Read mode.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, LAD0-LAD3. The Clock

conforms to the PCI specification.

Top Block Lock (TBL). The Top Block Lock in-

put is used to prevent the Top Block (Block 15)

from being changed. When Top Block Lock, TBL,

is set Low, V_IL, Program and Block Erase opera-

tions in the Top Block have no effect, regardless of

the state of the Lock Register. When Top Block

Lock, TBL, is set High, V_IH, the protection of the

Block is determined by the Lock Register. The

state of Top Block Lock, TBL, does not affect the

protection of the Main Blocks (Blocks 0 to 14).

Top Block Lock, TBL, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes

or unpredictable results may occur. Care should

be taken to avoid unpredictable behavior by

changing TBL during Program or Erase Suspend.

Write Protect (WP). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 14)

from being changed. When Write Protect, WP, is

set Low, V_IL, Program and Block Erase operations

in the Main Blocks have no effect, regardless of

the state of the Lock Register. When Write Protect,

WP, is set High, V_IH, the protection of the Block is

determined by the Lock Register. The state of

Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure

2. and Table 1..

Input/Output Communications (LAD0-LAD3).

All Input and Output Communication with the

memory take place on these pins. Addresses and

Data for Bus Read and Bus Write operations are

encoded on these pins.

Input Communication Frame (LFRAME). The

Input Communication Frame (LFRAME) signals

the start of a bus operation. When Input Commu-

nication Frame is Low, V_IL, on the rising edge of

the Clock a new bus operation is initiated. If Input

Communication Frame is Low, V_IL, during a bus

operation then the operation is aborted. When In-

put Communication Frame is High, V_IH, the cur-

rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID1). The Identification

Inputs (ID0-ID1) allow to address up to 4 memo-

ries on a bus. The value on addresses A20-A21 is

compared to the hardware strapping on the ID0-

ID1 pins to select which memory is being ad-

dressed. For an address bit to be ‘1’ the corre-

spondent ID pin can be left floating or driven Low,

V_IL; an internal pull-down resistor is included with

a value of R_IL. For an address bit to be ‘0’ the cor-

respondent ID pin must be driven High, V_IH; there

will be a leakage current of I_LI2through each pin

when pulled to V_IH(see Table 21.).

By convention the boot memory must have ID0-

ID1 pins left floating or driven Low, V_ILand a ‘11’

value on A20-A21 and all additional memories

take sequential ID0-ID1 configuration, as shown in

Table 3..

General Purpose Inputs (GPI0-GPI4). The Gener-

al Purpose Inputs can be used as digital inputs for

the CPU to read. The General Purpose Input Reg-

ister holds the values on these pins. The pins must

have stable data from before the start of the cycle

that reads the General Purpose Input Register un-

til after the cycle is complete. These pins must not

be left to float, they should be driven Low, V_IL,or

High, V_IH.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the Low Pin Count

10/44

M50LPW080

Write Protect, WP, does not affect the protection of

the Top Block (Block 15).

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They must be left disconnected.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row Ad-

dress bits (A0-A10) or the Column Address bits

(A11-A19). The Row Address bits are latched on

the falling edge of RC whereas the Column Ad-

dress bits are latched on the rising edge.

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, V_OL, the

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase command except the Program/Erase Sus-

Table 4. Block Addresses

Size

(Kbytes)

Block

Number

Address Range

Block Type

64

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

15

14

13

12

11

10

9

Top Block

Main Block

pend command. When Ready/Busy is High, V_OH

,

the memory is ready for any Read, Program or

Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

V

_CCSupply Voltage. The V_CCSupply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

8

7

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

6

V_LKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid. After V_CC

becomes valid the Command Interface is reset to

Read mode.

A 0.1µF capacitor should be connected between

the V_CCSupply Voltage pins and the V_SSGround

pin to decouple the current surges from the power

supply. Both V_CCSupply Voltage pins must be

connected to the power supply. The PCB track

widths must be sufficient to carry the currents re-

quired during program and erase operations.

5

4

3

2

1

0

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 3. and Table 2..

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A19). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

V_PPOptional Supply Voltage. The V_PPOptional

Supply Voltage pin is used to select the Fast Pro-

gram (see the Quadruple Byte Program Command

description) and Fast Erase options of the memory

and to protect the memory. When V_PP< V_PPLK

Program and Erase operations cannot be per-

formed and an error is reported in the Status Reg-

ister if an attempt to change the memory contents

is made. When V_PP= V_CCProgram and Erase op-

erations take place as normal. When V_PP= V_PPH

Fast Program (if a Quadruple Byte Program Com-

mand is performed) and Fast Erase operations are

11/44

M50LPW080

used. Any other voltage input to V_PPwill result in

undefined behavior and should not be used.

V_SSGround. V_SSis the reference for all the volt-

age measurements.

V_PPshould not be set to V_PPHfor more than 80

hours during the life of the memory.

BUS OPERATIONS

The two interfaces have similar bus operations but

the signals and timings are completely different.

The Low Pin Count (LPC) Interface is the usual in-

terface and all of the functionality of the part is

available through this interface. Only a subset of

functions are available through the Address/Ad-

dress Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus Op-

erations below and the section Address/Address

Multiplexed (A/A Mux) Interface Bus Operations

below for a description of the bus operations on

each interface.

On the following Clock cycles the Host will send

the Cycle Type + Dir, Address, other control bits,

Data0-Data3 and Data4-Data7 on LAD0-LAD3.

The memory outputs Sync data until the wait-

states have elapsed.

See Table 8. and Figure 7. for a description of the

Field definitions for each clock cycle of the trans-

fer. See Table 23. and Figure 11. for details on the

timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low,

V_IL, during the bus operation; the memory will tri-

state the Input/Output Communication pins,

LAD0-LAD3.

Note that, during a Bus Write operation, the Com-

mand Interface starts executing the command as

soon as the data is fully received; a Bus Abort dur-

ing the final TAR cycles is not guaranteed to abort

the command; the bus, however, will be released

immediately.

Low Pin Count (LPC) Bus Operations

The Low Pin Count (LPC) Interface consists of

four data signals (LAD0-LAD3), one control line

(LFRAME) and a clock (CLK). In addition protec-

tion against accidental or malicious data corrup-

tion can be achieved using two further signals

(TBL and WP). Finally two reset signals (RP and

INIT) are available to put the memory into a known

state.

The data signals, control signal and clock are de-

signed to be compatible with PCI electrical specifi-

cations. The interface operates with clock speeds

up to 33MHz.

Standby. When LFRAME is High, V_IH, the mem-

ory is put into Standby mode where LAD0-LAD3

are put into a high-impedance state and the Sup-

ply Current is reduced to the Standby level, I_CC1

.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, V_IL. RP or INIT must be held

Low, V_IL, for t_PLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset (see Table 13.). If RP or

INIT goes Low, V_IL, during a Program or Erase op-

eration, the operation is aborted and the memory

cells affected no longer contain valid data; the

memory can take up to t_PLRHto abort a Program

or Erase operation.

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Low Pin Count Registers. A valid Bus

Read operation starts when Input Communication

Frame, LFRAME, is Low, V_IL, as Clock rises and

the correct Start cycle is on LAD0-LAD3. On the

following clock cycles the Host will send the Cycle

Type + Dir, Address and other control bits on

LAD0-LAD3. The memory responds by outputting

Sync data until the wait-states have elapsed fol-

lowed by Data0-Data3 and Data4-Data7.

Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

See Table 7. and Figure 6. for a description of the

Field definitions for each clock cycle of the trans-

fer. See Table 23. and Figure 11. for details on the

timings of the signals.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux) Inter-

face has a more traditional style interface. The sig-

nals consist of a multiplexed address signals (A0-

Bus Write. Bus Write operations write to the

Command Interface or Low Pin Count Registers. A

valid Bus Write operation starts when Input Com-

munication Frame, LFRAME, is Low, V_IL, as Clock

rises and the correct Start cycle is on LAD0-LAD3.

12/44

M50LPW080

A10), data signals, (DQ0-DQ7) and three control

signals (RC, G, W). An additional signal, RP, can

be used to reset the memory.

Outputs will output the value, see Figure 13. and

Table 25. for details of when the output becomes

valid.

The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming

equipment for faster factory programming. Only a

subset of the features available to the Low Pin

Count (LPC) Interface are available; these include

all the Commands but exclude the Security fea-

tures and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by latching the Row Address and Column

Address signals into the memory using the Ad-

dress Inputs, A0-A10, and the Row/Column Ad-

dress Select RC. The data should be set up on the

Data Inputs/Outputs; Output Enable, G, and Inter-

face Reset, RP, must be High, V_IHand Write En-

able, W, must be Low, V_IL. The Data Inputs/

Outputs are latched on the rising edge of Write En-

able, W. See Figure 14. and Table 26. for details

of the timing requirements.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected all the blocks are unprotect-

ed. It is not possible to protect any blocks through

this interface.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at V_IH.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when RP is Low, V_IL. RP must be

held Low, V_ILfor t_PLPH. If RP is goes Low, V_IL, dur-

ing a Program or Erase operation, the operation is

aborted and the memory cells affected no longer

contain valid data; the memory can take up to t_PL-

_RHto abort a Program or Erase operation.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature and the Status Register. A valid

Bus Read operation begins by latching the Row

Address and Column Address signals into the

memory using the Address Inputs, A0-A10, and

the Row/Column Address Select RC. Then Write

Enable (W) and Interface Reset (RP) must be

High, V_IH, and Output Enable, G, Low, V_IL, in order

to perform a Bus Read operation. The Data Inputs/

Table 5. A/A Mux Bus Operations

V

Operation

Bus Read

G

W

RP

DQ7-DQ0

Data Output

Data Input

Hi-Z

PP

V

IH

Don't Care

V or V

CC

IL

IH

V

IH

Bus Write

Output Disable

Reset

IL

PPH

V

IH

Don't Care

IH

V

IL

or V

V

or V

V

IL

Hi-Z

IH

IL

IH

Table 6. Manufacturer and Device Codes

Operation

Manufacturer Code

Device Code

G

W

RP

A19-A1

A0

DQ7-DQ0

20h

V

IL

V

IH

V

IL

IH

IL

V

IL

V

IH

V

2Fh

IH

13/44

M50LPW080

Table 7. LPC Bus Read Field Definitions

Clock

Cycle

Number Count

Clock

Cycle

LAD0-

LAD3

Memory

I/O

Field

Description

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a

LPC cycle.

1

2

1

START

0000b

010Xb

I

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 0b for read. Bit 0 is don’t

care (X).

CYCTYPE

+ DIR

A 32-bit address phase is transferred starting with the most

significant nibble first. A23-A31 must be set to 1. A22 = 1

for Array, A22 = 0 for registers access. For A20-A21

values, see Table 3..

3-10

8

ADDR

XXXX

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

11

12

1

TAR

I

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3

during this cycle.

O

The LPC Flash Memory drives LAD0-LAD3 to 0101b

(short wait-sync) for two clock cycles, indicating that the

data is not yet available. Two wait-states are always

included.

13-14

15

2

1

WSYNC

RSYNC

0101b

0000b

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating that data will be available during the next clock

cycle.

Data transfer is two CLK cycles, starting with the least

significant nibble.

16-17

18

2

1

DATA

TAR

XXXX

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

1111b

(float)

The LPC Flash Memory floats its outputs, the host takes

control of LAD0-LAD3.

19

N/A

Figure 6. LPC Bus Read Waveforms

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

TAR

2

SYNC

3

DATA

2

TAR

2

Number of

clock cycles

1

AI04429

14/44

M50LPW080

Table 8. LPC Bus Write Field Definitions

Clock

Cycle

Number Count

Clock

Cycle

LAD0-

LAD3

Memory

I/O

Field

Description

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

1

2

1

START

0000b

011Xb

I

CYCTY

PE +

DIR

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t

care (X).

A 32-bit address phase is transferred starting with the most

significant nibble first. A23-A31 must be set to 1. A22 = 1 for

Array, A22 = 0 for registers access. For A20-A21 values, see

Table 3..

3-10

8

ADDR

XXXX

I

Data transfer is two cycles, starting with the least significant

nibble.

11-12

13

2

1

DATA

TAR

XXXX

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

14

TAR

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

15

SYNC

TAR

0000b

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

16

O

1111b

(float)

The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

17

TAR

N/A

Figure 7. LPC Bus Write Waveforms

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

DATA

2

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

1

AI04430

15/44

M50LPW080

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations.

After power-up or a Reset operation the memory

enters Read mode.

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

If the address falls in a protected block then the

Program operation will abort, the data in the mem-

ory array will not be changed and the Status Reg-

ister will output the error.

During the Program operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Program

times are given in Table 15..

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

not cause any modification on its value. One of the

Erase commands must be used to set all of the

bits in the block to ‘1’.

See Figure 17. for a suggested flowchart on using

the Program command.

The commands are summarized in Table 10.. The

following text descriptions should be read in con-

junction with Table 10..

Read Memory Array Command. The

Read

Memory Array command returns the memory to its

Read mode where it behaves like a ROM or

EPROM. One Bus Write cycle is required to issue

the Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read operations will access the memory array.

While the Program/Erase Controller is executing a

Program or Erase operation the memory will not

accept the Read Memory Array command until the

operation completes.

Read Status Register Command. The

Read

Quadruple Byte Program Command. The Qua-

druple Byte Program Command can be only used

in A/A Mux mode to program four adjacent bytes

in the memory array at a time. The four bytes must

differ only for the addresses A0 and A10. Pro-

gramming should not be attempted when V_PPis

not at V_PPH. The operation can also be executed if

V_PPis below V_PPH, but result could be uncertain.

Five Bus Write operations are required to issue the

command. The second, the third and the fourth

Bus Write cycle latches respectively the address

and data of the first, the second and the third byte

in the internal state machine. The fifth Bus Write

cycle latches the address and data of the fourth

byte in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

During the Quadruple Byte Program operation the

memory will only accept the Read Status register

command and the Program/Erase Suspend com-

mand. All other commands will be ignored. Typical

Quadruple Byte Program times are given in Table

15..

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and at-

tempting to do so will not cause any modification

on its value. One of the Erase commands must be

used to set all of the bits in the block to ‘1’.

Status Register command is used to read the Sta-

tus Register. One Bus Write cycle is required to is-

sue the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Register for details on the definitions of the Status

Register bits.

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code and the Device Code. One

Bus Write cycle is required to issue the Read Elec-

tronic Signature command. Once the command is

issued subsequent Bus Read operations read the

Manufacturer Code or the Device Code until an-

other command is issued.

After the Read Electronic Signature Command is

issued the Manufacturer Code and Device Code

can be read using Bus Read operations using the

addresses in Table 9..

Table 9. Read Electronic Signature

Code

Manufacturer Code

Device Code

Address

00000h

00001h

Data

20h

2Fh

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. Two Bus Write opera-

tions are required to issue the command; the sec-

ond Bus Write cycle latches the address and data

See Figure 18. for a suggested flowchart on using

the Quadruple Byte Program command.

16/44

M50LPW080

Chip Erase Command. The Chip Erase Com-

mand can be only used in A/A Mux mode to erase

the entire chip at a time. Erasing should not be at-

tempted when V_PPis not at V_PPH. The operation

can also be executed if V_PPis below V_PPH, but re-

sult could be uncertain. Two Bus Write operations

are required to issue the command and start the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits. During the Chip Erase operation the

memory will only accept the Read Status Register

command. All other commands will be ignored.

Typical Chip Erase times are given in Table 15..

The Chip Erase command sets all of the bits in the

memory to ‘1’. See Figure 20. for a suggested

flowchart on using the Chip Erase command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the block address

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the Status

Register for details on the definitions of the Status

Register bits.

If the block is protected then the Block Erase oper-

ation will abort, the data in the block will not be

changed and the Status Register will output the er-

ror.

During the Block Erase operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Block

Erase times are given in Table 15..

The Block Erase command sets all of the bits in

the block to ‘1’. All previous data in the block is

lost.

See Figure 21. for a suggested flowchart on using

the Block Erase command.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Program

or Erase command is issued. If an error occurs

then it is essential to clear any error bits in the Sta-

tus Register by issuing the Clear Status Register

command before attempting a new Program or

Erase command.

Program/Erase Suspend Command. The Pro-

gram/Erase Suspend command can be used to

pause a Program or Block Erase operation. One

Bus Write cycle is required to issue the Program/

Erase Suspend command and pause the Pro-

gram/Erase Controller. Once the command is is-

sued it is necessary to poll the Program/Erase

Controller Status bit to find out when the Program/

Erase Controller has paused; no other commands

will be accepted until the Program/Erase Control-

ler has paused. After the Program/Erase Control-

ler has paused, the memory will continue to output

the Status Register until another command is is-

sued.

During the polling period between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Controller pausing it is possible for the op-

eration to complete. Once Program/Erase Control-

ler Status bit indicates that the Program/Erase

Controller is no longer active, the Program Sus-

pend Status bit or the Erase Suspend Status bit

can be used to determine if the operation has com-

pleted or is suspended. For timing on the delay be-

tween issuing the Program/Erase Suspend

command and the Program/Erase Controller

pausing see Table 15..

During Program/Erase Suspend the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature and Program/Erase Resume com-

mands will be accepted by the Command Inter-

face. Additionally, if the suspended operation was

Block Erase then the Program command will also

be accepted; only the blocks not being erased may

be read or programmed correctly.

See Figure 19. and Figure 22. for suggested flow-

charts on using the Program/Erase Suspend com-

mand.

Clear Status Register Command. The

Clear

Status Register command can be used to reset

bits 1, 3, 4 and 5 in the Status Register to ‘0’. One

Bus Write is required to issue the Clear Status

Register command. Once the command is issued

the memory returns to its previous mode, subse-

quent Bus Read operations continue to output the

same data.

Program/Erase Resume Command. The Pro-

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

a

Program/Erase Suspend has paused it. One Bus

Write cycle is required to issue the Program/Erase

Resume command. Once the command is issued

subsequent Bus Read operations read the Status

Register.

17/44

M50LPW080

Table 10. Commands

Bus Write Operations

3rd

Command

1st

2nd

4th

5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Read Memory Array

Read Status Register

1

2

5

2

1

X

FFh

70h

90h

98h

40h

10h

30h

80h

20h

50h

B0h

D0h

00h

01h

60h

2Fh

C0h

Read Electronic Signature

Program

PA

PD

A

2

A

4

Quadruple Byte Program

Chip Erase

PD

1

3

X

10h

D0h

Block Erase

BA

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

Invalid/Reserved

Note: X Don’t Care, PA Program Address, PD Program Data, A

Consecutive Addresses, BA Any address in the Block.

1,2,3,4

Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.

Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.

Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-

mand is issued.

Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-

sued.

Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A , A , A and A must be consecutive addresses

1

2

3

4

differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another com-

mand is issued.

Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes

and another command is issued.

Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.

Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Erase suspend) and Program/Erase resume commands.

Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the

Status Register until the Program/Erase Controller Do not use Invalid or Reserved commands not use Invalid or Reserved commands.

18/44

M50LPW080

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

Different bits in the Status Register convey differ-

ent information and errors on the operation.

and still failed to verify that the block(s) has erased

correctly. The Erase Status bit should be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

To read the Status Register the Read Status Reg-

ister command can be issued. The Status Register

is automatically read after Program, Erase and

Program/Erase Resume commands are issued.

The Status Register can be read from any ad-

dress.

When the Erase Status bit is ‘0’ the memory has

successfully verified that the block(s) has erased

correctly; when the Erase Status bit is ‘1’ the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the block(s) and still failed to

verify that the block(s) has erased correctly.

The Status Register bits are summarized in Table

11.. The following text descriptions should be read

in conjunction with Table 11..

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when

the bit is ‘1’, the Program/Erase Controller is inac-

tive.

The Program/Erase Controller Status is ‘0’ imme-

diately after a Program/Erase Suspend command

is issued until the Program/Erase Controller paus-

es. After the Program/Erase Controller pauses the

bit is ‘1’.

During Program and Erase operation the Pro-

gram/Erase Controller Status bit can be polled to

find the end of the operation. The other bits in the

Status Register should not be tested until the Pro-

gram/Erase Controller completes the operation

and the bit is ‘1’.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V_PP

Status and Block Protection Status bits should be

tested for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that a Block Erase oper-

ation has been suspended and is waiting to be

resumed. The Erase Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’ the Pro-

gram/Erase Controller is active or has completed

its operation; when the bit is ‘1’ a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

Once the Erase Status bit is set to ‘1’ it can only be

reset to ‘0’ by a Clear Status Register command or

a hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

Program Status (Bit 4). The Program Status bit

can be used to identify if the memory has applied

the maximum number of program pulses to the

byte and still failed to verify that the byte has pro-

grammed correctly. The Program Status bit should

be read once the Program/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has

successfully verified that the byte has pro-

grammed correctly; when the Program Status bit is

‘1’ the Program/Erase Controller has applied the

maximum number of pulses to the byte and still

failed to verify that the byte has programmed cor-

rectly.

Once the Program Status bit is set to ‘1’ it can only

be reset to ‘0’ by a Clear Status Register com-

mand or a hardware reset. If it is set to ‘1’ it should

be reset before a new Program or Erase command

is issued, otherwise the new command will appear

to fail.

V_PPStatus (Bit 3). The V_PPStatus bit can be

used to identify an invalid voltage on the V_PPpin

during Program and Erase operations. The V_PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V_PPbecomes invalid during a Program or

Erase operation.

When the V_PPStatus bit is ‘0’ the voltage on the

V_PPpin was sampled at a valid voltage; when the

V_PPStatus bit is ‘1’ the V_PPpin has a voltage that

is below the V_PPLockout Voltage, V_PPLK, the

memory is protected; Program and Erase opera-

tion cannot be performed.

Once the V_PPStatus bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a

hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has applied the

maximum number of erase pulses to the block(s)

19/44

M50LPW080

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

gram or Block Erase operation has tried to modify

the contents of a protected block. When the Block

Protection Status bit is to ‘0’ no Program or Block

Erase operations have been attempted to protect-

ed blocks since the last Clear Status Register

command or hardware reset; when the Block Pro-

tection Status bit is ‘1’ a Program or Block Erase

operation has been attempted on a protected

block.

When the Program Suspend Status bit is ‘0’ the

Program/Erase Controller is active or has complet-

ed its operation; when the bit is ‘1’ a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

Once it is set to ‘1’ the Block Protection Status bit

can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it

should be reset before a new Program or Block

Erase command is issued, otherwise the new

command will appear to fail.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Using the A/A Mux Interface the Block Protection

Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if the Pro-

reserved. Its value should be masked.

Table 11. Status Register Bits

Operation

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active

‘0’

‘1

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

X

(1)

Program suspended

Program completed successfully

‘1’

Program failure due to V Error

PP

Program failure due to Block Protection (LPC Interface only)

Program failure due to cell failure

Erase active

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Block Erase suspended

Erase completed successfully

‘1’

‘0’

Erase failure due to V Error

PP

Block Erase failure due to Block Protection (LPC Interface

only)

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Erase failure due to failed cell(s)

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

20/44

M50LPW080

LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS

When the Low Pin Count Interface is selected sev-

eral additional registers can be accessed. These

registers control the protection status of the Blocks

and read the General Purpose Input pins. See Ta-

ble 12. for an example of the Register Configura-

tion map, valid for the boot memory, i.e. ID0-ID1

floating or driven L_OW, V_ILand A20-A21 set to ‘1’.

Table 12. Low Pin Count Register Configuration Map ⁽¹⁾

Default

Value

Memory

Address

Mnemonic

Register Name

Access

T_BLOCK_LK

Top Block Lock Register (Block 15)

FFBF0002h

FFBE0002h

FFBD0002h

FFBC0002h

FFBB0002h

FFBA0002h

FFB90002h

FFB80002h

FFB70002h

FFB60002h

FFB50002h

FFB40002h

FFB30002h

FFB20002h

FFB10002h

FFB00002h

FFBC0100h

01h

N/A

R/W

R

T_MINUS01_LK Top Block [-1] Lock Register (Block 14)

T_MINUS02_LK Top Block [-2] Lock Register (Block 13)

T_MINUS03_LK Top Block [-3] Lock Register (Block 12)

T_MINUS04_LK Top Block [-4] Lock Register (Block 11)

T_MINUS05_LK Top Block [-5] Lock Register (Block 10)

T_MINUS06_LK Top Block [-6] Lock Register (Block 9)

T_MINUS07_LK Top Block [-7] Lock Register (Block 8)

T_MINUS08_LK Top Block [-8] Lock Register (Block 7)

T_MINUS09_LK Top Block [-9] Lock Register (Block 6)

T_MINUS10_LK Top Block [-10] Lock Register (Block 5)

T_MINUS11_LK Top Block [-11] Lock Register (Block 4)

T_MINUS12_LK Top Block [-12] Lock Register (Block 3)

T_MINUS13_LK Top Block [-13] Lock Register (Block 2)

T_MINUS14_LK Top Block [-14] Lock Register (Block 1)

T_MINUS15_LK Top Block [-15] Lock Register (Block 0)

GPI_REG

General Purpose Input Register

Note: 1. This map is referred to the boot memory (ID0-ID1 floating or driven, L , V and A20-A21 set to ‘1’).

OW

IL

Lock Registers

through the Lock Register and may be modified

unless write protected through some other means.

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

When V_PPis less than V_PPLKall blocks are pro-

tected and cannot be modified, regardless of the

state of the Write Lock Bit. If Top Block Lock, TBL,

is Low, V_IL, then the Top Block (Block 15) is write

protected and cannot be modified. Similarly, if

Write Protect, WP, is Low, V_IL, then the Main

Blocks (Blocks 0 to 14) are write protected and

cannot be modified.

After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected).

See Table 13. for details on the bit definitions of

the Lock Registers.

Read Lock. The Read Lock bit determines

whether the contents of the Block can be read

(from Read mode). When the Read Lock Bit is set,

‘1’, the block is read protected; any operation that

attempts to read the contents of the block will read

00h instead. When the Read Lock Bit is reset, ‘0’,

read operations in the Block return the data pro-

grammed into the block as expected.

Write Lock. The Write Lock Bit determines

whether the contents of the Block can be modified

(using the Program or Block Erase Command).

When the Write Lock Bit is set, ‘1’, the block is

write protected; any operations that attempt to

change the data in the block will fail and the Status

Register will report the error. When the Write Lock

Bit is reset, ‘0’, the block is not write protected

After power-up or reset the Read Lock Bit is al-

ways reset to ‘0’ (not read protected).

21/44

M50LPW080

Lock Down. The Lock Down Bit provides a

mechanism for protecting software data from sim-

ple hacking and malicious attack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset or power-up is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

General Purpose Input Register

The General Purpose Input Register holds the

state of the General Purpose Input pins, GPI0-

GPI4. When this register is read, the state of these

pins is returned. This register is read-only and writ-

ing to it has no effect.

The signals on the General Purpose Input pins

should remain constant throughout the whole Bus

Read cycle in order to guarantee that the correct

data is read.

Table 13. Lock Register Bit Definitions

Bit

Bit Name

Value

Function

7-3

Reserved

‘1’

‘0’

Bus Read operations in this Block always return 00h.

2

1

Read-Lock

Bus read operations in this Block return the Memory Array contents. (Default

value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP or INIT) or after power-up.

‘1’

Lock-Down

Write-Lock

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

value).

‘0’

‘1’

‘0’

Program and Block Erase operations in this Block will set an error in the Status

Register. The memory contents will not be changed. (Default value).

0

Program and Block Erase operations in this Block are executed and will modify the

Block contents.

Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Reg-

ister (T_MINUS15_LK).

Table 14. General Purpose Input Register Definition

Bit

Bit Name

Value

Function

7-5

Reserved

Input Pin GPI4 is at V

Input Pin GPI3 is at V

Input Pin GPI2 is at V

Input Pin GPI1 is at V

Input Pin GPI0 is at V

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

4

3

2

1

0

GPI4

GPI3

GPI2

GPI1

GPI0

Note: Applies to the General Purpose Input Register (GPI_REG).

22/44

M50LPW080

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table

15..

Table 15. Program and Erase Times

(1)

Parameter

Interface

Test Condition

Min

Max

200

Unit

µs

Typ

10

Byte Program

V

= 12V ± 5%

= V

Quadruple Byte Program

Chip Erase

A/A Mux

10

9

µs

PP

sec

µs

(2)

5

0.1

Block Program

V

0.4

0.75

1

PP

CC

V

= 12V ± 5%

= V

8

PP

Block Erase

V

10

5

PP

CC

(3)

Program/Erase Suspend to Program pause

(3)

30

µs

Program/Erase Suspend to Block Erase pause

Note: 1. T = 25°C, V = 3.3V

A

CC

2. This time is obtained executing the Quadruple Byte Program Command.

3. Sampled only, not 100% tested.

23/44

M50LPW080

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 16. Absolute Maximum Ratings

Symbol

T_STG

Parameter

Min.

Max.

Unit

°C

Storage Temperature

–65

150

1

T_LEAD

Lead Temperature during Soldering

°C

See note

2

V

+ 0.6

V_IO

–0.60

–0.6

V

CC

Input or Output range

V_CC

Supply Voltage

4

V

Program Voltage

13

PP

3

V_ESD

–2000

2000

Electrostatic Discharge Voltage (Human Body model)

®

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to V + 2V for

CC

less than 20ns during transitions.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

24/44

M50LPW080

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 17., Table 18.

and Table 19. Designers should check that the op-

erating conditions in their circuit match the operat-

ing conditions when relying on the quoted

parameters.

Table 17. Operating Conditions

Symbol

Parameter

Min

3.0

0

Max

3.6

70

Unit

V

CC

Supply Voltage

Ambient Operating Temperature (Device Grade 1)

Ambient Operating Temperature (Device Grade 5)

°C

T

A

–20

85

Table 18. LPC Interface AC Measurement Conditions

Parameter

Value

Unit

Load Capacitance (C )

10

pF

ns

V

L

Input Rise and Fall Times

≤1.4

0.2 V and 0.6 V

Input Pulse Voltages

CC

0.4 V

Input and Output Timing Ref. Voltages

V

CC

Table 19. A/A Mux Interface AC Measurement Conditions

Parameter

Value

30

Unit

pF

ns

V

Load Capacitance (C )

L

Input Rise and Fall Times

≤10

Input Pulse Voltages

0 to 3

1.5

Input and Output Timing Ref. Voltages

V

Figure 8. LPC Interface AC Testing Input Output Waveforms

0.6 V

CC

0.4 V

CC

0.2 V

CC

Input and Output AC Testing Waveform

I

< I

I

> I

I

< I

O LO

O

LO

O

LO

Output AC Tri-state Testing Waveform

AI03404

25/44

M50LPW080

Figure 9. A/A Mux Interface AC Testing Input Output Waveform

3V

0V

1.5V

AI01417

Table 20. Impedance

(3)

Symbol

Parameter

Input Capacitance

Clock Capacitance

Min

Max

13

Unit

pF

Test Condition

(1)

V

= 0V

C

IN

(1)

V

3

12

pF

C

L

CLK

Recommended Pin

Inductance

(2)

20

nH

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.

3. TA = 25°C, f = 1MHz.

26/44

M50LPW080

Table 21. DC Characteristics

Symbol

Parameter

Interface

LPC

Test Condition

Min

Max

Unit

V

0.5 V

V

+ 0.5

CC

V

IH

Input High Voltage

0.7 V

+ 0.3

A/A Mux

LPC

V

CC

0.3 V

–0.5

-0.5

1.35

–0.5

V

CC

V

IL

Input Low Voltage

A/A Mux

LPC

0.8

+ 0.5

V

V (INIT)

IH

V

CC

INIT Input High Voltage

INIT Input Low Voltage

Input Leakage Current

V

V (INIT)

IL

0.2 V

CC

LPC

V

(2)

0V ≤V ≤V

CC

±10

200

µA

I

LI

IN

IC, IDx Input Leakage

Current

I

IC, ID0, ID1 = V

CC

LI2

IC, IDx Input Pull Low

Resistor

R

20

100

kΩ

IL

0.9 V

LPC

A/A Mux

LPC

I

= –500µA

V

CC

OH

V

Output High Voltage

OH

V

– 0.4

= –100µA

= 1.5mA

= 1.8mA

CC

OH

I

OL

0.1 V

V

CC

V

I

Output Low Voltage

OL

I

OL

A/A Mux

0.45

±10

3.6

V

0V ≤V

≤V

CC

Output Leakage Current

µA

V

LO

OUT

V

PP

Voltage

3

PP1

V

PP

Voltage (Fast

11.4

12.6

V

PPH

(1)

Program/Fast Erase)

V

Lockout Voltage

1.5

1.8

V

PP

CC

PPLK

(1)

V

2.3

V

LKO

LFRAME = 0.9 V , V = V

CC

PP

I

All other inputs 0.9 V to 0.1 V

CC

Supply Current (Standby)

LPC

100

µA

mA

CC1

CC

V

= 3.6V, f(CLK) = 33MHz

CC

LFRAME = 0.1 V , V = V

CC

PP

CC

I

All other inputs 0.9 V to 0.1 V

CC

10

60

CC2

CC

V

= 3.6V, f(CLK) = 33MHz

CC

V

= V max, V = V

Supply Current

(Any internal operation

active)

CC

PP

CC

f(CLK) = 33MHz

= 0mA

I

CC3

CC4

I

OUT

G = V , f = 6MHz

Supply Current (Read)

A/A Mux

20

mA

IH

Supply Current

(Program/Erase)

(1)

Program/Erase Controller Active

I

CC5

V

Supply Current

PP

I

V

> V

400

µA

PP

CC

(Read/Standby)

= V

40

15

mA

PP

CC

V

PP

Supply Current

(1)

PP1

(Program/Erase active)

V

= 12V ± 5%

PP

Note: 1. Sampled only, not 100% tested.

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

27/44

M50LPW080

Figure 10. LPC Interface Clock Waveform

tCYC

tHIGH

tLOW

0.6 V

CC

0.5 V

CC

0.4 V

,

CC p-to-p

0.4 V

CC

(minimum)

0.3 V

CC

0.2 V

CC

AI03403

Table 22. LPC Interface Clock Characteristics

Symbol

Parameter

Test Condition

Value

Unit

(1)

t

Min

30

ns

CYC

CLK Cycle Time

t

CLK High Time

CLK Low Time

Min

Max

11

1

ns

HIGH

t

LOW

V/ns

CLK Slew Rate

peak to peak

4

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

28/44

M50LPW080

Figure 11. LPC Interface AC Signal Timing Waveforms

CLK

tCHQV

tCHQZ

tCHQX

tDVCH

tCHDX

VALID

LAD0-LAD3

VALID OUTPUT DATA

FLOAT OUTPUT DATA

VALID INPUT DATA

AI04431

Table 23. LPC Interface AC Signal Timing Characteristics

PCI

Symbol

Parameter

Test Condition

Value

Unit

Symbol

Min

2

ns

t

val

CLK to Data Out

CHQV

Max

11

CLK to Active

(Float to Active Delay)

(1)

t

Min

Max

Min

2

28

7

ns

t

on

CHQX

CLK to Inactive

(Active to Float Delay)

t

CHQZ

off

t

AVCH

(2)

t

su

Input Set-up Time

DVCH

t

CHAX

(2)

t

Min

0

ns

h

Input Hold Time

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

29/44

M50LPW080

Figure 12. Reset AC Waveforms

RP, INIT

tPHWL, tPHGL, tPHFL

tPLPH

W, G, LFRAME

RB

tPLRH

AI04432

Table 24. Reset AC Characteristics

Symbol

Parameter

Test Condition

Value

Unit

ns

t

RP or INIT Reset Pulse Width

Min

Max

100

30

PLPH

Program/Erase Inactive

Program/Erase Active

ns

t

RP or INIT Low to Reset

PLRH

µs

(1)

Rising edge only

Min

50

30

mV/ns

RP or INIT Slew Rate

t

RP or INIT High to LFRAME Low

LPC Interface only

µs

PHFL

t

RP High to Write Enable or Output

Enable Low

PHWL

A/A Mux Interface only

Min

50

µs

PHGL

Note: 1. See Chapter 4 of the PCI Specification.

30/44

M50LPW080

Figure 13. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10

ROW ADDR VALID COLUMN ADDR VALID

NEXT ADDR VALID

tAVCL

tAVCH

tCLAX

tCHAX

RC

G

tCHQV

tGLQV

tGLQX

tGHQZ

tGHQX

VALID

DQ0-DQ7

W

tPHAV

RP

AI03406

Table 25. A/A Mux Interface Read AC Characteristics

Symbol

Parameter

Read Cycle Time

Test Condition

Value

250

Unit

ns

t

Min

AVAV

t

Row Address Valid to RC Low

50

ns

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC high

RC High to Column Address Transition

ns

CLAX

t

ns

AVCH

t

ns

CHAX

(1)

RC High to Output Valid

Max

150

ns

t

CHQV

(1)

Output Enable Low to Output Valid

RP High to Row Address Valid

Max

Min

Max

Min

50

1

ns

µs

ns

t

GLQV

t

PHAV

GLQX

t

Output Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Hold from Output Enable High

0

50

0

GHQZ

GHQX

t

Note: 1. G may be delayed up to t

– t

GLQV

after the rising edge of RC without impact on t

.

CHQV

31/44

M50LPW080

Figure 14. A/A Mux Interface Write AC Waveforms

Write erase or

program setup

Write erase confirm or Automated erase

valid address and data or program delay

Read Status

Register Data

Ready to write

another command

A0-A10

RC

R1

C1

R2

C2

tCLAX

tAVCH

tAVCL

tCHAX

tWHWL

tWLWH

tCHWH

W

G

tVPHWH

tWHGL

tWHRL

RB

tQVVPL

V

PP

tDVWH

tWHDX

DQ0-DQ7

D

VALID SRD

IN1

IN2

AI04194

Table 26. A/A Mux Interface Write AC Characteristics

Symbol

Parameter

Test Condition

Value

100

50

Unit

t

Write Enable Low to Write Enable High

Data Valid to Write Enable High

Write Enable High to Data Transition

Row Address Valid to RC Low

Min

ns

WLWH

t

Min

DVWH

t

5

WHDX

t

50

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC High

RC High to Column Address Transition

Write Enable High to Write Enable Low

RC High to Write Enable High

50

CLAX

t

50

AVCH

t

50

CHAX

t

100

50

WHWL

t

CHWH

(1)

V

PP

High to Write Enable High

100

t

VPHWH

t

Write Enable High to Output Enable Low

Write Enable High to RB Low

Min

30

0

ns

WHGL

t

WHRL

(1,2)

QVVPL

Output Valid, RB High to V Low

Min

0

ns

t

PP

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

32/44

M50LPW080

PACKAGE MECHANICAL

Figure 15. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline

D

A1

D1

A2

1 N

B1

e

E2

E3

E1 E

F

B

0.51 (.020)

E2

1.14 (.045)

D3

A

R

CP

D2

PLCC-A

Note: Drawing is not to scale.

33/44

M50LPW080

Table 27. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

3.56

2.41

–

Typ

Max

0.140

0.095

–

A

A1

A2

B

3.18

0.125

0.060

0.015

0.013

0.026

1.53

0.38

0.33

0.53

0.81

0.10

12.57

11.51

5.66

–

0.021

0.032

0.004

0.495

0.453

0.223

–

B1

CP

D

0.66

12.32

11.35

4.78

–

0.485

0.447

0.188

–

D1

D2

D3

E

7.62

0.300

14.86

13.89

6.05

–

15.11

14.05

6.93

–

0.585

0.547

0.238

–

0.595

0.553

0.273

–

E1

E2

E3

e

10.16

1.27

0.400

0.050

–

F

0.00

–

0.13

–

0.000

–

0.005

–

R

0.89

0.035

N

32

34/44

M50LPW080

Figure 16. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.100

20.200

18.500

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.0039

0.7953

0.7283

–

A

A1

A2

B

0.050

0.950

0.170

0.100

0.0020

0.0374

0.0067

0.0039

C

CP

D

19.800

18.300

–

0.7795

0.7205

–

D1

e

0.500

0.0197

E

9.900

0.500

0°

10.100

0.700

5°

0.3898

0.0197

0°

0.3976

0.0276

5°

L

α

N

40

35/44

M50LPW080

PART NUMBERING

Table 29. Ordering Information Scheme

Example:

M50LPW080

K

1

T

G

Device Type

M50 =

Architecture

LP = Low Pin Count Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

080 = 8 Mbit (1Mx8), Uniform Block

Package

K = PLCC32

N = TSOP40: 10 x 20 mm

Device Grade

5 = Temperature range –20 to 85 °C.

Device tested with standard test flow

1 = Temperature range 0 to 70 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free

2

3

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

36/44

M50LPW080

FLOWCHARTS AND PSEUDO CODES

Figure 17. Program Flowchart and Pseudo Code

Start

Program command:

– write 40h or 10h

Write 40h or 10h

– write Address & Data

(memory enters read status state after

the Program command)

Write Address

& Data

do:

NO

Read Status

–read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Error (1, 2)

Program

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Error (1, 2)

LPC

Interface

Only

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI04433

Note: 1. A Status check of b1 (Protected Block), b3 (V invalid) and b4 (Program Error) can be made after each Program operation by

PP

following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

37/44

M50LPW080

Figure 18. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

& Data 1 ⁽³⁾

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1 ⁽³⁾

– write Address 2 & Data 2 ⁽³⁾

– write Address 3 & Data 3 ⁽³⁾

Write Address 2

& Data 2 ⁽³⁾

– write Address 4 & Data 4 ⁽³⁾

(memory enters read status state after

the Quadruple Byte Program command)

Write Address 3

& Data 3 ⁽³⁾

Write Address 4

& Data 4 ⁽³⁾

do:

NO

– read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

V

Invalid

Error (1, 2)

If b3 = 1, V

invalid error:

– error handler

PP

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

End

AI03982

Note: 1. A Status check of b3 (V invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

PP

mand sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A10.

38/44

M50LPW080

Figure 19. Program Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b2 = 1

YES

Program Complete

If b2 = 0 Program completed

Write a read

Command

Read data from

another address

Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI03408

39/44

M50LPW080

Figure 20. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Chip Erase command:

Write 80h

– write 80h

– write 10h

(memory enters read Status Register after

the Chip Erase command)

Write 10h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

– error handler

invalid error:

PP

Error (1)

PP

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

Erase Error (1)

YES

End

AI04195

Note: If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

40/44

M50LPW080

Figure 21. Block Erase Flowchart and Pseudo Code

Start

Block Erase command:

– write 20h

Write 20h

– write Block Address & D0h

(memory enters read Status Register after

the Block Erase command)

Write Block Address

& D0h

do:

– read Status Register

– if Program/Erase Suspend command

given execute suspend erase loop

NO

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

– error handler

PP

Error (1)

PP

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase Error (1)

LPC

Interface

Only

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:

– error handler

b1 = 0

YES

End

AI04434

Note: If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

41/44

M50LPW080

Figure 22. Erase Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read Status Register

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

Erase Complete

If b6 = 0, Erase completed

Read data from

another block

or

Program

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Erase Continues

AI03410

42/44

M50LPW080

REVISION HISTORY

Table 30. Revision History

Date

Version

Revision Details

April 2001

-01

First Issue

Clock Cycle Number 2 changed (Table 7. and Table 8.)

Low Pin Count Register Configuration Map (Table 12.) clarification

22-June-2001

03-Sep-2001

24-Oct-2001

12-Mar-2002

-02

-03

-04

-05

PLCC32 package added

Note 2 changed under Table 4.

Document Status changed from Product Preview to Preliminary Data

V

Optional Supply Voltage section clarified

PP

RFU pins must be left disconnected

Specification of PLCC32 package mechanical data revised

Revision numbering modified. Document reformatted.

Temperature Range ordering information replaced by Device Grade, Standard

packing option added and Plating Technology added. T parameter added to

02-Aug-2004

07-Jul-2005

8.0

9.0

LEAD

Absolute Maximum Ratings and T

parameter removed.

BIAS

Inch values corrected in TSOP40 package mechanical data.

Datasheet Status updated to NOT FOR NEW DESIGN.

43/44

M50LPW080

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

44/44


型号：	M50LPW80K5G
厂家：	NUMONYX B.V
描述：	1MX8 FLASH 3V PROM, 11ns, PQCC32, ROHS COMPLIANT, PLASTIC, LCC-32 可编程只读存储器内存集成电路
文件：	总44页 (文件大小：692K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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