M58BW016FB8ZA3FT_技术文档

M58BW016DB M58BW016DT

M58BW016FT M58BW016FB

16 Mbit (512 Kbit x 32, boot block, burst)

3 V supply Flash memories

Features

■ Supply voltage

– V = 2.7 V to 3.6 V for program, erase

DD

and read

– V

= V

= 2.4 V to 3.6 V for I/O

DDQIN

DDQ

buffers

– V = 12 V for fast program (optional)

PP

■ High performance

– Access times: 70, 80 ns

– 56 MHz effective zero wait-state burst read

– Synchronous burst read

PQFP80 (T)

LBGA

– Asynchronous page read

■ Hardware block protection

– WP pin for write protect of the 4 outermost

parameter blocks and all main blocks

– RP pin for write protect of all blocks

■ Optimized for FDI drivers

LBGA80 10 × 12 mm

– Fast program / erase suspend latency

time < 6 µs

– Common Flash interface

■ Memory blocks

– 8 parameters blocks (top or bottom)

– 31 main blocks

■ Low power consumption

– 5 µA typical deep power-down

– 60 µA typical standby for M58BW016DT/B

150 µA typical standby for M58BW016FT/B

– Automatic standby after asynchronous read

■ Electronic signature

– Manufacturer code: 20h

– Top device code: 8836h

– Bottom device code: 8835h

■ 100 K write/erase cycling + 20 years data

retention (minimum)

■ High reliability level with over 1 M write/erase

cycling sustained

®

■ ECOPACK packages available

March 2008

Rev 17

1/70

www.numonyx.com

1

Contents

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address inputs (A0-A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset/Power-down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10 Burst Address Advance (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.11 Valid Data Ready (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.12 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.13 Supply voltage (V_{DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16}

2.14 Output supply voltage (V_DDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.15 Input supply voltage (V_DDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.16 Program/erase supply voltage (V_PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.17 Ground (V_SSand V_SSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.18 Don’t use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.19 Not connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

Asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

Asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . 18

Asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . 19

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Contents

3.1.7

3.1.8

3.1.9

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.10 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2

3.3

3.2.1

3.2.2

Synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.7

3.3.8

Read select bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

X-Latency bits (M14-M11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Y-Latency bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Valid data ready bit (M8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst type bit (M7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Valid clock edge bit (M6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Wrap burst bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Burst length bit (M2-M0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4

Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.10 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 32

5

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1

5.2

5.3

5.4

5.5

Program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

V_PPstatus (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3/70

Contents

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

5.6

5.7

Program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6

7

8

9

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix A Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Appendix B Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

List of tables

Table 1.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

M58BW016DT and M58BW016FT top boot block addresses . . . . . . . . . . . . . . . . . . . . . . 12

M58BW016DB and M58BW016FB bottom boot block addresses . . . . . . . . . . . . . . . . . . . 13

Asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Asynchronous read electronic signature operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Synchronous burst read bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Burst configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 33

Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Asynchronous bus read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Asynchronous latch controlled bus read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . 42

Asynchronous page read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Asynchronous write and latch controlled write AC characteristics . . . . . . . . . . . . . . . . . . . 46

Synchronous burst read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Power supply AC and DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Reset, power-down and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PQFP80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 53

LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package mechanical data . . 54

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

CFI - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

5/70

List of figures

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Example burst configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Asynchronous bus read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Asynchronous latch controlled bus read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 11. Asynchronous write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 12. Asynchronous latch controlled write AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge) . . . . . . . . . . . . . . . . . . . . . 47

Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge) . . . . . . . . . . . . . . . . . . . . . 48

Figure 15. Synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . . . . . . . 49

Figure 16. Synchronous burst read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 17. Reset, power-down and power-up AC waveforms - control pins low . . . . . . . . . . . . . . . . . 50

Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling . . . . . . . . . . . . . 50

Figure 19. Power supply slope specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 20. PQFP80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 21. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package outline . . . . . . . . . . 54

Figure 22. Program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 23. Program suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 24. Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 25. Erase suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 26. Power-up sequence followed by synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 27. Command interface and program/erase controller flowchart (a). . . . . . . . . . . . . . . . . . . . . 64

Figure 28. Command interface and program/erase controller flowchart (b). . . . . . . . . . . . . . . . . . . . . 65

Figure 29. Command interface and program/erase controller flowchart (c). . . . . . . . . . . . . . . . . . . . . 66

Figure 30. Command interface and program/erase controller flowchart (d). . . . . . . . . . . . . . . . . . . . . 67

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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Description

1

Description

The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB are 16-Mbit non-

volatile Flash memories that can be erased electrically at the block level and programmed

in-system on a double-word basis using a 2.7 V to 3.6 V V supply for the circuit and a

DD

V

supply down to 2.4 V for the input and output buffers. Optionally a 12 V V supply

DDQ

PP

can be used to provide fast program and erase for a limited time and number of

program/erase cycles.

The devices support asynchronous (latch controlled and page read) and synchronous bus

operations. The synchronous burst read interface allows a high data transfer rate controlled

by the burst clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The

burst type, latency and length can be configured and can be easily adapted to a large

variety of system clock frequencies and microprocessors. All writes are asynchronous. On

power-up the memory defaults to read mode with an asynchronous bus.

The devices have a boot block architecture with an array of 8 parameter blocks of 64 Kbits

each and 31 main blocks of 512 Kbits each. In the M58BW016DT and M58BW016FT the

parameter blocks are located at the top of the address space whereas in the M58BW016DB

and M58BW016FB, they are located at the bottom.

Program and erase commands are written to the command interface of the memory. An on-

chip program/erase controller simplifies the process of programming or erasing the memory

by taking care of all of the special operations that are required to update the memory

contents. The end of a program or erase operation can be detected and any error conditions

identified in the status register. The command set required to control the memory is

consistent with JEDEC standards.

Erase can be suspended in order to perform either read or program in any other block and

then resumed. Program can be suspended to read data in any other block and then

resumed. Each block can be programmed and erased over 100,000 cycles.

All blocks are protected during power-up.

The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB feature two different

levels of block protection to avoid unwanted program/erase operations:

●

The WP pin offers an hardware protection on two of the parameter blocks and all of the

main blocks

●

All program or erase operations are blocked when Reset, RP, is held Low. A

reset/power-down mode is entered when the RP input is Low. In this mode the power

consumption is lower than in the normal standby mode, the device is write protected

and both the status and the burst configuration registers are cleared. A recovery time is

required when the RP input goes High.

The memory is offered in a PQFP80 (14 x 20 mm) and LBGA80 (10 × 12 mm) package.

The memories are supplied with all the bits erased (set to ’1’).

In the present document, M58BW016DT, M58BW016DB, M58BW016FT and

M58BW016FB will be referred to as M58BW016 unless otherwise specified.

7/70

Description

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Logic diagram

Figure 1.

V

DD DDQ DDQIN PP

DQ0-DQ31

A0-A18

K

L

E

M58BW016DT

M58BW016DB

M58BW016FT

M58BW016FB

RP

G

R

GD

W

WP

B

V

SSQ

SS

AI11201b

8/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Description

Table 1.

Signal names

Signal

Description

Direction

A0-A18

Address inputs

Inputs

I/O

DQ0-DQ7

Data input/output, command input

Data input/output, Burst Configuration Register

Data input/output

DQ8-DQ15

I/O

DQ16-DQ31

I/O

B

E

Burst Address Advance

Chip Enable

Input

Output

Input

Supply

G

Output Enable

K

Burst Clock

L

Latch Enable

R

Valid Data Ready (open drain output)

Reset/Power-down

RP

W

Write Enable

GD

WP

V_DD

V_DDQ

V_DDQIN

Output Disable

Write Protect

Supply voltage

Power supply for output buffers

Power supply for input buffers only

Optional supply voltage for fast program and fast

erase operations

V_PP

Supply

V_SS

V_SSQ

NC

Ground

–

Input/output ground

Not connected internally

Don’t use as internally connected

DU

9/70

Description

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

PQFP connections (top view through package)

Figure 2.

DQ16

DQ17

DQ18

DQ19

1

DQ15

DQ14

DQ13

DQ12

64

V

DDQ

SSQ

DDQ

V

SSQ

DQ20

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

M58BW016DT

M58BW016DB

M58BW016FT

M58BW016FB

12

53

V

DDQ

SSQ

DDQ

V

SSQ

DQ28

DQ3

DQ2

DQ1

DQ0

NC

DQ29

DQ30

DQ31

DU

A0

A18

A17

A16

A1

A2

41

24

AI11202b

10/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Description

Figure 3.

LBGA connections (top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

H

I

A15

A14

V

A6

A3

A2

DD

PP

SS

A16

A17

DQ3

A13

A18

A12

A11

NC

A9

A10

NC

A8

NC

A5

A7

A4

NC

A1

A0

DQ0

DQ4

DQ7

DQ8

DQ12

DQ14

RP

NC

DQ31

DQ28

DQ25

DQ21

DQ19

G

DQ30

DQ26

DQ24

DQ23

DQ18

R

DQ29

V

DQ2

DQ6

DQ10

DQ11

L

DQ1

DQ5

DQ9

WP

B

DQ27

NC

V

DDQ

V

SSQ

V

DQ22

DQ17

E

V

DDQ

DQ13

DQ15

DQ20

DQ16

NC

J

V

K

V

W

GD

DDQIN

SS

DD

AI04151C

1.1

Block protection

The M58BW016 feature two different levels of block protection.

●

Write protect pin, WP - When WP is Low, V , all the lockable parameter blocks (two

IL

upper (top) or lower (bottom)) and all the main blocks are protected. When WP is High

(V ) all the lockable parameter blocks and all the main blocks are unprotected

IH

●

Reset/power-down pin, RP - If the device is held in reset mode (RP at V ), no

IL

program or erase operations can be performed on any block.

After a device reset the first two kinds of block protection (WP, RP) can be combined to give

a flexible block protection.

11/70

Description

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

M58BW016DT and M58BW016FT top boot block addresses

Table 2.

#

Size (Kbit)

Address range

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

64

7F800h-7FFFFh

7F000h-7F7FFh

7E800h-7EFFFh

7E000h-7E7FFh

7D800h-7DFFFh

7D000h-7D7FFh

7C800h-7CFFFh

7C000h-7C7FFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

00000h-03FFFh

64

512

8

7

6

5

4

3

2

1

0

12/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Description

Table 3.

#

M58BW016DB and M58BW016FB bottom boot block addresses

Size (Kbit)

Address range

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

512

64

7C000h-7FFFFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

03800h-03FFFh

03000h-037FFh

02800h-02FFFh

02000h-027FFh

01800h-01FFFh

01000h-017FFh

00800h-00FFFh

00000h-007FFh

8

7

6

64

5

64

4

64

3

64

2

64

1

64

0

64

13/70

Signal descriptions

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

2

Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A18)

The address inputs are used to select the cells to access in the memory array during bus

operations either to read or to program data. During bus write operations they control the

commands sent to the command interface of the program/erase controller. Chip Enable

must be Low when selecting the addresses.

The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,

whichever occurs first, in a read operation.The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation.

The address latch is transparent when Latch Enable is Low, V . The address is internally

IL

latched in an erase or program operation.

2.2

Data inputs/outputs (DQ0-DQ31)

The data inputs/outputs output the data stored at the selected address during a bus read

operation, or are used to input the data during a program operation. During bus write

operations they represent the commands sent to the command interface of the

program/erase controller. When used to input data or write commands they are latched on

the rising edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both Low, V , and Output Disable is at V the

IL

IH,

data bus outputs data from the memory array, the electronic signature, the CFI information

or the contents of the status register. The data bus is high impedance when the device is

deselected with Chip Enable at V , Output Enable at V , Output Disable at V or

IH

IL

Reset/Power-down at V . The status register content is output on DQ0-DQ7 and DQ8-

IL

DQ31 are at V .

IL

2.3

2.4

Chip Enable (E)

The Chip Enable, E, input activates the memory control logic, input buffers, decoders and

sense amplifiers. Chip Enable, E, at V deselects the memory and reduces the power

consumption to the standby level.

IH

Output Enable (G)

The Output Enable, G, gates the outputs through the data output buffers during a read

operation, when Output Disable GD is at V . When Output Enable G is at V , the outputs

IH

are high impedance independently of Output Disable.

14/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Signal descriptions

2.5

Output Disable (GD)

The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at

V , the outputs are driven by the Output Enable. When Output Disable, GD, is at V , the

IH

IL

outputs are high impedance independently of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as there is no internal pull-up resistor to drive

the pin.

2.6

2.7

Write Enable (W)

The Write Enable, W, input controls writing to the command interface, Address inputs and

Data latches. Both addresses and data can be latched on the rising edge of Write Enable

(also see Latch Enable, L).

Reset/Power-down (RP)

The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware

reset is achieved by holding Reset/Power-down Low, V , for at least t

. Writing is

IL

PLPH

inhibited to protect data, the command interface and the program/erase controller are reset.

The status register information is cleared and power consumption is reduced to deep power-

down level. The device acts as deselected, that is the data outputs are high impedance.

After Reset/Power-down goes High, V , the memory will be ready for bus read operations

IH

after a delay of t

or bus write operations after t

.

PHEL

PHWL

If Reset/Power-down goes Low, V , during a Block Erase, or a Program the operation is

IL

aborted, in a time of t

maximum, and data is altered and may be corrupted.

PLRH

During power-up power should be applied simultaneously to V and V

with RP held

DDQ(IN)

DD

at V . When the supplies are stable RP is taken to V . Output Enable, G, Chip Enable, E,

IL

IH

and Write Enable, W, should be held at V during power-up.

IH

In an application, it is recommended to associate reset/power-down pin, RP, with the reset

signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is

performing an erase or program operation, the memory may output the status register

information instead of being initialized to the default asynchronous random read.

See Table 22: Reset, power-down and power-up AC characteristics and Figure 17: Reset,

power-down and power-up AC waveforms - control pins low, for more details.

2.8

Latch Enable (L)

The bus interface can be configured to latch the address inputs on the rising edge of Latch

Enable, L, for asynchronous latch enable controlled read or write or synchronous burst read

operations. In synchronous burst read operations the address is latched on the active edge

of the Clock when Latch Enable is Low, V . Once latched, the addresses may change

IL

without affecting the address used by the memory. When Latch Enable is Low, V , the latch

IL

is transparent. Latch Enable, L, can remain at V for asynchronous random read and write

IL

operations.

15/70

Signal descriptions

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

2.9

Burst Clock (K)

The Burst Clock, K, is used to synchronize the memory with the external bus during

synchronous burst read operations. Bus signals are latched on the active edge of the Clock.

The Clock can be configured to have an active rising or falling edge. In synchronous burst

read mode the address is latched on the first active clock edge when Latch Enable is Low,

V , or on the rising edge of Latch Enable, whichever occurs first.

IL

During asynchronous bus operations the Clock is not used.

2.10

Burst Address Advance (B)

The Burst Address Advance, B, controls the advancing of the address by the internal

address counter during synchronous burst read operations.

Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the

X-latency time has expired. If Burst Address Advance is Low, V , the internal address

IL

counter advances. If Burst Address Advance is High, V , the internal address counter does

IH

not change; the same data remains on the data inputs/outputs and Burst Address Advance

is not sampled until the Y-latency expires.

The Burst Address Advance, B, may be tied to V .

IL

2.11

Valid Data Ready (R)

The Valid Data Ready output, R, is an open drain output that can be used, during

synchronous burst read operations, to identify if the memory is ready to output data or not.

The Valid Data Ready output can be configured to be active on the clock edge of the invalid

data read cycle or one cycle before. Valid Data Ready, at V , indicates that new data is or

IH

will be available. When Valid Data Ready is Low, V , the previous data outputs remain

IL

active.

In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other

components with the same Valid Data Ready signal to create a unique system Ready

signal. The Valid Data Ready output has an internal pull-up resistor of around 1 MΩpowered

from V

, designers should use an external pull-up resistor of the correct value to meet the

DDQ

external timing requirements for Valid Data Ready going to V .

IH

2.12

Write Protect (WP)

The Write Protect, WP, provides protection against program or erase operations. When

Write Protect, WP, is at V the first two (in the bottom configuration) or last two (in the top

IL

configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at

V

all the blocks can be programmed or erased, if no other protection is used.

IH

2.13

Supply voltage (V_DD)

The supply voltage, V , is the core power supply. All internal circuits draw their current from

DD

the V pin, including the program/erase controller.

DD

16/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Signal descriptions

2.14

2.15

2.16

Output supply voltage (V_DDQ)

The output supply voltage, V

, is the output buffer power supply for all operations (read,

DDQ

program and erase) used for DQ0-DQ31 when used as outputs.

Input supply voltage (V_DDQIN

)

The input supply voltage, V

, is the power supply for all input signal. Input signals are: K, B,

DDIN

L, W, GD, G, E, A0-A18 and DQ0-DQ31, when used as inputs.

Program/erase supply voltage (V_PP)

The program/erase supply voltage, V , is used for program and erase operations. The

PP

memory normally executes program and erase operations at V

voltage levels. In a

PP1

manufacturing environment, programming may be speeded up by applying a higher voltage

level, V , to the V pin.

PPH

PP

The voltage level V

may be applied for a total of 80 hours over a maximum of 1000

PPH

cycles. Stressing the device beyond these limits could damage the device.

2.17

Ground (V_SSand V_SSQ)

The ground V is the reference for the internal supply voltage V . The ground V is the

SSQ

SS

DD

reference for the output and input supplies V

and V

. It is essential to connect V

DDQ,

DDQIN SS

and V

together.

SSQ

Note:

A 0.1 µF capacitor should be connected between the supply voltages, V , V

and V

DD DDQ DDIN

and the grounds, V and V

to decouple the current surges from the power supply. The

SS

SSQ

PCB track widths must be sufficient to carry the currents required during all operations of

the parts, see Table 15: DC characteristics, for maximum current supply requirements.

2.18

2.19

Don’t use (DU)

This pin should not be used as it is internally connected. Its voltage level can be between

V

and V

or leave it unconnected.

SS

DDQ

Not connected (NC)

This pin is not physically connected to the device.

17/70

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

3

Bus operations

Each bus operation that controls the memory is described in this section, see Table 4,

Table 5 and Table 6 Bus operations, for a summary. The bus operation is selected through

the burst configuration register; the bits in this register are described at the end of this

section.

On power-up or after a hardware reset the memory defaults to asynchronous bus read and

asynchronous bus write, no other bus operation can be performed until the burst control

register has been configured.

The electronic signature, CFI or status register will be read in asynchronous mode

regardless of the burst control register settings.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1

Asynchronous bus operations

For asynchronous bus operations refer to Table 4 together with the following text.

3.1.1

Asynchronous bus read

Asynchronous bus read operations read from the memory cells, or specific registers

(electronic signature, status register, CFI and burst configuration register) in the command

interface. A valid bus operation involves setting the desired address on the address inputs,

applying a Low signal, V , to Chip Enable and Output Enable and keeping Write Enable and

IL

Output Disable High, V . The data inputs/outputs will output the value, see Figure 8:

IH

Asynchronous bus read AC waveforms, and Table 16: Asynchronous bus read AC

characteristics, for details of when the output becomes valid.

Asynchronous read is the default read mode which the device enters on power-up or on

return from reset/power-down.

3.1.2

Asynchronous latch controlled bus read

Asynchronous latch controlled bus read operations read from the memory cells or specific

registers in the command interface. The address is latched in the memory before the value

is output on the data bus, allowing the address to change during the cycle without affecting

the address that the memory uses.

A valid bus operation involves setting the desired address on the address inputs, setting

Chip Enable and Latch Enable Low, V and keeping Write Enable High, V ; the address is

IL

IH

latched on the rising edge of Latch Enable. Once latched, the address inputs can change.

Set Output Enable Low, V , to read the data on the data inputs/outputs; see Figure 9:

IL

Asynchronous latch controlled bus read AC waveforms, and Table 17: Asynchronous latch

controlled bus read AC characteristics, for details on when the output becomes valid.

Note that, since the Latch Enable input is transparent when set Low, V , asynchronous bus

IL

read operations can be performed when the memory is configured for asynchronous latch

enable bus operations by holding Latch Enable Low, V throughout the bus operation.

IL

18/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

3.1.3

Asynchronous page read

Asynchronous page read operations are used to read from several addresses within the

same memory page. Each memory page is 4 double-words and is addressed by the

address inputs A0 and A1.

Data is read internally and stored in the page buffer. Valid bus operations are the same as

asynchronous bus read operations but with different timings. The first read operation within

the page has identical timings, subsequent reads within the same page have much shorter

access times. If the page changes then the normal, longer timings apply again. Page read

does not support latched controlled read.

See Figure 10: Asynchronous page read AC waveforms, and Table 18: Asynchronous page

read AC characteristics, for details on when the outputs become valid.

3.1.4

Asynchronous bus write

Asynchronous bus write operations write to the command interface to send commands to

the memory or to latch addresses and input data to program. Bus write operations are

asynchronous, the clock, K, is don’t care during bus write operations.

A valid asynchronous bus write operation begins by setting the desired address on the

address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V , and

IL

Output Enable High, V , or Output Disable Low, V . The address inputs are latched by the

IH

IL

command interface on the rising edge of Chip Enable or Write Enable, whichever occurs

first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write

Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable

Low, during the whole asynchronous bus write operation.

See Figure 11: Asynchronous write AC waveforms, and Table 19: Asynchronous write and

latch controlled write AC characteristics, for details of the timing requirements.

3.1.5

Asynchronous latch controlled bus write

Asynchronous latch controlled bus write operations write to the command interface to send

commands to the memory or to latch addresses and input data to program. Bus write

operations are asynchronous, the clock, K, is don’t care during bus write operations.

A valid asynchronous latch controlled bus write operation begins by setting the desired

address on the address inputs and pulsing Latch Enable Low, V . The address inputs are

IL

latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip

Enable, whichever occurs first. Commands and input data are latched on the rising edge of

Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain

High, and Output Disable Low, during the whole asynchronous bus write operation.

See Figure 12: Asynchronous latch controlled write AC waveforms, and Table 19:

Asynchronous write and latch controlled write AC characteristics, for details of the timing

requirements.

3.1.6

Output Disable

The data outputs are high impedance when the Output Enable, G, is at V or Output

IH

Disable, GD, is at V .

IL

19/70

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

3.1.7

Standby mode

When Chip Enable is High, V , and the Program/Erase controller is idle, the memory enters

IH

Standby mode, the power consumption is reduced to the standby level and the Data

inputs/outputs pins are placed in the high impedance state regardless of Output Enable,

Write Enable or Output Disable inputs.

3.1.8

Automatic low power mode

If there is no change in the state of the bus for a short period of time during asynchronous

bus read operations the memory enters auto low power mode where the internal supply

current is reduced to the auto-standby supply current. The data inputs/outputs will still

output data if a bus read operation is in progress.

Automatic low power is only available in asynchronous read modes.

3.1.9

Power-down mode

The memory is in power-down when Reset/Power-down, RP, is at V . The power

IL

consumption is reduced to the power-down level and the outputs are high impedance,

independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable,

W, inputs.

3.1.10

Electronic signature

Two codes identifying the manufacturer and the device can be read from the memory

allowing programming equipment or applications to automatically match their interface to

the characteristics of the memory. The electronic signature is output by giving the Read

Electronic Signature command. The manufacturer code is output when all the address

inputs are at V . The device code is output when A1 is at V and all the other address pins

IL

IH

are at V (see Table 5: Asynchronous read electronic signature operation). Issue a Read

IL

Memory Array command to return to read mode.

(1)

Table 4.

Asynchronous bus operations

Step

Bus operation

E

G

GD

W

RP

L

A0-A18 DQ0-DQ31

Asynchronous bus read

V_ILV_ILV_IHV_IHV_IHV_ILAddress Data output

Address Latch V_ILV_IHV_IHV_ILV_IHV_ILAddress

Read V_ILV_ILV_IHV_IHV_IHV_IH

V_ILV_ILV_IHV_IHV_IH

V_ILV_IHV_ILV_IHV_ILAddress Data input

Address Latch V_ILV_ILV_IHV_IHV_IHV_ILAddress

High-Z

Asynchronous latch

controlled bus read

X

Data output

Asynchronous page read

Asynchronous bus write

X

Address Data output

X

High-Z

Data input

High-Z

Asynchronous latch

controlled bus write

Write

V_ILV_IH

X

V_ILV_IHV_IH

X

Output Enable, G

Output Disable, GD

Standby

V_ILV_IHV_IHV_IHV_IH

V_ILV_ILV_ILV_IHV_IH

X

High-Z

V_IH

X

V_IH

V_IL

High-Z

Reset/power-down

1. X = don’t care.

High-Z

20/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

Table 5.

Code

Asynchronous read electronic signature operation

Device

E

G

GD

W

A18-A0 DQ31-DQ0

Manufacturer

Device

All

V_IL

V_IH

00000h 00000020h

M58BW016DT

M58BW016FT

V_IL

V_IH

00001h 00008836h

00001h 00008835h

M58BW016DB

M58BW016FB

Burst configuration

register

00005h

BCR⁽¹⁾

1. BCR = Burst configuration register.

3.2

Synchronous bus operations

For synchronous bus operations refer to Table 6 together with the following text.

3.2.1

Synchronous burst read

Synchronous burst read operations are used to read from the memory at specific times

synchronized to an external reference clock.

In the M58BW016FT and M58BW016FB only, once the memory is configured in burst

mode, it is mandatory to have an active clock signal since the switching of the output buffer

data bus is synchronized to the active edge of the clock. In the absence of clock, no data is

output.

Caution:

The M58BW016DT and M58BW016DB are not concerned by the paragraph above.

The burst type, length and latency can be configured. The different configurations for

synchronous burst read operations are described in Section 3.3: Burst configuration

register. Refer to Figure 4 and Figure 5 for examples of synchronous burst operations.

In continuous burst read, one burst read operation can access the entire memory

sequentially by keeping the Burst Address Advance B at V for the appropriate number of

IL

clock cycles. At the end of the memory address space the burst read restarts from the

beginning at address 000000h.

A valid synchronous burst read operation begins when the Burst Clock is active and Chip

Enable and Latch Enable are Low, V . The burst start address is latched and loaded into

IL

the internal burst address counter on the valid Burst Clock K edge (rising or falling

depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle (or two clock

cycles depending on the value of M9). The Burst Address Advance B input controls the

memory burst output. The second burst output is on the next clock valid edge after the Burst

Address Advance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the burst

controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low

on the active clock edge, no new data is available and the memory does not increment the

internal address counter at the active clock edge even if Burst Address Advance, B, is Low.

21/70

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid

immediately at the valid clock edge or one data cycle before the valid clock edge.

Synchronous burst read will be suspended if Burst Address Advance, B, goes High, V .

IH

If Output Enable is at V and Output Disable is at V , the last data is still valid.

IL

IH

If Output Enable, G, is at V or Output Disable, GD, is at V , but the Burst Address

IH

IL

Advance, B, is at V the internal Burst Address counter is incremented at each Burst Clock

IL

K valid edge.

The synchronous burst read timing diagrams and AC characteristics are described in the AC

and DC parameters section. See Figure 13, Figure 14, Figure 15 and Figure 16, and

Table 20.

3.2.2

Synchronous burst read suspend

During a synchronous burst read operation it is possible to suspend the operation, freeing

the data bus for other higher priority devices.

A valid synchronous burst read operation is suspended when both Output Enable and Burst

Address Advance are High, V . The Burst Address Advance going High, V , stops the

IH

burst counter and the Output Enable going High, V , inhibits the data outputs. The

IH

synchronous burst read operation can be resumed by setting Output Enable Low.

(1)(2)

Table 6.

Synchronous burst read bus operations

A0-A18

DQ0-DQ31

Bus operation

Step

E

G

GD RP K⁽³⁾

L

B

Address Latch

Read

V_ILV_IH

V_ILV_ILV_IHV_IH

V_ILV_IHV_IH

V_ILV_ILV_IHV_IH

X

V_IH

T

X

T

V_IL

X

Address input

Data output

High-Z

V_IHV_IL

V_IHV_IH

V_IHV_IL

Read Suspend

Read Resume

X

Synchronous

burst read

Data output

Burst Address

Advance

V_ILV_IH

X

V_IH

T

V_IHV_IL

High-Z

Read Abort, E

V_IH

X

V_IH

V_IL

X

High-Z

Read Abort, RP

1. X = don't care, V_ILor V_IH

2. M15 = 0, bit M15 is in the burst configuration register.

3. T = transition, see M6 in the burst configuration register for details on the active edge of K.

.

22/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

3.3

Burst configuration register

The burst configuration register is used to configure the type of bus access that the memory

will perform.

The burst configuration register is set through the command interface and will retain its

information until it is re-configured, the device is reset, or the device goes into reset/power-

down mode. The burst configuration register bits are described in Table 7. They specify the

selection of the burst length, burst type, burst X and Y latencies and the read operation.

Refer to Figure 4 and Figure 5 for examples of synchronous burst configurations.

3.3.1

3.3.2

Read select bit (M15)

The read select bit, M15, is used to switch between asynchronous and synchronous bus

read operations. When the read select bit is set to ’1’, bus read operations are

asynchronous; when the read select bit is set to ’0’, bus read operations are synchronous.

On reset or power-up the read select bit is set to’1’ for asynchronous accesses.

X-Latency bits (M14-M11)

The X-Latency bits are used during synchronous bus read operations to set the number of

clock cycles between the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 7: Burst

configuration register. The X-Latency bits should also be selected in conjunction with

Table 8: Burst type definition to ensure valid settings.

3.3.3

Y-Latency bit (M9)

The Y-Latency bit is used during synchronous bus read operations to set the number of

clock cycles between consecutive reads. The Y-Latency value depends on both the X-

Latency value and the setting in M9.

When the Y-Latency is ‘1’ the data changes each clock cycle; when the Y-Latency is ‘2’ the

data changes every second clock cycle. See Table 7: Burst configuration register, and

Table 8: Burst type definition for valid combinations of the Y-Latency, the X-Latency and the

clock frequency.

3.3.4

3.3.5

Valid data ready bit (M8)

The valid data ready bit controls the timing of the valid data ready output pin, R. When the

valid data ready bit is ’0’ the valid data ready output pin is driven Low for the active clock

edge when invalid data is output on the bus. When the valid data ready bit is ’1’ the valid

data ready output pin is driven Low one clock cycle prior to invalid data being output on the

bus.

Burst type bit (M7)

The burst type bit is used to configure the sequence of addresses read as sequential or

interleaved. When the burst type bit is ’0’ the memory outputs from interleaved addresses;

when the burst type bit is ’1’ the memory outputs from sequential addresses. See Table 8:

Burst type definition, for the sequence of addresses output from a given starting address in

each mode.

23/70

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

3.3.6

3.3.7

3.3.8

Valid clock edge bit (M6)

The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, during

synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of

the clock is the active edge; when the valid clock edge bit is ’1’ the rising edge of the clock is

active.

Wrap burst bit (M3)

The burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or

overcome the boundary (no wrap). The wrap burst bit is used to select between wrap and no

wrap. When the wrap burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst

read does not wrap.

Burst length bit (M2-M0)

The burst length bits set the maximum number of double-words that can be output during a

synchronous burst read operation before the address wraps. Burst lengths of 4 or 8 are

available for both the sequential and interleaved burst types, and a continuous burst is

available for the sequential type.

Table 7: Burst configuration register gives the valid combinations of the burst length bits that

the memory accepts; Table 8: Burst type definition, gives the sequence of addresses output

from a given starting address for each length.

If either a continuous or a no wrap burst read has been initiated the device will output data

synchronously. Depending on the starting address, the device activates the valid data ready

output to indicate that a delay is necessary before the data is output. If the starting address

is aligned to an 8 double-word boundary, the continuous burst mode will run without

activating the valid data ready output. If the starting address is not aligned to an 8 double-

word boundary, valid data ready is activated to indicate that the device needs an internal

delay to read the successive words in the array.

M10, M5 and M4 are reserved for future use.

24/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

Table 7.

Bit

Burst configuration register

Description

Value

Description

Synchronous burst read

0

M15

M14

Read select

1

Asynchronous read (default at power-on)

Reserved (default value)

Reserved

4, 4-1-1-1⁽²⁾

5⁽³⁾, 5-1-1-1, 5-2-2-2

6⁽³⁾, 6-1-1-1, 6-2-2-2

0

000

001

010

011

100

101

110

111

0

M13-M11

X-Latency⁽¹⁾

7

8

⁽³⁾, 7-1-1-1, 7-2-2-2

⁽³⁾, 8-1-1-1, 8-2-2-2

Reserved

M10

M9

Reserved (default value)

One burst clock cycle (default value)

Two burst clock cycles

0

Y-Latency⁽⁴⁾

1

R valid Low during valid burst clock edge (default

value)

0

M8

Valid data ready

1

0

R valid Low 1 data cycle before valid burst clock edge

Interleaved (default value)

Sequential

M7

M6

Burst type

1

0

Falling burst clock edge (default value)

Rising burst clock edge

Reserved (default value)

Reserved

Valid clock edge

1

00

01

10

11

0

M5-M4

M3

Reserved

Wrap (default value)

No wrap

Wrapping

1

000

001

010

011

100

101

110

111

Reserved (default value)

4 double-words

8 double-words

Reserved

M2-M0

Burst length

Reserved

Continuous

1. X latencies can be calculated as: (t_AVQV– t_LLKH+ t_QVKH) + t_{SYSTEM MARGIN}< (X -1) t_K. (X is an integer

number from 4 to 8, t_Kis the clock period and t_{SYSTEM MARGIN}is the time margin required for the

calculation).

2. This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for

the M58BW016D version only if the operative frequency is below 45 MHz.

3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.

4. Y latencies can be calculated as: t_KHQV+ t_{SYSTEM MARGIN}+ t_QVKH< Y t_K.

25/70

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Table 8.

Burst type definition

Starting x 4 x 4

address sequential interleaved

x 8

sequential

x 8

interleaved

M 3

Continuous

0

1

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

–

0-1-2-3

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

–

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

0-1-2-3-4-5-6-7-8-9-10..

1-2-3-4-5-6-7-8-9-10-11..

2-3-4-5-6-7-8-9-10-11-12..

3-4-5-6-7-8-9-10-11-12-13..

4-5-6-7-8-9-10-11-2-13-14..

5-6-7-8-9-10-11-12-13-14..

1-0-3-2

2-3-0-1

3-2-1-0

–

6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15..

7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16..

–

8-9-10-11-12-13-14-15-16-17..

0-1-2-3-4-5-6-7-8-9-10..

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

4-5-6-7

5-6-7-8

6-7-8-9

7-8-9-10

8-9-10-11

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

8-9-10-11-12-13-14-15

1-2-3-4-5-6-7-8-9-10-11..

2-3-4-5-6-7-8-9-10-11-12..

3-4-5-6-7-8-9-10-11-12-13..

4-5-6-7-8-9-10-11-12-13-14..

5-6-7-8-9-10-11-12-13-14..

6-7-8-9-10-11-12-13-14-15..

7-8-9-10-11-12-13-14-15-16..

8-9-10-11-12-13-14-15-16-17..

26/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

Figure 4.

Example burst configuration X-1-1-1

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

VALID

4-1-1-1

5-1-1-1

DQ

VALID

DQ

VALID

6-1-1-1

7-1-1-1

8-1-1-1

VALID

AI03841

Figure 5.

Example burst configuration X-2-2-2

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

NV

VALID

NV

VALID

NV

VALID

5-2-2-2

DQ

NV

VALID

NV

VALID

NV

VALID

NV

VALID

NV

6-2-2-2

7-2-2-2

8-2-2-2

VALID

NV=NOT VALID

AI04406b

27/70

Command interface

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

4

Command interface

All bus write operations to the memory are interpreted by the command interface.

Commands consist of one or more sequential bus write operations. The commands are

summarized in Table 9: Commands. Refer to Table 9 in conjunction with the text

descriptions below.

4.1

4.2

Read Memory Array command

The Read Memory Array command returns the memory to read mode. One bus write cycle

is required to issue the Read Memory Array command and return the memory to read mode.

Subsequent read operations will output the addressed memory array data. Once the

command is issued the memory remains in read mode until another command is issued.

From read mode bus read commands will access the memory array.

Read Electronic Signature command

The Read Electronic Signature command is used to read the manufacturer code, the device

code or the burst configuration register. One bus write cycle is required to issue the Read

Electronic Signature command. Once the command is issued subsequent bus read

operations, depending on the address specified, read the manufacturer code, the device

code or the burst configuration register until another command is issued; see Table 5:

Asynchronous read electronic signature operation.

4.3

Read Query command

The Read Query command is used to read data from the common Flash interface (CFI)

memory area. One bus write cycle is required to issue the Read Query command. Once the

command is issued subsequent bus read operations, depending on the address specified,

read from the common Flash interface memory area. See Appendix A: Common Flash

interface (CFI), Table 26, Table 27, Table 28, Table 29 and Table 30 for details on the

information contained in the common Flash interface (CFI) memory area.

28/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Command interface

4.4

Read Status Register command

The Read Status Register command is used to read the status register. One bus write cycle

is required to issue the Read Status Register command. Once the command is issued

subsequent bus read operations read the status register until another command is issued.

The status register information is present on the output data bus (DQ1-DQ7) when Chip

Enable E and Output Enable G are at V and Output Disable is at V .

IL

IH

An interactive update of the status register bits is possible by toggling Output Enable or

Output Disable. It is also possible during a program or erase operation, by deactivating the

device with Chip Enable at V and then reactivating it with Chip Enable and Output Enable

IH

at V and Output Disable at V .

IL

IH

The content of the status register may also be read at the completion of a program, erase or

suspend operation. During a Block Erase or Program command, DQ7 indicates the

program/erase controller status. It is valid until the operation is completed or suspended.

See the section on the status register and Table 11 for details on the definitions of the status

register bits.

4.5

Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the status

register to ‘0’. One bus write is required to issue the Clear Status Register command. Once

the command is issued the memory returns to its previous mode, subsequent bus read

operations continue to output the same data.

The bits in the status register are sticky and do not automatically return to ‘0’ when a new

Program or Erase command is issued. If any error occurs then it is essential to clear any

error bits in the status register by issuing the Clear Status Register command before

attempting a new Program, Erase or Resume command.

29/70

Command interface

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

4.6

Block Erase command

The Block Erase command can be used to erase a block. It sets all of the bits in the block to

‘1’. All previous data in the block is lost. If the block is protected then the erase operation will

abort, the data in the block will not be changed and the status register will output the error.

Two bus write operations are required to issue the command; the first write cycle sets up the

Block Erase command, the second write cycle confirms the Block Erase command and

latches the block address in the program/erase controller and starts it. The sequence is

aborted if the Confirm command is not given and the device will output the status register

data with bits 4 and 5 set to '1'.

Once the command is issued subsequent bus read operations read the status register. See

the section on the status register for details on the definitions of the status register bits.

During the erase operation the memory will only accept the Read Status Register command

and the Program/Erase Suspend command. All other commands will be ignored. The

command can be executed using either V (for a normal erase operation) or V (for a fast

DD

PP

erase operation). If V is in the V

range when the command is issued then a fast erase

PP

PPH

operation will be executed, otherwise the operation will use V . If V goes below the V

DD

PP

lockout voltage, V

, during a fast erase the operation aborts, the status register V

PPLK

PP

status bit is set to ‘1’ and the command must be re-issued.

Typical erase times are given in Table 10.

See Appendix B: Flowcharts, Figure 24: Block erase flowchart and pseudocode, for a

suggested flowchart on using the Block Erase command.

4.7

Program command

The Program command is used to program the memory array. Two bus write operations are

required to issue the command; the first write cycle sets up the Program command, the

second write cycle latches the address and data to be programmed in the program/erase

controller and starts it. A program operation can be aborted by writing FFFFFFFFh to any

address after the program set-up command has been given.

Once the command is issued subsequent bus read operations read the status register. See

the section on the status register for details on the definitions of the status register bits.

During the program operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

If Reset/Power-down, RP, falls to V during programming the operation will be aborted.

IL

The command can be executed using either V (for a normal program operation) or V

DD

PP

(for a fast program operation). If V is in the V

range when the command is issued then

PP

PPH

a fast program operation will be executed, otherwise the operation will use V . If V goes

DD

PP

below the V lockout voltage, V

, during a fast program the operation aborts and the

PP

PPLK

status register V status bit is set to ‘1’. As data integrity cannot be guaranteed when the

PP

program operation is aborted, the memory block must be erased and reprogrammed.

See Appendix B: Flowcharts on page 59, Figure 22: Program flowchart and pseudocode, for

a suggested flowchart on using the Program command.

30/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Command interface

4.8

Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a program or erase operation. The

command will only be accepted during a program or erase operation. It can be issued at any

time during a program or erase operation. The command is ignored if the device is already

in suspend mode.

One bus write cycle is required to issue the Program/Erase Suspend command and pause

the program/erase controller. Once the command is issued it is necessary to poll the

program/erase controller status bit (bit 7) to find out when the program/erase controller has

paused; no other commands will be accepted until the program/erase controller has paused.

After the program/erase controller has paused, the memory will continue to output the status

register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the

program/erase controller pausing it is possible for the operation to complete. Once the

program/erase controller status bit (bit 7) indicates that the program/erase controller is no

longer active, the program suspend status bit (bit 2) or the erase suspend status bit (bit 6)

can be used to determine if the operation has completed or is suspended. For timing on the

delay between issuing the Program/Erase Suspend command and the program/erase

controller pausing see Table 10.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read

Electronic Signature, Read Query and Program/Erase Resume commands will be accepted

by the command interface. Additionally, if the suspended operation was erase then the

Program and the Program Suspend commands will also be accepted. When a program

operation is completed inside a Block Erase Suspend the Read Memory Array command

must be issued to reset the device in read mode, then the Erase Resume command can be

issued to complete the whole sequence. Only the blocks not being erased may be read or

programmed correctly.

See Appendix B: Flowcharts, Figure 23: Program suspend & resume flowchart and

pseudocode, and Figure 25: Erase suspend & resume flowchart and pseudocode, for

suggested flowcharts on using the Program/Erase Suspend command.

4.9

Program/Erase Resume command

The Program/Erase Resume command can be used to restart the program/erase controller

after a program/erase suspend operation has paused it. One bus write cycle is required to

issue the Program/Erase Resume command.

See Appendix B: Flowcharts, Figure 23: Program suspend & resume flowchart and

pseudocode, and Figure 25: Erase suspend & resume flowchart and pseudocode, for

suggested flowcharts on using the Program/Erase Resume command.

31/70

Command interface

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

4.10

Set Burst Configuration Register command

The Set Burst Configuration Register command is used to write a new value to the burst

configuration control register which defines the burst length, type, X and Y latencies,

synchronous/asynchronous read mode and the valid clock edge configuration.

Two bus write cycles are required to issue the Set Burst Configuration Register command.

The first cycle writes the setup command and the address corresponding to the set burst

configuration register content. The second cycle writes the burst configuration register data

and the confirm command. Once the command is issued the memory returns to read mode

as if a Read Memory Array command had been issued.

The value for the burst configuration register is always presented on A0-A15. M0 is on A0,

M1 on A1, etc.; the other address bits are ignored.

(1)

Table 9.

Commands

Bus operations

Command

1st cycle

2nd cycle

Op.

Addr.

Data

Op.

Addr.

Data

Read Memory Array

≥ 2

Write

X

FFh

Read

RA

RD

Read Electronic Signature

(manufacturer code)

Write

X

90h

Read

00000h

00001h

00005h

20h

IDh

Read Electronic Signature

(device code)

≥ 2

Read Electronic Signature

(burst configuration register)

BCRh

Read Status Register

Read Query

2

≥ 2

1

Write

X

70h

98h

50h

20h

Read

X

SRDh

QDh

QAh

Clear Status Register

Block Erase

2

Write

BAh

PA

D0h

PD

40h

10h

Program

2

Write

X

Program/Erase Suspend

Program/Erase Resume

1

2

Write

X

B0h

D0h

60h

Set Burst Configuration Register

Write

BCRh

03h

1. X = Don’t care; RA = Read Address, RD = Read Data, ID = Device Code, SRD = Status Register Data, PA

= Program Address; PD = Program Data, QA = Query Address, QD = Query Data, BA = Any address in the

Block, BCR = Burst Configuration Register value.

32/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Command interface

(1)

Table 10. Program, erase times and program, erase endurance cycles

M58BW016

Parameters

Typ

Max

Unit

Min

V_PP= V_DDV_PP= 12 V V_PP= V_DDV_PP= 12 V

Parameter Block (64 Kbits)

Program

0.030

0.23

0.016

0.13

0.060

0.46

0.032

0.26

s

Main Block (512 Kbits)

Program

Parameter Block Erase

Main Block Erase

0.8

1.5

0.64

0.9

1.8

3

1.5

1.8

s

Program Suspend Latency

time

3

10

30

µs

Erase Suspend Latency time

10

Program/Erase cycles (per

block)

100,000

cycles

1. T_A= –40 to 125 °C, V_DD= 2.7 V to 3.6 V, V_DDQ= 2.4 V to V_DD

.

33/70

Status register

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

5

Status register

The Status register provides information on the current or previous program or erase

operation. The various bits in the status register convey information and errors on the

operation. They are output on DQ7-DQ0.

To read the status register the Read Status Register command can be issued. The status

register is automatically read after Program, Erase or Program/Erase Resume commands.

The status register can be read from any address.

The contents of the status register can be updated during an erase or program operation by

toggling the Output Enable or Output Disable pins or by deactivating (Chip Enable, V ) and

IH

then reactivating (Chip Enable and Output Enable, V , and Output Disable, V .) the device.

IL

IH

The status register bits are summarized in Table 11: Status register bits. Refer to Table 11 in

conjunction with the following text descriptions.

5.1

Program/erase controller status (bit 7)

The Program/erase controller status bit indicates whether the program/erase controller is

active or inactive. When the program/erase controller status bit is set to ‘0’, the

program/erase controller is active; when bit7 is set to ‘1’, the program/erase controller is

inactive.

The program/erase controller status is set to ‘0’ immediately after a Program/Erase Suspend

command is issued until the program/erase controller pauses. After the program/erase

controller pauses the bit is set to ‘1’.

During program and erase operations the program/erase controller status bit can be polled

to find the end of the operation. The other bits in the status register should not be tested until

the program/erase controller completes the operation and the bit is set to ‘1’.

After the program/erase controller completes its operation the erase status (bit5), program

status bits should be tested for errors.

5.2

Erase suspend status (bit 6)

The erase suspend status bit indicates that an erase operation has been suspended and is

waiting to be resumed. The erase suspend status should only be considered valid when the

program/erase controller status bit is set to ‘1’ (program/erase controller inactive); after a

Program/Erase Suspend command is issued the memory may still complete the operation

rather than entering the suspend mode.

When the erase suspend status bit is set to ‘0’, the program/erase controller is active or has

completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has

been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the erase suspend status bit returns to

‘0’.

34/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Status register

5.3

Erase status (bit 5)

The erase status bit can be used to identify if the memory has failed to verify that the block

has erased correctly. The erase status bit should be read once the program/erase controller

status bit is High (program/erase controller inactive).

When the erase status bit is set to ‘0’, the memory has successfully verified that the block

has erased correctly. When the erase status bit is set to ‘1’, the program/erase controller has

applied the maximum number of pulses to the block and still failed to verify that the block

has erased correctly.

Once set to ‘1’, the erase status bit can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

5.4

Program status (bit 4)

The program status bit is used to identify a program failure. Bit4 should be read once the

program/erase controller status bit is High (program/erase controller inactive).

When bit4 is set to ‘0’ the memory has successfully verified that the device has programmed

correctly. When bit4 is set to ‘1’ the device has failed to verify that the data has been

programmed correctly.

Once set to 1’, the program status bit can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

5.5

V_PPstatus (bit 3)

The V status bit can be used to identify an invalid voltage on the V pin during fast

PP

program and erase operations. The V pin is only sampled at the beginning of a program

PP

or erase operation. Indeterminate results can occur if V becomes invalid during a fast

PP

program or erase operation.

When the V status bit is set to ‘0’, the voltage on the V pin was sampled at a valid

PP

voltage; when the V status bit is set to ‘1’, the V pin has a voltage that is below the V

PP

lockout voltage, V

.

PPLK

Once set to ‘1’, the V status bit can only be reset to ‘0’ by a Clear Status Register

PP

command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

35/70

Status register

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

5.6

Program suspend status (bit 2)

The program suspend status bit indicates that a program operation has been suspended

and is waiting to be resumed. The program suspend status should only be considered valid

when the program/erase controller status bit is set to ‘1’ (program/erase controller inactive);

after a Program/Erase Suspend command is issued the memory may still complete the

operation rather than entering the suspend mode.

When the program suspend status bit is set to ‘0’, the program/erase controller is active or

has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command

has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the program suspend status bit returns

to ‘0’.

5.7

Block protection status (bit 1)

The block protection status bit can be used to identify if a program or erase operation has

tried to modify the contents of a protected block.

When the block protection status bit is set to ‘0’, no program or erase operations have been

attempted to protected blocks since the last Clear Status Register command or hardware

reset; when the block protection status bit is set to ‘1’, a program or erase operation has

been attempted on a protected block.

Once set to ‘1’, the block protection status bit can only be reset Low by a Clear Status

Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program

or Erase command is issued, otherwise the new command will appear to fail.

All others bits are reserved.

Table 11. Status register bits

Bit

Name

Logic level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

Ready

Program/erase controller

status

7

Busy

Suspended

6

5

4

3

2

1

Erase suspend status

Erase status

In progress or completed

Erase error

Erase success

Program error

Program status,

Program success

V_PPinvalid, abort

V_PPstatus

V_PPOK

Suspended

Program suspend status

In progress or completed

Program/erase on protected block, abort

No operations to protected sectors

Erase/program in a protected

block

Other bits reserved

36/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Maximum ratings

6

Maximum ratings

Stressing the device above the ratings listed in Table 12: Absolute maximum ratings, may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 12. Absolute maximum ratings

Value

Symbol

Parameter

Unit

Min

Max

T_BIAS

T_STG

Temperature under bias

Storage temperature

–40

–55

125

155

°C

V_DDQ+ 0.6

V_IO

Input or output voltage

–0.6

V

V_DDQIN+ 0.6

V

_DD, V_DDQ,V_DDQINSupply voltage

–0.6

4.2

V

V_PPProgram voltage

13.5⁽¹⁾

1. Cumulative time at a high voltage level of 13.5 V should not exceed 80 hours on V_PPpin.

37/70

DC and AC parameters

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

7

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 13: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the measurement conditions when relying on the

quoted parameters.

Table 13. Operating and AC measurement conditions

Value

Parameter

Units

Min

Max

Supply voltage (V_DD

)

2.7

2.4

3.6

V_DD

90

V

Input/output supply voltage (V_DDQ

)

Grade 6

Grade 3

–40

°C

pF

ns

V

Ambient temperature (T_A)

125

Load capacitance (C_L)

Clock rise and fall times

Input rise and fall times

Input pulses voltages

30

4

0 to V_DDQ

V_DDQ/2

Input and output timing ref. voltages

V

Figure 6.

AC measurement input/output waveform

V

DDQ

V

DDQIN

V

/2

DDQ

V

DDQIN

0 V

AI04153

1. V_DD= V_DDQ

.

38/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Figure 7. AC measurement load circuit

DC and AC parameters

1.3 V

1N914

3.3 kΩ

DEVICE

UNDER

TEST

OUT

C

L

C

includes JIG capacitance

L

AI04154

(1)(2)

Table 14. Device capacitance

Symbol

Parameter

Test condition

Typ

Max

Unit

C_IN

Input capacitance

V_IN= 0 V

6

8

pF

C_OUT

Output capacitance

V_OUT= 0 V

12

1. T_A= 25 °C, f = 1 MHz.

2. Sampled only, not 100% tested.

39/70

DC and AC parameters

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Table 15. DC characteristics

Symbol

Parameter

Test condition

Min

Max

Unit

I_LI

Input Leakage current

Output Leakage current

0 V≤V_IN≤V_DDQ

0 V≤V_OUT≤V_DDQ

1

5

µA

I_LO

M58BW016DT/B

M58BW016FT/B

20

25

E = V_IL,G = V_IH,

f_add= 6 MHz

I_DD

Supply current (Random Read)

Supply current (Power-up)

mA

applies only to

M58BW016FT/B

(1)

I_DDP-UP

E = V_IH

20

30

M58BW016DT/B

M58BW016FT/B

M58BW016DT/B

M58BW016FT/B

M58BW016DT/B

M58BW016FT/B

E = V_IL,G = V_IH,

f

_clock= 40 MHz

I_DDB

Supply current (Burst Read)

Supply current (Standby)

30

40

mA

µA

E = V_IL,G = V_IH,

f_clock= 56 MHz

60

E = RP = V_DD

0.2 V

150

µA

I_DD1

E = V_SS0.2 V,

RP = V_DD0.2 V

Supply current (Auto Low-Power)

Supply current (Reset/Power-down)

60

30

µA

I_DD2

I_DD3

RP = V_SS0.2 V

Supply current (Program or Erase,

Set Lock bit, Erase Lock bit)

Program, Block Erase in progress

mA

M58BW016DT/B

E = V_IH

40

150

30

µA

mA

µA

mA

V

Supply current

(Erase/Program Suspend)

I_DD4

M58BW016FT/B

I_PP

I_PP1

I_PP2

Program current (Read or Standby)

Program current (Power-down)

V_PP≥ V_PP1

V_PP≤V_PP1

RP = V_IL

30

5

V_PP= V_PP1

V_PP= V_PPH

V_PP= V_PP1

200

20

Program current (Program)

Program in progress

I_PP3

200

20

Program current (Erase) Erase in

progress

I_PP4

V_PP= V_PPH

V_IL

Input Low voltage

–0.5

0.2V_DDQIN

V_IH

Input High voltage (for DQ lines)

0.8V_DDQINV_DDQ+0.3

V

Input High voltage (for input only

lines)

V_IH

0.8V_DDQIN

3.6

0.1

V

V_OL

V_OH

Output Low voltage

I_OL= 100 µA

V

Output High voltage CMOS

I_OH= –100 µA

V_DDQ–0.1

2.7

Program voltage

(program or erase operations)

V_PP1

V_PPH

V_LKO

V_PPLK

3.6

12.6

2.2

V

Program voltage

(program or erase operations)

11.4

V_DDsupply voltage (erase and

program lockout)

V_PPsupply voltage (erase and

program lockout)

11.4

1. I_DDP-UPis defined only during the power-up phase of the M58BW016FT/B, from the moment current is applied with RP Low

to the moment when the supply voltage has become stable and RP is brought to High.

40/70

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

DC and AC parameters

Figure 8.

Asynchronous bus read AC waveforms

tAVAV

VALID

A0-A18

tAVQV

tEHLX

tLLEL

L

tELQX

tELQV

tAXQX

E

tGLQX

tGLQV

tEHQX

tEHQZ

G

GD

tGHQX

tGHQZ

DQ0-DQ31

OUTPUT


型号：	M58BW016FB8ZA3FT
厂家：	NUMONYX B.V
描述：	16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories 16兆位（ 512千位×32 ，引导块，爆） 3 V电源闪存闪存
文件：	总70页 (文件大小：1354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58BW016FB8ZA3FT [NUMONYX]

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