M58WT032KT70ZAQ6F [NUMONYX]
Flash, 2MX16, 70ns, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88;
| 型号： | M58WT032KT70ZAQ6F |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 2MX16, 70ns, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88 内存集成电路 闪存 |
| 文件： | 总117页 (文件大小：2112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M58WT032KT M58WT064KT
M58WT032KB M58WT064KB
32- and 64-Mbit (×16, multiple bank, burst)
1.8 V core, 3.0 V I/O supply Flash memories
Features
■ Supply voltage
– V = 1.7 V to 2 V for program, erase and
DD
read
FBGA
– V
= 2.7 V to 3.3 V for I/O buffers
DDQ
– V = 9 V for fast program
PP
■ Synchronous/asynchronous read
TFBGA88 (ZAQ)
8 × 10 mm
– Synchronous burst read mode: 52 MHz
– Asynchronous/synchronous page read
mode
– Random access times: 70 ns
■ Synchronous burst read suspend
■ Programming time
■ Security
– 10 µs by word typical for fast factory
program
– 128-bit user programmable OTP cells
– 64-bit unique device number
– Double/quadruple word program option
– Enhanced factory program options
■ Common Flash interface (CFI)
■ 100 000 program/erase cycles per block
■ Memory blocks
■ Electronic signature
– Multiple bank memory array: 4 Mbit banks
– Parameter blocks (top or bottom location)
– Manufacturer code: 20h
– Device codes:
M58WT032KT (top): 8866h
M58WT032KB (bottom): 8867h
– M58WT064KT (top): 8810h
M58WT064KB (bottom): 8811h
■ Dual operations
– Program erase in one bank while read in
others
– No delay between read and write
operations
■ ECOPACK® package available
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
– WP for block lock-down
March 2008
Rev 2
1/117
www.numonyx.com
1
Contents
M58WTxxxKT, M58WTxxxKB
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11
2.12
2.13
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
3.2
3.3
3.4
3.5
3.6
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
5
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command interface - standard commands . . . . . . . . . . . . . . . . . . . . . 21
5.1
5.2
5.3
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M58WTxxxKT, M58WTxxxKB
Contents
5.4
5.5
5.6
5.7
5.8
5.9
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.10 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.11 The Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . 25
5.12 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.13 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.14 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Command interface - factory program commands . . . . . . . . . . . . . . . 29
6.1
6.2
6.3
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1
6.3.2
6.3.3
6.3.4
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4
Quadruple Enhanced Factory Program command . . . . . . . . . . . . . . . . . . 33
6.4.1
6.4.2
6.4.3
6.4.4
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Load phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 36
Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Program suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 39
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Contents
M58WTxxxKT, M58WTxxxKB
8
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
X latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data output configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Valid clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1
9.2
9.3
9.4
Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10
11
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 51
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1 Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.2 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.5 Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 54
12
13
14
15
16
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 56
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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M58WTxxxKT, M58WTxxxKB
Contents
Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix B Common Flash interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
16.1 Enhanced factory program pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 108
16.2 Quadruple enhanced factory program pseudo code . . . . . . . . . . . . . . . 110
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5/117
List of tables
M58WTxxxKT, M58WTxxxKB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M58WT032KT/B bank architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M58WT064KT/B bank architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Factory program commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TFBGA88 8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch, package mechanical data. . . . . . . 74
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Top boot block addresses, M58WT032KT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Bottom boot block addresses, M58WT032KB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Top boot block addresses, M58WT064KT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Bottom boot block addresses, M58WT064KB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Bank and Erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Command interface states - modify table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Command interface states - Lock table, next state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Command interface states - lock table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
6/117
M58WTxxxKT, M58WTxxxKB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58WT032KT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
M58WT064KT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
X latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 12. Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 13. Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 14. Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15. Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. TFBGA88 8 × 10 mm, 8 × 10 ball array, 0.8 mm, package outline. . . . . . . . . . . . . . . . . . . 73
Figure 20. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 21. Double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 22. Quadruple word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 23. Program suspend and resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 24. Block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 25. Erase suspend and resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 26. Locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 27. Protection Register program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 28. Enhanced factory program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 29. Quadruple enhanced factory program flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7/117
Description
M58WTxxxKT, M58WTxxxKB
1
Description
The M58WT032KT/B and M58WT064KT/B are 32 Mbit (2 Mbit ×16) and 64 Mbit (4 Mbit
×16) non-volatile Flash memories, respectively. They can be erased electrically at block
level and programmed in-system on a word-by-word basis using a 1.7 V to 2 V V supply
DD
for the circuitry and a 2.7 V to 3.3 V V
supply for the input/output pins. An optional 9 V
DDQ
V
power supply is provided to speed up customer programming.
PP
M58WTxxxKT/B is the collective name for all these devices. They feature an asymmetrical
block architecture.
●
●
The M58WT032KT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There
are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank
containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
The M58WT064KT/B has an array of 135 blocks, and is divided into 4 Mbit banks.
There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter
bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
The multiple bank architecture allows dual operations. While programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architectures are summarized in Table 2 and Table 3 and the memory maps are
shown in Figure 3 and Figure 4. The parameter blocks are located at the top of the memory
address space for the M58WT032KT and M58WT064KT, and at the bottom for the
M58WT032KB and M58WT064KB.
Each block can be erased separately. Erase can be suspended to perform program in any
other block, and then resumed. Program can be suspended to read data in any other block
and then resumed. Each block can be programmed and erased over 100 000 cycles using
the supply voltage V . Two enhanced factory programming commands are available to
DD
speed up programming.
Program and erase commands are written to the command interface of the memory. An
internal Program/Erase Controller manages the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst mode, data is output on each clock cycle at frequencies of up to 52 MHz. The
synchronous burst read operation can be suspended and resumed.
The device features an automatic standby mode. When the bus is inactive during
asynchronous read operations, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value I
outputs are still driven.
and the
DD4
8/117
M58WTxxxKT, M58WTxxxKB
Description
The M58WTxxxKT/B feature an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is additional hardware protection
against program and erase. When V ≤V
all blocks are protected against program or
PP
PPLK
erase. All blocks are locked at power-up.
The device includes a Protection Register to increase the protection of a system’s design.
The Protection Register is divided into two segments: a 64-bit segment containing a unique
device number written by Numonyx, and a 128-bit segment one-time-programmable (OTP)
by the user. The user programmable segment can be permanently protected. Figure 5
shows the Protection Register memory map.
The memory is offered TFBGA88, 8 × 10 mm, 8 × 10 active ball array, 0.8 mm pitch package
and is supplied with all the bits erased (set to ’1’).
9/117
Description
M58WTxxxKT, M58WTxxxKB
Figure 1.
Logic diagram
V
V
V
DD DDQ PP
16
(1)
A0-Amax
DQ0-DQ15
WAIT
W
E
M58WT032KT
M58WT032KB
M58WT064KT
M58WT064KB
G
RP
WP
L
K
V
SS
AI13420c
1. Amax is equal to A20 in the M58WT032KT/B and to A21 in the M58WT064KT/B.
Table 1.
Signal names
Signal name
Function
Direction
A0-Amax(1)
Address inputs
Inputs
I/O
DQ0-DQ15
Data input/outputs, command inputs
E
Chip Enable
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
G
Output Enable
W
Write Enable
RP
WP
K
Reset
Write Protect
Clock
L
Latch Enable
WAIT
VDD
VDDQ
VPP
VSS
NC
Wait
Supply voltage
Supply voltage for input/output buffers
Optional supply voltage for fast program and erase Input
Ground
Not connected internally
1. Amax is equal to A20 in the M58WT032KT/B and, to A21 in the M58WT064KT/B.
10/117
M58WTxxxKT, M58WTxxxKB
Description
(1)
Figure 2.
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
A5
A3
A2
DU
A18
NC
A17
A7
DU
DU
A11
A12
A13
A15
A16
NC
A21/
A19
NC
VSS
VDD
NC
NC
K
NC(1)
VSS
NC
A9
NC
VPP
NC
NC
NC
WP
L
A20
A8
A10
A1
A0
A6
NC
RP
W
A14
G
H
J
DQ8
DQ0
G
DQ2
DQ1
DQ9
DQ10
DQ3
DQ11
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
WAIT
DQ7
DQ15
VDDQ
VSS
NC
NC
E
NC
VDDQ
K
L
NC
VSS
DU
NC
NC
NC
NC
NC
VSS
DU
VSS
DU
VDDQ
VDD
VSS
VSS
M
DU
AI13811b
1. Ball B7 is A21 in the M58WT064KT/B, and is not connected internally (NC) in the M58WT032KT/B.
11/117
Description
M58WTxxxKT, M58WTxxxKB
Table 2.
Number
Parameter bank
M58WT032KT/B bank architecture
Bank size
Parameter blocks
Main blocks
4 Mbit
4 Mbit
4 Mbit
4 Mbit
8 blocks of 4 Kword
7 blocks of 32 Kword
8 blocks of 32 Kword
8 blocks of 32 Kword
8 blocks of 32 Kword
Bank 1
Bank 2
Bank 3
-
-
-
Bank 6
Bank 7
4 Mbit
4 Mbit
-
-
8 blocks of 32 Kword
8 blocks of 32 Kword
Table 3.
Number
Parameter Bank
M58WT064KT/B bank architecture
Bank size
Parameter blocks
Main blocks
4 Mbit
4 Mbit
4 Mbit
4 Mbit
8 blocks of 4 Kword
7 blocks of 32 Kword
8 blocks of 32 Kword
8 blocks of 32 Kword
8 blocks of 32 Kword
Bank 1
Bank 2
Bank 3
-
-
-
Bank 14
Bank 15
4 Mbit
4 Mbit
-
-
8 blocks of 32 Kword
8 blocks of 32 Kword
12/117
M58WTxxxKT, M58WTxxxKB
Description
Figure 3.
M58WT032KT/B memory map
M58WT032KT - Top Boot Block
Address lines A20-A0
M58WT032KB - Bottom Boot Block
Address lines A20-A0
000000h
007FFFh
000000h
000FFFh
32 KWord
32 KWord
4 KWord
8 Main
Blocks
8 Parameter
Blocks
Bank 7
038000h
03FFFFh
007000h
007FFFh
008000h
00FFFFh
4KWord
Parameter
Bank
32 KWord
7 Main
Blocks
038000h
03FFFFh
040000h
047FFFh
32 KWord
32 KWord
100000h
107FFFh
32 KWord
8 Main
Blocks
8 Main
Blocks
Bank 3
Bank 2
Bank 1
Bank 1
Bank 2
Bank 3
138000h
13FFFFh
140000h
147FFFh
078000h
07FFFFh
080000h
087FFFh
32 KWord
32 KWord
32 KWord
32 KWord
8 Main
Blocks
8 Main
Blocks
178000h
17FFFFh
180000h
187FFFh
0B8000h
0BFFFFh
0C0000h
0C7FFFh
32 KWord
32 KWord
32 KWord
32 KWord
8 Main
Blocks
8 Main
Blocks
1B8000h
1BFFFFh
1C0000h
1C7FFFh
0F8000h
0FFFFFh
32 KWord
32 KWord
32 KWord
7 Main
Blocks
1F0000h
1F7FFFh
1F8000h
1F8FFFh
32 KWord
4 KWord
Parameter
Bank
1C0000h
1C7FFFh
32 KWord
32 KWord
8 Parameter
Blocks
8 Main
Blocks
Bank 7
1FF000h
1FFFFFh
1F8000h
1FFFFFh
4 KWord
AI13421b
13/117
Description
M58WTxxxKT, M58WTxxxKB
Figure 4.
M58WT064KT/B memory map
M58WT064KT - Top Boot Block
Address lines A21-A0
M58WT064KB - Bottom Boot Block
Address lines A21-A0
000000h
007FFFh
000000h
4 KWord
32 KWord
000FFFh
8 Main
8 Parameter
Blocks
Blocks
Bank 15
038000h
03FFFFh
007000h
4KWord
007FFFh
32 KWord
Parameter
Bank
008000h
00FFFFh
32 KWord
7 Main
Blocks
038000h
32 KWord
03FFFFh
300000h
307FFFh
040000h
047FFFh
32 KWord
32 KWord
8 Main
Blocks
8 Main
Blocks
Bank 3
Bank 2
Bank 1
Bank 1
Bank 2
Bank 3
338000h
33FFFFh
340000h
347FFFh
078000h
32 KWord
07FFFFh
32 KWord
32 KWord
080000h
087FFFh
32 KWord
8 Main
Blocks
8 Main
Blocks
378000h
37FFFFh
380000h
387FFFh
0B8000h
32 KWord
0BFFFFh
32 KWord
32 KWord
0C0000h
32 KWord
8 Main
Blocks
0C7FFFh
8 Main
Blocks
3B8000h
3BFFFFh
3C0000h
3C7FFFh
0F8000h
32 KWord
0FFFFFh
32 KWord
32 KWord
7 Main
Blocks
3F0000h
3F7FFFh
3F8000h
3F8FFFh
32 KWord
4 KWord
Parameter
Bank
3C0000h
32 KWord
3C7FFFh
8 Main
8 Parameter
Blocks
Blocks
Bank 15
3FF000h
3FFFFFh
3F8000h
32 KWord
3FFFFFh
4 KWord
AI13784b
14/117
M58WTxxxKT, M58WTxxxKB
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-Amax)
Amax is the highest order address input. It is equal to A20 in the M58WT032KT/B and, to
A21 in the M58WT064KT/B. The address inputs select the cells in the memory array to
access during bus read operations. During bus write operations they control the commands
sent to the command interface of the Program/Erase Controller.
2.2
2.3
Data inputs/outputs (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance and the power consumption is reduced to the standby level.
2.4
2.5
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is at V , the lock-down is enabled and the protection status of the locked-
IL
down blocks cannot be changed. When Write Protect is at V , the lock-down is disabled
IH
and the locked-down blocks can be locked or unlocked. (refer to Table 16: Lock status).
15/117
Signal descriptions
M58WTxxxKT, M58WTxxxKB
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the reset supply current I
. Refer to Table 21: DC characteristics - currents for
DD2
the value of I
After Reset all blocks are in the locked state and the Configuration
DD2.
Register is reset. When Reset is at V , the device is in normal operation. Upon exiting reset
IH
mode the device enters asynchronous read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
2.8
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at V and it is inhibited when Latch Enable is at V . Latch Enable can
IL
IH
be kept Low (also at board level) when the Latch Enable function is not required or
supported.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V . Clock is ‘don't care’ during
IL
asynchronous read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V or Reset is
IH
at V . It can be configured to be active during the wait cycle or one clock cycle in advance.
IL
The WAIT signal is not gated by Output Enable.
2.11
2.12
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
VDDQ supply voltage
V
provides the power supply to the I/O pins and enables all outputs to be powered
DDQ
independently of V
.
DD
16/117
M58WTxxxKT, M58WTxxxKB
Signal descriptions
2.13
VPP program supply voltage
V
is both a control input and a power supply pin. The two functions are selected by the
PP
voltage range applied to the pin.
If V is kept in a low voltage range (0 V to V
) V is seen as a control input. In this case
PP
DDQ
PP
a voltage lower than V
provides absolute protection against program or erase, while
PPLK
V
in the V
range enables these functions (see Tables 21 and 22, DC characteristics for
PP
PP1
the relevant values). V is only sampled at the beginning of a program or erase; a change
PP
in its value after the operation has started does not have any effect and program or erase
operations continue.
If V is in the range of V
it acts as a power supply pin. In this condition V must be
PP
PP
PPH
stable until the program/erase algorithm is completed.
2.14
VSS ground
V
is the common ground reference for all votage measurements in the Flash (core and I/O
SS
buffers). It must be connected to the system ground.
Note:
Each device in a system should have V , V and V decoupled with a 0.1 µF ceramic
DD DDQ
PP
capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be
as close as possible to the package). See Figure 9: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required V program and erase currents.
PP
17/117
Bus operations
M58WTxxxKT, M58WTxxxKB
3
Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See Table 4: Bus operations for a
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1
Bus read
Bus read operations output the contents of the memory array, the electronic signature, the
Status Register and the common Flash interface. Both Chip Enable and Output Enable must
be at V in order to perform a read operation. The Chip Enable input should be used to
IL
enable the device. Output Enable should be used to gate data onto the output. The data
read depends on the previous command written to the memory (see Section 4: Command
interface). See Figures 10, 11, 12 and 13, read AC waveforms, and Tables 23 and 24, read
AC characteristics, for details of when the output becomes valid.
3.2
Bus write
Bus write operations write commands to the memory or latch input data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at V with Output
IL
Enable at V . Commands, input data and addresses are latched on the rising edge of Write
IH
Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to
the write operation by toggling Latch Enable. In this case the Latch Enable should be tied to
V
during the bus write operation.
IH
See Figures 16 and 17, write AC waveforms, and Tables 25 and 26, write AC characteristics
for details of the timing requirements.
3.3
3.4
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at V during address latch operations. The addresses are latched on the rising edge of
IL
Latch Enable.
Output Disable
The outputs are high impedance when the Output Enable is at V .
IH
18/117
M58WTxxxKT, M58WTxxxKB
Bus operations
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at V . The power
IH
consumption is reduced to the standby level and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V
during a program or erase operation, the device enters standby mode when finished.
IH
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when Reset is at V . The power consumption is reduced to the
IL
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to V during a program or erase, this operation is aborted and the memory
SS
content is no longer valid.
(1)
Table 4.
Operation
Bus operations
E
G
W
L
RP
WAIT(2)
DQ15-DQ0
(3)
Bus read
VIL
VIL
VIL
VIL
VIH
X
VIL
VIH
X
VIH
VIL
VIH
VIH
X
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIL
Data output
(3)
Bus write
Data input
Address latch
Output disable
Standby
VIL
Data output or Hi-Z (4)
VIH
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reset
X
X
1. X = ‘don't care’
2. WAIT signal polarity is configured using the Set Configuration Register command.
3. L can be tied to VIH if the valid address has been previously latched.
4. Depends on G.
19/117
Command interface
M58WTxxxKT, M58WTxxxKB
4
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. An internal
Program/Erase Controller manages all timings and verifies the correct execution of the
program and erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor the progress or the result of the operation.
The command interface is reset to read mode when power is first applied, when exiting from
Reset, or whenever V is lower than V
. Command sequences must be followed exactly.
DD
LKO
Any invalid combination of commands is ignored.
Refer to Table 5: Command codes, and Appendix D, Tables 44, 45, 46 and 47, command
interface states - modify and lock tables, for a summary of the command interface.
The command interface is split into two types of commands: standard commands and
factory program commands. The following sections explain in detail how to perform each
command.
Table 5.
Command codes
Hex Code
Command
01h
03h
10h
20h
2Fh
30h
35h
40h
50h
56h
Block Lock Confirm
Set Configuration Register Confirm
Alternative Program Setup
Block Erase Setup
Block Lock-Down Confirm
Enhanced Factory Program Setup
Double Word Program Setup
Program Setup
Clear Status Register
Quadruple Word Program Setup
Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set
Configuration Register Setup
60h
70h
75h
90h
98h
B0h
C0h
Read Status Register
Quadruple Enhanced Factory Program Setup
Read Electronic Signature
Read CFI Query
Program/Erase Suspend
Protection Register Program
Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or
Enhanced Factory Program Confirm
D0h
FFh
Read Array
20/117
M58WTxxxKT, M58WTxxxKB
Command interface - standard commands
5
Command interface - standard commands
The following commands are the basic commands used to read, write to and configure the
device. Refer to Table 6: Standard commands, in conjunction with the following descriptions
in this section.
5.1
Read Array command
The Read Array command returns the addressed bank to read array mode. One bus write
cycle is required to issue the Read Array command and return the addressed bank to read
array mode. Subsequent read operations read the addressed location and output the data.
A Read Array command can be issued in one bank while programming or erasing in another
bank. However, if a Read Array command is issued to a bank currently executing a program
or erase operation the command is executed but the output data is not guaranteed.
5.2
Read Status Register command
The Status Register indicates when a program or erase operation is complete and the
success or failure of operation itself. Issue a Read Status Register command to read the
Status Register content. The Read Status Register command can be issued at any time,
even during program or erase operations.
The following read operations output the content of the Status Register of the addressed
bank. The Status Register is latched on the falling edge of E or G signals, and can be read
until E or G returns to V . Either E or G must be toggled to update the latched data. See
IH
Table 9 for the description of the Status Register bits. This mode supports asynchronous or
single synchronous reads only.
5.3
Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the
block locking status, the Protection Register, and the Configuration Register.
The Read Electronic Signature command consists of one write cycle to an address within
one of the banks. A subsequent read operation in the same bank outputs the manufacturer
code, the device code, the protection status of the blocks in the targeted bank, the
Protection Register, or the Configuration Register (see Table 7).
Dual operations between the parameter bank and the electronic signature locations are not
allowed (see Table 15: Dual operation limitations).
If a Read Electronic Signature command is issued in a bank that is executing a program or
erase operation, the bank goes into read electronic signature mode, subsequent bus read
cycles output the electronic signature data, and the Program/Erase Controller continues to
program or erase in the background. This mode supports asynchronous or single
synchronous reads only; it does not support page mode or synchronous burst reads.
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5.4
Read CFI Query command
The Read CFI Query command reads data from the common Flash interface (CFI). The
Read CFI Query command consists of one bus write cycle to an address within one of the
banks. Once the command is issued subsequent bus read operations in the same bank
read from the common Flash interface.
If a Read CFI Query command is issued in a bank that is executing a program or erase
operation, the bankgoes into Read CFI Query mode, subsequent bus read cycles output the
CFI data, and the Program/Erase Controller continues to program or erase in the
background. This mode supports asynchronous or single synchronous reads only; it does
not support page mode or synchronous burst reads.
The status of the other banks is not affected by the command (see Table 13). After issuing a
Read CFI Query command, a Read Array command should be issued to the addressed
bank to return the bank to read array mode.
Dual operations between the parameter bank and the CFI memory space are not allowed
(see Table 15: Dual operation limitations for details).
See Appendix B: Common Flash interface, Tables 34, 35, 36, 37, 38, 39, 40, 41, 42 and 43
for details on the information contained in the common Flash interface memory area.
5.5
Clear Status Register command
The Clear Status Register command resets (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in
the Status Register. One bus write cycle is required to issue the Clear Status Register
command. The Clear Status Register command does not change the read mode of the
bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
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Command interface - standard commands
5.6
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to ’1’.
All previous data in the block is lost. If the block is protected then the erase operation aborts,
the data in the block does not change, and the Status Register outputs the error. The Block
Erase command can be issued at any moment, regardless of whether the block has been
programmed or not.
Two bus write cycles are required to issue the command:
●
The first bus cycle sets up the erase command
●
The second latches the block address in the Program/Erase Controller and starts it
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if Reset turns to V . As data integrity cannot
IL
be guaranteed when the erase operation is aborted, the block must be erased again.
Once the command is issued, the device outputs the Status Register data when any
address within the bank is read. At the end of the operation the bank remains in Read
Status Register mode until a Read Array, Read CFI Query, or Read Electronic Signature
command is issued.
During erase operations the bank containing the block being erased only accepts the Read
Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend commands; all other commands are ignored. Refer to Section 10
for detailed information about simultaneous operations allowed in banks not being erased.
Typical erase times are given in Table 17: Program/erase times and endurance cycles.
See Appendix C, Figure 24: Block erase flowchart and pseudo code for a suggested
flowchart for using the Block Erase command.
5.7
Program command
The memory array can be programmed word-by-word. Only one word in one bank can be
programmed at any one time. If the block is protected, the program operation aborts, the
data in the block does not change, and the Status Register outputs the error.
Two bus write cycles are required to issue the Program command:
●
The first bus cycle sets up the Program command
●
The second latches the address and the data to be written and starts the
Program/Erase Controller
After programming has started, read operations in the bank being programmed output the
Status Register content.
During Program operations the bank being programmed only accepts the Read Array, Read
Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands. Refer to Section 10 for detailed information about simultaneous
operations allowed in banks not being programmed. Typical program times are given in
Table 17: Program/erase times and endurance cycles.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the memory location must be reprogrammed.
See Appendix C, Figure 20: Program flowchart and pseudo code for the flowchart for using
the Program command.
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5.8
Program/Erase Suspend command
The Program/Erase Suspend command pauses a program or block erase operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register are
set to ‘1’. The command can be addressed to any bank.
During program/erase suspend the command interface accepts the Program/Erase
Resume, Read Array (cannot read the erase-suspended block or the program-suspended
word), Read Status Register, Read Electronic Signature, Clear Status Register, and Read
CFI Query commands. In addition, if the suspended operation is erase then the Set
Configuration Register, Program, Block Lock, Block Lock-Down or Block Unlock commands
are also accepted. The block being erased may be protected by issuing the Block Lock, or
Block Lock-Down commands. Only the blocks not being erased may be read or
programmed correctly. When the Program/Erase Resume command is issued the operation
completes. Refer to Section 10 for detailed information about simultaneous operations
allowed during Program/Erase Suspend.
During a program/erase suspend, the device is placed in standby mode by taking Chip
Enable to V . Program/erase is aborted if Reset turns to V .
IH
IL
See Appendix C, Figure 23: Program suspend and resume flowchart and pseudo code, and
Figure 25: Erase suspend and resume flowchart and pseudo code for flowcharts for using
the Program/Erase Suspend command.
5.9
Program/Erase Resume command
The Program/Erase Resume command restarts the Program/Erase Controller after a
Program/Erase Suspend command has paused it. One bus write cycle is required to issue
the command. The command can be written to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank is in read Status Register, read electronic signature or read CFI query
mode the bank remains in that mode and outputs the corresponding data. If the bank is in
read array mode, subsequent read operations output invalid data.
If a Program command is issued during a block erase suspend, the erase cannot be
resumed until the programming operation has completed. It is possible to accumulate
suspend operations. For example, it is possible to suspend an erase operation, start a
programming operation, suspend the programming operation, and then read the array. See
Appendix C, Figure 23: Program suspend and resume flowchart and pseudo code and
Figure 25: Erase suspend and resume flowchart and pseudo code for flowcharts for using
the Program/Erase Resume command.
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Command interface - standard commands
5.10
Protection Register Program command
The Protection Register Program command programs the 128-bit user OTP segment of the
Protection Register and the Protection Register lock. The segment is programmed 16 bits at
a time. When shipped, all bits in the segment are set to ‘1’. The user can only program the
bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command:
●
The first bus cycle sets up the Protection Register Program command.
●
The second latches the address and the data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 5: Protection Register memory map). Attempting to program a previously protected
Protection Register results in a Status Register error. The protection of the Protection
Register is not reversible. The Protection Register program cannot be suspended. Dual
operations between the parameter bank and the Protection Register memory space are not
allowed (see Table 15: Dual operation limitations).
5.11
The Set Configuration Register command
The Set Configuration Register command writes a new value to the Configuration Register,
which defines the burst length, type, X latency, synchronous/asynchronous read mode, and
the valid Clock edge configuration.
Two bus write cycles are required to issue the Set Configuration Register command:
●
The first cycle writes the setup command and the address corresponding to the
Configuration Register content.
●
The second cycle writes the Configuration Register data and the confirm command.
Read operations output the memory array content after the Set Configuration Register
command is issued.
The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1
on A1, etc.; the other address bits are ignored.
5.12
Block Lock command
The Block Lock command locks a block and prevents program or erase operations from
changing the data in it. All blocks are locked at power-up or reset.
Two bus write cycles are required to issue the Block Lock command:
●
The first bus cycle sets up the Block Lock command.
The second bus write cycle latches the block address.
●
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 16 shows the lock status after issuing a Block Lock command.
The block lock bits are volatile; once set they remain set until a hardware reset or power-
down/power-up. They are cleared by a Block Unlock command. Refer to Section 11: Block
locking for a detailed explanation. See Appendix C, Figure 26: Locking operations flowchart
and pseudo code for a flowchart for using the Lock command.
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5.13
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or
erased. Two bus write cycles are required to issue the Block Unlock command:
●
The first bus cycle sets up the Block Unlock command.
The second bus write cycle latches the block address.
●
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 16 shows the protection status after issuing a Block Unlock command.
Refer to Section 11: Block locking for a detailed explanation and Appendix C, Figure 26:
Locking operations flowchart and pseudo code for a flowchart for using the Unlock
command.
5.14
Block Lock-Down command
A locked or unlocked block can be locked down by issuing the Block Lock-Down command.
A locked-down block cannot be programmed or erased, or have its protection status
changed when WP is low, V . When WP is high, V the lock-down function is disabled and
IL
IH,
the locked blocks can be individually unlocked by the Block Unlock command.
Two bus write cycles are required to issue the Block Lock-Down command:
●
●
The first bus cycle sets up the Block Lock command.
The second bus write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature
command. Locked-down blocks revert to the locked (and not locked-down) state when the
device is reset on power-down. Table 16 shows the lock status after issuing a Block Lock-
Down command. Refer to Section 11: Block locking for a detailed explanation and Appendix
C, Figure 26: Locking operations flowchart and pseudo code for a flowchart for using the
Lock-Down command.
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Command interface - standard commands
Table 6.
Standard commands
Bus operations(1)
2nd cycle
Commands
1st cycle
Add
Op.
Data
Op.
Add
Data
Read Array
1+
Write
Write
Write
Write
Write
BKA
BKA
BKA
BKA
X
FFh
70h
90h
98h
50h
Read
Read
Read
Read
WA
RD
SRD
ESD
QD
Read Status Register
Read Electronic Signature
Read CFI Query
1+
1+
1+
1
BKA(2)
BKA(2)
BKA(2)
Clear Status Register
BKA or
BA(3)
Block Erase
Program
2
2
Write
Write
20h
Write
Write
BA
D0h
PD
BKA or
WA(3)
40h or 10h
WA
Program/Erase Suspend
Program/Erase Resume
Protection Register Program
Set Configuration Register
1
1
2
2
Write
Write
Write
Write
X
B0h
D0h
C0h
60h
X
PRA
CRD
Write
Write
PRA
CRD
PRD
03h
BKA or
BA(3)
Block Lock
2
2
2
Write
Write
Write
60h
60h
60h
Write
Write
Write
BA
BA
BA
01h
D0h
2Fh
BKA or
BA(3)
Block Unlock
Block Lock-Down
BKA or
BA(3)
1. X = ‘don't care’, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic
Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection
Register Address, PRD = Protection Register Data, CRD = Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.
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Table 7.
Electronic signature codes
Code
Address (h)
Data (h)
Manufacturer code
Bank address + 00
Bank address + 01
0020
8866 (M58WT032KT)
8810 (M58WT064KT)
Top
Device code
8867 (M58WT032KB)
8811 (M58WT064KB)
Bottom
Bank address + 01
Block address + 02
Locked
0001
0000
Unlocked
Block protection
Locked and locked-down
Unlocked and locked-down
0003
0002
Reserved
Bank address + 03
Bank address + 05
Reserved
CR(1)
0002
Configuration Register
Numonyx factory default
Protection Register
lock
Bank address + 80
OTP area permanently locked
0000
Bank address + 81
Bank address + 84
Unique device number
OTP Area
Protection Register
Bank address + 85
Bank address + 8C
1. CR = Configuration Register.
Figure 5.
Protection Register memory map
PROTECTION REGISTER
User Programmable OTP
8Ch
85h
84h
Unique device number
Protection Register Lock
81h
80h
1
0
AI08149
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Command interface - factory program commands
6
Command interface - factory program commands
The factory program commands are specifically designed to speed up programming. They
require V to be at V
. Refer to Table 8: Factory program commands in conjunction with
PP
PPH
the descriptions in this section.
The use of factory program commands requires certain operating conditions:
●
●
●
●
V
V
must be set to V
.
PPH
PP
DD
must be within operating range.
Ambient temperature, T must be 25°C 5°C.
A
The targeted block must be unlocked.
6.1
Double Word Program command
The Double Word Program command improves the programming throughput by writing a
page of two adjacent words in parallel. The two words must only differ for the address A0.
If the block is protected, then the Double Word Program operation aborts, the data in the
block does not change, and the Status Register outputs the error.
V
must be set to V
during Double Word Program, otherwise the command is ignored
PPH
PP
and the Status Register does not output any error.
Three bus write cycles are necessary to issue the Double Word Program command:
●
●
●
The first bus cycle sets up the Double Word Program command.
The second bus cycle latches the address and the data of the first word to be written.
The third bus cycle latches the address and the data of the second word to be written
and starts the Program/Erase Controller.
Read operations in the bank being programmed output the Status Register content after the
programming has started.
During double word program operations the bank being programmed only accepts the Read
Array, Read Status Register, Read Electronic Signature and Read CFI Query commands; all
other commands are ignored. Dual operations are not supported during double word
program operations and the command cannot be suspended. Typical program times are
given in Table 17: Program/erase times and endurance cycles.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the memory locations must be reprogrammed.
See Appendix C, Figure 21: Double word program flowchart and pseudo code for the
flowchart for using the Double Word Program command.
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6.2
Quadruple Word Program command
The Quadruple Word Program command improves the programming throughput by writing a
page of four adjacent words in parallel. The four words must only differ for the addresses A0
and A1.
V
must be set to V
during Quadruple Word Program, otherwise the command is
PPH
PP
ignored and the Status Register does not output any error.
If the block is protected, then the Quadruple Word Program operation aborts, the data in the
block does not change, and the Status Register outputs the error.
Five bus write cycles are necessary to issue the Quadruple Word Program command:
●
●
●
●
●
The first bus cycle sets up the Double Word Program command.
The second bus cycle latches the address and the data of the first word to be written.
The third bus cycle latches the address and the data of the second word to be written.
The fourth bus cycle latches the address and the data of the third word to be written.
The fifth bus cycle latches the address and the data of the fourth word to be written and
starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
programming has started.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the memory locations must be reprogrammed.
During Quadruple Word Program operations the bank being programmed only accepts the
Read Array, Read Status Register, Read Electronic Signature and Read CFI Query
commands; all other commands are ignored.
Dual operations are not supported during quadruple word program operations and the
command cannot be suspended. Typical program times are given in Table 17:
Program/erase times and endurance cycles.
See Appendix C, Figure 22: Quadruple word program flowchart and pseudo code for the
flowchart for using the Quadruple Word Program command.
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Command interface - factory program commands
6.3
Enhanced Factory Program command
The Enhanced Factory Program command programs large streams of data within any one
block. It greatly reduces the total programming time when a large number of words are
written to a block at any one time.
Dual operations are not supported during the Enhanced Factory Program operation and the
command cannot be suspended.
For optimum performance the Enhanced Factory Program commands should be limited to a
maximum of 10 program/erase cycles per block. If this limit is exceeded the internal
algorithm continues to work properly but some degradation in performance is possible.
Typical program times are given in Table 17
If the block is protected then the Enhanced Factory Program operation aborts, the data in
the block does not change, and the Status Register outputs the error.
The Enhanced Factory Program command has four phases: the setup phase, the program
phase to program the data to the memory, the verify phase to check that the data has been
correctly programmed and reprogram if necessary and the exit phase. Refer to Table 8:
Factory program commands, and Figure 28: Enhanced factory program flowchart.
6.3.1
Setup phase
The Enhanced Factory Program command requires two bus write operations to initiate the
command:
●
The first bus cycle sets up the Enhanced Factory Program command
The second bus cycle confirms the command.
●
The Status Register P/EC bit SR7 should be read to check that the P/EC is ready. After the
confirm command is issued, read operations output the Status Register data. The read
Status Register command must not be issued or it is interpreted as data to program.
If the second bus cycle is not EFP confirm (D0h), Status Register bits SR4 and SR5 are set
and the command aborts.
V
value must be in the V
range during the confirm command, otherwise SR4 and SR3
PPH
PP
are set and command are aborted.
6.3.2
Program phase
The program phase requires n+1 cycles, where n is the number of words (refer to Table 8:
Factory program commands, and Figure 28: Enhanced factory program flowchart).
Three successive steps are required to issue and execute the program phase of the
command:
1. Use one bus write operation to latch the start address and the first word to be
programmed, where the start address is the location of the first data to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check
that the P/EC is ready for the next word.
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2. Each subsequent word to be programmed is latched with a new bus write operation.
The address can either remain the start address, in which case the P/EC increments
the address location. Or the address can be incremented, in which case the P/EC
jumps to the new address. If any address is given that is not in the same block as the
start address with data FFFFh, the program phase terminates and the verify phase
begins. The Status Register bit SR0 should be read between each bus write cycle to
check that the P/EC is ready for the next word.
3. Finally, after all words have been programmed, write one bus write operation with data
FFFFh to any address outside the block containing the start address, to terminate the
programming phase. If the data is not FFFFh, the command is ignored.
The memory is now set to enter the verify phase.
6.3.3
Verify phase
The verify phase is similar to the program phase in that all words must be resent to the
memory for them to be checked against the programmed data. The Program/Erase
Controller checks the stream of data with the data that was programmed in the program
phase and reprograms the memory location, if necessary.
Three successive steps are required to execute the verify phase of the command:
1. Use one bus write operation to latch the start address and the first word to be verified.
The Status Register bit SR0 should be read to check that the Program/Erase Controller
is ready for the next word.
2. Each subsequent word to be verified is latched with a new bus write operation. The
words must be written in the same order as in the program phase. The address can
remain the start address or be incremented. If any address that is not in the same block
as the start address is given with data FFFFh, the verify phase terminates. Status
Register bit SR0 should be read to check that the P/EC is ready for the next word.
3. Finally, after all words have been verified, write one bus write operation with data
FFFFh to any address outside the block containing the start address, to terminate the
verify phase.
If the verify phase is successfully completed, the memory remains in read Status Register
mode. If the Program/Erase Controller fails to reprogram a given location, the error is
signaled in the Status Register.
6.3.4
Exit phase
Status Register P/EC bit SR7 set to ‘1’ indicates that the device has returned to read mode.
A full Status Register check should be done to ensure that the block has been successfully
programmed. See Section 7: Status Register for more details.
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6.4
Quadruple Enhanced Factory Program command
The Quadruple Enhanced Factory Program command programs one or more pages of four
adjacent words in parallel. The four words must only differ for the addresses A0 and A1.
V
must be set to V
during the Quadruple Enhanced Factory Program, otherwise the
PPH
PP
command is ignored and the Status Register does not output any error.
Dual operations are not supported during Quadruple Enhanced Factory Program operations
and the command cannot be suspended.
If the block is protected then the Quadruple Enhanced Factory Program operation aborts,
the data in the block does not change, and the Status Register outputs the error.
The Quadruple Enhanced Factory Program command has four phases: the setup phase,
the load phase where the data is loaded into the buffer, the combined program and verify
phase where the loaded data is programmed to the memory and then automatically checked
and reprogrammed if necessary and the exit phase. Unlike the Enhanced Factory Program it
is not necessary to resubmit the data for the verify phase. The load phase and the program
and verify phase can be repeated to program any number of pages within the block.
6.4.1
6.4.2
Setup phase
The Quadruple Enhanced Factory Program command requires one bus write operation to
initiate the load phase. After the setup command is issued, read operations output the
Status Register data. The Read Status Register command must not be issued or it is
interpreted as data to program.
Load phase
The load phase requires 4 cycles to load the data (refer to Table 8: Factory program
commands and Figure 29: Quadruple enhanced factory program flowchart). Once the first
word of each page is written it is impossible to exit the load phase until all four words have
been written.
Two successive steps are required to issue and execute the load phase of the Quadruple
Enhanced Factory Program command.
1. Use one bus write operation to latch the start address and the first word of the first
page to be programmed, where the start address is the location of the first data to be
programmed. For subsequent pages the first word address can remain the start
address (in which case the next page is programmed) or can be any address in the
same block. If any address with data FFFFh is given that is not in the same block as the
start address, the device enters the exit phase. For the first load phase Status Register
bit SR7 should be read after the first word has been issued to check that the command
has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent load
phases.
2. Each subsequent word to be programmed is latched with a new bus write operation.
The address is only checked for the first word of each page as the order of the words to
be programmed is fixed.
The memory is now set to enter the program and verify phase.
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6.4.3
Program and verify phase
In the program and verify phase the four words that were loaded in the load phase are
programmed in the memory array and then verified by the Program/Erase Controller. If any
errors are found, the Program/Erase Controller reprograms the location. During this phase
the Status Register shows that the Program/Erase Controller is busy, the Status Register bit
SR7 is set to ‘0’, and that the device is not waiting for new data (Status Register bit SR0 set
to ‘1’). When Status Register bit SR0 is set to ‘0’ the program and verify phase has
terminated.
Once the verify phase has successfully completed, subsequent pages in the same block
can be loaded and programmed. The device returns to the beginning of the load phase by
issuing one bus write operation to latch the address and the first of the four new words to be
programmed.
6.4.4
Exit phase
Finally, after all the pages have been programmed, write one bus write operation with data
FFFFh to any address outside the block containing the start address, to terminate the load
and program and verify phases.
Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple
Enhanced Factory Program command has terminated. A full Status Register check should
be done to ensure that the block has been successfully programmed. See Section 7: Status
Register for more details.
If the program and verify phase has successfully completed the memory returns to read
mode. If the P/EC fails to program and reprogram a given location, the error is signaled in
the Status Register.
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Command interface - factory program commands
Bus write operations(1)
Table 8.
Factory program commands
Command
Phase
1st
2nd
3rd
Final -1
Final
Add
Data
Add Data Add
Data
Add Data Add
Data
BKA or
WA1(3)
Double Word Program(2)
3
5
35h
WA1 PD1 WA2
PD2
Quadruple Word
Program(4)
BKA or
WA1(3)
56h
30h
WA1 PD1 WA2
BA or
PD2
WA3 PD3 WA4
PD4
Setup,
Program
2+n+ BKA or
WA1(3)
NOT
WAn(8) PAn
WA1(7)
D0h WA1(7) PD1
FFFFh
FFFFh
Enhanced
Factory
1
WA1(6)
Program
NOT
WAn(8) PAn
WA1(7)
n+1 WA1(7) PD1 WA2(8) PD2 WA3(8) PD3
(5)
Verify, Exit
Setup,
BKA or
5
4
1
75h WA1(7) PD1 WA2(9) PD2
WA3(9) PD3 WA4(9) PD4
WA1(3)
first Load
First
Program &
Verify
Automatic
PD1i WA2i(9) PD2i WA3i(9) PD3i
Automatic
Quadruple
Enhanced
Factory
Subsequent
Loads
WA1i
WA4i(9) PD4i
(7)
Program
(4),(5)
Subsequent
Program &
Verify
NOT
Exit
FFFFh
WA1(7)
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address.
2. Word addresses 1 and 2 must be consecutive Addresses differing only for A0.
3. Any address within the bank can be used.
4. Word addresses 1,2,3 and 4 must be consecutive addresses differing only for A0 and A1.
5. A bus read must be done between each write cycle where the data is programmed or verified to read the Status Register
and check that the memory is ready to accept the next data. n = number of words, i = number of pages to be programmed.
6. Any address within the block can be used.
7. WA1 is the start address. NOT WA1 is any address that is not in the same block as WA1.
8. Address can remain starting address WA1 or be incremented.
9. Address is only checked for the first word of each page as the order to program the words in each page is fixed so
subsequent words in each page can be written to any address.
35/117
Status Register
M58WTxxxKT, M58WTxxxKB
7
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register (refer to Section 5.2: Read Status Register command for more details). To output
the contents, the Status Register is latched and updated on the falling edge of the Chip
Enable or Output Enable signals and can be read until Chip Enable or Output Enable
returns to V . The Status Register can only be read using single asynchronous or single
IH
synchronous reads. Bus read operations from any address within the bank always read the
Status Register during Program and Erase operations, as long as no Read Array command
has been issued.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 provide information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 provide information on errors. TThey are
set by the device but must be reset by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing
another command. SR7 to SR1 refer to the status of the device while SR0 refers to the
status of the addressed bank.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the descriptions in the following sections.
7.1
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is
active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to
‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the
Program/Erase Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
During program and erase operations the Program/Erase Controller status bit can be polled
to find the end of the operation. Other bits in the Status Register should not be tested until
the Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the erase status, program
status, V status and block lock status bits should be tested for errors.
PP
36/117
M58WTxxxKT, M58WTxxxKB
Status Register
7.2
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended or is
going to be suspended in the addressed block. When the erase suspend status bit is High
(set to ‘1’), a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
The erase suspend status should only be considered valid when the Program/Erase
Controller status bit is High (Program/Erase Controller inactive). SR7 is set within the erase
suspend latency time of the Program/Erase Suspend command being issued, therefore, the
memory may still complete the operation rather than entering the suspend mode.
When a Program/Erase Resume command is issued the erase suspend status bit returns
Low.
7.3
7.4
Erase status bit (SR5)
The erase status bit identifies if the memory has failed to verify that the block has erased
correctly. When the erase status bit is High (set to ‘1’), the Program/Erase Controller has
applied the maximum number of pulses to the block and still failed to verify that it has erased
correctly. The erase status bit should be read once the Program/Erase Controller status bit
is High (Program/Erase Controller inactive).
Once set High, the erase status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new program or erase
command is issued, otherwise the new command appears to fail.
Program status bit (SR4)
The program status bit identifies a program failure or an attempt to program a ‘1’ to an
already programmed bit when V = V
.
PP
PPH
When the program status bit is High (set to ‘1’), the Program/Erase Controller has applied
the maximum number of pulses to the byte and still failed to verify that it has programmed
correctly.
After an attempt to program a '1' to an already programmed bit, the program status bit SR4
only goes High (set to '1') if V = V
(if V is different from V
, SR4 remains Low (set
PP
PPH
PP
PPH
to '0') and the attempt is not shown).
The program status bit should be read once the Program/Erase Controller status bit is High
(Program/Erase Controller inactive).
Once set High, the program status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new command is
issued, otherwise the new command appears to fail.
37/117
Status Register
M58WTxxxKT, M58WTxxxKB
7.5
VPP status bit (SR3)
The V status bit identifies an invalid voltage on the V pin during program and erase
PP
PP
operations. The V pin is only sampled at the beginning of a program or erase operation.
PP
Indeterminate results can occur if V becomes invalid during an operation.
PP
When the V status bit is Low (set to ‘0’), the voltage on the V pin was sampled at a valid
PP
PP
voltage. When the V status bit is High (set to ‘1’), the V pin has a voltage that is below
PP
PP
the V lockout voltage, V
, the memory is protected and program and erase operations
PP
PPLK
cannot be performed.
Once set High, the V status bit can only be reset Low by a Clear Status Register
PP
command or a hardware reset. If set High it should be reset before a new program or erase
command is issued, otherwise the new command appears to fail.
7.6
Program suspend status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in
the addressed block. When the program suspend status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command. The program suspend status should only be considered
valid when the Program/Erase Controller status bit is High (Program/Erase Controller
inactive). SR2 is set within the program suspend latency time of the Program/Erase
Suspend command being issued, therefore, the memory may still complete the operation
rather than entering the suspend mode.
When a Program/Erase Resume command is issued, the program suspend status bit
returns Low.
7.7
Block protection status bit (SR1)
The block protection status bit can be used to identify if a program or block erase operation
has tried to modify the contents of a locked or locked-down block.
When the block protection status bit is High (set to ‘1’), a program or erase operation has
been attempted on a locked or locked-down block.
Once set High, the block protection status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set High it should be reset before a new
command is issued, otherwise the new command appears to fail.
38/117
M58WTxxxKT, M58WTxxxKB
Status Register
7.8
Bank write/multiple word program status bit (SR0)
The bank write status bit indicates whether the addressed bank is programming or erasing.
In enhanced factory program mode the multiple word program bit shows if a word has
finished programming or verifying depending on the phase. The bank write status bit should
only be considered valid when the Program/Erase Controller status SR7 is Low (set to ‘0’).
When both the Program/Erase Controller status bit and the bank write status bit are Low (set
to ‘0’), the addressed bank is executing a program or erase operation. When the
Program/Erase Controller status bit is Low (set to ‘0’) and the bank write status bit is High
(set to ‘1’), a program or erase operation is being executed in a bank other than the one
being addressed.
In enhanced factory program mode if the multiple word program status bit is Low (set to ‘0’),
the device is ready for the next word. If the multiple word program status bit is High (set to
‘1’) the device is not ready for the next word.
Refer to Appendix C: Flowcharts and pseudo codes for using the Status Register.
39/117
Status Register
M58WTxxxKT, M58WTxxxKB
Definition
Table 9.
Bit
Status Register bits
Name Type
Logic
level(1)
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Ready
Busy
SR7 P/EC status
Status
Status
Error
Erase suspended
Erase in progress or completed
Erase error
SR6 Erase suspend status
SR5 Erase status
SR4 Program status
SR3 VPP status
Erase success
Program error
Error
Program success
VPP invalid, abort
Error
VPP OK
Program suspended
SR2 Program suspend status Status
Program in progress or completed
Program/erase on protected block, abort
No operation to protected blocks
SR7 = ‘1’ Not allowed
SR1 Block protection status
Error
'1'
'0'
Program or erase operation in a
SR7 = ‘0’
bank other than the addressed bank
Bank write status
Status
No program or erase operation in the
SR7 = ‘1’
device
Program or erase operation in
SR7 = ‘0’
SR0
addressed bank
SR7 = ‘1’ Not allowed
'1'
'0'
The device is NOT ready for the next
Multiple word program
status (enhanced factory Status
program mode)
SR7 = ‘0’
word
SR7 = ‘1’ The device is exiting EFP
SR7 = ‘0’ The device is ready for the next word
1. Logic level '1' is High, '0' is Low.
40/117
M58WTxxxKT, M58WTxxxKB
Configuration Register
8
Configuration Register
The Configuration Register configures the type of bus access that the memory performs.
Refer to Section 9: Read modes for details on read operations.
The Configuration Register is set through the command interface. After a reset or power-up
the device is configured for asynchronous page read (CR15 = 1). The Configuration
Register bits are described in Table 11. They specify the selection of the burst length, burst
type, burst X latency, and the Read operation. Refer to Figures 6 and 7 for examples of
synchronous burst configurations.
8.1
8.2
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous bus read
operations. When the read select bit is set to ’1’, read operations are asynchronous; when
the read select bit is set to ’0’, read operations are synchronous. Synchronous burst read is
supported in both parameter and main blocks and can be performed across banks.
On reset or power-up the read select bit is set to’1’ for asynchronous access.
X latency bits (CR13-CR11)
The X latency bits are used during synchronous read operations to set the number of clock
cycles between the address being latched and the first data becoming available. For correct
operation the X latency bits can only assume the values in Table 11: Configuration Register.
Table 10shows how to set the X latency parameter, taking into account the speed class of
the device and the frequency used to read the Flash memory in synchronous mode.
Table 10. Latency settings
fmax
tKmin
X latency min
30 MHz
40 MHz
52 MHz
33 ns
25 ns
19 ns
2
3
4
8.3
Wait polarity bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data are valid or a
WAIT state must be inserted. The wait polarity bit is used to set the polarity of the Wait
signal. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait
polarity bit is set to ‘1’ the Wait signal is active High.
41/117
Configuration Register
M58WTxxxKT, M58WTxxxKB
8.4
Data output configuration bit (CR9)
The data output configuration bit determines whether the output remains valid for one or two
clock cycles. When the data output configuration bit is ’0’ the output data is valid for one
clock cycle. When the data output configuration bit is ’1’ the output data is valid for two clock
cycles.
The data output configuration depends on the condition:
t > t
+ t
QVK_CPU
K
KQV
where t is the clock period, t
is the data setup time required by the system CPU
K
QVK_CPU
and t
is the clock to data valid time. If this condition is not satisfied, the data output
KQV
configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6: X latency and data
output configuration example.
8.5
8.6
8.7
8.8
Wait configuration bit (CR8)
In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is
asserted, data is not valid and when WAIT is de-asserted, data is valid. When the Wait bit is
’0’ the Wait output pin is asserted during the wait state. When the Wait bit is ’1’ the Wait
output pin is asserted one clock cycle before the wait state.
Burst type bit (CR7)
The burst type bit configures the sequence of addresses read as sequential or interleaved.
When the burst type bit is ’0’ the memory outputs from interleaved addresses. When the
burst type bit is ’1’ the memory outputs from sequential addresses. See Table 12: Burst type
definition for the sequence of addresses output from a given starting address in each mode.
Valid clock edge bit (CR6)
The valid clock edge bit, CR6, configures the active edge of the Clock, K, during
synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of
the Clock is the active edge. When the Valid Clock Edge bit is ’1’ the rising edge of the Clock
is active.
Wrap burst bit (CR3)
The burst reads can be confined inside the 4 or 8-word boundary (wrap) or overcome the
boundary (no wrap). The wrap burst bit selects between wrap and no wrap. When the wrap
burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.
42/117
M58WTxxxKT, M58WTxxxKB
Configuration Register
8.9
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read
operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16
words or continuous burst, where all the words are read sequentially.
In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address,
the device asserts the WAIT output to indicate that a delay is necessary before the data is
output.
If the starting address is aligned to a 4 word boundary no wait states are needed and the
WAIT output is not asserted.
If the starting address is shifted by 1, 2 or 3 positions from the 4-word boundary, WAIT is
asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word
boundary to indicate that the device needs an internal delay to read the successive words in
the array. WAIT is asserted only once during a continuous burst access. See also Table 12:
Burst type definition.
CR14, CR5 and CR4 are reserved for future use.
43/117
Configuration Register
M58WTxxxKT, M58WTxxxKB
Description
Table 11. Configuration Register
Bit
Description
Value
0
1
Synchronous read
CR15
CR14
Read select
Reserved
Asynchronous read (default at power-on)
010
011
100
101
111
2 clock latency
3 clock latency
4 clock latency
5 clock latency
Reserved (default)
CR13-CR11 X latency
Other configurations reserved
0
1
0
1
0
1
0
1
0
1
WAIT is active Low
CR10
CR9
CR8
CR7
CR6
Wait polarity
WAIT is active High (default)
Data held for one clock cycle
Data held for two clock cycles (default)
WAIT is active during wait state
WAIT is active one data cycle before wait state (default)
Interleaved
Data output
configuration
Wait
configuration
Burst type
Sequential (default)
Falling Clock edge
Valid clock
edge
Rising Clock edge (default)
CR5-CR4 Reserved
CR3 Wrap burst
0
Wrap
1
No wrap (default)
001
010
011
111
4 words
8 words
CR2-CR0 Burst length
16 words
Continuous (CR7 must be set to ‘1’) (default)
44/117
M58WTxxxKT, M58WTxxxKB
Configuration Register
Table 12. Burst type definition
4 words
Start
8 words
16 words
Sequential Interleaved
Continuous
burst
add
Sequential Interleaved Sequential Interleaved
0-1-2-3-4-5-6- 0-1-2-3-4-5-6-
7-8-9-10-11-12- 7-8-9-10-11- 0-1-2-3-4-5-6...
0-1-2-3-4- 0-1-2-3-4-5-
0
1
0-1-2-3
1-2-3-0
0-1-2-3
1-0-3-2
5-6-7
6-7
13-14-15
12-13-14-15
1-2-3-4-5-6-7- 1-0-3-2-5-4-7- 1-2-3-4-5-6-7-
8-9-10-11-12- 6-9-8-11-10- ...15-WAIT-16-
1-2-3-4-5- 1-0-3-2-5-4-
6-7-0 7-6
13-14-15-0
13-12-15-14
17-18...
2-3-4-5-6-
7...15-WAIT-
WAIT-16-17-
18...
2-3-4-5-6-7-8- 2-3-0-1-6-7-4-
9-10-11-12-13- 5-10-11-8-9-
2-3-4-5-6- 2-3-0-1-6-7-
7-0-1 4-5
2
2-3-0-1
3-0-1-2
2-3-0-1
3-2-1-0
14-15-0-1
14-15-12-13
3-4-5-6-7...15-
WAIT-WAIT-
WAIT-16-17-
18...
3-4-5-6-7-8-9- 3-2-1-0-7-6-5-
3-4-5-6-7- 3-2-1-0-7-6-
0-1-2 5-4
3
...
7
10-11-12-13-
14-15-0-1-2
4-11-10-9-8-
15-14-13-12
7-8-9-10-11-12-
13-14-15-WAIT-
WAIT-WAIT-16-
17...
7-8-9-10-11-12- 7-6-5-4-3-2-1-
13-14-15-0-1-2- 0-15-14-13-
7-0-1-2-3- 7-6-5-4-3-2-
4-5-6 1-0
7-4-5-6
7-6-5-4
3-4-5-6
12-11-10-9-8
...
12-13-14-15-
16-17-18...
12
13-14-15-WAIT-
16-17-18...
13
14
14-15-WAIT-
WAIT-16-17-
18....
15-WAIT-WAIT-
WAIT-16-17-
18...
15
45/117
Configuration Register
M58WTxxxKT, M58WTxxxKB
Table 12. Burst type definition (continued)
4 words
8 words
16 words
Start
add
Continuous
burst
Sequential Interleaved Sequential Interleaved
Sequential
Interleaved
0-1-2-3-4-5-6-
7-8-9-10-11-12-
13-14-15
0-1-2-3-4-
0
1
0-1-2-3
5-6-7
1-2-3-4-5-6-7-
8-9-10-11-12-
13-14-15-
1-2-3-4-5-
1-2-3-4
6-7-8
WAIT-16
2-3-4-5-6-7-8-
9-10-11-12-13-
14-15-WAIT-
WAIT-16-17
2-3-4-5-6-
2
2-3-4-5
7-8-9...
3-4-5-6-7-8-9-
10-11-12-13-
14-15-WAIT-
WAIT-WAIT-
16-17-18
3-4-5-6-7-
3
...
7
3-4-5-6
8-9-10
7-8-9-10-11-12-
13-14-15-
WAIT-WAIT-
WAIT-16-17-
18-19-20-21-22
7-8-9-10-
11-12-13-
14
Same as for
Wrap
7-8-9-10
(Wrap /No Wrap
has no effect on
...
Continuous
Burst)
12-13-14-15-
16-17-18-19-
20-21-22-23-
24-25-26-27
12-13-14-
15-16-17-
18-19
12-13-14-
15
12
13-14-15-
WAIT-16-17-
18-19-20-21-
22-23-24-25-
26-27-28
13-14-15-
WAIT-16-
17-18-19-
20
13-14-15-
WAIT-16
13
14
14-15-
WAIT-
WAIT-16-
17-18-19-
20-21
14-15-WAIT-
WAIT-16-17-
18-19-20-21-
22-23-24-25-
26-27-28-29
14-15-
WAIT-
WAIT-16-
17
15-WAIT-
WAIT-WAIT-
16-17-18-19-
20-21-22-23-
24-25-26-27-
28-29-30
15-WAIT-
WAIT-
WAIT-16-
17-18-19-
20-21-22
15-WAIT-
WAIT-
WAIT-16-
17-18
15
46/117
M58WTxxxKT, M58WTxxxKB
Configuration Register
Figure 6.
X latency and data output configuration example
X-latency
2nd cycle 3rd cycle
1st cycle
4th cycle
K
E
L
(1)
Amax-A0
VALID ADDRESS
tQVK_CPU
tK
tKQV
VALID DATA VALID DATA
DQ15-DQ0
Ai13422b
1. Amax is equal to A20 in the M58WT032KT/B and to A21 in the M58WT064KT/B.
2. Settings shown: X latency = 4, data output held for one clock cycle.
Figure 7.
Wait configuration example
E
K
L
(1)
Amax-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA NOT VALID VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI13423b
1. Amax is equal to A20 in the M58WT032KT/B and, to A21 in the M58WT064KT/B.
47/117
Read modes
M58WTxxxKT, M58WTxxxKB
9
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous. If the data output is synchronized with clock, the read operation
is synchronous.
The read mode and data output format are determined by the Configuration Register (see
Section 8: Configuration Register for details). All banks supports both asynchronous and
synchronous read operations. The multiple bank architecture allows read operations in one
bank, while write operations are being executed in another (see Tables 13 and 14).
9.1
Asynchronous read mode
In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, that is the memory array, Status Register, common
Flash interface or electronic signature, depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations.
In asynchronous read mode a page of data is internally read and stored in a page buffer.
The page has a size of 4 words and is addressed by A0 and A1 address inputs. The address
inputs A0 and A1 are not gated by Latch Enable in asynchronous read mode.
The first read operation within the page has a longer access time (T , random access
acc
time), and subsequent reads within the same page have much shorter access times. If the
page changes then the normal, longer timings apply again.
Asynchronous read operations can be performed in two different ways, Asynchronous
random access read and asynchronous page read. Only asynchronous page read takes full
advantage of the internal page storage so different timings are applied.
During asynchronous read operations, after a bus inactivity of 150 ns, the device
automatically switches to automatic standby mode. In this condition the power consumption
is reduced to the standby value and the outputs are still driven.
In asynchronous read mode, the WAIT signal is always asserted.
See Table 23: Asynchronous read AC characteristics, Figure 10: Asynchronous random
access read AC waveforms and Figure 11: Asynchronous page read AC waveforms for
details.
48/117
M58WTxxxKT, M58WTxxxKB
Read modes
9.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI, and read electronic signature, single
synchronous read or asynchronous random access read must be used.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence is started at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2
to 5 clock cycles (X latency bits CR13-CR11) the corresponding data is output on each clock
cycle.
The number of words to be output during a synchronous burst read operation can be
configured as 4, 8, 16 words, or continuous (burst length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cycles (data output configuration bit CR9).
The order of the data output can be modified through the burst type and the wrap burst bits
in the Configuration Register. The burst sequence may be configured to be sequential or
interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 word boundary
(wrap) or overcome the boundary (no wrap). If the starting address is aligned to the burst
length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence.
Interleaved mode is not allowed in continuous burst read mode or with no wrap sequences.
A WAIT signal may be asserted to indicate to the system that an output delay occurs. This
delay depends on the starting address of the burst sequence. The worst case delay occurs
when the sequence is crossing a 16-word boundary and the starting address was at the end
of a four word boundary.
WAIT is asserted during X latency, the Wait state, and at the end of 4-, 8- or 16-word burst.
It is only de-asserted when output data are valid. In continuous burst read mode a Wait state
occurs when crossing the first 16-word boundary. If the burst starting address is aligned to a
4-word page, the Wait state does not occur.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register. The WAIT signal is meaningful only in synchronous burst read
mode. In other modes, WAIT is always asserted (except for read array mode).
See Table 24: Synchronous read AC characteristics and Figure 12: Synchronous burst read
AC waveforms for details.
49/117
Read modes
M58WTxxxKT, M58WTxxxKB
9.3
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output), or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when E is low and the current address
has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal
is then halted at V or at V , and G goes high.
IH
IL
When G becomes low again and the clock signal restarts, the synchronous burst read
operation is resumed exactly where it stopped.
WAIT being gated by E remains active and does not revert to high-impedance when G goes
high. Therefore, if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the Flash memory should not be directly
connected to the system’s READY signal.
See Table 24: Synchronous read AC characteristics and Figure 14: Synchronous burst read
suspend AC waveforms for details.
9.4
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations
except that only the first data output after the X latency is valid. Synchronous single reads
are used to read the electronic signature, Status Register, CFI, block protection status,
Configuration Register status or Protection Register status. When the addressed bank is in
read CFI, read Status Register or read electronic signature mode, the WAIT signal is always
asserted.
See Table 24: Synchronous read AC characteristics and Figure 13: Single synchronous
read AC waveforms for details.
50/117
M58WTxxxKT, M58WTxxxKB
Dual operations and multiple bank architecture
10
Dual operations and multiple bank architecture
The multiple bank architecture of the M58WTxxxKT/B provides flexibility for software
developers by allowing code and data to be split with 4 Mbit granularity. The dual operations
feature simplifies the software management of the device and allows code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode). If a Read operation is required in a bank that is
programming or erasing, the program or erase operation can be suspended. Also, if the
suspended operation is erase then a program command can be issued to another block.
This means the device can have one block in erase suspend mode, one programming, and
other banks in read mode. Bus read operations are allowed in another bank between setup
and confirm cycles of program or erase operations. The combination of these features
means that read operations are possible at any moment.
Dual operations between the parameter bank and either the CFI, OTP, or the electronic
signature memory space are not allowed. Table 15, however, shows dual operations that are
allowed between the CFI, OTP, electronic signature locations, and the memory array.
Tables 13 and 14 show the dual operations possible in other banks and in the same bank.
For a complete list of possible commands refer to Appendix D: Command interface state
tables.
Table 13. Dual operations allowed in other banks
Commands allowed in another bank
Read
Status
Read
Read
Program/ Program/
Status of bank
Read
Array
Block
Erase
CFI Electronic Program
Erase
Erase
Register Query Signature
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
–
Yes
Yes
Yes
Yes
–
Programming
Erasing
–
–
–
Program
suspended
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
–
–
–
Yes
Yes
Erase suspended
Yes
51/117
Dual operations and multiple bank architecture
M58WTxxxKT, M58WTxxxKB
Table 14. Dual operations allowed in same bank
Commands allowed in same bank
Read
Electroni
c
Read
Status
Register Query
Read
CFI
Program/ Program/
Block
Status of bank
Read
Array
Program
Erase
Erase
Erase
Suspend Resume
Signature
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
–
Yes
Yes
Yes
Yes
–
(2)
Programming
Erasing
–
(2)
–
–
–
–
Program
suspended
Yes(1)
Yes(1)
Yes
Yes
Yes
Yes
Yes
Yes
–
–
–
–
–
Yes
Yes
Erase
suspended
Yes(1)
1. Not allowed in the block or word that is being erased or programmed.
2. The Read Array command is accepted but the data output is no guaranteed until the program or erase has
completed.
Table 15. Dual operation limitations
Commands allowed
Read Main Blocks
Read CFI / OTP /
Electronic
Read
Parameter
Blocks
Current status
Located in
parameter
bank
Not located in
parameter
bank
Signature
Programming/erasing
parameter blocks
No
No
No
No
No
Yes
Yes
Located in
parameter bank
Yes
Programming/
erasing main
blocks
Not located in
parameter bank
In different bank
only
Yes
No
Yes
No
Yes
No
Programming OTP
No
52/117
M58WTxxxKT, M58WTxxxKB
Block locking
11
Block locking
The M58WTxxxKT/B features an instant, individual block locking scheme that enables any
block to be locked or unlocked with no latency. This locking scheme has three levels of
protection.
●
Lock/unlock - this first level allows software-only control of block locking.
●
Lock-down - this second level requires hardware interaction before locking can be
changed.
●
V
≤V
- the third level offers a complete hardware protection against program and
PPLK
PP
erase on all blocks.
The protection status of each block can be set to locked, unlocked, and lock-down. Table 16,
defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 26,
shows a flowchart for the locking operations.
11.1
Reading a block’s lock status
The lock status of every block can be read in the read electronic signature mode of the
device. To enter this mode write 90h to the device. Subsequent reads at the address
specified in Table 7 output the protection status of that block. The lock status is represented
by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock
command and cleared by the Unlock command. It is also automatically set when entering
lock-down. DQ1 indicates the lock-down status and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware reset or power-down.
The following sections explain the operation of the locking system.
11.2
11.3
Locked state
The default status of all blocks on power-up or after a hardware reset is locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any
program or erase operations attempted on a locked block returns an error in the Status
Register. The status of a locked block can be changed to unlocked or lock-down using the
appropriate software commands. An unlocked block can be locked by issuing the Lock
command.
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked
blocks return to the locked state after a hardware reset or when the device is powered-down.
The status of an unlocked block can be changed to locked or locked-down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
53/117
Block locking
M58WTxxxKT, M58WTxxxKB
11.4
Lock-down state
Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations
(as for locked blocks) but their protection status cannot be changed using software
commands alone. A locked or unlocked block can be locked-down by issuing the Lock-Down
command. Locked-down blocks revert to the locked state when the device is reset or
powered-down.
The lock-down function is dependent on the WP input pin. When WP=0 (V ), the blocks in
IL
the lock-down state (0,1,x) are protected from program, erase and protection status
changes. When WP=1 (V ) the lock-down function is disabled (1,1,x) and locked-down
IH
blocks can be individually unlocked to the (1,1,0) state by issuing the software command,
where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and
unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were
previously locked-down return to the lock-down state (0,1,x) regardless of any changes
made while WP was High. Device reset or power-down resets all blocks, including those in
lock-down, to the locked state.
11.5
Locking operations during erase suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the status register until it indicates that the erase operation has been
suspended. Next ,write the desired lock command sequence to a block and the lock status
changes. After completing any desired lock, read, or program operations, resume the erase
operation with the Erase Resume command.
If a block is locked or locked down during an erase suspend of the same block, the locking
status bits change immediately. But when the erase is resumed, the erase operation
completes. Locking operations cannot be performed during a program suspend. Refer to
Appendix D: Command interface state tables for detailed information on which commands
are valid during erase suspend.
54/117
M58WTxxxKT, M58WTxxxKB
Block locking
Table 16. Lock status
Current protection status(1)
(WP, DQ1, DQ0)
Next protection status(1)
(WP, DQ1, DQ0)
After Block After Block
Program/erase
Current state
After Block
Lock command
After WP
transition
Unlock
Lock-Down
command
allowed
command
1,0,0
1,0,1(2)
1,1,0
yes
no
1,0,1
1,0,1
1,1,1
1,1,1
0,0,1
0,0,1
0,1,1
1,0,0
1,0,0
1,1,0
1,1,0
0,0,0
0,0,0
0,1,1
1,1,1
1,1,1
1,1,1
1,1,1
0,1,1
0,1,1
0,1,1
0,0,0
0,0,1
yes
no
0,1,1
1,1,1
0,1,1
0,0,0
yes
no
1,0,0
0,0,1(2)
1,0,1
0,1,1
no
1,1,1 or 1,1,0(3)
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block restores the previous DQ0 value, giving a 111 or 110.
55/117
Program and erase times and endurance cycles
M58WTxxxKT, M58WTxxxKB
12
Program and erase times and endurance cycles
The program and erase times and the number of program/ erase cycles per block are shown
in Table 17. Exact erase times may change depending on the memory array condition. The
best case is when all the bits in the block or bank are at ‘0’ (preprogrammed). The worst
case is when all the bits in the block or bank are at ‘1’ (not preprogrammed). Usually, the
system overhead is negligible with respect to the erase time. In the M58WTxxxKT/B the
maximum number of program/ erase cycles depends on the V voltage supply used.
PP
(1)
Table 17. Program/erase times and endurance cycles
Parameter Condition
Parameter block (4 Kword)(2)
Typical
Min
Typ after 100 k Max Unit
W/E cycles
0.3
0.8
1
1
3
2.5
4
s
s
Erase
Preprogrammed
Main block (32
Kword)
Not preprogrammed
4
s
Word
12
40
300
5
12
100
µs
Program(3)
Parameter block (4 Kword)
Main block (32 Kword)
Program
ms
ms
µs
10
20
Suspend latency
Erase
5
µs
Main blocks
100 000
100 000
cycles
cycles
s
Program/Erase
Cycles (per Block)
Parameter blocks
Parameter block (4 Kword)
Main block (32 Kword)
Word/ double word/ quadruple word(4)
Quad-enhanced factory
0.25
0.8
10
2.5
4
Erase
s
100
µs
11
ms
ms
ms
ms
ms
ms
ms
ms
s
Enhanced factory
Quadruple word(4)
Word
45
Parameter
block (4 Kword)
10
40
Program(3)
Quad-enhanced factory
Enhanced factory
Quadruple word(4)
Word
Quad-enhanced factory(4)
Quadruple word(4)
94
360
80
Main block (
32 Kword)
328
0.75
0.65
Bank (4 Mbit)
s
Main blocks
1000 cycles
2500 cycles
Program/erase
cycles (per block)
Parameter blocks
1. TA = –40 to 85 °C; VDD = VDDQ = 1.7 V to 2 V; VDDQ = 2.7 V to 3.3 V.
2. The difference between preprogrammed and not preprogrammed is not significant (< 30 ms).
3. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
4. Measurements performed at 25°C. TA = 30 °C 10 °C for quadruple word, double word and quadruple enhanced factory
program.
56/117
M58WTxxxKT, M58WTxxxKB
Maximum ratings
13
Maximum ratings
Stressing the device above the ratings listed in Table 18: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 18. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TA
TBIAS
TSTG
VIO
Ambient operating temperature
Temperature under bias
Storage temperature
Input or output voltage
Supply voltage
–40
–40
85
125
°C
°C
°C
V
–65
155
–0.5
–0.2
–0.2
–0.2
VDDQ + 0.6
2.45
VDD
VDDQ
VPP
V
Input/output supply voltage
Program voltage
3.6
V
10
V
IO
Output short circuit current
Time for VPP at VPPH
100
mA
hours
tVPPH
100
57/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
14
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables in this
section are derived from tests performed under the measurement conditions summarized in
Table 19: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 19. Operating and AC measurement conditions
Parameter
Min
Max
Unit
V
DD supply voltage
VDDQ supply voltage
PP supply voltage (factory environment)
1.7
2.7
2
3.3
V
V
V
8.5
9.5
V
VPP supply voltage (application environment)
Ambient operating temperature
Load capacitance (CL)
–0.4
–40
VDDQ+0.4
85
V
°C
pF
ns
V
30
Input rise and fall times
5
Input pulse voltages
0 to VDDQ
VDDQ/2
Input and output timing ref. voltages
V
Figure 8.
AC measurement I/O waveform
V
DDQ
V
/2
DDQ
0V
AI06161
58/117
M58WTxxxKT, M58WTxxxKB
Figure 9. AC measurement load circuit
DC and AC parameters
V
DDQ
V
DDQ
V
DD
16.7kΩ
DEVICE
UNDER
TEST
C
L
16.7kΩ
0.1µF
0.1µF
C
includes JIG capacitance
L
AI06162
(1)
Table 20. Capacitance
Symbol
Parameter
Test condition
Min
Max
Unit
CIN
Input capacitance
Output capacitance
VIN = 0 V
6
8
8
pF
pF
COUT
VOUT = 0 V
12
1. Sampled only, not 100% tested.
59/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
Min Typ Max Unit
Table 21. DC characteristics - currents
Symbol
Parameter
Test condition
ILI
Input leakage current
Output leakage current
0V ≤VIN ≤VDDQ
2
µA
µA
ILO
0V ≤VOUT ≤VDDQ
10
Supply current
asynchronous read (f = 5 MHz)
E = VIL, G = VIH
10
20
mA
4 word
8 word
18
20
25
28
20
22
27
30
mA
mA
mA
mA
IDD1
Supply current
synchronous Read (f = 52 MHz)
16 word
Continuous
Supply current
(reset/power-down)
IDD2
IDD3
IDD4
RP = VSS 0.2 V
E = VDDQ 0.2 V,
15
15
15
50
50
50
µA
µA
µA
Supply current (standby)
K = V
SS
Supply current (automatic
standby)
E = VIL, G = VIH
V
PP = VPPH
8
15
8
15
40
15
40
mA
mA
mA
mA
Supply current (program)
Supply current (erase)
V
PP = VDD
(1)
IDD5
VPP = VPPH
V
PP = VDD
15
Program/erase in one
bank, asynchronousread
in another bank
25
60
mA
Supply current
(1)(2)
IDD6
Program/erase in one
bank, synchronous read
(continuous burst 66
MHz) in another bank
(dual operations)
43
15
70
50
mA
µA
Supply current program/ erase
suspended (standby)
E = VDDQ 0.2 V,
(1)
IDD7
K = V
SS
VPP = VPPH
VPP = VDD
5
10
5
mA
µA
mA
µA
µA
µA
µA
VPP supply current (program)
0.2
5
(1)
IPP1
VPP = VPPH
10
5
VPP supply current (erase)
VPP = VDD
0.2
VPP = VPPH
100 400
IPP2
VPP supply current (read)
VPP ≤VDD
VPP ≤VDD
0.2
0.2
5
5
(1)
IPP3
VPP supply current (standby)
1. Sampled only, not 100% tested.
2. VDD dual operation current is the sum of read and program or erase currents.
60/117
M58WTxxxKT, M58WTxxxKB
DC and AC parameters
Table 22. DC characteristics - voltages
Symbol
Parameter
Input low voltage
Test condition
Min
Typ
Max
Unit
VIL
VIH
–0.5
0.4
VDDQ + 0.4
0.1
V
V
V
V
V
V
V
V
Input high voltage
Output low voltage
Output high voltage
VDDQ –0.4
VOL
VOH
IOL = 100 µA
IOH = –100 µA
Program, erase
Program, erase
VDDQ –0.1
1.3
VPP1 VPP program voltage-logic
VPPH VPP program voltage factory
VPPLK Program or erase lockout
VLKO VDD lock voltage
3.3
9.5
0.4
1
8.5
9
Figure 10. Asynchronous random access read AC waveforms
A0-Amax(1)
VALID
VALID
tAVAV
tAXQX
tAVLH
tLHAX
L
tLLLH
tLLQV
tELQV
tELQX
tELLH
tLHGL
E
tEHQZ
tEHQX
G
tGLQV
tGLQX
tGHQX
tGHQZ
tELTV
tEHTZ
Hi-Z
Hi-Z
WAIT
tAVQV
DQ0-DQ15
VALID
Valid Address Latch
Outputs Enabled
Data Valid
Standby
AI13424b
1. Amax is equal to A20 in the M58WT032KT/B and, to A21 in the M58WT064KT/B.
2. Write Enable, W, is High, WAIT is active Low.
61/117
DC and AC parameters
Figure 11. Asynchronous page read AC waveforms
M58WTxxxKT, M58WTxxxKB
62/117
M58WTxxxKT, M58WTxxxKB
DC and AC parameters
Table 23. Asynchronous read AC characteristics
Symbol
Alt
Parameter
Value
Unit
tAVAV
tAVQV
tAVQV1
tRC
tACC
tPAGE
tOH
Address Valid to Next Address Valid
Address Valid to Output Valid (Random)
Address Valid to Output Valid (page)
Address Transition to Output Transition
Chip Enable Low to Wait Valid
Min
Max
Max
Min
Max
Max
Min
Max
Min
Max
Max
Min
Min
Max
Min
Min
Min
Min
70
70
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAXQX
tELTV
20
70
0
(2)
tELQV
tCE
tLZ
Chip Enable Low to Output Valid
Chip Enable Low to Output Transition
Chip Enable High to Wait Hi-Z
(1)
tELQX
tEHTZ
25
0
(1)
tEHQX
tEHQZ
tGLQV
tGLQX
tOH
tHZ
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
(1)
(2)
(1)
(1)
20
30
0
tOE
tOLZ
tOH
tDF
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
tGHQX
0
(1)
tGHQZ
14
10
10
9
tAVLH
tELLH
tLHAX
tLLLH
tAVADVH Address Valid to Latch Enable High
tELADVH Chip Enable Low to Latch Enable High
tADVHAX Latch Enable High to Address Transition
tADVLADVH Latch Enable Pulse Width
10
Latch Enable Low to Output Valid
(Random)
tLLQV
tLHGL
tADVLQV
Max
Min
70
0
ns
ns
tADVHGL Latch Enable High to Output Enable Low
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
.
63/117
DC and AC parameters
Figure 12. Synchronous burst read AC waveforms
M58WTxxxKT, M58WTxxxKB
64/117
M58WTxxxKT, M58WTxxxKB
Figure 13. Single synchronous read AC waveforms
DC and AC parameters
65/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
Figure 14. Synchronous burst read suspend AC waveforms
66/117
M58WTxxxKT, M58WTxxxKB
Figure 15. Clock input AC waveform
DC and AC parameters
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
(1) (2)
Table 24. Synchronous read AC characteristics
Symbol
tAVKH
tELKH
tELTV
Alt
Parameter
Value
Unit
tAVCLKH
tELCLKH
Address Valid to Clock High
Chip Enable Low to Clock High
Chip Enable Low to Wait Valid
Min
Min
Max
9
9
ns
ns
ns
20
Chip Enable Pulse Width (subsequent
synchronous reads)
tEHEL
Min
20
ns
tEHTZ
tKHAX
tKHQV
tKHTV
tKHQX
tKHTX
Chip Enable High to Wait Hi-Z
Clock High to Address Transition
Max
Min
20
10
ns
ns
tCLKHAX
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
Min
17
3
ns
ns
Clock High to Output Transition
Clock High to WAIT Transition
tCLKHQX
tLLKH
tADVLCLKH Latch Enable Low to Clock High
Min
Min
9
ns
ns
tKHKH
tCLK
Clock Period (f=52MHz)
19
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
9.5
3
ns
ns
tf
tr
Clock Fall or Rise Time
Max
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 23: Asynchronous read AC characteristics.
67/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
Figure 16. Write AC waveforms, Write Enable controlled
68/117
M58WTxxxKT, M58WTxxxKB
DC and AC parameters
(1)
Table 25. Write AC characteristics, Write Enable controlled
Symbol
Alt
Parameter
Value Unit
tAVAV
tAVLH
tWC Address Valid to Next Address Valid
Address Valid to Latch Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
10
45
45
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tAVWH
tDVWH
tELLH
tELWL
tELQV
tELKV
tGHWL
tLHAX
tLLLH
Address Valid to Write Enable High
tDS Data Valid to Write Enable High
Chip Enable Low to Latch Enable High
tCS Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
70
9
Chip Enable Low to Clock Valid
Output Enable High to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
17
9
10
0
(2)
tWHAV
Write Enable High to Address Valid
(2)
tWHAX
tWHDX
tWHEH
tAH Write Enable High to Address Transition
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Latch Enable Low
tWPH Write Enable High to Write Enable Low
tWP Write Enable Low to Write Enable High
Output (Status Register) Valid to VPP Low
0
0
0
(3)
tWHEL
tWHGL
25
0
(3)
tWHLL
tWHWL
tWLWH
tQVVPL
25
25
45
0
Output (Status Register) Valid to Write
Protect Low
tQVWPL
Min
0
ns
tVPHWH
tWHVPL
tWHWPL
tWPHWH
tVPS VPP High to Write Enable High
Write Enable High to VPP Low
Min
Min
Min
Min
200
200
200
200
ns
ns
ns
ns
Write Enable High to Write Protect Low
Write Protect High to Write Enable High
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a
Set Configuration Register command. System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing any
command and to delay the first read to any address after issuing a Set Configuration Register
command. If the first read after the command is a Read Array operation in a different bank and
no changes to the Configuration Register have been issued, tWHEL and tWHLL are 0ns.
69/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
Figure 17. Write AC waveforms, Chip Enable controlled
70/117
M58WTxxxKT, M58WTxxxKB
DC and AC parameters
(1)
Table 26. Write AC characteristics, Chip Enable controlled
Symbol
Alt
Parameter
Value
Unit
tAVAV
tAVEH
tAVLH
tDVEH
tEHAX
tEHDX
tEHEL
tEHGL
tEHWH
tELKV
tELEH
tELLH
tELQV
tGHEL
tLHAX
tLLLH
tWC Address Valid to Next Address Valid
Address Valid to Chip Enable High
Min
70
45
10
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Address Valid to Latch Enable High
tDS Data Valid to Chip Enable High
tAH Chip Enable High to Address Transition
tDH Chip Enable High to Input Transition
tCPH Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
tCH Chip Enable High to Write Enable High
Chip Enable Low to Clock Valid
0
25
0
0
9
tCP Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Output Valid
45
10
70
17
9
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
10
25
0
(2)
tWHEL
tWLEL
Write Enable High to Chip Enable Low
tCS Write Enable Low to Chip Enable Low
Chip Enable High to VPP Low
tEHVPL
tEHWPL
tQVVPL
200
200
0
Chip Enable High to Write Protect Low
Output (Status Register) Valid to VPP Low
Output (Status Register) Valid to Write
Protect Low
tQVWPL
Min
0
ns
tVPHEH tVPS VPP High to Chip Enable High
tWPHEH Write Protect High to Chip Enable High
Min
Min
200
200
ns
ns
1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading following a Set
Configuration Register command. System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing any
command and to delay the first read to any address after issuing a Set Configuration Register
command. If the first read after the command is a read array operation in a different bank and
no changes to the Configuration Register have been issued, tWHEL is 0 ns.
71/117
DC and AC parameters
M58WTxxxKT, M58WTxxxKB
Figure 18. Reset and power-up AC waveforms
tPHWL
tPHEL
tPHGL
tPHLL
tPLWL
tPLEL
tPLGL
tPLLL
W, E, G, L
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 27. Reset and power-up AC characteristics
Symbol
Parameter
Test condition
Value
Unit
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to Write Enable Low,
Reset Low to Chip Enable Low,
Reset Low to Output Enable Low,
Reset Low to Latch Enable Low
During program
During erase
Min
Min
10
20
µs
µs
Other conditions
Min
80
ns
tPHWL
tPHEL
tPHGL
tPHLL
Reset High to Write Enable Low
Reset High to Chip Enable Low
Reset High to Output Enable Low
Reset High to Latch Enable Low
Min
30
ns
(1),(2)
tPLPH
RP pulse width
Min
Min
50
ns
µs
(3)
tVDHPH
Supply Voltages High to Reset High
200
1. The device Reset is possible but not guaranteed if tPLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset.
72/117
M58WTxxxKT, M58WTxxxKB
Package mechanical
15
Package mechanical
To meet environmental requirements, Numonyx offers the M58WTxxxKT/B in ECOPACK®
packages, which have a lead-free, second-level interconnect. In compliance with JEDEC
Standard JESD97, the category of second-level interconnect is marked on the package and
on the inner box label.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Figure 19. TFBGA88 8 × 10 mm, 8 × 10 ball array, 0.8 mm, package outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
73/117
Package mechanical
M58WTxxxKT, M58WTxxxKB
Table 28. TFBGA88 8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch, package mechanical
data
Millimeters
Inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
–
E1
E2
e
–
–
FD
FE
FE1
SD
SE
74/117
M58WTxxxKT, M58WTxxxKB
Part numbering
16
Part numbering
Table 29. Ordering information scheme
Example:
M58WT032KT
70 ZAQ 6 E
Device type
M58
Architecture
W = Multiple bank, burst mode
Operating voltage
T = VDD = 1.8 V to 2 V ; VDDQ = 2.7 V to 3.3 V
Density
032 = 32 Mbit (×16)
064 = 64 Mbit (×16)
Technology
K = 65 nm technology
Parameter bank location
T = top boot
B = bottom boot
Speed
70 = 70 ns
Package
ZAQ = TFBGA88 8 × 10 mm, 0.80 mm pitch, quadruple
stacked footprint
Temperature range
6 = –40 to 85 °C
Options
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (speed, etc.) or for further information on any aspect of this device, please
contact the nearest Numonyx sales office.
75/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Appendix A
Block address tables
Table 30. Top boot block addresses, M58WT032KT
Bank(1)
#
Size (Kword)
Address range
0
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
76/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Address range
Table 30. Top boot block addresses, M58WT032KT (continued)
Bank(1)
#
Size (Kword)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
77/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 30. Top boot block addresses, M58WT032KT (continued)
Bank(1)
#
Size (Kword)
Address range
63
64
65
66
67
68
69
70
32
32
32
32
32
32
32
32
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;
Bank Region 2 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 31. Bottom boot block addresses, M58WT032KB
Bank(1)
#
Size (Kword)
Address range
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
78/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Table 31. Bottom boot block addresses, M58WT032KB (continued)
Bank(1)
#
Size (Kword)
Address range
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
79/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 31. Bottom boot block addresses, M58WT032KB (continued)
Bank(1)
#
Size (Kword)
Address range
14
13
12
11
10
9
32
32
32
32
32
32
32
4
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only;
bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
80/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Address range
Table 32. Top boot block addresses, M58WT064KT
Bank(1)
#
Size (Kword)
0
4
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 32. Top boot block addresses, M58WT064KT (continued)
Bank(1)
#
Size (Kword)
Address range
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
82/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Address range
Table 32. Top boot block addresses, M58WT064KT (continued)
Bank(1)
#
Size (Kword)
79
80
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
83/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 32. Top boot block addresses, M58WT064KT (continued)
Bank(1)
#
Size (Kword)
Address range
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only;
bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 33. Bottom boot block addresses, M58WT064KB
Bank(1)
#
Size (Kword)
Address range
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
84/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Table 33. Bottom boot block addresses, M58WT064KB (continued)
Bank(1)
#
Size (Kword)
Address range
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
98
97
96
95
94
93
92
91
90
89
88
87
85/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 33. Bottom boot block addresses, M58WT064KB (continued)
Bank(1)
#
Size (Kword)
Address range
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
86/117
M58WTxxxKT, M58WTxxxKB
Block address tables
Table 33. Bottom boot block addresses, M58WT064KB (continued)
Bank(1)
#
Size (Kword)
Address range
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
87/117
Block address tables
M58WTxxxKT, M58WTxxxKB
Table 33. Bottom boot block addresses, M58WT064KB (continued)
Bank(1)
#
Size (Kword)
Address range
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only;
bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
88/117
M58WTxxxKT, M58WTxxxKB
Common Flash interface
Appendix B
Common Flash interface
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query Command is issued the device enters CFI query mode and the
data structure is read from the memory. Tables 34, 35, 36, 37, 38, 39, 40, 41, 42 and 43
show the addresses used to retrieve the data. The query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Figure 5: Protection Register memory map). This area can be accessed only
in read mode by the final user. It is impossible to change the security number after it has
been written by Numonyx. Issue a Read Array command to return to read mode.
(1)
Table 34. Query structure overview
Offset
Sub-section name
Description
00h
10h
1Bh
27h
Reserved
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing and voltage information
Flash device layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary Algorithm-specific Extended Query Additional information specific to the
P
A
table
primary algorithm (optional)
Alternate Algorithm-specific Extended
Query table
Additional information specific to the
Alternate Algorithm (optional)
Lock Protection Register
Unique device Number and
User Programmable OTP
80h
Security Code Area
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in Tables 35, 36, 37 and 38. Query data is always presented on the
lowest order data outputs.
89/117
Common Flash interface
M58WTxxxKT, M58WTxxxKB
Table 35. CFI query identification string
Sub-section
name
Offset
Description
Manufacturer code
Value
00h
0020h
Numonyx
8866h
8810h
8867h
8811h
M58WT032KT (Top)
M58WT064KT (Top)
M58WT032KB (Bottom)
M58WT064KB (Bottom)
01h
Device code
02h
03h
reserved
reserved
reserved
0051h
Reserved
Reserved
Reserved
04h-0Fh
10h
"Q"
"R"
"Y"
11h
0052h
Query Unique ASCII String "QRY"
12h
0059h
13h
0003h
Primary Algorithm Command Set and
Control Interface ID code 16 bit ID code
defining a specific algorithm
14h
0000h
15h
16h
17h
offset = P = 0039h
0000h
Address for Primary Algorithm extended
Query table (see Table 38)
p = 39h
NA
0000h
Alternate Vendor Command Set and
Control Interface ID Code second vendor
- specified algorithm supported
18h
0000h
19h
1Ah
value = A = 0000h
0000h
Address for Alternate Algorithm extended
Query table
NA
90/117
M58WTxxxKT, M58WTxxxKB
Common Flash interface
Value
Table 36. CFI query system interface information
Offset Data Description
V
V
V
V
DD Logic Supply Minimum Program/Erase or Write voltage
1Bh
1Ch
1Dh
1Eh
0017h
0020h
0085h
0095h
1.7V
2V
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
DD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
PP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5V
9.5V
PP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0000h
000Ah
0000h
0003h
0000h
0002h
0000h
Typical time-out per single byte/word program = 2n µs
Typical time-out for multi-byte programming = 2n µs
Typical time-out per individual block erase = 2n ms
Typical time-out for full chip erase = 2n ms
16µs
NA
1s
NA
Maximum time-out for word program = 2n times typical
Maximum time-out for multi-byte programming = 2n times typical
Maximum time-out per individual block erase = 2n times typical
Maximum time-out for chip erase = 2n times typical
128µs
NA
4s
NA
91/117
Common Flash interface
M58WTxxxKT, M58WTxxxKB
Table 37. Device geometry definition
Offset
word
Data
Description
Value
mode
0016h M58WT032KT/B Device Size = 2n in number of bytes
0017h M58WT064KT/B Device Size = 2n in number of bytes
4 Mbytes
8 Mbytes
27h
28h
29h
0001h
x16
Flash Device Interface Code description
0000h
Async.
2Ah
2Bh
0000h
Maximum number of bytes in multi-byte program or page = 2n
0000h
NA
2
Number of identical sized erase block regions within the device
0002h
2Ch
bit 7 to 0 = x = number of Erase Block Regions
003Eh M58WT032KT Region 1 Information
63
0000h Number of identical-size erase blocks = 003Eh+1
2Dh
2Eh
007Eh M58WT064KT Region 1 Information
127
0000h Number of identical-size erase blocks = 007Eh+1
2Fh
30h
0000h Region 1 Information
64 Kbyte
8
0001h Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h Region 2 Information
0000h Number of identical-size erase blocks = 0007h+1
33h
34h
0020h Region 2 Information
8 Kbyte
NA
0000h Block size in Region 2 = 0020h * 256 byte
35h
38h
Reserved for future erase block region information
2Dh
2Eh
0007h Region 1 Information
8
0000h Number of identical-size erase block = 0007h+1
2Fh
30h
0020h Region 1 Information
8 Kbyte
63
0000h Block size in Region 1 = 0020h * 256 byte
003Eh M58WT032KB Region 1 Information
0000h Number of identical-size erase blocks = 003Eh+1
31h
32h
007Eh M58WT064KB Region 1 Information
127
0000h Number of identical-size erase blocks = 007Eh+1
33h
34h
0000h Region 2 Information
64 Kbyte
NA
0001h Block size in Region 2 = 0100h * 256 byte
35h
38h
Reserved for future erase block region information
92/117
M58WTxxxKT, M58WTxxxKB
Common Flash interface
(1)
Table 38. Primary algorithm-specific extended query table
Offset
Data
Description
Value
(P)h = 39h
0050h
"P"
0052h Primary Algorithm extended Query table unique ASCII string “PRI”
0049h
"R"
"I"
(P+3)h = 3Ch 0031h Major version number, ASCII
"1"
"3"
(P+4)h = 3Dh 0033h Minor version number, ASCII
(P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains
less significant byte.
0003h
(P+7)h = 40h
(P+8)h = 41h
0000h
0000h
bit 0 Chip Erase supported (1 = Yes, 0 = No)
bit 1 Erase Suspend supported (1 = Yes, 0 = No)
bit 2 Program Suspend supported (1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4 Queued Erase supported (1 = Yes, 0 = No)
bit 5 Instant individual block locking supported (1 = Yes, 0 = No)
bit 6 Protection bits supported (1 = Yes, 0 = No)
bit 7 Page mode read supported (1 = Yes, 0 = No)
bit 8 Synchronous read supported (1 = Yes, 0 = No)
bit 9 Simultaneous operation supported (1 = Yes, 0 = No)
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31 bit
field of optional features follows at the end of the bit-30 field.
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
(P+9)h = 42h
(P+A)h = 43h
0001h
0003h
Yes
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Block Protect status
Defines which bits in the Block Status Register section of the Query are
implemented.
(P+B)h = 44h
0000h
bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register lock-down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD Logic Supply Optimum Program/Erase voltage (highest performance)
(P+C)h = 45h 0018h
(P+D)h = 46h 0090h
1.8V
9V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
VPP Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1. The variable P is a pointer that is defined at CFI offset 15h.
93/117
Common Flash interface
M58WTxxxKT, M58WTxxxKB
Value
(1)
Table 39. Protection Register information
Offset
Data
Description
Number of protection register fields in JEDEC ID space. 0000h indicates
that 256 fields are available.
(P+E)h = 47h
0001h
1
(P+F)h = 48h
(P+10)h = 49h
0080h
0000h
Protection Field 1: Protection Description
0080h
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
(P+11)h =
4Ah
0003h
0004h
8 bytes
(P+12)h= 4Bh
16 bytes
1. The variable P is a pointer that is defined at CFI offset 15h.
(1)
Table 40. Burst read information
Offset
Data
Description
Value
Page-mode read capability
bits 0-7 ’n’ such that 2n HEX value represents the number of read-page
bytes. See offset 28h for device word width to determine page-mode data
output width.
(P+13)h = 4Ch
(P+14)h = 4Dh
0003h
0004h
8 bytes
4
Number of synchronous mode read configuration fields that follow.
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads when the device is configured for its
maximum word width. A value of 07h indicates that the device is capable of
continuous linear bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space. This field’s 3-bit
value can be written directly to the read configuration register bit 0-2 if the
device is configured for its maximum word width. See offset 28h for word
width to determine the burst data output width.
(P+15)h = 4Eh
0001h
4
(P+16)h = 4Fh
(P+17)h = 50h
(P+18)h = 51h
0002h
0003h
0007h
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
8
16
Cont.
1. The variable P is a pointer that is defined at CFI offset 15h.
(1) (2)
Table 41. Bank and erase block region information
M58WT032KT,
M58WT064KT
M58WT032KB,
M58WT064KB
Description
Offset
Data
02h
Offset
Data
02h
(P+19)h = 52h
(P+19)h = 52h
Number of bank regions within the device
1. The variable P is a pointer that is defined at CFI offset 15h.
2. Bank regions. There are two bank regions, see Tables 30, 31, 32 and 33.
94/117
M58WTxxxKT, M58WTxxxKB
Common Flash interface
(1)
Table 42. Bank and erase block region 1 information
M58WT032KT,
M58WT064KT
M58WT032KB,
M58WT064KB
Description
Offset
Data
Offset
Data
07h(2)
0Fh(3)
(P+1A)h = 53h
(P+1B)h = 54h
(P+1A)h = 53h
(P+1B)h = 54h
01h
00h
Number of identical banks within Bank Region 1
00h
Number of program or erase operations allowed in Bank
Region 1:
(P+1C)h = 55h
(P+1D)h = 56h
(P+1E)h = 57h
(P+1F)h = 58h
11h
(P+1C)h = 55h
(P+1D)h = 56h
(P+1E)h = 57h
(P+1F)h = 58h
11h
00h
00h
02h
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other
banks while a bank in same region is programming
00h
00h
01h
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank Region 1
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region.(4)
(P+20)h = 59h
(P+21)h = 5Ah
(P+22)h = 5Bh
(P+23)h = 5Ch
(P+24)h = 5Dh
(P+25)h = 5Eh
07h
00h
00h
01h
64h
00h
(P+20)h = 59h
(P+21)h = 5Ah
(P+22)h = 5Bh
(P+23)h = 5Ch
(P+24)h = 5Dh
(P+25)h = 5Eh
07h
00h
20h
00h
64h
00h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 1 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved 5Eh 01 5Eh 01
(P+26)h = 5Fh
(P+27)h = 60h
01h
03h
(P+26)h = 5Fh
(P+27)h = 60h
01h
03h
Bank Region 1 (Erase Block Type 1): page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
95/117
Common Flash interface
M58WTxxxKT, M58WTxxxKB
(1)
Table 42. Bank and erase block region 1 information (continued)
M58WT032KT,
M58WT064KT
M58WT032KB,
M58WT064KB
Description
Offset
Data
Offset
Data
(P+28)h = 61h
(P+29)h = 62h
(P+2A)h = 63h
(P+2B)h = 64h
(P+2C)h = 65h
(P+2D)h = 66h
06h
00h
00h
01h
64h
00h
Bank Region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Regions 1 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+2E)h = 67h
(P+2F)h = 68h
01h
03h
Bank Region 1 (Erase Block Type 2): page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Applies to M58WT032KT.
3. Applies to M58WT064KT.
4. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.
96/117
M58WTxxxKT, M58WTxxxKB
Common Flash interface
(1)
Table 43. Bank and Erase block region 2 information
M58WT032KT,
M58WT064KT
M58WT032KB,
M58WT064KB
Description
Offset
Data
Offset
Data
07h(2)
0Fh(3)
(P+28)h = 61h
(P+29)h = 62h
01h
00h
(P+30)h = 69h
(P+31)h = 6Ah
Number of identical banks within Bank Region 2
00h
Number of program or erase operations allowed in Bank
Region 2:
(P+2A)h = 63h
(P+2B)h = 64h
(P+2C)h = 65h
(P+2D)h = 66h
11h
00h
00h
02h
(P+32)h = 6Bh
(P+33)h = 6Ch
(P+34)h = 6Dh
(P+35)h = 6Eh
11h
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other
banks while a bank in this region is programming
00h
00h
01h
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank Region 2
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region.(4)
(P+2E)h = 67h
(P+2F)h = 68h
(P+30)h = 69h
(P+31)h = 6Ah
(P+32)h = 6Bh
(P+33)h = 6Ch
06h
00h
00h
01h
64h
00h
(P+36)h = 6Fh
(P+37)h = 70h
(P+38)h = 71h
(P+39)h = 72h
(P+3A)h = 73h
(P+3B)h = 74h
07h
00h
00h
01h
64h
00h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+34)h = 6Dh
(P+35)h = 6Eh
01h
03h
(P+3C)h = 75h
(P+3D)h = 76h
01h
03h
Bank Region 2 (Erase Block Type 1): page mode and
synchronous mode capabilities (defined in Table 40)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
97/117
Common Flash interface
M58WTxxxKT, M58WTxxxKB
(1)
Table 43. Bank and Erase block region 2 information (continued)
M58WT032KT,
M58WT064KT
M58WT032KB,
M58WT064KB
Description
Offset
Data
Offset
Data
(P+36)h = 6Fh
(P+37)h = 70h
(P+38)h = 71h
(P+39)h = 72h
(P+3A)h = 73h
(P+3B)h = 74h
07h
00h
20h
00h
64h
00h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+3C)h = 75h
(P+3D)h = 76h
01h
03h
Bank Region 2 (Erase Block Type 2): page mode and
synchronous mode capabilities (defined in Table 40)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3E)h = 77h
(P+3F)h = 78h
(P+3E)h = 77h
(P+3F)h = 78h
Feature Space definitions
Reserved
1. The variable P is a pointer which is defined at CFI offset 15h.
2. Applies to M58WT032KB.
3. Applies to M58WT064KB.
4. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32 and 33.
98/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Appendix C
Flowcharts and pseudo codes
Figure 20. Program flowchart and pseudo code
Start
program_command (addressToProgram, dataToProgram) {:
"
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
Write 40h or 10h (3)
"
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register (3)
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
NO
SR7 = 1
} while (status_register.SR7== 0) ;
YES
NO
NO
NO
V
Invalid
if (status_register.SR3==1) /*V
invalid error */
PP
PP
SR3 = 0
YES
Error (1, 2)
error_handler ( ) ;
Program
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
SR4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
99/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
Figure 21. Double word program flowchart and pseudo code
Start
Write 35h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (addressToProgram1, 0x35);
/*see note (4)*/
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3, 4)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (addressToProgram) ;
"see note (4)"
/* E or G must be toggled*/
Read Status
Register (4)
NO
NO
NO
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
V
Invalid
if (status_register.SR3==1) /*V
error_handler ( ) ;
invalid error */
PP
PP
SR3 = 0
YES
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
Program
SR4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06171b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
4. Any address within the bank can equally be used.
100/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Figure 22. Quadruple word program flowchart and pseudo code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write 56h
Write Address 1
& Data 1 (3, 4)
writeToFlash (addressToProgram1, 0x56);
/*see note (4) */
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (addressToProgram) ;
/"see note (4) "/
/* E or G must be toggled*/
Read Status
Register (4)
NO
NO
NO
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
V
Invalid
if (status_register.SR3==1) /*V
error_handler ( ) ;
invalid error */
PP
PP
SR3 = 0
YES
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
Program
SR4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.SR==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06977b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
4. Any address within the bank can equally be used.
101/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
Figure 23. Program suspend and resume flowchart and pseudo code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
SR2 = 1
Program Complete
Write FFh
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Read Data
YES
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
102/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Figure 24. Block erase flowchart and pseudo code
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significant */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register (2)
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
NO
YES
NO
NO
V
Invalid
if (status_register.SR3==1) /*V
error_handler ( ) ;
invalid error */
PP
Error (1)
PP
SR3 = 0
YES
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
Command
Sequence Error (1)
SR4, SR5 = 1
NO
error_handler ( ) ;
if ( (status_register.SR5==1) )
/* erase error */
SR5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI13431
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can be used also.
103/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
Figure 25. Erase suspend and resume flowchart and pseudo code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
NO
NO
} while (status_register.SR7== 0) ;
SR7 = 1
YES
SR6 = 1
Erase Complete
Write FFh
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
Read Data
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
YES
Write FFh
}
else
{ writeToFlash (bank_address, 0xFF) ;
Read data from another block,
Program,
read_program_data ( );
Set Configuration Register
or
/*read or program data from another block*/
Block Lock/Unlock/Lock-Down
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
(1)
Write 70h
}
}
Erase Continues with
Bank in Read Status
Register Mode
AI10116d
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
104/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Figure 26. Locking operations flowchart and pseudo code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
Write 60h (1)
/* see note (1) */
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
Write
01h, D0h or 2Fh
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
NO
Locking
change
/*Check the locking state (see Read Block Signature table )*/
confirmed?
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI06176b
1. Any address within the bank can equally be used.
105/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
Figure 27. Protection Register program flowchart and pseudo code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register (3)
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
NO
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
SR3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
SR4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06177b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
106/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Figure 28. Enhanced factory program flowchart
SETUP PHASE
Start
VERIFY PHASE
Write PD1
Address WA1
Write 30h
Address WA1
1)
(
Write D0h
Address WA1
Read Status
Register
Read Status
Register
NO
SR0 = 0?
YES
NO
SR7 = 0?
Check SR4, SR3
Write PD2
Address WA2
YES
1)
and SR1 for program,
(
V
and Lock Errors
PP
NO
SR0 = 0?
YES
Exit
Read Status
Register
Write PD1
Address WA1
PROGRAM PHASE
NO
SR0 = 0?
Read Status
Register
YES
Write PDn
Address WAn
NO
1)
(
SR0 = 0?
YES
Read Status
Register
Write PD2
Address WA2
1)
(
NO
Read Status
Register
SR0 = 0?
YES
NO
Write FFFFh
SR0 = 0?
Address Block WA1
=
/
YES
EXIT PHASE
Write PDn
Address WAn
1)
(
Read Status
Register
Read Status
Register
NO
SR7 = 1?
YES
NO
SR0 = 0?
YES
Check Status
Register for Errors
Write FFFFh
=
Address Block WA1
/
End
AI06160
1. Address can remain Starting Address WA1 or be incremented.
107/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
16.1
Enhanced factory program pseudo code
efp_command(addressFlow,dataFlow,n)
/* n is the number of data to be programmed */
{
/* setup phase */
writeToFlash(addressFlow[0],0x30);
writeToFlash(addressFlow[0],0xD0);
status_register=readFlash(any_address);
if (status_register.SR7==1){
/*EFP aborted for an error*/
if (status_register.SR4==1) /*program error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block error*/
error_handler();
}
else{
/*Program Phase*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1)
/*Ready for first data*/
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* Verify Phase */
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.SR0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* exit program phase */
/* Exit Phase */
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.SR7==0);
if (status_register.SR4==1) /*program failure error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block error*/
error_handler();
}
}
108/117
M58WTxxxKT, M58WTxxxKB
Flowcharts and pseudo codes
Figure 29. Quadruple enhanced factory program flowchart
SETUP PHASE
Start
LOAD PHASE
Write PD1
1)
Write 75h
Address WA1
Address WA1(
FIRST
LOAD PHASE
Write PD2
Write PD1
Address WA1
2)
Address WA2(
Read Status
Register
Write PD3
2)
Address WA3(
NO
SR7 = 0?
YES
Write PD4
2)
Address WA4(
EXIT PHASE
Write FFFFh
Check SR4, SR3
and SR1 for program,
PROGRAM AND
VERIFY PHASE
VPP and Lock Errors
Read Status
Register
Address =Block WA1
/
Exit
Check SR4 for
Programming Errors
NO
NO
SR0 = 0?
YES
End
Last Page?
YES
AI06178b
1. Address can remain Starting Address WA1 (in which case the next page is programmed) or can be any address in the
same block.
2. The address is only checked for the first word of each page as the order to program the words is fixed, so subsequent
words in each page can be written to any address.
109/117
Flowcharts and pseudo codes
M58WTxxxKT, M58WTxxxKB
16.2
Quadruple enhanced factory program pseudo code
quad_efp_command(addressFlow,dataFlow,n)
/* n is the number of pages to be programmed.*/
{
/* Setup phase */
writeToFlash(addressFlow[0],0x75);
for (i=0; i++; i< n){
/*Data Load Phase*/
/*First Data*/
writeToFlash(addressFlow[i],dataFlow[i,0]);
/*at the first data of the first page, Quad-EFP may be aborted*/
if (First_Page) {
status_register=readFlash(any_address);
if (status_register.SR7==1){
/*EFP aborted for an error*/
if (status_register.SR4==1) /*program error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR1==1) /*program to protect block
error*/
}
error_handler();
}
/*2nd data*/
writeToFlash(addressFlow[i],dataFlow[i,1]);
/*3rd data*/
writeToFlash(addressFlow[i],dataFlow[i,2]);
/*4th data*/
writeToFlash(addressFlow[i],dataFlow[i,3]);
/* Program&Verify Phase */
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.SR0==1)
}
/* Exit Phase */
writeToFlash(another_block_address,FFFFh);
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.SR7==0);
if (status_register.SR1==1) /*program to protected block error*/
error_handler();
if (status_register.SR3==1) /*VPP invalid error*/
error_handler();
if (status_register.SR4==1) /*program failure error*/
error_handler();
}
}
110/117
M58WTxxxKT, M58WTxxxKB
Command interface state tables
Appendix D
Command interface state tables
(1)
Table 44. Command interface states - modify table, next state
Command Input
Erase
Confirm, P/E
Resume,
Block Unlock
confirm, EFP
Confirm
Read
Clear
Status
DWP,
QWP
Setup
Block
Erase
Setup
Program/ Read
Erase Status
Suspend Register
Electronic
signature,
Read CFI
Query
Current CI State
Read
Array
(FFh)
WP
setup
(10/40h)
EFP Quad-EFP
Setup Setup
(3)(4)
(2)
(3)(4)
Register
(3)(4)
(5)
(30h)
(75h)
(B0h)
(70h)
(35h, 56h)
(20h)
(50h)
(90h, 98h)
(D0h)
Program Program
Erase
Setup
EFP Quad-EFP
Setup Setup
Ready
Ready
Ready
Ready (Lock Error)
Setup
Setup
Lock/CR Setup
Setup
Ready (Lock Error)
Ready
OTP Busy
Busy
OTP Busy
IS in OTP busy
OTP Busy
OTP
IS in OTP
busy
OTP busy
Setup
Busy
Program Busy
Program
busy
IS in Program busy
Program busy
PS
Program busy
IS in Program
busy
Program
Program Busy
Suspend
IS in PS
Setup
PS
IS in Program Suspend
Program Busy
Program suspend
Erase Busy
Program Suspend
Ready (error)
Ready (error)
Erase Busy
Erase
Busy
Busy
IS in Erase busy
Erase Busy
ES
IS in Erase
busy
Erase
Erase busy
Program
in ES
Suspend
ES
IS in Erase Suspend
Erase Busy
Erase Suspend
IS in ES
Setup
Erase Suspend
Program Busy in Erase Suspend
Program Busy
Program
Busy in ES
Program Busy in Erase
Suspend
Busy
IS in Program Busy in Erase Suspend
PS in ES
in ES
Program Busy in Erase Suspend
Program Busy
Program
in ES
IS in Program
busy in ES
Suspend
PS in ES
IS in Program suspend in ES
Program Suspend in Erase Suspend
Erase Suspend (Lock Error)
in ES
IS in PS in ES
Program Suspend in Erase Suspend
Lock/CR Setup in ES
Erase Suspend (Lock Error)
ES
111/117
Command interface state tables
M58WTxxxKT, M58WTxxxKB
(1)
Table 44. Command interface states - modify table, next state (continued)
Command Input
Erase
Confirm, P/E
Resume,
Block Unlock
confirm, EFP
Confirm
Read
Clear
Status
DWP,
QWP
Setup
Block
Erase
Setup
Program/ Read
Electronic
signature,
Read CFI
Query
Current CI State
Read
Array
(FFh)
WP
setup
(10/40h)
EFP Quad-EFP
Setup Setup
(3)(4)
Erase
Suspend Register
(B0h) (70h)
Status
(2)
(3)(4)
Register
(3)(4)
(5)
(30h)
(75h)
(35h, 56h)
(20h)
(50h)
(90h, 98h)
(D0h)
Setup
EFP Busy
Verify
Ready (error)
EFP Busy
(6)
Ready (error)
EFP Busy
(6)
EFP Verify
(6)
Setup
Quad
Quad EFP Busy
Quad EFP Busy
EFP
(6)
Busy
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase
Controller, PS = program suspend, ES = erase suspend, IS = Illegal state.
2. At Power-Up, all banks are in read array mode. A Read Array command issued to a busy bank, results in undetermined
data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/EC is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/EC is busy or suspended.
6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block
Address is first EFP Address. Any other commands are treated as data.
112/117
M58WTxxxKT, M58WTxxxKB
Command interface state tables
(1)
Table 45. Command interface states - modify table, next output
(2)
Command Input
Erase Confirm
Block
Erase
Setup
Quad-
EFP
Setup
(75h)
Program/
Erase
Suspend Register
Read
Status
Read Electronic
signature, Read
CFI Query (90h,
98h)
Current CI State
Read DWP, QWP
Clear Status
Register
EFP
Setup
(30h)
P/E Resume,
Block Unlock
confirm, EFP
Confirm (D0h)
(3)
(4)(5)
(6)
Array
Setup
(4)(5)
(FFh) (35h, 56h)
(50h)
(B0h)
(70h)
(20h)
Program Setup
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
EFP Setup
EFP Busy
Status Register
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
OTP Busy
Ready
Status Register
Program Busy
Erase Busy
Status
Register Unchanged
Output
Array
Status Register
Output Unchanged
Electronic
Signature/CFI
Program/Erase
Suspend
Program Busy in
Erase Suspend
Program Suspend
in Erase Suspend
Illegal State
Output Unchanged
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase
Controller, IS = Illegal State, ES = Erase suspend, PS = Program suspend.
2. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in read array, Read Status Register, Read Electronic Signature or Read CFI Query mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued. The next
state does not depend on the bank’s output state.
3. At Power-Up, all banks are in read array mode. A Read Array command issued to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/EC is active, both cycles are ignored.
6. The Clear Status Register command clears the Status Register error bits except when the P/EC is busy or suspended.
113/117
Command interface state tables
M58WTxxxKT, M58WTxxxKB
(1)
Table 46. Command interface states - Lock table, next state
Command Input
Current CI State
Lock/CR
Setup
(60h)
OTP
Setup
(C0h)
Block Lock
Confirm
(01h)
Block Lock- Set CR EFP Exit,
Down Confirm Quad EFP
P/E. C.
Operation
Completed
Illegal
Command
(2)
(2)
(4)
(3)
Confirm (2Fh) (03h)
Exit
Ready
Lock/CR Setup
Setup
Lock/CR Setup OTP Setup
Ready (Lock error)
Ready
N/A
N/A
Ready
Ready (Lock error)
OTP Busy
OTP
Busy
IS in OTP busy
Setup
IS in OTP busy
OTP Busy
Ready
IS Ready
N/A
OTP Busy
Program Busy
Program Busy
Busy
IS in Program busy
IS in PS
Ready
IS in Program
busy
Program
Program busy
IS Ready
Suspend
IS in PS
Program Suspend
N/A
N/A
Program Suspend
Ready (error)
Setup
N/A
Busy
IS in Erase Busy
Erase Busy
Ready
IS Ready
IS in Erase Busy
Erase Busy
Erase
Lock/CR Setup IS in Erase
Suspend
Erase Suspend
N/A
N/A
in ES
Suspend
IS in ES
Setup
Busy
Erase Suspend
Program Busy in Erase Suspend
Program Busy in Erase Suspend
Program busy in ES
Program Suspend in Erase Suspend
IS in Program busy in ES
ES
Program
in Erase
Suspend
IS in Program
busy in ES
IS in ES
Suspend
IS in PS in ES
N/A
IS in PS in ES
Program Suspend in Erase Suspend
Erase Suspend
Lock/CR Setup in ES
Setup
Erase Suspend (Lock error)
Erase Suspend (Lock error)
(5)
N/A
N/A
Ready (error)
(5)
EFP
Busy
Verify
Setup
EFP Busy
EFP Verify
EFP Busy
N/A
(5)
(5)
EFP Verify
Ready
EFP Verify
Ready
N/A
(5)
Quad EFP Busy
QuadEFP
Quad EFP
Busy
(5)
Busy
Quad EFP Busy
Ready
Ready
(4)
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, P/E. C. = Program/Erase Controller, IS = Illegal state, ES = Erase suspend, PS = Program
suspend.
2. If the P/EC is active, both cycles are ignored.
3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
4. Illegal commands are those not defined in the command set.
5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block
Address is first EFP Address. Any other commands are treated as data.
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Command interface state tables
(1)
Table 47. Command interface states - lock table, next output
Command Input
Block Lock-
Current CI State
Lock/CR
Setup
(60h)
Block Lock
Confirm
(01h)
Set CR
Confirm
(03h)
EFP Exit,
P/E. C.
Operation
Completed
(2)
OTPSetup
(C0h)
Down
Confirm
(2Fh)
Illegal
Command
(2)
Quad EFP
(4)
(3)
Exit
Program Setup
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
Status Register
EFP Setup
EFP Busy
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Output
Unchanged
Status Register
Array
Status Register
Lock/CR Setup in
Erase Suspend
OTP Busy
Ready
Program Busy
Erase Busy
Output
Unchanged
Status Register
Output Unchanged
Array
Program/Erase
Suspend
Program Busy in
Erase Suspend
Program Suspend in
Erase Suspend
Illegal State
Output Unchanged
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, P/E. C. = Program/Erase Controller.
2. If the P/EC is active, both cycles are ignored.
3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
4. Illegal commands are those not defined in the command set.
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Revision history
M58WTxxxKT, M58WTxxxKB
Revision history
Table 48. Document revision history
Date
Revision
Changes
30-Jan-2008
20-Mar-2008
1
2
Initial release.
Applied Numonyx branding.
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M58WTxxxKT, M58WTxxxKB
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