NAND16GW3C2AN1E [NUMONYX]
8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory; 8/16千兆， 2112字节的页， 3 V电源供电，多层次，多平面， NAND闪存
| 型号： | NAND16GW3C2AN1E |
| 厂家： | 
NUMONYX B.V |
| 描述： | 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory |
| 文件： | 总58页 (文件大小：1398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND08GW3C2A
NAND16GW3C4A
8/16 Gbit, 2112 byte page,
3 V supply, multilevel, multiplane, NAND Flash memory
Features
■ High density multilevel cell (MLC) Flash
memory
– Up to 16 Gbit memory array
– Up to 512 Mbit spare area
– Cost-effective solutions for mass storage
applications
■ NAND interface
TSOP48 12 x 20 mm (N)
– x 8 bus width
– Multiplexed address/data
■ Supply voltage: V = 2.7 to 3.6 V
DD
■ Page size: (2048 + 64 spare) bytes
■ Block size: (256K + 8K spare) bytes
LGA52 12 x 17 mm (N)
■ Multiplane architecture
– Array split into two independent planes
– Program/erase operations can be
■ Data protection
performed on both planes at the same time
– Hardware program/erase locked during
power transitions
■ Page read/program
– Random access: 60 µs (max)
– Sequential access: 25 ns (min)
– Page program operation time: 800 µs (typ)
■ Development tools
– Error correction code models
– Bad block management and wear leveling
algorithm
■ Multipage program time (2 pages): 800 µs (typ)
– HW simulation models
■ Fast block erase
■ Data integrity
– Block erase time: 2.5 ms (typ)
– 10,000 program/erase cycles (with ECC)
– 10 years data retention
■ Multiblock erase time (2 blocks): 2.5 ms (typ)
■ Status register
®
■ ECOPACK packages available
■ Electronic signature
■ Serial number option
■ Chip enable ‘don’t care’
January 2008
Rev 2
1/58
www.numonyx.com
1
NAND08GW3C2A, NAND16GW3C2A
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB1, RB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
4.3
4.4
4.5
4.6
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
6.2
6.3
6.4
Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/58
NAND08GW3C2A, NAND16GW3C2A
6.5
6.6
6.7
6.8
6.9
Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Multiplane Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.12 SR5, SR4, SR3, SR2 and SR1 bits are reserved . . . . . . . . . . . . . . . . . . . 29
6.13 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
8
9
Concurrent operations and ERS on the NAND16GW3C2A . . . . . . . . . 32
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1
9.2
9.3
9.4
9.5
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.5.1
9.5.2
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10
11
12
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 38
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52
12.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/58
NAND08GW3C2A, NAND16GW3C2A
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14
15
4/58
NAND08GW3C2A, NAND16GW3C2A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Extended Read Status Register commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Program and erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . 38
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 54
LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 55
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5/58
NAND08GW3C2A, NAND16GW3C2A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 connections for NAND08GW3C2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TSOP48 connections for NAND16GW3C4A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ULGA52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Random Data Input during Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Block Erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Multiplane Block Erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 18. Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19. Sequential data output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 20. Sequential data output after Read AC waveforms (EDO mode). . . . . . . . . . . . . . . . . . . . . 46
Figure 21. Read Status Register AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22. Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23. Page Read operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 25. Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 26. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. Program/Erase Enable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 28. Program/Erase Disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 29. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 30. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 31. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 53
Figure 32. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 33. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 54
Figure 34. LGA52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6/58
NAND08GW3C2A, NAND16GW3C2A
Description
1
Description
The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the
NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A
and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The
NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently
using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD
power supply.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8
input/output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with ECC on). The device
also has hardware security features; a write protect pin is available to give hardware
protection against Program and Erase operations.
The devices feature an open-drain, ready/busy output that can be used to identify if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the ready/busy pins of several memories to be connected to a single pull-up resistor.
The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture
makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a
time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable “Don’t Care” feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the Read operation.
There is the option of a unique identifier (serial number), which allows the
NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an
NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more
details of this option contact your nearest Numonyx Sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm)
packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK
®
packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard
JESD97, the category of second level interconnect is marked on the package and on the
inner box label. The maximum ratings related to soldering conditions are also marked on the
inner box label.
The devices are shipped from the factory with block 0 always valid and the memory content
bits, in valid blocks, erased to ‘1’.
Refer to the list of available part numbers and to Table 24: Ordering information scheme for
information on how to order these options.
7/58
Description
Table 1.
NAND08GW3C2A, NAND16GW3C2A
Device summary
Timings
Operatin
gvoltage
Bus
width size
Page Block Memory
Random
access
time
Part number Density
Sequentia
l access program erase
time (min)
Page
Block Package
size
array
(VDD
)
(typ)
(typ)
(max)
128
pages x
4096
TSOP48
ULGA52
NAND08GW3
8 Gb
C2A
2048+ 256 K
64 + 8 K
bytes bytes
blocks
2.7 to
3.6 V
x 8
60 µs
25 ns
800 µs
2.5 ms
128
pages x
8192
TSOP48
ULGA52
NAND16GW3
16 Gb
C4A(1)
blocks
1. The NAND16GW3C2A is composed of two 8-Gbit dice.
Figure 1.
Logic block diagram
Address
register/counter
AL
NAND Flash
memory array
CL
W
E
P/E/R controller
high voltage
generator
Command
interface
logic
1
E
2
WP
R
Page buffer
Y decoder
Command register
Data register
Buffers
I/O
RB
RB
2
1
AI13296b
1. E2 and RB2 are only present in the NAND16GW3C4A.
8/58
NAND08GW3C2A, NAND16GW3C2A
Description
Figure 2.
Logic diagram
V
DD
E
E
1
I/O0 - I/O7 x8
2
R
NAND Flash
W
RB
1
AL
CL
RB
2
WP
V
SS
AI13632b
1. E2 and RB2 are only present in the NAND16GW3C4A.
Table 2.
Signal names
Signal
Function
Data input/outputs(1)
Direction
I/O0 - I/O7
CL
Input/output
Input
Command Latch Enable
Address Latch Enable
Chip Enable(2)
AL
Input
E1, E2
R
Input
Read Enable
Input
W
Write Enable
Input
WP
Write Protect
Input
RB1, RB2
VDD
VSS
Ready/Busy (open drain output)(2)
Output
Power supply
Ground
Power supply
Ground
NC
No connection
DU
Do not use
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of I/Os and control
signals.
2. E2 and RB2 are only present in the NAND16GW3C4A.
9/58
Description
NAND08GW3C2A, NAND16GW3C2A
Figure 3.
TSOP48 connections for NAND08GW3C2A
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
NAND Flash
V
V
12
13
37
36
DD
DD
V
V
SS
NC
SS
NC
NC
CL
AL
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI13633
10/58
NAND08GW3C2A, NAND16GW3C2A
Description
Figure 4.
TSOP48 connections for NAND16GW3C4A
NC
NC
1
48
NC
NC
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
RB2
RB1
R
E1
E2
NC
NC
NC
V
12
13
37
36
V
V
DD
DD
SS
NAND FLASH
V
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI13169
11/58
Description
Figure 5.
NAND08GW3C2A, NAND16GW3C2A
ULGA52 connections
0
1
2
3
4
5
6
7
8
OA
OB
NC
NC
NC
NC
A
B
C
NC
AL
CL
E
NC
1
1
2
V
V
DD
SS
CL
W
E
R
1
1
2
D
E
OC
NC
AL
R
NC
2
2
W
RB
2
RB
2
1
1
F
WP
V
SS
1
G
I/O0
I/O1
I/O2
I/O0
I/O2
V
I/O7
I/O6
I/O5
WP
2
2
2
1
2
2
2
2
H
J
I/O1
I/O3
V
I/O7
I/O5
V
1
1
I/O6
1
1
NC
NC
NC
OD
OE
OF
NC
NC
NC
K
L
1
1
I/O4
1
SS
M
N
SS
DD
I/O4
NC
I/O3
NC
2
2
AI13634
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of signals.
12/58
NAND08GW3C2A, NAND16GW3C2A
Memory array organization
2
Memory array organization
The memory array is comprised of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 128 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data, whereas the spare area is typically used to store software flags or bad block
identification.
The pages are split into a 2048-byte main area and a spare area of 64 bytes. Refer to
Figure 6: Memory array organization.
2.1
Bad blocks
The NAND08GW3C2A and NAND16GW3C2A devices may contain bad blocks, where the
reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block Information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 3: Valid blocks shows the minimum number of valid blocks in each device. The values
shown include both the bad blocks that are present when the device is shipped and the bad
blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management and Block Replacement
(refer to Section 9: Software algorithms).
(1)
Table 3.
Valid blocks
Density of device
Minimum
Maximum
8 Gbits
4016
8032
4096
8192
16 Gbits
1. The NAND16GW3C4A is composed of two 8-Gbit dice. The minimum number of valid blocks is 4096 for
each die.
13/58
Memory array organization
NAND08GW3C2A, NAND16GW3C2A
Figure 6.
Memory array organization
x8 bus width
Plane = 2048 blocks
Block = 128 Pages
Page = 2112 Bytes (2,048 + 64)
First Plane
Second Plane
Spare Area
Spare Area
Main Area
Main Area
Block
Page
8 bits
2048 Bytes
2048 Bytes
64
Bytes
64
Bytes
Page Buffer, 2112 Bytes
64
Page Buffer, 2112 Bytes
64
2,048 Bytes
2,048 Bytes
Bytes
Bytes
8 bits
2 Page Buffer, 2x 2112 Bytes
AI13170
14/58
NAND08GW3C2A, NAND16GW3C2A
Signal descriptions
3
Signal descriptions
See Figure 1: Logic block diagram, and Table 2: Signal names, for a brief overview of the
signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a Read
operation, or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
3.3
3.4
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E1, E2)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V , the device is selected. If Chip Enable goes
IL
High, v , while the device is busy, the device remains selected and does not go into standby
IH
mode.
E is only available on the NAND16GW3C4A.
2
3.5
3.6
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during Read operations. Data
is valid t
after the falling edge of R. The falling edge of R also increments the internal
RLQV
column address counter by one.
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
15/58
Signal descriptions
NAND08GW3C2A, NAND16GW3C2A
3.7
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted
Program or Erase operations. When Write Protect is Low, V , the device does not accept
IL
any Program or Erase operations.
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
3.8
Ready/Busy (RB1, RB2)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, V , a Read, Program or Erase operation is in progress. When
OL
the operation completes, Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the Ready/Busy signal
is Low, VOL.
RB is only available on the NAND16GW3C4A.
2
Refer to Section 12.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.9
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for operations (Read, Program and Erase).
3.10
VSS ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
16/58
NAND08GW3C2A, NAND16GW3C2A
Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section. See the summary in Table 4: Bus operations.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 16 and Table 20 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Five bus cycles are
required to input the addresses (refer to Table 5: Address insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 17 and Table 20 for details of the timings requirements.
4.3
4.4
Data Input
Data Input bus operations are used to input the data to be programmed. Data is only
accepted when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable
is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the Write Enable signal.
See Figure 18 and Table 20 for details of the timing requirements.
Data Output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
If the Read Enable pulse frequency is lower then 33 MHz (t
higher than 30 ns), the
RLRL
output data is latched on the rising edge of Read Enable signal (see Figure 19).
17/58
Bus operations
NAND08GW3C2A, NAND16GW3C2A
For higher frequencies (t
lower than 30 ns), the Extended Data Out (EDO) mode must
RLRL
be considered. In this mode, data output is valid on the input/output bus for a time of t
RLQX
after the falling edge of Read Enable signal (see Figure 20).
See Table 21 for details on the timings requirements.
4.5
Write Protect
Write Protect bus operations are used to protect the memory against Program or Erase
operations. When the Write Protect signal is Low the device does not accept Program or
Erase operations, therefore, the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
The memory enters Standby mode by driving Chip Enable, E, High. In Standby mode, the
device is deselected, outputs are disabled and power consumption is reduced.
Table 4.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7
Command input
Address input
Data input
VIL
VIL
VIL
VIL
X
VIL
VIH
VIL
VIL
X
VIH
VIL
VIL
VIL
X
VIH
VIH
VIH
Falling
X
Rising
Rising
Rising
VIH
X(1)
X
Command
Address
Data input
Data output
X
VIH
Data output
Write protect
Standby
X
X
VIL
VIH
X
X
X
X
VIL/VDD
X
1. WP must be VIH when issuing a program or erase command.
(1)
Table 5.
Address insertion
Bus Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
4th
5th
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
A11
A2
A1
A9
A0
A8
A10
A14
A22
A30
A19
A27
VIL
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A15
A13
A21
A29
A12
A20
A28
A23
A31(2)
1. Any additional address input cycles will be ignored.
2. A31 is valid only for the NAND16GW3C2A.
18/58
NAND08GW3C2A, NAND16GW3C2A
Bus operations
Table 6.
Address definitions
Address
Definition
A0 - A11
A12 - A18
A19 - A31
Column address
Page address
Block address
19/58
Command set
NAND08GW3C2A, NAND16GW3C2A
5
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
Program and Erase operations are imposed to maximize data security.
The commands are summarized in Table 7: Commands.
Table 7.
Commands
Bus write operations(1)
Commands
accepted
during busy
Command
1st cycle
2nd cycle
3rd cycle
4th cycle
Read
00h
05h
30h
E0h
–
–
–
–
Random Data Output
Page Program
80h
10h
–
–
(sequential input default)
Multiplane Page Program
Random Data Input
Block Erase
80h
85h
60h
60h
FFh
90h
70h
11h
–
81h
–
10h
–
D0h
60h
–
–
–
Multiplane Block Erase
Reset
D0h
–
–
–
Yes
Yes
Read Electronic Signature
Read Status Register
–
–
–
–
–
–
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
20/58
NAND08GW3C2A, NAND16GW3C2A
Device operations
6
Device operations
This section gives the details of the device operations.
6.1
Read Memory Array
At power-up the device defaults to Read mode. To enter Read mode from another mode the
Read command must be issued, see Table 7: Commands. Once a Read command is
issued, subsequent consecutive Read commands only require the confirm command code
(30h).
Once a Read command is issued, two types of operations are available: Random Read and
Page Read.
6.2
6.3
Random Read
Each time the Read command is issued, the first read is random-read.
Page Read
After the first random read access, the page data (2112 bytes) is transferred to the page
buffer in a time of t
(refer to Table 21 for value). Once the transfer is complete, the
WHBH
Ready/Busy signal goes High. The data can then be read out sequentially (from the
selected column address to last column address) by pulsing the Read Enable signal.
The device can output random data in a page, instead of the consecutive sequential data, by
issuing a Random Data Output command. The Random Data Output command can be used
to skip some data during a sequential data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command.The Random
Data Output command can be issued as many times as required within a page.
21/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
Figure 7.
Read operations
CL
E
W
AL
R
tBLBH1
30h
RB
I/O
Address Input
00h
Data Output (sequentially)
Command
Code
Command
Code
Busy
Ai11016
1. Highest address depends on device density.
22/58
NAND08GW3C2A, NAND16GW3C2A
Device operations
Figure 8.
Random data output
tBLBH1
(Read Busy time)
RB
Busy
R
Address
Inputs
Address
Inputs
30h
E0h
I/O
000h
05h
Data Output
Data Output
Cmd
Cmd
Cmd
Cmd
Code
Code
Code
Code
5 Add cycles
2Add cycles
Row Add 1,2,3 Col Add 1,2
Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08658b
6.4
Page Program
The Page Program operation is the standard operation to program data to the memory
array. Generally, data is programmed sequentially, however, the device does support
random input within a page.
The memory array is programmed by page, however, partial page programming is allowed
where any number of bytes (1 to 2112) can be programmed.
Only one consecutive partial Page Program operation is allowed on the same page. After
exceeding this a Block Erase command must be issued before any further Program
operations can take place in that page.
23/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
6.5
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block.
For Sequential Input, each Page Program operation comprises five steps:
1. One bus cycle is required to set up the Page Program (Sequential Input) command
(see Table 7).
2. Five bus cycles are then required to input the program address (refer to Table 5).
3. The data is loaded into the data registers.
4. One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R only starts if the data has been loaded in step 3.
5. The P/E/R controller then programs the data into the array.
6.6
Random Data Input
During a Sequential Input operation, the next sequential address to be programmed can be
replaced by a random address issuing a Random Data Input command. The following two
steps are required to issue the command:
1. One bus cycle is required to setup the Random Data Input command (see Table 7).
2. Two bus cycles are then required to input the new column address (refer to Table 5).
Random Data Input can be repeated as often as required in any given page.
Once the Program operation has started the Status Register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to ‘1’ that have not been successfully programmed to ‘0’.
During the Program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored. Once the Program operation has completed, the
P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the command interface.
Figure 9.
Page Program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
Data Input
10h
Address Inputs
80h
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai08659
24/58
NAND08GW3C2A, NAND16GW3C2A
Device operations
Figure 10. Random Data Input during Sequential Data Input
tBLBH2
(Program Busy time)
RB
I/O
Busy
Address
Inputs
Address
Inputs
80h
85h
10h
Data Intput
Data Input
70h
SR0
Cmd
Code
Cmd
Confirm
Code
Read Status Register
Code 2 Add cycles
5 Add cycles
Col Add 1,2
Row Add 1,2,3 Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08664
6.7
Multiplane Page Program
The devices support Multiplane Page Program, that allows the programming of two pages in
parallel, one in each plane.
A Multiplane Page Program operation requires two steps:
1. The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
–
–
–
One clock cycle to set up the Page Program command (see Section 6.5:
Sequential Input).
Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0).
One bus write cycle to issue the Page Program Confirm code. After this the device
is busy for a time of t
.
BLBH5
When the device returns to the ready state (Ready/Busy High), a Multiplane Page
Program Setup code must be issued, followed by the second page address (5
write cycles) and data. The address of the second page must be within the second
plane (A19=1), and A18 to A12 must be the address bits loaded during the first
address insertion.
25/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
2. The second step programs, in parallel, the two pages of data loaded into the data buffer
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
As for standard Page Program operations, the device supports Random Data Input during
both data loading phases.
Once the Multiplane Page Program operation has started, maintaining a delay of t
, the
BLBH5
Status Register can be read using the Read Status Register command. Once the Multiplane
Page Program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
If the Multiplane Page Program fails, an error is signaled on bit SR0 of the Status Register.
However, there is no way to identify for which page the program operation failed.
See Figure 11 for a description of Multiplane Page Program waveforms.
Figure 11. Multiplane Page Program
tBLBH5
tBLBH2
(Program Busy time)
RB
Busy
Busy
I/O
Data Input
11h
Data Input
10h
Address Inputs
A19=0
Address Inputs
A19=1
80h
81h
70h
SR0
Confirm
Code
Confirm
Code
Multiplane Page
Program Setup
code
Read Status Register
Page Program
Setup Code
ai13636
6.8
Block Erase
Erase operations are done one block at a time. An Erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An Erase operation consists of three steps (refer to Figure 12):
1. One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A31 are used; the other address inputs are ignored.
2. Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 6 for the block addresses of each device.
3. One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The Erase operation is initiated on the rising edge of write Enable, W, after the Confirm
command is issued. The P/E/R Controller handles Block Erase and implements the verify
process.
During the Block Erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
26/58
NAND08GW3C2A, NAND16GW3C2A
Device operations
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 12. Block Erase operation
tBLBH3
(Erase Busy time)
RB
I/O
Busy
Block Address
Inputs
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
6.9
Multiplane Block Erase
The Multiplane Block Erase operation allows erasing two blocks in parallel, one in each
plane. It consists of three steps (refer to Figure 13: Multiplane Block Erase operation):
1. Eight bus cycles are required to set up the Block Erase command and load the
addresses of the blocks to be erased. The Setup command, followed by the address of
the block to be erased, must be issued for each block. No dummy busy time is required
between the first and second block address insertion. As for Multiplane Page Program,
the address of the first and second page must be within the first plane (A19 = 0) and
second plane (A19 = 1), respectively.
2. One bus cycle is then required to issue the Multiplane Block Erase confirm command
and start the P/E/R controller.
If the Multiplane Block Erase fails, an error is signaled on bit SR0 of the status register.
However, there is no way to identify for which page the Multiplane Block Erase operation
failed.
Figure 13. Multiplane Block Erase operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
Block Address
Inputs
I/O
60h
60h
D0h
70h
SR0
A19=1
Confirm
Code
A19=0
Block Erase
Setup Code
Read Status Register
Block Erase
Setup Code
ai13637
27/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
6.10
Reset
The Reset command is used to reset the command interface and Status Register. If the
Reset command is issued during any operation, the operation is aborted. If it is a Program
or Erase operation that is being aborted, the contents of the memory locations being
modified are no longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued. Refer to Table 21 for the values.
6.11
Read Status Register
The device contains a Status Register that provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle a new Read command must be issued to
continue with a Page Read operation.
Refer to Table 8 which summarizes Status Register bits and should be read in conjunction
with the following text descriptions.
6.11.1
6.11.2
6.11.3
Write protection bit (SR7)
The write protection bit can identify if the device is protected or not. If the write protection bit
is set to ‘1’ the device is not protected and Program or Erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and Program or Erase operations are
not allowed.
P/E/R controller bit (SR6)
Status register bit SR6 acts as a P/E/R controller bit, which indicates whether the P/E/R
controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller
is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is
ready).
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ‘1’ when a Program or Erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’, the operation has completed successfully.
28/58
NAND08GW3C2A, NAND16GW3C2A
Device operations
6.12
SR5, SR4, SR3, SR2 and SR1 bits are reserved
Table 8.
Status Register bits
Name
Bit
Logic level
Definition
‘1’
‘0’
‘1’
‘0’
Not protected
Protected
SR7
Write protection
P/E/R C inactive, device ready
P/E/R C active, device busy
SR6
Program/erase/read controller
Reserved
SR5, SR4,
SR3, SR2, SR1
Don’t care
‘1’
‘0’
Error – operation failed
SR0
Generic error
No error – operation successful
6.13
Read Electronic Signature
The device contains a manufacturer code and device code. The following three steps are
required to read these codes:
1. One bus write cycle to issue the Read Electronic Signature command (90h)
2. One bus write cycle to input the address (00h)
3. Four bus read cycles to sequentially output the data (as shown in Table 9: Electronic
signature)
Table 9.
Electronic signature
Byte/word 1
Byte/word 2
Device code
Byte 3
Byte 4
Byte 5
Part number
Manufacturer
code
(see Table 10)
(see Table 11)
(see Table 12)
NAND08GW3C2A
20h
D3h
14h
A5h
6Ch
NAND16GW3C2A(1)
1. Each 8-Gbit die returns its own electronic signature.
29/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
Table 10. Electronic signature byte 3
I/O
Definition
Value
Description
0 0
0 1
1 0
1 1
1
2
4
8
I/O1-I/O0
Internal chip number
0 0
0 1
1 0
1 1
2-level cell
4-level cell
8-level cell
16-level cell
I/O3-I/O2
I/O5-I/O4
Cell type
0 0
0 1
1 0
1 1
1
2
4
8
Number of simultaneously
programmed pages
0
1
Not supported
Supported
Interleaved programming
between multiple devices
I/O6
I/O7
0
1
Not supported
Supported
Cache program
Table 11. Electronic signature byte 4
I/O
Definition
Value
Description
0 0
0 1
1 0
1 1
1 KBytes
2 Kbytes
4 Kbytes
8 Kbytes
Page size
I/O1-I/O0
(without spare area)
Spare area size
(byte/512 byte)
0
1
8
I/O2
16
0 0
1 0
0 1
1 1
30/50 ns
25 ns
Minimum sequential access
time
I/O7, I/O3
Reserved
Reserved
0 0
0 1
1 0
1 1
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
Block size
I/O5-I/O4
I/O6
(without spare area)
0
1
x8
Organization
x16
30/58
NAND08GW3C2A, NAND16GW3C2A
Table 12. Electronic signature byte 5
Device operations
Description
I/O
Definition
Value
I/O1 - I/O0
Reserved
0 0
0 0
0 1
1 0
1 1
1 Plane
2 Planes
4 Planes
8 Planes
I/O3 - I/O2
Plane number
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
64 Mbits
128 Mbits
256 Mbits
512 Mbits
1 Gb
Plane size
I/O6 - I/O4
(without spare area)
2 Gb
4 Gb
8 Gb
I/O7
Reserved
0
31/58
Concurrent operations and ERS on the NAND16GW3C2A
NAND08GW3C2A, NAND16GW3C2A
7
Concurrent operations and ERS on the
NAND16GW3C2A
The NAND16GW3C2A is composed by two 8-Gbit dice stacked together. This configuration
allows the device to support concurrent operations. This means that while performing an
operation in one die (Erase, Read, Program, etc.), another operation is possible in the other
die.
The standard Read Status Register (ERS) operation returns the status of the
NAND16GW3C2A device. To provide information on each 8-Gbit die, the NAND16GW3C2A
features an Extended Read Status Register command that allows to check independently
the status of each die.
The following steps are required to perform concurrent operations:
1. Select one of the two dice by setting the most significant address bit A31 to ‘0’ or ‘1’.
2. Execute one operation on this die.
3. Launch a concurrent operation on the other die.
4. Check the status of these operations by performing an Extended Read Status Register
operation.
All combinations of operations are possible except executing Read on both dice. This is due
to the fact that the input/output bus is common to both dice.
Refer to Table 13 for the description of the Extended Read Status Register command
sequence, and to Table 8. for the definition of the Status Register bits.
Table 13. Extended Read Status Register commands
Command
Address range
1 bus write cycle
Read 1st die status
Read 2nd die status
Address ≤ 0x7FFFFFFF
F1h
F2h
0x7FFFFFFF < Address ≤ 0xFFFFFFF
32/58
NAND08GW3C2A, NAND16GW3C2A
Data protection
8
Data protection
The device has hardware features to protect against Program and Erase operations. It
features a Write Protect, WP, pin, which protects the device against program and erase
operations. It is recommended to keep WP at V during power-up and power-down.
IL
9
Software algorithms
This section gives information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using
high voltage. Exposing the device to high voltage for extended periods can cause the oxide
layer to be damaged. For this reason, the number of program and erase cycles is limited
(see Table 15 for value). It is recommended to implement garbage collection, wear-leveling
and error correction code algorithms to extend the number of program and erase cycles and
to increase data retention.
To help integrate a NAND memory into an application Numonyx can provide a File System
OS Native reference software, which supports the basic commands of file management.
Contact the nearest Numonyx sales office for more details.
9.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st byte in the spare area
of the last page, does not contain FFh, is a bad block.
The bad block information must be read before any erase is attempted as the bad block
Information may be erased. For the system to be able to recognize the bad blocks based on
the original information it is recommended to create a bad block table following the flowchart
shown in Figure 14.
33/58
Software algorithms
NAND08GW3C2A, NAND16GW3C2A
9.2
NAND Flash memory failure modes
The NAND08GW3C2A and NAND16GW3C2A devices may contain bad blocks, where the
reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
To implement a highly reliable system, all the possible failure modes must be considered:
■
Program/erase failure
in this case, the block has to be replaced by copying the data to a valid block. These
additional bad blocks can be identified as attempts to program or erase them and will
give errors in the Status Register.
Because the failure of a Page Program operation does not affect the data in other
pages in the same block, the block can be replaced by re-programming the current data
and copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Section Figure
10.: Random Data Input during Sequential Data Input for more details.
■
Read failure
in this case, ECC correction must be implemented. To efficiently use the memory
space, it is recommended to recover single-bit errors in read by ECC, without replacing
the whole block.
Refer to Table 14 for the procedure to follow if an error occurs during an operation.
Table 14. Block failure
Operation
Procedure
Erase
Program
Read
Block replacement
Block replacement or ECC (with 4 bit/528 byte)
ECC (with 4 bit/528 byte)
34/58
NAND08GW3C2A, NAND16GW3C2A
Software algorithms
Figure 14. Bad block management flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
9.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page and
mark the previous page as invalid. After several updates it is necessary to remove invalid
pages to free some memory space.
To free this memory space and allow further program operations, it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 15).
Figure 15. Garbage collection
Old Area
New Area (After GC)
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
35/58
Software algorithms
NAND08GW3C2A, NAND16GW3C2A
9.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm, not all blocks get used at the same
rate. The wear-leveling algorithm ensures that equal use is made of all the available write
cycles for each block.
There are two wear-leveling levels:
1. First level wear-leveling, where new data is programmed to the free blocks that have
had the fewest write cycles
2. Second level wear-leveling, where long-lived data is copied to another block so that the
original block can be used for more frequently changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
36/58
NAND08GW3C2A, NAND16GW3C2A
Software algorithms
9.5
Hardware simulation models
9.5.1
Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and, therefore,
allow software to be developed before hardware.
9.5.2
IBIS simulations models
I/O buffer information specification (IBIS) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.
These models provide information such as AC characteristics, rise/fall times, and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
37/58
Program and erase times and endurance cycles
NAND08GW3C2A, NAND16GW3C2A
10
Program and erase times and endurance cycles
Table 15 shows the program and erase times and the number of program/erase cycles per
block.
Table 15. Program and erase times and program erase endurance cycles
NAND08GW3C2A, NAND16GW3C2A
Parameters
Unit
Min
Typ
Max
Page program time
800
2.5
2000
3
µs
Block erase time
ms
Program/erase cycles (per block (with ECC)
Data retention
10,000
10
cycles
years
38/58
NAND08GW3C2A, NAND16GW3C2A
Maximum ratings
11
Maximum ratings
Stressing the device above the ratings listed in Table 16: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 16. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature under bias
Storage temperature
Input or output voltage
Supply voltage
– 50
– 65
– 0.6
– 0.6
125
150
4.6
4.6
°C
°C
V
(1)
VIO
VDD
V
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
39/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
12
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristics
tables are derived from tests performed under the measurement conditions summarized in
Table 17: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 17. Operating and ac measurement conditions
NAND08GW3C2A,
NAND16GW3C2A
Parameter
Units
Min
Max
Supply voltage (VDD
)
2.7
0
3.6
70
85
V
°C
°C
pF
V
Ambient temperature (TA)
–40
Load capacitance (CL) (1 TTL GATE and CL)
Input pulses voltages
50
0.4
2.4
Input and output timing ref. voltages
Output circuit resistor Rref
1.5
8.35
5
V
kΩ
ns
Input rise and fall times
(1)
Table 18. Capacitance
Symbol
Parameter
Test condition
Typ
Max
Unit
CIN
Input capacitance
VIN = 0 V
10
pF
pF
Input/output
capacitance
CI/O
VIL = 0 V
10
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
40/58
NAND08GW3C2A, NAND16GW3C2A
Table 19. DC characteristics
DC and AC parameters
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
read
IDD1
-
15
30
mA
E=VIL, OUT = 0 mA
I
Operating
current
IDD2
IDD3
Program
Erase
-
-
-
-
15
15
30
30
1
mA
mA
mA
I
Standby current (TTL)
E=VIH, WP=0/VDD
DD4
E=VDD-0.2,
WP=0/VDD
IDD5
Standby current (CMOS)
-
10
50
µA
ILI
ILO
Input leakage Current
Output leakage Current
Input high voltage
VIN= 0 to 3.6V
VOUT= 0 to 3.6V
-
-
-
-
-
±10
±10
µA
µA
V
VIH
2.0
-0.3
2.4
-
-
VDD+0.3
0.8
VIL
Input low voltage
-
-
V
VOH
VOL
Output high voltage level
Output low voltage level
Output low current (RB)
IOH = -400µA
IOL = 2.1mA
VOL = 0.4V
-
-
V
-
0.4
V
IOL (RB)
8
10
mA
41/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Table 20. AC characteristics for command, address, data input
Symbol
Alt. symbol
Parameter
Value
Unit
tALLWH
tALHWH
tCLHWH
tCLLWH
tDVWH
tELWH
Address Latch Low to Write Enable High
Address Latch High to Write Enable High
Command Latch High to Write Enable High
Command Latch Low to Write Enable High
Data Valid to Write Enable High
tALS
AL setup time
CL setup time
Min
Min
12
ns
tCLS
12
ns
tDS
tCS
Data setup time Min
12
20
ns
ns
Chip Enable Low to Write Enable High
Write Enable High to Address Latch High
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
E setup time
Min
tWHALH
tWHALL
tWHCLH
tWHCLL
tWHDX
tWHEH
tWHWL
tWLWH
tWLWL
tALH
AL hold time
Min
5
5
ns
ns
tCLH
CL hold time
Min
tDH
tCH
tWH
tWP
tWC
Data hold time
E hold time
Min
Min
5
ns
ns
ns
ns
ns
5
W High hold time Min
W pulse width Min
Write cycle time Min
10
12
25
42/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Table 21. AC characteristics for operations
Alt.
Value
Unit
Min Typ Max
Symbol
Parameter
Symbol
tALLRL1
tALLRL2
tBHRL
Read Electronic Signature
Read cycle
10
10
20
ns
ns
ns
µs
Address Latch Low to Read Enable
Low
tAR
tRR
Ready/Busy High to Read Enable Low
tBLBH1
tBLBH2
tBLBH3
Read Busy time
Program Busy time
Erase Busy time
60
tPROG
tBERS
Ready/Busy Low to Ready/Busy High
2000 µs
3
5
ms
µs
µs
µs
Reset Busy time, during ready
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
5
tBLBH4
tRST
10
500 µs
tBLBH5
tCLLRL
tDZRL
tEHQZ
tELQV
tRHRL
tEHQX
tRHQX
tRLQX
tRHQZ
tRLRH
tRLRL
tCBSY
tCLR
tIR
Dummy Busy Time for Multiplane operations
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
1
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
10
0
tCHZ
tCEA
tREH
tCOH
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
30
25
Read Enable High to Read Enable Low Read Enable High Hold time 10
Chip Enable High to Output Hold
15
15
5
tRHOH Read Enable High to Output Hold
tRLOH Read Enable Low to Output Hold (EDO Mode)
tRHZ
tRP
Read Enable High to Output Hi-Z
100 ns
Read Enable Low to Read Enable High
Read Enable Pulse Width
Read Cycle time
12
25
ns
ns
tRC
Read Enable Low to Read Enable Low
Read Enable Access time
Read ES Access time(1)
Read Busy time
tRLQV
tREA
Read Enable Low to Output Valid
20
60
ns
tWHBH
tWHBL
tWHRL
tR
Write Enable High to Ready/Busy High
µs
tWB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
100 ns
tWHR
tADL
80
ns
ns
ns
ns
(2)
tWHWH
Last Address latched on Data Loading Time during Program operations 70
(3)
tVHWH
100
tWW
Write Protection time
100
(3)
tVLWH
1. ES = Electronic Signature.
2. tWHWH is the delay from Write Enable rising edge during the final address cycle to Write Enable rising edge during the first
data cycle.
3. WP High to W High during Program/Erase Enable operations.
43/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Figure 16. Command latch AC waveforms
CL
tCLHWH
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWH
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai12470b
Figure 17. Address latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tWLWL
tWLWL
tWLWL
tELWH
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 5
Adrress
cycle 1
ai12471
44/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 18. Data input latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai12472
1. The last data input is the 2112th.
Figure 19. Sequential data output after Read AC waveforms
tRLRL
(Read Cycle time)
E
tEHQX
tEHQZ
tRHRL
(R High Holdtime)
R
tRHQZ
tRHQZ
(2)
tRHQX
tRLQV
tRLQV
tRLQV
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai13174
1. CL = Low, AL = Low, W = High.
2. tRHQX is applicable for frequencies lower than 33 MHz (i.e. tRLRL higher than 30 ns).
45/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Figure 20. Sequential data output after Read AC waveforms (EDO mode)
tRLRL
E
tEHQX
tEHQZ
tRLRH
tRLQV
tRHRL
R
tRHQZ
(2)
tELQV
tRLQX
tRLQV
tRHQX
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH
.
2. tRLQX is applicable for frequencies higher than 33 MHz (i.e. tRLRL lower than 30 ns).
Figure 21. Read Status Register AC waveform
tCLLRL
CL
tWHCLL
tCLHWH
tWHEH
E
tELWH
tWLWH
W
R
tELQV
tEHQZ
tWHRL
tEHQX
tDZRL
tWHDX
tRHQZ
tRHQX
tDVWH
(Data Setup time)
tRLQV
(Data Hold time)
Status Register
Output
I/O
70h or 7Bh
ai13177
46/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 22. Read electronic signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
00h
Byte1
Byte2
Byte3
Byte4
Byte5
Man.
code
Device
code
Read Electronic 1st Cycle
see Note.1
Signature
Command
Address
ai13178
1. Refer to Table 9 for the values of the manufacturer and device codes, and to Table 10, Table 11, and Table 12 for the
information contained in byte 3, byte 4, and byte 5.
47/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Figure 23. Page Read operation AC waveform
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
Data
N
Data
N+1
Data
N+2
Data
Last
Add.N Add.N Add.N Add.N
cycle 1 cycle 2 cycle 3 cycle 4
Add.N
cycle 5
I/O
30h
00h
Data Output
from Address N to Last Byte or Word in Page
Command Address N Input
Code
Busy
ai13638
48/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 24. Page Program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tWHWH
tBLBH2
(Program Busy time)
AL
R
Add.N Add.N
cycle 4 cycle 5
Add.N
Add.N
Add.N
cycle 3
I/O
RB
80h
Last
N
10h
70h
SR0
cycle 1 cycle 2
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai13639
49/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Figure 25. Block Erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
AL
R
tBLBH3
tWHBL
(Erase Busy time)
Add.
Add.
Add.
I/O
RB
70h
SR0
60h
D0h
cycle 1 cycle 2
cycle 3
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038c
Figure 26. Reset AC waveform
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
50/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 27. Program/Erase Enable waveform
W
tVHWH
WP
RB
I/O
80h
10h
ai12477
Figure 28. Program/Erase Disable waveform
W
tVLWH
WP
High
RB
I/O
80h
10h
ai12478
51/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
12.1
Ready/Busy signal electrical characteristics
Figure 30, Figure 29 and Figure 31 show the electrical characteristics for the Ready/Busy
signal. The value required for the resistor R can be calculated using the following equation:
P
(
–
)
V
V
DDmax
OLmax
+ I
R min= -------------------------------------------------------------
P
I
L
OL
So,
3.2V
R min= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R
L
P
max is determined by the maximum value of t .
r
Figure 29. Ready/Busy AC waveform
ready V
DD
V
OH
V
OL
busy
t
t
r
f
AI07564B
Figure 30. Ready/Busy load circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
52/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 31. Resistor value versus waveform timings for Ready/Busy signal
V
= 3.3 V, C = 50 pF
L
DD
200
150
100
4
3
2
1
200
2.4
150
1.2
100
0.8
50
0
50
0.6
1.8
1.8
1.8
1.8
1
2
3
4
R
(KΩ)
P
t
t
ibusy
f
r
a
1. T = 25°C.
12.2
Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
Low (V ) to guarantee hardware protection during power transitions as shown in Figure 32.
IL
Figure 32. Data protection
Nominal Range
V
DD
V
LKO
Locked
Locked
W
Ai11086
53/58
Package mechanical
NAND08GW3C2A, NAND16GW3C2A
13
Package mechanical
This section contains mechanical data for the packages.
Figure 33. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 22. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
5°
L1
a
0°
5°
0°
54/58
NAND08GW3C2A, NAND16GW3C2A
Package mechanical
Figure 34. LGA52 12 x 17 mm, 1 mm pitch, package outline
D
D2
D1
FD1
FD
FE1
FE
BALL "A1"
eE1
E
E2 E1
e
ddd
e
b1 b2
A2
A
LGA-9G
Table 23. LGA52 12 x 17 mm, 1 mm pitch, package mechanical data
millimeters
Symbol
inches
Typ
Min
Max
Typ
Min
Max
A
A2
b1
0.650
0.650
0.750
1.050
12.100
0.0256
0.0256
0.0295
0.0413
0.4764
0.700
1.000
0.650
0.950
0.0276
0.0394
0.4724
0.2362
0.3937
0.0256
0.0374
0.4685
b2
D
12.000
6.000
11.900
D1
D2
ddd
E
10.000
0.100
0.0039
0.6732
17.000
12.000
13.000
1.000
2.000
3.000
1.000
2.500
2.000
16.900
17.100
0.6693
0.4724
0.5118
0.0394
0.0787
0.1181
0.0394
0.0984
0.0787
0.6654
E1
E2
e
–
–
–
–
–
–
–
–
eE1
FD
FD1
FE
FE1
55/58
Ordering information
NAND08GW3C2A, NAND16GW3C2A
14
Ordering information
Table 24. Ordering information scheme
Example:
NAND08G W 3 C 2
A
N 1
E
Device type
NAND Flash memory
Density
08G = 8 Gbits
16G = 16 Gbits
Operating voltage
W = VDD = 2.7 to 3.6 V
Bus width
3 = x 8
Family identifier
C = 2112 bytes Page MLC
Device options
2 = Chip Enable Don't Care Enabled
4 = Chip Enable Don't Care Enabled with 2 Chip
Enable and 2 Ready/Busy signals
Product version
A = First version
Package
N = TSOP48 12 x 20 mm
ZL = ULGA52 12 x 17 mm
Temperature range
1 = 0 to 70 °C
6 = −40 to 85 °C
Option
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape & reel packing
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
‘1’. For further information on any aspect of this device, please contact your nearest
Numonyx Sales Office.
56/58
NAND08GW3C2A, NAND16GW3C2A
Revision history
15
Revision history
Table 25. Document revision history
Date
Revision
Changes
22-Dec-2006
0.1
Initial release.
– Changed throughout the document "NAND16GW3C2A" to
"NAND16GW3C4A.
– Listed throughout document the details relating to the two 8-Gbit
dice, the two Chip Enable, and two Ready/Busy signals in the
NAND16GZ3C4A, which required changes in several figures and
tables.
– Added power-up and power-down minimum recovery time
information in Section 3.8: Ready/Busy (RB1, RB2).
11-Jun-2007
1
– Added program and read information in Section Table 14.: Block
failure.
– Modified page program time parameters and program/erase cycles
parameters in Section Table 15.: Program and erase times and
program erase endurance cycles.
– Modified AC characteristics in Section Table 21.: AC
characteristics for operations.
04-Jan-2008
2
Applied Numonyx branding.
57/58
NAND08GW3C2A, NAND16GW3C2A
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
58/58
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