NAND256W3A0CN6E [NUMONYX]
Flash, 32MX8, 35ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48;
| 型号： | NAND256W3A0CN6E |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 32MX8, 35ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 光电二极管 内存集成电路 |
| 文件： | 总58页 (文件大小：1409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND128-A NAND256-A
128-Mbit or 256-Mbit, 528-byte/264-word page,
3 V, NAND flash memories
Features
■ High density NAND flash memories
– Up to 256-Mbit memory array
– Up to 32-Mbit spare area
– Cost effective solutions for mass storage
applications
TSOP48 12 x 20 mm
■
NAND interface
– x8 or x16 bus width
– Multiplexed address/ data
– Pinout compatibility for all densities
FBGA
■ Supply voltage
VFBGA55 8 x 10 x 1 mm
– V = 2.7 to 3.6 V
DD
■ Page size
– x8 device: (512 + 16 spare) bytes
– x16 device: (256 + 8 spare) words
■ Hardware data protection
■ Block size
– Program/erase locked during power
transitions
– x8 device: (16 K + 512 spare) bytes
– x16 device: (8 K + 256 spare) words
■ Data integrity
■ Page read/program
– 100,000 program/erase cycles
– 10 years data retention
– Random access: 12 µs (max)
– Sequential access: 50 ns (min)
– Page program time: 200 µs (typ)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
■ Copy back program mode
– Fast page copy without external buffering
■ Development tools
■ Fast block erase
– Error correction code software and
hardware models
– Block erase time: 2 ms (typical)
■ Status register
– Bad blocks management and wear leveling
algorithms
■ Electronic signature
– File system OS native reference software
– Hardware simulation models
■ Chip enable ‘don’t care’
– Simple interface with microcontroller
■ Serial number option
August 2008
Rev 15
1/58
www.numonyx.com
1
Contents
NAND128-A, NAND256-A
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
4.2
4.3
4.4
4.5
4.6
Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
6.2
6.3
Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/58
NAND128-A, NAND256-A
Contents
6.4
6.5
6.6
6.7
Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7.1
6.7.2
6.7.3
Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
7.2
7.3
7.4
7.5
7.6
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6.1
7.6.2
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 35
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.1 Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11
12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A Hardware interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3/58
List of tables
NAND128-A, NAND256-A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
NAND128-A and NAND256-A device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 35
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 50
VFBGA55 8 x 10 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data . . . . . . 52
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4/58
NAND128-A, NAND256-A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VFBGA55 connections, x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . 11
VFBGA55 connections, x16 devices (top view through package) . . . . . . . . . . . . . . . . . . . 12
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Read (A, B, C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 24. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 25. Read status register AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. Page read A/read B operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 28. Read C operation, one page AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 29. Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 30. Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 31. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 32. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 33. Ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 34. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 48
Figure 35. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 36. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 50
Figure 37. VFBGA55 8 x 10 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline. . . . . . . . . 51
Figure 38. Connection to microcontroller, without glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 39. Connection to microcontroller, with glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 40. Building storage modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5/58
Description
NAND128-A, NAND256-A
1
Description
The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND cell technology, referred to as the SLC small page
family. The devices are either 128 Mbits or 256 Mbits and operate with 3 V voltage supply.
The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare)
depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased up to 100,000 cycles. To extend the lifetime of
NAND flash devices it is strongly recommended to implement an error correction code
(ECC). A Write Protect pin is available to provide hardware protection against program and
erase operations.
The devices feature an open-drain ready/busy output that identifies if the program/erase/
read (P/E/R) controller is currently active. The use of an open-drain output allows the
Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page program operation fails, the data can be programmed in another page without having
to resend the data to be programmed.
Table 1 lists the individual part numbers of the device.
Table 1.
NAND128-A and NAND256-A device summary
Reference
Part Number
NAND128-A
NAND128W3A
NAND256W3A
NAND256W4A
NAND256-A(1)
1. x16 organization only available for MCP.
The devices are available in the following packages:
■
■
TSOP48 12 x 20 mm for all products
VFBGA55 (8 x 10 x 1 mm, 6 x 8 ball array, 0.8 mm pitch)
and in two different versions:
■
No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
■
With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are simultaneously active as Chip Enable transitions during
latency do not stop read operations. Program and erase operations are not interrupted
by Chip Enable transitions.
A serial number (unique identifier) option enables each device to be uniquely identified. The
serial number options is subject to an NDA (non-disclosure agreement) and is not described
in this datasheet. For more details of this option contact your nearest Numonyx sales office.
6/58
NAND128-A, NAND256-A
Description
For information on how to order these options refer to Table 23: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits in valid blocks erased to ’1’.
See Table 2 for all the devices available in the family.
Table 2.
Product description
Timings
32 pages
x 1024
blocks
128
Mbits
512+16 16K+51
bytes 2 bytes
NAND128-A
NAND128W3A
x8
TSOP48
512+16 16K+51
bytes 2 bytes
2.7 to 3.6V 12 µs
50 ns
200 µs
2 ms
NAND256W3A
NAND256W4A
x8
32 pages
x 2048
blocks
256
Mbits
TSOP48
VFBGA55
(1)
NAND256-A
256+8 8K+256
words words
x16
1. x16 organization only available for MCP.
Figure 1.
Logic diagram
V
DD
I/O8-I/O15, x16
E
I/O0-I/O7, x8/x16
R
W
NAND flash
RB
AL
CL
WP
V
SS
AI07557C
7/58
Description
NAND128-A, NAND256-A
Table 3.
Symbol
Signal names
Function
Data input/outputs for x16 devices
Direction
I/O8-15
I/O0-7
I/O
Data input/outputs, address inputs, or command inputs for x8
and x16 devices
I/O
AL
CL
E
Address Latch Enable
Command Latch Enable
Chip Enable
Input
Input
Input
Input
Output
Input
Input
–
R
Read Enable
RB
W
Ready/Busy (open-drain output)
Write Enable
WP
VDD
VSS
NC
DU
Write Protect
Supply voltage
Ground
–
Not connected internally
Do not use
–
–
Figure 2.
Logic block diagram
Address
register/counter
AL
NAND flash
memory array
CL
W
P/E/R controller,
high voltage
generator
Command
interface
logic
E
WP
R
Page buffer
Y decoder
Command register
I/O buffers & latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI07561c
8/58
NAND128-A, NAND256-A
Figure 3.
Description
TSOP48 connections, x8 devices
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
NAND flash
(x8)
V
12
13
37
36
V
V
DD
DD
SS
V
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI07585C
9/58
Description
NAND128-A, NAND256-A
Figure 4.
TSOP48 connections, x16 devices
NC
NC
NC
NC
NC
NC
RB
R
1
48
V
SS
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
E
NC
NC
NC
NAND flash
(x16)
V
12
13
37
36
V
DD
NC
DD
V
SS
NC
NC
NC
NC
CL
AL
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
W
WP
NC
NC
NC
NC
NC
24
25
V
SS
AI07559C
10/58
NAND128-A, NAND256-A
Figure 5.
Description
VFBGA55 connections, x8 devices (top view through package)
1
2
3
4
5
6
7
8
DU
DU
A
B
DU
C
WP
AL
E
W
RB
V
SS
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
G
H
J
NC
NC
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
M
AI09366b
11/58
Description
NAND128-A, NAND256-A
Figure 6.
VFBGA55 connections, x16 devices (top view through package)
1
2
3
4
5
6
7
8
A
B
DU
DU
DU
C
WP
AL
E
W
RB
V
SS
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G
H
J
NC
NC
I/O5
I/O12
I/O7
I/O14
I/O6
I/O13
I/O8
I/O0
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
V
DD
V
I/O15
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
M
AI09365b
12/58
NAND128-A, NAND256-A
Memory array organization
2
Memory array organization
The memory array comprises NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array stores
data, whereas the spare area is typically used to store error correction codes, software flags
or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 bytes each and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 7: Memory array organization.
2.1
Bad blocks
The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 2.1: Bad blocks for
more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4.
Valid blocks
Density of device
Minimum
Maximum
256 Mbits
128 Mbits
2008
1004
2048
1024
13/58
Memory array organization
NAND128-A, NAND256-A
Figure 7.
Memory array organization
x8 DEVICES
x16 DEVICES
Block = 32 pages
Block = 32 pages
Page = 528 bytes (512+16)
Page = 264 words (256+8)
Spare area
Spare area
1st half page 2nd half page
(256 bytes) (256 bytes)
Main area
Block
Page
Block
Page
8 bits
16 bits
256 words
512 bytes
16
bytes
8
words
Page buffer, 264 words
8
Page buffer, 512 bytes
16
256 words
words
512 bytes
16 bits
AI07587
bytes
8 bits
14/58
NAND128-A, NAND256-A
Signal descriptions
3
Signal descriptions
See Figure 1: Logic diagram and Table 3: Signal names for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/Outputs 0 to 7 input the selected address, output the data during a read operation or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
3.4
3.5
Address Latch Enable (AL)
Address Latch Enable activates the latching of the address inputs in the command interface.
When AL is high, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V , the device is selected.
IL
While the device is busy programming or erasing, Chip Enable transitions to High (V ) are
IH
ignored and the device does not go into standby mode.
While the device is busy reading:
■
■
the Chip Enable input should be held Low during the whole busy time (t
devices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
) for
BLBH1
for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the busy time (t
go into standby mode.
) will not interrupt the read operation and the device will not
BLBH1
15/58
Signal descriptions
NAND128-A, NAND256-A
3.6
Read Enable (R)
Read Enable, R, controls the sequential data output during read operations. Data is valid
t
after the falling edge of R. The falling edge of R also increments the internal column
RLQV
address counter by one.
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
3.8
3.9
Write Protect (WP)
The Write Protect pin is an input that provides hardware protection against unwanted
program or erase operations. When Write Protect is Low, V , the device does not accept
any program or erase operations.
IL
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, V , a read, program or erase operation is in progress. When the
OL
operation completes Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
Refer to the Section 10.1: Ready/busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V is below the V
threshold
LKO
DD
(see paragraph Figure 35: Data protection) to protect the device from any involuntary
program/erase operations during power-transitions.
Each device in a system should have V decoupled with a 0.1 µF capacitor. The PCB track
DD
widths should be sufficient to carry the required program and erase currents
16/58
NAND128-A, NAND256-A
Signal descriptions
3.11
VSS ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
17/58
Bus operations
NAND128-A, NAND256-A
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations for a summary.
4.1
Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low,
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 input commands.
See Figure 21: Command Latch AC waveforms and Table 14: Program, erase times and
program erase endurance cycles for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory address. Three bus cycles are required to
input the addresses (refer to Tables Table 6: Address insertion, x8 devices and Table 7:
Address insertion, x16 devices).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 input addresses.
See Figure 22: Address Latch AC waveforms and Table 14: Program, erase times and
program erase endurance cycles for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal and is input sequentially using the Write Enable signal.
See Figure 23: Data Input Latch AC waveforms and Table 14: Program, erase times and
program erase endurance cycles and Table 20: AC characteristics for operations for details
of the timings requirements.
18/58
NAND128-A, NAND256-A
Bus operations
4.4
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 24: Sequential data output after read AC waveforms and Table 20: AC
characteristics for operations for details of the timings requirements.
4.5
4.6
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, therefore, the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
Standby
When Chip Enable is High the memory enters standby mode: the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7 I/O8 - I/O15(1)
Command input
Address input
Data input
VIL
VIL
VIL
VIL
X
VIL
VIH
VIL
VIL
X
VIH
VIL
VIL
VIL
X
VIH
VIH
VIH
Falling
X
Rising
Rising
Rising
VIH
X(2)
X
Command
Address
X
X
X
Data input
Data input
Data output
X
Data output Data output
Write protect
Standby
X
VIL
X
X
X
X
X
VIH
X
X
X
X
1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
(1)(2)
Table 6.
Address insertion, x8 devices
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
A7
A6
A5
A4
A3
A2
A1
A0
A9
A16
A24
A15
A23
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
A17
1. A8 is set Low or High by the 00h or 01h command (see Section 6.1: Pointer operations).
2. Any additional address input cycles are ignored.
19/58
Bus operations
NAND128-A, NAND256-A
(1)(2)(3)
I/O4
Table 7.
Address insertion, x16 devices
I/O8-
Bus
Cycle
I/O7
I/O6
I/O5
I/O3
I/O2
I/O1
I/O0
I/O15
1st
2nd
3rd
X
X
X
A7
A6
A5
A4
A3
A2
A1
A0
A9
A16
A24
A15
A23
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
A17
1. A8 is ’don’t care’ in x16 devices.
2. Any additional address input cycles are ignored.
3. The 01h command is not used in x16 devices.
Table 8.
Address
Address definitions
Definition
A0 - A7
A9 - A26
A9 - A13
A14 - A26
A8
Column address
Page address
Address in block
Block address
A8 is set Low or High by the 00h or 01h command, and is ’don’t care’ in x16 devices
20/58
NAND128-A, NAND256-A
Command set
5
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 9.
Table 9.
Commands
Command
Bus write operations(1)(2)
Command accepted
during busy
1st cycle
2nd cycle
3rd cycle
Read A
Read B
Read C
00h
01h(2)
50h
–
–
–
–
–
–
Read Electronic Signature
Read Status Register
Page Program
90h
–
–
70h
–
–
Yes
Yes
80h
10h
8Ah
D0h
–
–
Copy Back Program
Block Erase
00h
10h
–
60h
Reset
FFh
–
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence is ignored by the device.
21/58
Device operations
NAND128-A, NAND256-A
6
Device operations
6.1
Pointer operations
As the NAND flash memories contain two different areas for x16 devices and three different
areas for x8 devices (see Figure 8) the read command codes (00h, 01h, 50h) act as pointers
to the different areas of the memory array (they select the most significant column address).
The Read A and Read B commands act as pointers to the main memory area. Their use
depends on the bus width of the device.
■
In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the
main area), that is words 0 to 255.
■
In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the
main area), that is bytes 0 to 255, and the Read B command (01h) sets the pointer to
Area B (the second half of the main area), that is bytes 256 to 511.
In both the x8 and x16 devices the Read C command (50h) acts as a pointer to Area C (the
spare memory area), that is bytes 512 to 527 or words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been executed in Area B the pointer
returns automatically to Area A.
The pointer operations can also be used before a program operation, that is the appropriate
code (00h, 01h or 50h) can be issued before the program command 80h is issued (see
Figure 9: Pointer operations for programming).
Figure 8.
Pointer operations
x8 Devices
x16 Devices
Area A
(00h)
Area B
(01h)
Area C
(50h)
Area A
(00h)
Area C
(50h)
Bytes 512
-527
Words 256
-263
Bytes 0- 255
Bytes 256-511
Words 0- 255
A
B
C
Page Buffer
A
C
Page Buffer
Pointer
(00h,01h,50h)
Pointer
(00h,50h)
AI07592
22/58
NAND128-A, NAND256-A
Figure 9.
Device operations
Pointer operations for programming
AREA A
10h
Address
Inputs
Address
Inputs
80h
I/O
00h
Data Input
80h
00h
Data Input
10h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA B
Address
Inputs
Address
Inputs
80h
I/O
01h
Data Input
10h
80h
01h
Data Input
10h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA C
Address
Inputs
Address
Inputs
80h
I/O
50h
Data Input
10h
80h
50h
Data Input
10h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
ai07591
6.2
Read memory array
Each operation to read the memory area starts with a pointer operation as shown in the
Section 6.1: Pointer operations. Once the area (main or spare) has been selected using the
Read A, Read B or Read C commands three bus cycles are required to input the address of
the data to be read.
The device defaults to Read A mode after power-up or a reset operation.
When reading the following spare area addresses:
■
■
A0 to A3 (x8 devices)
A0 to A2 (x16 devices)
set the start address of the spare area, while the following addresses are ignored:
■
■
A4 to A7 (x8 devices)
A3 to A7 (x16 devices)
Once the Read A or Read C commands have been issued they do not need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is effective for only one operation; once an operation has been executed
in Area B the pointer returns automatically to Area A. Another Read B command is required
to start another read operation in Area B.
Once a read command is issued two types of operations are available: random read and
page read.
■
Random read
Each time the command is issued the first read is random read.
Page read
■
After the random read access the page data is transferred to the page buffer in a time
of t
(refer to Table 20: AC characteristics for operations for the value). Once the
WHBH
transfer is complete the Ready/Busy signal goes High. The data can then be read out
sequentially (from the selected column address to the last column address) by pulsing
the Read Enable signal.
■
Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed
23/58
Device operations
NAND128-A, NAND256-A
and Chip Enable remains Low, then the next page is automatically loaded into the page
buffer and the read operation continues. A sequential row read operation can only be
used to read within a block. If the block changes a new read command must be issued.
Refer to Figure 12: Sequential row read operations and Figure 13: Sequential row read
block diagrams for details about sequential row read operations. To terminate a
sequential row read operation, set to High the Chip Enable signal for more than t
.
EHEL
Sequential row read is not available when the Chip Enable don’t care option is enabled.
Figure 10. Read (A, B, C) operations
CL
E
W
AL
R
tBLBH1
(read)
RB
00h/
I/O
Data Output (sequentially)
Address Input
01h/ 50h
Command
Code
Busy
ai07595c
Figure 11. Read block diagrams
Read A command, x8 devices
Read A command, x16 devices
Area B
(2nd half page)
Area A
(1st half page)
Area C
(spare)
Area A
(main area)
Area C
(spare)
(1)
A9-A26
(1)
A9-A26
A0-A7
A0-A7
Read B command, x8 devices
Read C command, x8/x16 devices
Area B
(2nd half page)
Area A/ B
Area A
(1st half page)
Area C
(spare)
Area A
Area C
(spare)
(1)
A9-A26
(1)
A9-A26
A0-A3 (x8)
A0-A2 (x16)
A0-A7
A4-A7 (x8), A3-A7 (x16) are don't care
AI07596
1. The highest address depends on the device density.
24/58
NAND128-A, NAND256-A
Device operations
Figure 12. Sequential row read operations
tBLBH1
tBLBH1
tBLBH1
(Read busy time)
RB
Busy
Busy
Busy
1st
2nd
page output
Nth
00h/
I/O
Address inputs
page output
page output
01h/ 50h
Command
code
ai07597
Figure 13. Sequential row read block diagrams
Read A command, x8 devices
Read A command, x16 devices
Area B
(2nd half Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
(main area)
Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
Read B command, x8 devices
Read C command, x8/x16 devices
Area B
(2nd half Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
Area A/ B
Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
AI07598
25/58
Device operations
NAND128-A, NAND256-A
6.3
Page program
The page program operation is the standard operation to program data to the memory array.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to Section 6.1: Pointer operations and Figure 9: Pointer
operations for programming for details.
Each page program operation consists of the following five steps (see Figure 14: Page
program operation):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 6:
Address insertion, x8 devices)
3. The data is then input (up to 528 bytes/ 264 words) and loaded into the page buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R controller.
5. The P/E/R controller then programs the data into the array.
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 14. Page program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Data Input
10h
Address Inputs
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai07566
1. Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1:
Pointer operations for details.
26/58
NAND128-A, NAND256-A
Device operations
6.4
Copy back program
The copy back program operation copies the data stored in one page and reprogram it in
another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails an error is signalled in the status register. However,
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires the following three steps:
1. The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 words/ 528 bytes from the page into the page buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that must be the same for the source and target
pages.
3. Then the confirm command is issued to start the P/E/R controller.
After a copy back program operation, a partial-page program is not allowed in the target
page until the block has been erased. See Figure 15 for an example of the copy back
operation.
Table 10. Copy back program addresses
Density
Same address for source and target pages
128 Mbits
256 Mbits
A23
A24
Figure 15. Copy back operation
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Source
Target
I/O
00h
8Ah
10h
70h
SR0
Address Inputs
Address Inputs
Read
Code
Copy Back
Code
Read Status Register
ai07590b
27/58
Device operations
NAND128-A, NAND256-A
6.5
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of the following three steps (refer to Figure 16: Block erase
operation):
1. One bus cycle is required to set up the Block Erase command.
2. Only two bus cycles are required to input the block address. The first cycle (A0 to A7) is
not required as only addresses A14 to A26 (highest address depends on device
density) are valid, A9 to A13 are ignored. In the last address cycle I/O2 to I/O7 must be
set to V .
IL
3. One bus cycle is required to issue the confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 16. Block erase operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
6.6
Reset
The Reset command resets the command interface and status register. If the Reset
command is issued during any operation, the operation is aborted. If it was a program or
erase operation that was aborted, the contents of the memory locations being modified are
no longer valid as the data is partially programmed or erased.
If the device has already been reset then the new Reset command is not accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued (refer to Table 20: AC characteristics for operations for the values.)
6.7
Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. the various bits in the status register convey information and
errors on the operation.
the status register is read by issuing the read status register command. the status register
information is present on the output data bus (I/O0-I/O7) on the falling edge of chip enable
or read enable, whichever occurs last. when several memories are connected in a system,
the use of chip enable and read enable signals allows the system to poll each device
separately, even when the ready/busy pins are common-wired. it is not necessary to toggle
the chip enable or read enable signals to update the contents of the status register.
28/58
NAND128-A, NAND256-A
Device operations
After the read status register command has been issued, the device remains in read status
register mode until another command is issued. therefore if a read status register command
is issued during a random read cycle a new read command must be issued to continue with
a page read.
The status register bits are summarized in Table 11: Status register bits, to which you should
refer in conjunction with the following sections.
6.7.1
Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is
set to ‘1’ the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
6.7.2
6.7.3
P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R controller. The error bit
is set to ’1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are reserved.
Table 11. Status register bits
Bit
Name
Logic level
Definition
'1'
'0'
'1'
'0'
Not protected
Protected
SR7
Write protection
P/E/R C inactive, device ready
P/E/R C active, device busy
Program/erase/read
controller
SR6
SR5, SR4, SR3,
SR2, SR1
Reserved
’don’t care’
‘1’
‘0’
Error – operation failed
SR0
Generic error
No error – operation successful
6.8
Read electronic signature
The device contains a manufacturer code and device code. To read these codes the following
two steps are required:
1. First use one bus write cycle to issue the Read Electronic Signature command (90h),
followed by an address input of 00h.
2. Then, perform two bus read operations. The first one reads the manufacturer code and
the second reads the device code. Further bus read operations are ignored.
29/58
Device operations
NAND128-A, NAND256-A
Refer to Table 12 for information on the addresses.
Table 12. Electronic signature
Part number
Manufacturer code
Device code
NAND128W3A
NAND256W3A
NAND256W4A
20h
20h
73h
75h
0020h
0055h
30/58
NAND128-A, NAND256-A
Software algorithms
7
Software algorithms
This section gives information on the software algorithms that Numonyx recommends to
implement to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 14: Program, erase times and program erase endurance cycles for the
values) and it is recommended to implement garbage collection, a wear-leveling algorithm
and an error correction code to extend the number of program and erase cycles and
increase the data retention.
For the integration of NAND memories into an application, Numonyx provides a full range of
software solutions such as file systems, sector managers, drivers, and code management.
Contact the nearest Numonyx sales office or visit www.numonyx.com for more details.
7.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block where the 6th byte (x8 devices)/1st
word (x16 devices) in the spare area of the 1st page does not contain FFh is a bad block.
The bad block information must be read before any erase is attempted as the bad block
information may be erased. For the system to be able to recognize the bad blocks based on
the original information it is recommended to create a bad block table following the flowchart
shown in Figure 17: Bad block management flowchart.
7.2
Block replacement
Over the lifetime of the device additional bad blocks may develop. In this case the block has
to be replaced by copying the data to a valid block. These additional bad blocks can be
identified as attempts to program or erase them outputs errors to the status register.
As the failure of a page program operation does not affect the data in other pages in the
same block, the block can be replaced by re-programming the current data and copying the
rest of the replaced block to an available valid block. The Copy Back Program command can
be used to copy the data to a valid block.
Refer to Section 6.4: Copy back program for more details.
31/58
Software algorithms
NAND128-A, NAND256-A
Refer to Table 13 for the recommended procedure to follow if an error occurs during an
operation.
Table 13. Block failure
Operation
Recommended procedure
Erase
Program
Read
Block replacement
Block replacement or ECC
ECC
Figure 17. Bad block management flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
32/58
NAND128-A, NAND256-A
Software algorithms
7.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 18: Garbage collection).
Figure 18. Garbage collection
Old Area
New Area (After GC)
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
7.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
■
First level wear-leveling: new data is programmed to the free blocks that have had the
fewest write cycles.
■
Second level wear-leveling: long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
33/58
Software algorithms
NAND128-A, NAND256-A
7.5
Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify
and correct errors in the data.
The recommendation is to implement 23 bits of ECC for every 4096 bits in the device.
Figure 19. Error detection
New ECC generated
during read
XOR previous ECC
with new ECC
NO
NO
>1 bit
= zero?
All results
= zero?
YES
YES
22 bit data = 0
11 bit data = 1
1 bit data = 1
ECC Error
Correctable
Error
No Error
ai08332
7.6
Hardware simulation models
7.6.1
Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and, therefore, allow
software to be developed before hardware.
7.6.2
IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC characteristics, rise/fall times, and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models simulate PCB connections and can resolve compatibility issues when
upgrading devices. They can be imported into SPICETOOLS.
34/58
NAND128-A, NAND256-A
Program and erase times and endurance cycles
8
Program and erase times and endurance cycles
The program and erase times and the number of program/ erase cycles per block are shown
in Table 14.
Table 14. Program, erase times and program erase endurance cycles
NAND flash
Parameters
Unit
Min
Typ
Max
Page program time
200
2
500
3
µs
ms
Block erase time
Program/erase cycles (per block)
Data retention
100,000
10
cycles
years
35/58
Maximum ratings
NAND128-A, NAND256-A
9
Maximum ratings
Stressing the device above the ratings listed in Table 15: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
Table 15. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature under bias
– 50
– 65
125
150
260
4.6
°C
°C
°C
V
Storage temperature
TLEAD
Lead temperature during soldering (1)
Input or output voltage
Supply voltage
(2)
VIO
– 0.6
– 0.6
VDD
4.6
V
1. Compatibility with lead-free soldering processes in accordance with ECOPACK 7191395 specifications.
Not exceeding 250 °C for more than 10 s, and peaking at 260 °C.
2. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
36/58
NAND128-A, NAND256-A
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables in this
section are derived from tests performed under the measurement conditions summarized in
Table 16. Designers should check that the operating conditions in their circuit match the
measurement conditions when relying on the quoted parameters.
Table 16. Operating and AC measurement conditions
NAND flash
Parameter
Units
Min
Max
Supply voltage (VDD
Ambient (TA)
)
3 V devices
Grade 6
2.7
3.6
85
V
°C
pF
pF
V
–40
3 V devices (2.7 - 3.6 V)
3 V devices (3.0 - 3.6V)
3 V devices
50
Load capacitance (CL) (1 TTL GATE
and CL)
100
Input pulses voltages
0.4
2.4
Input and output timing ref. voltages
Input rise and fall times
3 V devices
1.5
5
V
ns
kΩ
Output circuit resistors, Rref
8.35
(1)(2)
Table 17. Capacitance
Symbol
Parameter
Test condition
Typ
Max
Unit
CIN
Input capacitance
VIN = 0 V
VIL = 0 V
10
10
pF
pF
CI/O
Input/output capacitance
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double on stacked devices.
37/58
DC and AC parameters
NAND128-A, NAND256-A
Figure 20. Equivalent testing circuit for AC characteristics measurement
V
DD
2R
ref
NAND Flash
C
L
2R
ref
GND
GND
Ai11085
38/58
NAND128-A, NAND256-A
DC and AC parameters
(1)
Table 18. DC characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
read
IDD1
–
10
20
mA
E=VIL, OUT = 0 mA
I
Operating current
IDD2
IDD3
Program
Erase
–
–
–
–
–
–
–
–
–
10
10
–
20
20
1
mA
mA
mA
mA
µA
E = VIH,
WP = 0 V/VDD
IDD4
Standby current (TTL)
–
2
10
20
–
50
100
±10
E = VDD-0.2
IDD5
Standby current (CMOS)
WP = 0 V/VDD
µA
ILI
Input leakage current
Output leakage current
VIN = 0 to VDDmax
µA
VOUT= 0 to
VDDmax
ILO
–
–
±10
µA
VIH
VIL
Input High voltage
Input Low voltage
–
2.0
−0.3
2.4
–
–
–
VDD+0.3
V
V
–
0.8
-
VOH
Output High voltage level
Output Low voltage level
Output Low current (RB)
IOH = −400 µA
IOL = 2.1 mA
VOL = 0.4 V
–
V
VOL
–
0.4
V
IOL (RB)
8
10
mA
VDD supply voltage
(erase and program lockout)
VLKO
–
–
–
1.7
V
1. Leakage currents double on stacked devices.
39/58
DC and AC parameters
NAND128-A, NAND256-A
3 V devices Unit
t
Table 19. AC characteristics for command, address, data input
Alt.
symbol
Symbol
Parameter
tALLWL
tALHWL
tCLHWL
tCLLWL
tDVWH
tELWL
Address Latch Low to Write Enable Low
Address Latch High to Write Enable Low
Command Latch High to Write Enable Low
Command Latch Low to Write Enable Low
Data Valid to Write Enable High
tALS
AL setup time
CL setup time
Min
Min
0
0
ns
ns
tCLS
tDS
tCS
Data setup time
E setup time
Min
Min
20
0
ns
ns
Chip Enable Low to Write Enable Low
Write Enable High to Address Latch High
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
tWHALH
tWHALL
tWHCLH
tWHCLL
tWHDX
tWHEH
tWHWL
tWLWH
tWLWL
tALH
AL hold time
CL hold time
Min
Min
10
10
ns
ns
tCLH
tDH
tCH
tWH
tWP
tWC
Data hold time
E hold time
Min
Min
Min
Min
Min
10
10
ns
ns
ns
ns
ns
W High hold time
W pulse width
Write cycle time
15
25(1)
50
1. If tELWL is less than 10 ns, tWLWH must be minimum 35 ns, otherwise, tWLWH may be minimum 25 ns.
40/58
NAND128-A, NAND256-A
DC and AC parameters
3 V devices Unit
(1)
Table 20. AC characteristics for operations
Alt.
Symbol
Parameter
symbol
tALLRL1
tALLRL2
tBHRL
Read electronic signature
Read cycle
Min
Min
Min
10
10
20
ns
ns
ns
Address Latch Low to
Read Enable Low
tAR
tRR
Ready/Busy High to Read Enable Low
Read busy time, 128-Mbit, 256-Mbit,
tBLBH1
Max
12
µs
dual die
Ready/Busy Low to
Ready/Busy High
tBLBH2
tBLBH3
tBLBH4
tPROG
tBERS
Program busy time
Max
Max
Max
Max
Max
Max
Min
500
3
µs
ms
µs
µs
µs
µs
ns
ns
ns
ns
Erase busy time
Reset busy time, during ready
Reset busy time, during read
Reset busy time, during program
Reset busy time, during erase
5
5
Write Enable High to
Ready/Busy High
tWHBH1
tRST
10
500
10
0
tCLLRL
tDZRL
tEHQZ
tELQV
tCLR
tIR
tCHZ
tCEA
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Read Enable High to
Min
Max
Max
20
45
tRHRL
tREH
tRHZ
Read Enable High hold time
Min
15
30
ns
ns
Read Enable Low
tRHQZ
TEHQX
TRHQX
Read Enable High to Output Hi-Z
Max
TOH
Chip Enable High or Read Enable High to Output Hold
Min
10
ns
Read Enable Low to Read
Read Enable pulse width
Enable High
tRLRH
tRLRL
tRP
tRC
Min
Min
25
50
ns
ns
Read Enable Low to Read
Read cycle time
Enable Low
Read Enable access time
Read Enable Low to
Read ES access time(1)
Output Valid
tRLQV
tREA
Max
Max
35
12
ns
µs
Write Enable High to
Ready/Busy High
Read busy time, 128-Mbit, 256-Mbit
dual die
tWHBH
tR
tWHBL
tWHRL
tWB
Write Enable High to Ready/Busy Low
Max
Min
100
60
ns
ns
tWHR Write Enable High to Read Enable Low
Write Enable Low to Write
tWLWL
tWC
Write cycle time
Min
50
ns
Enable Low
1. ES = electronic signature.
41/58
DC and AC parameters
NAND128-A, NAND256-A
Figure 21. Command Latch AC waveforms
CL
tCLHWL
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWL
(E Setup time)
E
tWLWH
W
tALLWL
tWHALH
(ALSetup time)
(AL Hold time)
AL
I/O
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Command
ai08028
Figure 22. Address Latch AC waveforms
tCLLWL
(CL Setup time)
CL
tELWL
tWLWL
tWLWL
(E Setup time)
E
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHALL
tALHWL
tWHWL
tWHALL
(AL Setup time)
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 1
ai08029b
42/58
NAND128-A, NAND256-A
DC and AC parameters
Figure 23. Data Input Latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWL
tWLWL
(ALSetup time)
AL
W
tWLWH
tWLWH
tWLWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
Figure 24. Sequential data output after read AC waveforms
tEHQX
tEHQZ
1. CL = Low, AL = Low, W = High.
43/58
DC and AC parameters
NAND128-A, NAND256-A
Figure 25. Read status register AC waveform
tEHQX
Figure 26. Read electronic signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
Man.
code
Device
code
I/O
90h
00h
Read Electronic 1st Cycle
Manufacturer and
Device Codes
Signature
Command
Address
ai08039b
1. Refer to Table 12: Electronic signature for the values of the manufacturer and device codes.
44/58
NAND128-A, NAND256-A
DC and AC parameters
Figure 27. Page read A/read B operation AC waveform
CL
E
tWLWL
tEHQZ
W
tWHBL
tWHBH
AL
tALLRL2
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
Data
N
Data
N+1
Data
N+2
Data
Last
00h or
01h
Add.N Add.N
cycle 2 cycle 3
Add.N
cycle 1
Command
Code
Data Output
from Address N to Last Byte or Word in Page
Address N Input
Busy
tRHQX
tEHQX
ai08033d
Figure 28. Read C operation, one page AC waveform
CL
E
W
tWHBH
tWHALL
AL
tALLRL2
tBHRL
R
Data
Last
Add. M Add. M Add. M
cycle 1 cycle 2 cycle 3
I/O
50h
Data M
RB
Command
Code
Data Output from M to
Last Byte or Word in Area C
Address M Input
Busy
ai08035c
1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’.
45/58
DC and AC parameters
NAND128-A, NAND256-A
Figure 29. Page program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tBLBH2
(Program Busy time)
AL
R
Add.N Add.N
cycle 1 cycle 2
Add.N
cycle 3
I/O
80h
Last
N
10h
70h
SR0
RB
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai08037b
Figure 30. Block erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
tBLBH3
tWHBL
(Erase Busy time)
AL
R
Add.
Add.
70h
I/O
RB
60h
D0h
SR0
cycle 1 cycle 2
Block Erase
Setup Command
Block Address Confirm
Block Erase
Read Status Register
Code
Input
ai08038c
46/58
NAND128-A, NAND256-A
DC and AC parameters
Figure 31. Reset AC waveform
W
AL
CL
R
I/O
FFh
tBLBH4
(Reset Busy time)
RB
ai08043
10.1
Ready/busy signal electrical characteristics
Figures Figure 32, Figure 33, and Figure 34 show the electrical characteristics for the
Ready/Busy signal. The value required for the resistor R can be calculated using the
P
following equation:
(
–
)
V
V
DDmax
OLmax
+ I
R min= -------------------------------------------------------------
P
I
L
OL
Therefore,
3.2V
R min(3V)= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R
L
P
max is determined by the maximum value of t .
r
Figure 32. Ready/Busy AC waveform
ready V
DD
V
OH
V
OL
busy
t
t
r
f
AI07564B
47/58
DC and AC parameters
NAND128-A, NAND256-A
Figure 33. Ready/busy load circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
Figure 34. Resistor value versus waveform timings for Ready/Busy signal
V
= 3.3 V, C = 100 pF
L
DD
400
300
200
4
3
2
400
300
2.4
200
1.2
100
0
1
0.8
100
3.6
0.6
3.6
3.6
3.6
1
2
3
4
R
(KΩ)
P
t
t
ibusy
f
r
ai07565C
1. T = 25 °C.
48/58
NAND128-A, NAND256-A
DC and AC parameters
10.2
Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
Low (V ) to guarantee hardware protection during power transitions as shown in the below
IL
figure.
Figure 35. Data protection
Nominal Range
V
DD
V
LKO
Locked
Locked
W
Ai11086
49/58
Package mechanical
NAND128-A, NAND256-A
11
Package mechanical
®
To meet environmental requirements, Numonyx offers the devices in ECOPACK packages,
which are lead-free. In compliance with JEDEC Standard JESD97, the category of second
level interconnect is marked on the package and on the inner box label. The maximum
®
ratings related to soldering conditions are also marked on the inner box label. ECOPACK
specifications are available at www.numonyx.com.
Figure 36. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 21. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package
mechanical data
Millimeters
Min
Inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.20
0.15
1.05
0.27
0.21
0.08
12.10
20.20
18.50
–
0.047
0.006
0.041
0.011
0.008
0.003
0.476
0.795
0.728
–
0.10
1.00
0.22
0.05
0.95
0.17
0.10
0.004
0.039
0.009
0.002
0.037
0.007
0.004
C
CP
D1
E
12.00
20.00
18.40
0.50
0.60
0.80
3°
11.90
19.80
18.30
–
0.472
0.787
0.724
0.020
0.024
0.031
3°
0.468
0.779
0.720
–
E1
e
L
0.50
0.70
0.020
0.028
L1
a
0°
5°
0°
5°
50/58
NAND128-A, NAND256-A
Package mechanical
Figure 37. VFBGA55 8 x 10 mm - 6 x 8 active ball array, 0.80 mm pitch, package
outline
D
D2
D1
SD
e
SE
E1
E2
E
FE
FE1
FD1
FD
b
ddd
A
A2
A1
BGA-Z61
1. Drawing is not to scale.
51/58
Package mechanical
NAND128-A, NAND256-A
Table 22. VFBGA55 8 x 10 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical
data
Millimeters
Min
Inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.05
0.041
0.25
0.010
0.70
0.50
8.10
0.028
0.020
0.319
0.45
8.00
4.00
5.60
0.40
7.90
0.018
0.315
0.157
0.220
0.016
0.311
D
D1
D2
ddd
E
0.10
0.004
0.398
10.00
5.60
8.80
0.80
2.00
1.20
2.20
0.60
0.40
0.40
9.90
–
10.10
0.394
0.220
0.346
0.031
0.079
0.047
0.087
0.024
0.016
0.016
0.390
–
E1
E2
e
–
–
FD
FD1
FE
FE1
SD
SE
52/58
NAND128-A, NAND256-A
Ordering information
12
Ordering information
Table 23. Ordering information scheme
Example:
NAND128 W 3 A 2
B
ZA 6
E
Device type
NAND flash memory
Density
128 = 128 Mbits
256 = 256 Mbits
Operating voltage
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
4 = x16(1)
Family identifier
A = 528-byte/264-word page
Device options
0 = No options (Chip Enable ‘care’; sequential row read enabled)
2 = Chip Enable ‘don't care’ enabled
Product version
A = first version
B = second version
C = third version
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA55 8 x 10 x 1 mm
Temperature range
6 = −40 to 85 °C
Option
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
1.
1. x16 organization only available for MCP.
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest
Numonyx sales office.
53/58
Hardware interface examples
NAND128-A, NAND256-A
Appendix A
Hardware interface examples
NAND flash devices can be connected to a microcontroller system bus for code and data
storage. For microcontrollers that have an embedded NAND controller the NAND flash can
be connected without the addition of glue logic (see Figure 38). However, a minimum of glue
logic is required for general purpose microcontrollers that do not have an embedded NAND
controller. The glue logic usually consists of a flip-flop to hold the Chip Enable, Address
Latch Enable, and Command Latch Enable signals stable during command and address
latch operations, and some logic gates to simplify the firmware or make the design more
robust.
Figure 39 provides an example of how to connect a NAND flash to a general purpose
microcontroller. The additional OR gates allow the microcontroller’s Output Enable and
Write Enable signals to be used for other peripherals. The OR gate between A3 and CSn
maps the flip-flop and NAND I/O in different address spaces inside the same chip select
unit, which improves the setup and hold times and simplifies the firmware. The structure
uses the microcontroller DMA (direct memory access) engines to optimize the transfer
between the NAND flash and the system RAM.
For any interface with glue logic, the extra delay caused by the gates and flip-flop must be
taken into account. This delay must be added to the microcontroller’s AC characteristics and
register settings to get the NAND flash setup and hold times.
For mass storage applications (hard disk emulations or systems where a huge amount of
storage is required) NAND flash memories can be connected together to build storage
modules (see Figure 40).
Figure 38. Connection to microcontroller, without glue logic
AD17
AD(24:16)
AL
CL
R
AD16
Microcontroller
G
W
E
W
NAND
Flash
CSn
DQ
I/O
PWAITEN
RB
V
DD
V
or V
SS
DD
or General Purpose I/O
WP
AI08045b
54/58
NAND128-A, NAND256-A
Hardware interface examples
Figure 39. Connection to microcontroller, with glue logic
G
R
W
CSn
A3
W
CLK
D flip-flop
NAND Flash
Microcontroller
A2
A1
A0
Q2
Q1
Q0
D2
CL
AL
E
D1
D0
DQ
I/O
AI07589
Figure 40. Building storage modules
E
E
E
E
E
n+1
1
2
3
n
CL
AL
W
NAND Flash
Device 1
NAND Flash
Device 2
NAND Flash
Device 3
NAND Flash
Device n
NAND Flash
Device n+1
G
RB
I/O0-I/O7 or
I/O0-I/O15
AI08331
55/58
Revision history
NAND128-A, NAND256-A
13
Revision history
Table 24. Document revision history
Date
Version
Revision details
06-Jun-2003
07-Aug-2003
27-Oct-2003
1
2
3
Initial release.
Design phase.
Engineering phase.
Document promoted from Target Specification to Preliminary Data status.
VCC changed to VDD and ICC to IDD
.
03-Dec-2003
4
Changed title of Table 2: Product description and page program typical
timing for NANDXXXR3A devices corrected. Table 1: NAND128-A and
NAND256-A device summary, inserted on page 2.
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm)
removed.
Figure 19., Cache Program Operation, modified and note 2 modified.
Note removed for tWLWH timing in Table 19: AC characteristics for
command, address, data input. Meaning of tBLBH4 modified, partly
replaced by tWHBH1 and tWHRL min for 3 V devices modified in Table 20:
AC characteristics for operations.
References removed from Section 13: Revision history section and
reference made to ST website instead.
13-Apr-2004
5
Figure 5: VFBGA55 connections, x8 devices (top view through package),
Figure 6: VFBGA55 connections, x16 devices (top view through
package), Figure 27: Page read A/read B operation AC waveform and
Figure 30: Block erase AC waveform modified. Section 6.8: Read
electronic signature clarified and Figure 26: Read electronic signature AC
waveform, modified. Note 2 to Figure 28: Read C operation, one page AC
waveform removed. Only 00h pointer operations are valid before a cache
program operation. Note added to Figure 30: Block erase AC waveform.
Small text changes.
TFBGA55 package added (mechanical data to be announced). 512-Mbit
dual die devices added. Figure 19., Cache Program Operation modified.
28-May-2004
02-Jul-2004
6
7
Package code changed for TFBGA63 8.5 x 15 x 1.2 mm, 6x8 ball array,
0.8 mm pitch (1-Gbit dual die devices) in Table 23: Ordering information
scheme.
Cache Program removed from document. TFBGA55 package
specifications added (Figure 40., TFBGA55 8 x 10mm - 6x8 active ball
array - 0.80mm pitch, Package Outline and Table 25., TFBGA55 8 x
10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data).
Test conditions modified for VOL and VOH parameters.
Section 6.5: Block erase last address cycle modified. Definition of a bad
block modified in Section 7.1: Bad block management. RoHS compliance
added to Section 1: Description. Figure 2: Logic block diagram modified.
01-Oct-2004
03-Dec-2004
8
9
Document promoted from Preliminary Data to Full Datasheet status.
Automatic Page 0 Read at power-up option no longer available.
PC Demo board with simulation software removed from list of available
development tools. Section 3.5: Chip Enable (E) paragraph clarified.
56/58
NAND128-A, NAND256-A
Revision history
Table 24. Document revision history (continued)
Date
Version
Revision details
Rref parameter added to the description of the family clarified in the
Section 1: Description.
13-Dec-2004
10
WSOP48 replaced with USOP48 package,
VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm)
package,
25-Feb-2005
11
TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm)
package.
Changes to Table 20: AC characteristics for operations.
tEHBH, tEHEL, tRHBL removed throughout document. TFBGA63 and TFBGA55
packages removed throughout document. Sequential row read removed
throughout document.
TEHQX and TRHQX added throughout document. Section 10.2: Data
protection section and Figure 20: Equivalent testing circuit for AC
characteristics measurement added.
23-June-2005
12
Modified Section 3.7: Write Enable (W), Section 3.5: Chip Enable (E),
Section 6.2: Read memory array, Section 6.3: Page program,
Section 6.8: Read electronic signature, Section 7.1: Bad block
management and Section 12: Ordering information.
Figure 10: Read (A, B, C) operations and Figure 26: Read electronic
signature AC waveform modified.
Note added to Figure 3: TSOP48 connections, x8 devices and Figure 4:
TSOP48 connections, x16 devices regarding the USOP package.
09-Aug-2005
20-Jun-2008
13
14
Removed all information pertaining to the 512-Mbit and 1-Gbit devices.
Applied Numonyx branding.
Removed all the information pertaining the 1.8 V devices (VDD = 1.7 to
1.95 V) and the USOP48 and VFBGA63 packages. Added the sequential
row read option throughout the document.
13-Aug-2008
15
57/58
NAND128-A, NAND256-A
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
58/58
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