NAND512R3A2CN6E [NUMONYX]
512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories; 512兆， 528字节/ 264字页， 1.8V / 3V ， NAND闪存
| 型号： | NAND512R3A2CN6E |
| 厂家： | 
NUMONYX B.V |
| 描述： | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| 文件： | 总51页 (文件大小：1272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND512R3A2C NAND512R4A2C
NAND512W3A2C NAND512W4A2C
512 Mbit, 528 byte/264 word page,
1.8 V/3 V, NAND Flash memories
Features
●
High density NAND Flash memories
–
–
512 Mbit memory array
Cost effective solutions for mass
storage applications
●
NAND interface
–
–
x 8 or x 16 bus width
Multiplexed Address/ Data
TSOP48 12 x 20 mm
●
●
Supply voltage: 1.8 V, 3.0 V
Page size
FBGA
–
–
x 8 device: (512 + 16 spare) bytes
x 16 device: (256 + 8 spare) words
VFBGA55 8 x 10 x 1 mm
VFBGA63 9 x 11 x 1 mm
●
●
Block size
–
–
x 8 device: (16 K + 512 spare) bytes
x 16 device: (8 K + 256 spare) words
●
●
Hardware Data Protection
Page Read/Program
–
Program/Erase locked during Power
transitions
–
–
–
Random access:
12 µs (3 V)/15 µs (1.8 V) (max)
Data integrity
Sequential access:
30 ns (3 V)/50 ns (1.8 V) (min)
–
100,000 Program/Erase cycles (with
ECC)
Page Program time: 200 µs (typ)
–
10 years Data Retention
®
●
●
●
●
●
●
Copy Back Program mode
Fast Block Erase: 2 ms (typ)
Status Register
●
●
ECOPACK packages
Development tools
–
–
Error Correction Code models
Electronic signature
Bad Blocks Management and Wear
Leveling algorithms
Chip Enable ‘don’t care’
Serial Number option
–
Hardware simulation models
Table 1.
Device summary
Reference
Part number
NAND512R3A2C
NAND512R4A2C(1)
NAND512W3A2C
NAND512W4A2C(1)
NAND512-A2C
1. x16 organization only available for MCP.
January 2008
Rev 2
1/51
www.numonyx.com
1
Contents
NAND512-A2C
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
V
DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
4.3
4.4
4.5
4.6
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.1
6.2.2
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/51
NAND512-A2C
Contents
6.3
6.4
6.5
6.6
6.7
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7.1
6.7.2
6.7.3
6.7.4
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
P/E/R Controller Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 26
6.8
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
7.2
7.3
7.4
7.5
7.6
Bad Block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6.1
7.6.2
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 32
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 45
10.2 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11
12
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/51
List of tables
NAND512-A2C
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Copy Back Program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
NAND Flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC characteristics, 1.8 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Characteristics, 3V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data. . . . 47
VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data . . . . 48
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/51
NAND512-A2C
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FBGA63 connections - x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . . 10
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Page Program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Copy Back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Block Erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Bad Block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Read Status Register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Read Electronic Signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Page Read A/ Read B operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. Read C operation, One Page AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 26. Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 29. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 30. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 46
Figure 31. Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 47
Figure 33. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline. . . . . . . . . . . . 48
5/51
Description
NAND512-A2C
1
Description
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that
uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page
family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C
have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of
a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on
whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or
x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an
Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A Write Protect pin is available to give a hardware
protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the Ready/Busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a Page Program operation fails, the data can be programmed in another page without
having to resend the data to be programmed.
The devices are available in the following packages:
●
●
TSOP48 12 x 20mm
VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch)
®
In order to meet environmental requirements, Numonyx offers the devices in ECOPACK
packages. ECOPACK packages are Lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
All devices have the Chip Enable Don't Care option, which allows the code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the read operation.
A Serial Number option, allows each device to be uniquely identified. The Serial Number
options is subject to an NDA (Non Disclosure Agreement) and so not described in the
datasheet. For more details of this option contact your nearest Numonyx Sales office.
For information on how to order these options refer to Table 24: Ordering information
scheme. Devices are shipped from the factory with Block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
See Table 2: Product description, for all the devices available in the family.
6/51
NAND512-A2C
Description
Table 2.
Product description
Timings
Bus
Width
Page
Size
Block
Size
Memory
Array
Operating
Voltage
Block
Erase
Typica
l
Reference
Part Number
Density
Package
Random Sequential
Page
Program
Typical
Access
Max
Access
Min
NAND512R3A2C
NAND512W3A2C
NAND512R4A2C
NAND512W4A2C
1.7to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
15µs
12µs
15µs
12µs
50ns
30ns
50ns
30ns
200µs
200µs
200µs
200µs
512+16 16K+512
TSOP48
VFBGA63
x8
Bytes
Bytes
NAND512-
A2C
32 Pages x
4096 Blocks
512Mbit
2ms
256+8
Words
8K+256
Words
(1)
x16
1.
x16 organization only available for MCP.
Figure 1.
Logic diagram
V
DD
I/O8-I/O15, x16
E
I/O0-I/O7, x8/x16
R
W
NAND Flash
RB
AL
CL
WP
V
SS
AI07557C
7/51
Description
Table 3.
NAND512-A2C
Signal names
I/O8-15
Data Input/Outputs for x16 devices
I/O0-7
AL
Data Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices
Address Latch Enable
Command Latch Enable
Chip Enable
CL
E
R
Read Enable
RB
W
Ready/Busy (open-drain output)
Write Enable
WP
VDD
VSS
NC
DU
Write Protect
Supply Voltage
Ground
Not Connected Internally
Do Not Use
Figure 2.
Logic block diagram
Address
Register/Counter
AL
NAND Flash
Memory Array
CL
W
P/E/R Controller,
High Voltage
Generator
Command
Interface
Logic
E
WP
R
Page Buffer
Y Decoder
Command Register
I/O Buffers & Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI07561c
8/51
NAND512-A2C
Description
Figure 3.
TSOP48 connections - x8 devices
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
NAND Flash
(x8)
V
12
13
37
36
V
V
DD
DD
SS
V
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI07585C
9/51
Description
Figure 4.
NAND512-A2C
FBGA63 connections - x8 devices (top view through package)
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
V
SS
C
WP
AL
E
W
RB
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
G
H
J
NC
NC
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI07586B
10/51
NAND512-A2C
Memory array organization
2
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and
a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area
and an 8 Word spare area. Refer to Figure 5: Memory array organization.
Bad blocks
The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad
Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 7.1: Bad Block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the Bad Blocks that are present when the device is shipped and the Bad Blocks
that could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to Section 7: Software algorithms).
Table 4.
Valid blocks
Density of device
Min
Max
512 Mbits
4016
4096
11/51
Memory array organization
NAND512-A2C
Figure 5.
Memory array organization
x8 DEVICES
x16 DEVICES
Block = 32 Pages
Block = 32 Pages
Page = 528 Bytes (512+16)
Page = 264 Words (256+8)
1st half Page 2nd half Page
(256 bytes) (256 bytes)
Main Area
Block
Page
Block
Page
8 bits
16 bits
256 Words
512 Bytes
16
Bytes
8
Words
Page Buffer, 264 Words
8
Page Buffer, 512 Bytes
16
256 Words
Words
512 Bytes
16 bits
Bytes
8 bits
AI07587
12/51
NAND512-A2C
Signal descriptions
3
Signal descriptions
See Figure 1: Logic diagram, and Table 3: Signal names, for a brief overview of the signals
connected to this device.
3.1
Inputs/Outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Inputs/Outputs (I/O8-I/O15)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a Read operation or input data during a Write operation. Command and Address
Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
3.4
3.5
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and read
circuitry. When Chip Enable is low, V , the device is selected.
IL
If Chip Enable goes High (V ) while the device is busy, the device remains selected and
IH
does not go into standby mode.
3.6
Read Enable (R)
The Read Enable, R, controls the sequential data output during Read operations. Data is
valid t
after the falling edge of R. The falling edge of R also increments the internal
RLQV
column address counter by one.
13/51
Signal descriptions
NAND512-A2C
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
3.8
3.9
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V , the device does not accept any
program or erase operations.
IL
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
Controller is currently active.
When Ready/Busy is Low, V , a read, program or erase operation is in progress. When the
OL
operation completes Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Refer to the Section 10.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V is below the V
threshold
LKO
DD
(see Section Figure 31.: Data Protection) to protect the device from any involuntary
Program/Erase operations during power-transitions.
Each device in a system should have V decoupled with a 0.1µF capacitor. The PCB track
DD
widths should be sufficient to carry the required program and erase currents
3.11
VSS ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
14/51
NAND512-A2C
Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 17 and Table 20 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory address. Three bus cycles are
required to input the addresses for the 128Mb and 256Mb devices and four bus cycles are
required to input the addresses for the 512Mb and 1Gb devices (refer to Table 6 and
Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 18 and Table 20 for details of the timings requirements.
4.3
4.4
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 19, Table 20, and Table 21 for details of the timings requirements.
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 20 and Table 21 for details of the timings requirements.
15/51
Bus operations
NAND512-A2C
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus operations
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
Command Input
Address Input
Data Input
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIH Rising X(2)
Command
Address
X
X
VIH Rising
VIH Rising
X
X
Data Input
Data Input
Fallin
VIH
g
Data Output
VIL
VIL
VIL
X
Data Output
Data Output
Write Protect
Standby
X
X
X
X
X
X
X
X
X
VIL
X
X
X
X
X
VIH
1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
(1)(2)
Table 6.
Address Insertion, x8 devices
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
4th
A7
A16
A24
VIL
A6
A15
A23
VIL
A5
A14
A22
VIL
A4
A13
A21
VIL
A3
A12
A20
VIL
A2
A11
A19
VIL
A1
A10
A18
VIL
A0
A9
A17
A25
1. A8 is set Low or High by the 00h or 01h Command, see Section 6.1: Pointer operations.
2. Any additional address input cycles will be ignored.
(1)(2)
Table 7.
Address Insertion, x16 devices
I/O8-
I/O15
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
X
X
X
X
A7
A16
A24
VIL
A6
A15
A23
VIL
A5
A14
A22
VIL
A4
A13
A21
VIL
A3
A12
A20
VIL
A2
A11
A19
VIL
A1
A10
A18
VIL
A0
A9
3rd
A17
A25
4th(4)
1. A8 is Don’t Care in x16 devices.
2. Any additional address input cycles will be ignored.
16/51
NAND512-A2C
Bus operations
Table 8.
Address definition
Address
Definition
A0 - A7
A9 - A25
A9 - A13
A14 - A25
Column Address
Page Address
Address in Block
Block Address
A8 is set Low or High by the 00h or 01h
Command, and is Don’t Care in x16 devices
A8
17/51
Command set
NAND512-A2C
5
Command set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in Table 9.
Table 9.
Commands
Command
Bus Write operations(1)(2)
st CYCLE 2nd CYCLE 3rd CYCLE
Command
accepted during
busy
1
Read A
00h
01h
50h
90h
70h
80h
00h
60h
FFh
-
-
Read B(3)
-
-
Read C
-
-
-
Read Electronic Signature
Read Status Register
Page Program
-
-
-
Yes
Yes
10h
8Ah
D0h
-
-
Copy Back Program
Block Erase
(10h)(4)
-
-
Reset
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence will be ignored by the device.
3. The Read B command (code 01h) is not used in x16 devices.
4. The Program Confirm command (code 10h) is no more necessary for NAND512-A2C devices. It is optional
and has been maintained for backward compatibility
18/51
NAND512-A2C
Device operations
6
Device operations
6.1
Pointer operations
As the NAND Flash memories contain two different areas for x16 devices and three different
areas for x8 devices (see Figure 6) the read command codes (00h, 01h, 50h) are used to
act as pointers to the different areas of the memory array (they select the most significant
column address).
The Read A and Read B commands act as pointers to the main memory area. Their use
depends on the bus width of the device.
●
In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the
main area) that is Words 0 to 255.
●
In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the
main area) that is Bytes 0 to 255, and the Read B command (01h) sets the pointer to
Area B (the second half of the main area) that is Bytes 256 to 511.
In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the
spare memory area) that is Bytes 512 to 527 or Words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been executed in Area B the pointer
returns automatically to Area A.
The pointer operations can also be used before a program operation, that is the appropriate
code (00h, 01h or 50h) can be issued before the program command 80h is issued (see
Figure 7).
Figure 6.
Pointer operations
x8 Devices
x16 Devices
Area A
(00h)
Area B
(01h)
Area C
(50h)
Area A
(00h)
Area C
(50h)
Bytes 512
-527
Words 256
-263
Bytes 0- 255
Bytes 256-511
Words 0- 255
A
B
C
Page Buffer
A
C
Page Buffer
Pointer
(00h,01h,50h)
Pointer
(00h,50h)
AI07592
19/51
Device operations
NAND512-A2C
Figure 7.
Pointer operations for programming
AREA A
10h
Address
Inputs
Address
Inputs
80h
I/O
00h
Data Input
80h
00h
Data Input
10h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA B
Address
Inputs
Address
Inputs
80h
I/O
01h
Data Input
10h
80h
01h
Data Input
10h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA C
Address
Inputs
Address
Inputs
80h
I/O
50h
Data Input
10h
80h
50h
Data Input
10h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
ai07591
6.2
Read Memory Array
Each operation to read the memory area starts with a pointer operation as shown in the
Section 6.1: Pointer operations. Once the area (main or spare) has been selected using the
Read A, Read B or Read C commands four bus cycles (for 512Mb and 1Gb devices) or
three bus cycles (for 128Mb and 256Mb devices) are required to input the address (refer to
Table 6 and Table 7) of the data to be read.
The device defaults to Read A mode after power-up or a Reset operation.
When reading the spare area addresses:
●
A0 to A3 (x8 devices)
A0 to A2 (x16 devices)
●
are used to set the start address of the spare area while addresses:
●
●
A4 to A7 (x8 devices)
A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is effective for only one operation, once an operation has been executed
in Area B the pointer returns automatically to Area A and so another Read B command is
required to start another read operation in Area B.
Once a read command is issued two types of operations are available: Random Read and
Page Read.
6.2.1
Random Read
Each time the command is issued the first read is Random Read.
20/51
NAND512-A2C
Device operations
6.2.2
Page Read
After the Random Read access the page data is transferred to the Page Buffer in a time of
t
(refer to Table 21 for value). Once the transfer is complete the Ready/Busy signal
WHBH
goes High. The data can then be read out sequentially (from selected column address to
last column address) by pulsing the Read Enable signal.
Figure 8.
Read (A,B,C) operations
CL
E
W
AL
R
tBLBH1
(read)
RB
I/O
00h/
Data Output (sequentially)
Address Input
01h/ 50h
Command
Code
Busy
ai07595c
21/51
Device operations
NAND512-A2C
Figure 9.
Read block diagrams
Read A Command, X8 Devices
Read A Command, X16 Devices
Area B
(2nd half Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
(main area)
Area C
(Spare)
(1)
A9-A26
(1)
A9-A26
A0-A7
A0-A7
Read B Command, X8 Devices
Read C Command, X8/x16 Devices
Area B
(2nd half Page)
Area A/ B
Area A
(1st half Page)
Area C
(Spare)
Area A
Area C
(Spare)
(1)
A9-A26
(1)
A9-A26
A0-A3 (x8)
A0-A2 (x16)
A0-A7
A4-A7 (x8), A3-A7 (x16) are don't care
AI07596
1. Highest address depends on device density.
22/51
NAND512-A2C
Device operations
6.3
Page Program
The Page Program operation is the standard operation to program data to the memory
array.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a Page Program operation a Pointer operation can be performed to point to
the area to be programmed. Refer to the Section 6.1: Pointer operations and Figure 7 for
details.
Each Page Program operation consists of five steps (see Figure 10):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 6 and
Table 7)
3. The data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
5. The P/E/R Controller then programs the data into the array.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During program operations the Status Register will only flag
errors for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands will be
accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in Read Status Register mode until another valid command is written to
the Command Interface.
Figure 10. Page Program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Data Input
10h
Address Inputs
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai07566
1. Before starting a Page Program operation a Pointer operation can be performed. Refer to Section 6.1: Pointer operations
for details.
23/51
Device operations
NAND512-A2C
6.4
Copy Back Program
The Copy Back Program operation is used to copy the data stored in one page and
reprogram it in another page.
The Copy Back Program operation does not require external memory and so the operation
is faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the Copy Back Program operation fails an error is signalled in the Status Register.
However as the standard external ECC cannot be used with the Copy Back operation bit
error due to charge loss cannot be detected. For this reason it is recommended to limit the
number of Copy Back operations on the same data and or to improve the performance of the
ECC.
The Copy Back Program operation requires two steps:
1. The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 Words/ 528 Bytes from the page into the Page Buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that must be the same for the Source and Target
pages.
3. The Program Confirm command (code 10h) is no more necessary on NAND512-A2C
devices. It is optional and has been maintained for backward compatibility.
After a Copy Back Program operation, a partial-page program is not allowed in the target
page until the block has been erased.
See Figure 11 for an example of the Copy Back operation.
Table 10. Copy Back Program addresses
Density
Same Address for Source and Target Pages
512 Mbit
A25
Figure 11. Copy Back operation
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Source
Target
Address Inputs
(1)
I/O
00h
8Ah
10h
70h
SR0
Address Inputs
Read
Code
Copy Back
Code
Read Status Register
ai13187
1. The Program Confirm command (code 10h) is no more necessary on NAND512-A2C devices. It is optional and has been
maintained for backward compatibility.
24/51
NAND512-A2C
Device operations
6.5
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 12):
1. One bus cycle is required to setup the Block Erase command.
2. Only three bus cycles for 512Mb and 1Gb devices, or two for 128Mb and 256Mb
devices are required to input the block address. The first cycle (A0 to A7) is not
required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the last
address cycle I/O2 to I/O7 must be set to V .
IL
3. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
Once the erase operation has completed the Status Register can be checked for errors.
Figure 12. Block Erase operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
6.6
Reset
The Reset command is used to reset the Command Interface and Status Register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued, refer to Table 21 for the values.
25/51
Device operations
NAND512-A2C
6.7
Read Status Register
The device contains a Status Register which provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the Status
Register.
After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore if a Read Status Register
command is issued during a Random Read cycle a new read command must be issued to
continue with a Page Read.
The Status Register bits are summarized in Table 11: Status Register bits. Refer to Table 11
in conjunction with the following text descriptions.
6.7.1
Write Protection Bit (SR7)
The Write Protection bit can be used to identify if the device is protected or not. If the Write
Protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2
6.7.3
6.7.4
P/E/R Controller Bit (SR6)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready).
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The
Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error Bit is set to ‘0’ the operation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are reserved
26/51
NAND512-A2C
Device operations
Table 11. Status Register bits
Bit
Name
Logic Level
Definition
'1'
'0'
'1'
'0'
Not Protected
Protected
SR7
Write Protection
P/E/R C inactive, device ready
P/E/R C active, device busy
Program/ Erase/ Read
Controller
SR6
SR5, SR4,
SR3, SR2,
SR1
Reserved
Don’t Care
‘1’
‘0’
Error – operation failed
SR0
Generic Error
No Error – operation successful
6.8
Read Electronic Signature
The device contains a Manufacturer Code and Device Code. To read these codes two steps
are required:
1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h),
followed by an address input of 00h.
2. then perform two Bus Read operations – the first will read the Manufacturer Code and
the second, the Device Code. Further Bus Read operations will be ignored.
Refer to Table 12: Electronic signature, for information on the addresses.
Table 12. Electronic signature
Part number
Manufacturer code
Device code
NAND512R3A2C
NAND512W3A2C
NAND512R4A2C
NAND512W4A2C
36h
76h
20h
0046h
0056h
0020h
27/51
Software algorithms
NAND512-A2C
7
Software algorithms
This section gives information on the software algorithms that Numonyx recommends to
implement to manage the Bad Blocks and extend the lifetime of the NAND device.
NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 14 for value) and it is recommended to implement Garbage Collection, a
Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program
and erase cycles and increase the data retention.
To help integrate a NAND memory into an application Numonyx can provide:
●
File System OS Native reference software, which supports the basic commands of file
management.
Contact the nearest Numonyx sales office for more details.
7.1
Bad Block management
Devices with Bad Blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A Bad Block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad
Block Information is written prior to shipping. Any block where the 6th byte (x8 device) / 1st
word (x16 device) in the spare area of the 1st page does not contain FFh is a Bad Block.
The Bad Block Information must be read before any erase is attempted as the Bad Block
Information may be erased. For the system to be able to recognize the Bad Blocks based on
the original information it is recommended to create a Bad Block table following the
flowchart shown in Figure 13.
7.2
NAND Flash memory failure modes
Over the lifetime of the device additional Bad Blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
●
Program/Erase failure: in this case the block has to be replaced by copying the data to
a valid block. These additional Bad Blocks can be identified as attempts to program or
erase them will give errors in the Status Register.
As the failure of a Page Program operation does not affect the data in other pages in
the same block, the block can be replaced by re-programming the current data and
copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Section 6.4:
Copy Back Program for more details.
●
Read failure: in this case, ECC correction must be implemented. To efficiently use the
memory space, it is recommended to recover single-bit error in read by ECC, without
replacing the whole block.
Refer to Table 13 for the procedure to follow if an error occurs during an operation.
28/51
NAND512-A2C
Software algorithms
Table 13. NAND Flash failure modes
Operation
Procedure
Erase
Program
Read
Block Replacement
Block Replacement or ECC
ECC
Figure 13. Bad Block management flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
29/51
Software algorithms
NAND512-A2C
7.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a Garbage Collection algorithm. In a Garbage Collection software the valid
pages are copied into a free area and the block containing the invalid pages is erased (see
Figure 14).
Figure 14. Garbage collection
Old Area
New Area (After GC)
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
7.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
●
First Level Wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
●
Second Level Wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The Second Level Wear-leveling is triggered when the difference between the maximum
and the minimum number of write cycles per block reaches a specific threshold.
7.5
Error Correction Code
An Error Correction Code (ECC) can be implemented in the Nand Flash memories to
identify and correct errors in the data.
For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for
line parity plus 6 bits for column parity).
30/51
NAND512-A2C
Software algorithms
An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for
more details.
Figure 15. Error Detection
New ECC generated
during read
XOR previous ECC
with new ECC
NO
NO
>1 bit
= zero?
All results
= zero?
YES
YES
22 bit data = 0
11 bit data = 1
1 bit data = 1
ECC Error
Correctable
Error
No Error
ai08332
7.6
Hardware simulation models
7.6.1
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and so allow
software to be developed before hardware.
7.6.2
IBIS simulations models
IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.
These models provide information such as AC characteristics, rise/fall times and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
31/51
Program and erase times and endurance cycles
NAND512-A2C
8
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are
shown in Table 14.
Table 14. Program, Erase Times and Program Erase Endurance Cycles
NAND Flash
Parameters
Unit
Min
Typ
Max
Page Program Time
Block Erase Time
200
2
500
3
µs
ms
Program/Erase Cycles per block (with
ECC)
100,000
10
cycles
years
Data Retention
32/51
NAND512-A2C
Maximum rating
9
Maximum rating
Stressing the device above the ratings listed in Table 15: Absolute Maximum Ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 15. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
– 50
– 65
125
150
260
2.7
4.6
2.7
4.6
°C
°C
°C
V
TLEAD
Lead temperature during soldering
1.8V devices
– 0.6
– 0.6
– 0.6
– 0.6
(1)
VIO
Input or Output Voltage
Supply Voltage
3 V devices
1.8V devices
3 V devices
V
V
VDD
V
1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.
33/51
DC and AC parameters
NAND512-A2C
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 16: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 16. Operating and AC measurement conditions
NAND Flash
Parameter
Units
Min
Max
1.8 V devices
3 V devices
Grade 6
1.7
2.7
1.95
3.6
85
V
V
Supply Voltage (VDD
)
Ambient Temperature (TA)
–40
°C
pF
pF
V
1.8 V devices
3 V devices
1.8 V devices
3 V devices
1.8 V devices
3 V devices
30
50
Load Capacitance (CL) (1 TTL GATE
and CL)
0
VDD
2.4
Input Pulses Voltages
0.4
V
0.9
1.5
5
V
Input and Output Timing Ref. Voltages
V
Input Rise and Fall Times
ns
kΩ
Output Circuit Resistors, Rref
8.35
(1)(2)
Table 17. Capacitance
Symbol
Parameter
Test Condition
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0 V
10
pF
Input/Output
Capacitance
CI/O
VIL = 0 V
10
pF
1.
TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/Output capacitances double on stacked devices.
34/51
NAND512-A2C
DC and AC parameters
M
(1)
Table 18. DC characteristics, 1.8 V devices
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
Read
IDD1
-
8
15
mA
E=VIL, OUT = 0 mA
I
Operating Current
IDD2
IDD3
Program
Erase
-
-
-
-
8
8
15
15
mA
mA
E=VDD-0.2,
WP=0/VDD
IDD5
Stand-By Current (CMOS)
-
10
50
µA
ILI
ILO
Input Leakage Current
Output Leakage Current
Input High Voltage
VIN= 0 to VDDmax
VOUT= 0 to VDDmax
-
-
-
-
±10
±10
µA
µA
V
-
VIH
VDD-0.4
-
VDD+0.3
0.4
VIL
Input Low Voltage
-
-0.3
-
V
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
IOH = -100 µA
IOL = 100 µA
VOL = 0.1 V
VDD-0.1
-
-
V
-
-
0.1
V
IOL (RB)
3
4
mA
VDD Supply Voltage (Erase and
Program lockout)
VLKO
-
-
-
1.1
V
1. Leakage currents double on stacked devices.
Figure 16. Equivalent testing circuit for AC characteristics measurement
V
DD
2R
ref
NAND Flash
C
L
2R
ref
GND
GND
Ai11085
35/51
DC and AC parameters
NAND512-A2C
(1)
Table 19. DC Characteristics, 3V devices
Symbol
Parameter
Test Conditions
tRLRL minimum
E=VIL, OUT = 0 mA
Min
Typ
Max
Unit
Sequential
Read
IDD1
-
10
20
mA
I
Operating
Current
IDD2
IDD3
IDD4
IDD5
ILI
Program
Erase
-
-
-
10
10
-
20
20
mA
mA
mA
µA
µA
µA
V
-
Stand-by Current (TTL),
Stand-By Current (CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
E=VIH, WP=0V/VDD
E=VDD-0.2, WP=0/VDD
VIN= 0 to VDDmax
VOUT= 0 to VDDmax
-
-
1
-
-
10
-
50
±10
±10
VDD+0.3
0.8
ILO
-
-
VIH
2.0
−0.3
2.4
-
-
VIL
Input Low Voltage
-
-
V
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
IOH = −400µA
IOL = 2.1mA
-
-
V
-
0.4
V
IOL (RB)
VOL = 0.4V
8
10
mA
VDD Supply Voltage (Erase and
Program lockout)
VLKO
-
-
-
1.7
V
1. Leakage currents double on stacked devices.
Table 20. AC characteristics for Command, Address, Data Input
Alt.
1.8V
devices devices
3V
Symbol
Parameter
Unit
ns
Symbol
tALLWH
tALHWH
tCLHWH
tCLLWH
tDVWH
Address Latch Low to Write Enable High
Address Latch High to Write Enable High
Command Latch High to Write Enable High
Command Latch Low to Write Enable High
Data Valid to Write Enable High
tALS
AL Setup time
Min
Min
25
25
15
15
tCLS
CL Setup time
ns
tDS
tCS
Data Setup time Min
20
30
15
20
ns
ns
tELWH
Chip Enable Low to Write Enable High
Write Enable High to Address Latch High
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
E Setup time
Min
tWHALH
tWHALL
tWHCLH
tWHCLL
tWHDX
tWHEH
tALH
AL Hold time
Min
10
10
5
5
ns
ns
tCLH
CL hold time
Min
tDH
tCH
Data Hold time Min
10
10
5
5
ns
ns
Write Enable High to Chip Enable High
E Hold time
Min
Min
Min
W High Hold
time
tWHWL
tWH
Write Enable High to Write Enable Low
15
10
ns
tWLWH
tWLWL
tWP
tWC
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
W Pulse Width
25
45
15
30
ns
ns
Write Cycle time Min
36/51
NAND512-A2C
DC and AC parameters
Table 21. AC Characteristics for operations
Alt.
1.8V
3V
Symbol
Parameter
Unit
Symbol
devices devices
tALLRL1
tALLRL2
tBHRL
Read Electronic Signature
Read cycle
Min
Min
10
10
20
15
500
3
10
10
20
12
500
3
ns
ns
ns
µs
µs
ms
µs
µs
µs
µs
ns
ns
ns
ns
Address Latch Low to
Read Enable Low
tAR
tRR
Ready/Busy High to Read Enable Low
Read Busy time
Min
tBLBH1
tBLBH2
tBLBH3
Max
Max
Max
Max
Max
Max
Max
Min
tPROG
tBERS
Program Busy time
Erase Busy time
Ready/Busy Low to
Ready/Busy High
Reset Busy time, during ready
5
5
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
5
5
tBLBH4
tRST
10
500
10
0
10
500
10
0
tCLLRL
tDZRL
tEHQZ
tELQV
tCLR
tIR
tCHZ
tCEA
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Read Enable High to
Min
Max
Max
30
45
30
35
tRHRL
tREH
tRHZ
Read Enable High Hold time
Min
15
30
10
30
ns
ns
Read Enable Low
tRHQZ
tEHQX
tRHQX
Read Enable High to Output Hi-Z
Max
TOH
Chip Enable high or Read Enable high to Output Hold
Min
10
10
ns
Read Enable Low to
Read Enable Pulse Width
Read Enable High
tRLRH
tRLRL
tRP
tRC
Min
Min
25
50
15
30
ns
ns
Read Enable Low to
Read Cycle time
Read Enable Low
Read Enable Access time
Read Enable Low to
Read ES Access time(1)
Output Valid
tRLQV
tREA
Max
Max
30
15
18
12
ns
µs
Write Enable High to
Read Busy time
tWHBH
tR
Ready/Busy High
tWHBL
tWHRL
tWB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Max
Min
100
60
100
60
ns
ns
tWHR
1. ES = Electronic Signature.
37/51
DC and AC parameters
NAND512-A2C
Figure 17. Command Latch AC waveforms
CL
tCLHWH
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWH
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai13105
Figure 18. Address Latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tWLWL
tWLWL
tWLWL
tELWH
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 5
Adrress
cycle 1
ai13106
38/51
NAND512-A2C
DC and AC parameters
Figure 19. Data Input Latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai13107
Figure 20. Sequential Data Output after Read AC waveforms
tEHQX
tEHQZ
1. CL = Low, AL = Low, W = High.
39/51
DC and AC parameters
NAND512-A2C
Figure 21. Read Status Register AC waveforms
tEHQX
Figure 22. Read Electronic Signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
Man.
code
Device
code
I/O
90h
00h
Read Electronic 1st Cycle
Manufacturer and
Device Codes
Signature
Command
Address
ai08039b
1. Refer to Table 12 for the values of the Manufacturer and Device Codes.
40/51
NAND512-A2C
DC and AC parameters
Figure 23. Page Read A/ Read B operation AC waveform
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
Data
N
Data
N+1
Data
N+2
Data
Last
00h or
01h
Add.N Add.N Add.N
cycle 2 cycle 3 cycle 4
Add.N
cycle 1
Data Output
from Address N to Last Byte or Word in Page
Command
Code
Address N Input
Busy
tRHQX
tEHQX
ai08033c
41/51
DC and AC parameters
NAND512-A2C
Figure 24. Read C operation, One Page AC waveform
CL
E
W
tWHBH
tWHALL
AL
tALLRL2
tBHRL
R
Data
Last
Add. M Add. M Add. M Add. M
cycle 1 cycle 2 cycle 3 cycle 4
I/O
RB
50h
Data M
Command
Code
Data Output from M to
Last Byte or Word in Area C
Address M Input
Busy
ai08035b
1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’.
42/51
NAND512-A2C
DC and AC parameters
Figure 25. Page Program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tBLBH2
(Program Busy time)
AL
R
Add.N
Add.N Add.N
cycle 1 cycle 2
Add.N
cycle 3
I/O
RB
80h
Last
N
10h
70h
SR0
cycle 4
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai08037
43/51
DC and AC parameters
NAND512-A2C
Figure 26. Block Erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
AL
R
tBLBH3
tWHBL
(Erase Busy time)
Add.
Add.
Add.
I/O
RB
60h
D0h
70h
SR0
cycle 1 cycle 2
cycle 3
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038b
Figure 27. Reset AC waveform
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
44/51
NAND512-A2C
DC and AC parameters
10.1
Ready/Busy signal electrical characteristics
Figure 28, Figure 29 and Figure 30 show the electrical characteristics for the Ready/Busy
signal. The value required for the resistor R can be calculated using the following equation:
P
(
–
)
V
V
DDmax
OLmax
+ I
R min= -------------------------------------------------------------
P
I
L
OL
So,
1.85V
R min(1.8V)= ---------------------------
P
+
3mA
I
L
3.2V
R min(3V)= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R
L
P
max is determined by the maximum value of t .
r
Figure 28. Ready/Busy AC waveform
ready V
DD
V
OH
V
OL
busy
t
t
r
f
AI07564B
Figure 29. Ready/Busy load circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
45/51
DC and AC parameters
NAND512-A2C
Figure 30. Resistor value versus waveform timings for Ready/Busy signal
V
= 1.8V, C = 30pF
V = 3.3V, C = 100pF
DD L
DD
L
400
300
200
400
300
200
4
3
2
4
400
3
2
300
2.4
200
1.7
120
1.2
100
0
1
100
0
1
0.85
0.8
100
3.6
90
0.57
0.6
3.6
60
1.7
0.43
1.7
30
1.7
3.6
3.6
1.7
1
2
3
4
1
2
3
4
R
(KΩ)
R (KΩ)
P
P
t
t
r
ibusy
f
ai07565B
1. T = 25°C.
10.2
Data Protection
The Numonyx NAND device is designed to guarantee Data Protection during Power
Transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
low (V ) to guarantee hardware protection during power transitions as shown in the below
IL
figure.
Figure 31. Data Protection
Nominal Range
V
DD
V
LKO
Locked
Locked
WP
Ai13188
46/51
NAND512-A2C
Package mechanical
11
Package mechanical
Figure 32. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0°
5°
0°
5°
47/51
Package mechanical
NAND512-A2C
Figure 33. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline
D
D2
D1
FD1
FE
e
SE
b
E
E2 E1
ddd
BALL "A1"
FE1
A
A2
e
SD
FD
A1
BGA-Z75
1. Drawing is not to scale.
Table 23. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.05
0.041
0.25
0.010
0.70
0.50
9.10
0.028
0.020
0.358
0.45
9.00
4.00
7.20
0.40
8.90
0.018
0.354
0.157
0.283
0.016
0.350
D
D1
D2
ddd
E
0.10
0.004
0.437
11.00
5.60
8.80
0.80
2.50
0.90
2.70
1.10
0.40
0.40
10.90
–
11.10
0.433
0.220
0.346
0.031
0.098
0.035
0.106
0.043
0.016
0.016
0.429
–
E1
E2
e
–
–
FD
FD1
FE
FE1
SD
SE
–
–
–
–
–
–
–
–
48/51
NAND512-A2C
Ordering information
12
Ordering information
Table 24. Ordering information scheme
Example:
NAND512R3A
2
C
ZA
6
E
Device type
NAND = NAND Flash memory
Density
512 = 512Mb
Operating voltage
R = VDD = 1.7 to 1.95 V
W = VDD = 2.7 to 3.6 V
Bus width
3 = x 8
4 = x 16(1)
Family identifier
A = 528 bytes/ 264 word page
Device options
2 = Chip Enable Don’t Care Enabled
Product version
C = Third Version
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA63 9 x 11 x 1 mm, 6 x 8 ball array, 0.8 mm pitch
Temperature range
6 = –40 to 85 °C
Option
E = ECOPACK package, standard packing
F = ECOPACK package, tape & reel packing
1. x16 organization available for MCP only.
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest
Numonyx Sales Office.
49/51
Revision history
NAND512-A2C
13
Revision history
Table 25. Document revision history
Date
Revision
Changes
26-Oct-2006
0.1
Initial release.
Datasheet status upgraded to ‘Full datasheet’.
USOP48 package removed.
08-Feb-2007
04-Jan-2008
1
2
Data integrity of 100,000 specified for ECC implemented.
tWHBH1 removed from Table 21: AC Characteristics for operations.
Applied Numonyx branding.
50/51
NAND512-A2C
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
51/51
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