NAND512R4A0DN6E [NUMONYX]
Flash, 32MX16, 15000ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48;
| 型号： | NAND512R4A0DN6E |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 32MX16, 15000ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 光电二极管 内存集成电路 |
| 文件： | 总53页 (文件大小：1334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND512xxA2D
NAND01GxxA2C
512-Mbit, 1-Gbit, 528-byte/264-word page,
1.8 V/3 V, SLC NAND flash memories
Features
●
High density SLC NAND flash memories
–
–
512-Mbit, 1-Gbit memory array
Cost effective solutions for mass
storage applications
●
NAND interface
TSOP48 12 x 20 mm (N)
–
–
x8 or x16 bus width
Multiplexed address/ data
FBGA
●
●
Supply voltage: 1.8 V, 3 V
Page size
VFBGA63 9 x 11 x 1.05 mm (ZA)
–
–
x8 device: (512 + 16 spare) bytes
x16 device: (256 + 8 spare) words
●
●
Block size
●
●
Hardware data protection: program/erase
locked during power transitions
–
–
x8 device: (16 K + 512 spare) bytes
x16 device: (8 K + 256 spare) words
Security features
Page read/program
–
–
OTP area
–
–
–
Random access:
12 µs (3 V)/15 µs (1.8 V) (max)
Serial number (unique ID)
●
Data integrity
Sequential access:
30 ns (3 V)/50 ns (1.8 V) (min)
–
100,000 program/erase cycles (with
ECC)
Page program time: 200 µs (typ)
–
10 years data retention
●
●
●
●
●
Copy back program mode
Fast block erase: 1.5 ms (typ)
Status register
●
●
RoHS compliant packages
Development tools
–
–
Error correction code models
Electronic signature
Bad blocks management and wear
leveling algorithms
Chip Enable ‘don’t care’
–
Hardware simulation models
Table 1.
Device summary
NAND512xxA2D
NAND01GxxA2C
NAND512R3A2D
NAND512R4A2D
NAND512W3A2D
NAND512W4A2D
NAND01GR3A2C
NAND01GR4A2C
NAND01GW3A2C
NAND01GW4A2C
November 2009
Rev 7
1/53
www.numonyx.com
1
Contents
NAND512xxA2D, NAND01GxxA2C
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
V
DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
4.4
4.5
4.6
Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
6.2
Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2.1
6.2.2
6.2.3
Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/53
NAND512xxA2D, NAND01GxxA2C
Contents
6.3
6.4
6.5
6.6
6.7
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7.1
6.7.2
6.7.3
6.7.4
Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 27
6.8
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
7.4
7.5
7.6
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.6.1
7.6.2
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 33
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 45
10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11
12
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
List of tables
NAND512xxA2D, NAND01GxxA2C
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signals names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 33
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC characteristics, 1.8 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC characteristics, 3 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 48
VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package mechanical data . . . . . 50
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/53
NAND512xxA2D, NAND01GxxA2C
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VFBGA63 connections - x8 devices (top view through package). . . . . . . . . . . . . . . . . . . . 10
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. Page read A/ read B operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 25. Read C operation, one page AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 26. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 27. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 29. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 30. Program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 31. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 33. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 47
Figure 34. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 35. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 48
Figure 36. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package outline . . . . . . . . . . . . . 49
5/53
Description
NAND512xxA2D, NAND01GxxA2C
1
Description
The NAND flash 528-byte/264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page family.
The NAND512xxA2D and NAND01GxxA2C devices have a density of 512 Mbits and 1 Gbit,
respectively. They operate with either a 1.8 V or 3 V voltage supply. The size of a page is
either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
To extend the lifetime of NAND flash devices it is mandatory to implement an error
correction code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.
The devices feature an open-drain ready/busy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page program operation fails, the data can be programmed in another page without having
to resend the data to be programmed.
The NAND512xxA2D devices are available in the TSOP48 (12 x 20 mm) and VFBGA63
(9 x 11 x 1.05 mm) packages while the NAND01GxxA2C devices are only available in the
TSOP48 (12 x 20 mm) package.
The NAND512xxA2D and NAND01GxxA2C devices are available in two different versions:
●
No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
●
With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are simultaneously active as Chip Enable transitions during
latency do not stop read operations. Program and erase operations are not interrupted
by Chip Enable transitions.
and come with two security features:
●
OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
●
Serial number (unique identifier), which enables each device to be uniquely identified. It
is subject to an NDA and is, therefore, not described in the datasheet.
For more details about these security features, contact your nearest Numonyx sales office.
For information on how to order these options refer to Table 24: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
Table 2: Product description lists the part numbers and other information for all the devices
in the family.
6/53
NAND512xxA2D, NAND01GxxA2C
Description
Table 2.
Product description
Timings
Random Sequential
Bus
width
Page
size
Block
size
Memory
array
Operating
voltage
Reference
Part number
Density
Package
Page
Block
access
Max
access
Min
program erase
Typ
Typ
NAND512R3A2D
NAND512W3A2D
NAND512R4A2D
NAND512W4A2D
NAND01GR3A2C
NAND01GW3A2C
NAND01GR4A2C
NAND01GW4A2C
1.7 to 1.95 V
2.7 to 3.6 V
1.7 to 1.95 V
2.7 to 3.6 V
1.7 to 1.95 V
2.7 to 3.6 V
1.7 to 1.95 V
2.7 to 3.6 V
15 µs
12 µs
15 µs
12 µs
15 µs
12 µs
15 µs
12 µs
50 ns
30 ns
50 ns
30 ns
50 ns
30 ns
50 ns
30 ns
512+16 16K+512
x8
x16
x8
bytes
bytes
512
Mbits
32 pages x
4096 blocks
TSOP48
VFBGA63
NAND512xxA2D
256+8
words
8K+256
words
200 µs
2 ms
512+16 16K+512
bytes
bytes
32 pages x
8192 blocks
NAND01GxxA2C
1 Gbit
TSOP48
256+8
words
8K+256
words
x16
Figure 1.
Logic diagram
V
DD
8
I/O8-I/O15, x16
E
I/O0-I/O7, x8/x16
R
W
NAND flash
RB
AL
CL
WP
V
SS
AI07557C
7/53
Description
NAND512xxA2D, NAND01GxxA2C
Table 3.
Signal
Signals names
Function
Data input/outputs for x16 devices
Direction
I/O8-I/O15
I/O0-I/O7
I/O
Data inputs/outputs, address inputs, or command inputs for x8 and
x16 devices
I/O
AL
CL
E
Address Latch Enable
Command Latch Enable
Chip Enable
Input
Input
Input
R
Read Enable
Input
RB
W
Ready/Busy (open-drain output)
Write Enable
Output
Input
WP
VDD
VSS
NC
DU
Write Protect
Input
Supply voltage
Power supply
Ground
–
Ground
Not connected internally
Do not use
–
Figure 2.
Logic block diagram
Address
register/counter
AL
CL
W
NAND flash
memory array
P/E/R controller,
high voltage
generator
Command
interface
logic
E
WP
R
Page buffer
Y decoder
Command register
I/O buffers & latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI07561c
8/53
NAND512xxA2D, NAND01GxxA2C
Description
Figure 3.
TSOP48 connections - x8 devices
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
NAND flash
(x8)
V
12
13
37
36
V
V
DD
DD
SS
V
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI07585C
9/53
Description
Figure 4.
NAND512xxA2D, NAND01GxxA2C
VFBGA63 connections - x8 devices (top view through package)
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
AL
V
SS
C
WP
E
W
RB
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
G
H
J
NC
NC
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI13103
10/53
NAND512xxA2D, NAND01GxxA2C
Memory array organization
2
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 bytes each and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 5: Memory array organization.
Bad blocks
The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 7.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4.
Valid blocks
Density of device
Min
Max
512 Mbits
1 Gbit
4016
8032
4096
8192
11/53
Memory array organization
NAND512xxA2D, NAND01GxxA2C
Figure 5.
Memory array organization
x8 DEVICES
x16 DEVICES
Block = 32 pages
Block = 32 pages
Page = 528 bytes (512+16)
Page = 264 words (256+8)
Spare area
Spare area
Main area
1st half page 2nd half page
(256 bytes) (256 bytes)
Block
Page
Block
Page
8 bits
16 bits
256 words
8
512 bytes
16
bytes
words
Page buffer, 264 words
8
Page buffer, 512 bytes
16
256 words
words
512 bytes
16 bits
bytes
8 bits
AI07587
12/53
NAND512xxA2D, NAND01GxxA2C
Signals description
3
Signals description
See Figure 1: Logic diagram, and Table 3: Signals names, for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Inputs/outputs 0 to 7 are used to input the selected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Inputs/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
3.4
3.5
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and read
circuitry. When Chip Enable is Low, V , the device is selected.
IL
If Chip Enable goes High (V ) while the device is busy programming or erasing, the device
IH
remains selected and does not go into standby mode.
While the device is busy reading:
●
●
the Chip Enable input should be held Low during the whole busy time (t
devices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
) for
BLBH1
for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the busy time (t
go into standby mode.
) will not interrupt the read operation and the device will not
BLBH1
13/53
Signals description
NAND512xxA2D, NAND01GxxA2C
3.6
Read Enable (R)
The Read Enable, R, controls the sequential data output during read operations. Data is
valid t
after the falling edge of R. The falling edge of R also increments the internal
RLQV
column address counter by one.
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
3.8
3.9
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V , the device does not accept any
program or erase operations.
IL
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, V , a read, program or erase operation is in progress. When the
OL
operation completes Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. During the recovery time the RB signal is
Low, V
.
OL
Refer to the Section 10.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V is below the V
threshold
LKO
DD
(see Figure 34: Data protection) to protect the device from any involuntary program/erase
operations during power-transitions.
Each device in a system should have V decoupled with a 0.1 µF capacitor. The PCB track
DD
widths should be sufficient to carry the required program and erase currents
14/53
NAND512xxA2D, NAND01GxxA2C
Signals description
3.11
VSS ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
15/53
Bus operations
NAND512xxA2D, NAND01GxxA2C
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
4.1
Command input
Command input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 18 and Table 20 for details of the timings requirements.
4.2
Address input
Address input bus operations are used to input the memory address. Three bus cycles are
required to input the addresses for the 128-Mbit and 256-Mbit devices and four bus cycles
are required to input the addresses for the 512-Mbit and 1-Gbit devices (refer to Table 6 and
Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 19 and Table 20 for details of the timings requirements.
4.3
4.4
Data input
Data input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 20, Table 20, and Table 21 for details of the timings requirements.
Data output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 21 and Table 21 for details of the timings requirements.
16/53
NAND512xxA2D, NAND01GxxA2C
Bus operations
4.5
Write protect
Write protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
Command input
Address input
Data input
VIL
VIL
VIL
VIL
X
VIL
VIH
VIL
VIL
X
VIH
VIL
VIL
VIL
X
VIH
VIH
VIH
Falling
X
Rising X(2)
Command
Address
Data input
Data output
X
X
Rising
Rising
VIH
X
X
X
Data input
Data output
Write protect
Standby
X
Data output
X
VIL
X
X
X
VIH
X
X
X
X
X
1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
(1)(2)
Table 6.
Address insertion, x8 devices
Bus
cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
4th
A7
A16
A24
VIL
A6
A15
A23
VIL
A5
A14
A22
VIL
A4
A13
A21
VIL
A3
A12
A20
VIL
A2
A11
A19
VIL
A1
A10
A0
A9
A18
A17
A25
A26(3)
1. A8 is set Low or High by the 00h or 01h command, see Section 6.1: Pointer operations.
2. Any additional address input cycles is ignored.
3. Only for 1-Gbit devices.
(1)(2)
Table 7.
Address insertion, x16 devices
I/O8-
I/O15
Bus
cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
2nd
3rd
4th
X
X
X
X
A7
A16
A24
VIL
A6
A15
A23
VIL
A5
A14
A22
VIL
A4
A13
A21
VIL
A3
A12
A20
VIL
A2
A11
A19
VIL
A1
A10
A0
A9
A18
A17
A25
A26(3)
1. A8 is don’t care in x16 devices.
2. Any additional address input cycle is ignored.
3. Only for 1-Gbit devices.
17/53
Bus operations
NAND512xxA2D, NAND01GxxA2C
Table 8.
Address definition
NAND512xxA2D
NAND01GxxA2C
Definition
Address
Definition
Address
A0 - A7
A9 - A25
A9 - A13
A14 - A25
Column address
Page address
Address in block
Block address
A0 - A7
A9 - A26
A9 - A13
A14 - A26
Column address
Page address
Address in block
Block address
A8 is set Low or High by the 00h or
01h command, and is don’t care in
x16 devices
A8 is set Low or High by the 00h or
01h command, and is don’t care in
x16 devices
A8
A8
A25
Plane address
A25, A26
Plane address
18/53
NAND512xxA2D, NAND01GxxA2C
Command set
5
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 9.
Table 9.
Commands
Command
Bus write operations(1)(2)
Command
accepted during
busy
1
st cycle
2nd cycle
3rd cycle
Read A
00h
01h
50h
90h
70h
80h
00h
60h
FFh
–
–
–
Read B(3)
–
Read C
–
–
Read Electronic Signature
Read Status Register
Page Program
–
–
–
–
Yes
Yes
10h
8Ah
D0h
–
–
Copy Back Program
Block Erase
(10h)(4)
–
–
Reset
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence is ignored by the device.
3. The Read B command (code 01h) is not used in x16 devices.
4. The Program Confirm command (code 10h) is no more necessary for NAND512xxA2D devices. It is
optional and has been maintained for backward compatibility.
19/53
Device operations
NAND512xxA2D, NAND01GxxA2C
6
Device operations
6.1
Pointer operations
As the NAND flash memories contain two different areas for x16 devices and three different
areas for x8 devices (see Figure 6) the read command codes (00h, 01h, 50h) are used to
act as pointers to the different areas of the memory array (they select the most significant
column address).
The Read A and Read B commands act as pointers to the main memory area. Their use
depends on the bus width of the device.
●
In x16 devices the Read A command (00h) sets the pointer to area A (the whole of the
main area) that is words 0 to 255.
●
In x8 devices the Read A command (00h) sets the pointer to area A (the first half of the
main area) that is bytes 0 to 255, and the Read B command (01h) sets the pointer to
area B (the second half of the main area) that is bytes 256 to 511.
In both the x8 and x16 devices the Read C command (50h), acts as a pointer to area C (the
spare memory area) that is bytes 512 to 527 or words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been executed in area B the pointer
returns automatically to area A.
The pointer operations can also be used before a program operation, that is the appropriate
code (00h, 01h or 50h) can be issued before the program command 80h is issued (see
Figure 7).
Figure 6.
Pointer operations
x8 devices
x16 devices
Area A
(00h)
Area B
(01h)
Area C
(50h)
Area A
(00h)
Area C
(50h)
bytes
words
bytes 0 - 255 bytes 256 - 511
words 0 - 255
512 - 527
256 - 263
A
B
C
Page buffer
A
C
Page buffer
Pointer
(00h,01h,50h)
Pointer
(00h,50h)
AI07592
20/53
NAND512xxA2D, NAND01GxxA2C
Device operations
Figure 7.
Pointer operations for programming
AREA A
10h
Address
Inputs
Address
Inputs
80h
I/O
00h
Data Input
80h
00h
Data Input
10h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA B
Address
Inputs
Address
Inputs
80h
I/O
01h
Data Input
10h
80h
01h
Data Input
10h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA C
Address
Inputs
Address
Inputs
80h
I/O
50h
Data Input
10h
80h
50h
Data Input
10h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
ai07591
6.2
Read memory array
Each operation to read the memory area starts with a pointer operation as shown in the
Section 6.1: Pointer operations. Once the area (main or spare) has been selected using the
Read A, Read B or Read C commands, four bus cycles (for 512-Mbit and 1-Gbit devices) or
three bus cycles (for 128-Mbit and 256-Mbit devices) are required to input the address (refer
to Table 6 and Table 7) of the data to be read.
The device defaults to read A mode after power-up or a reset operation.
When reading the spare area addresses:
●
A0 to A3 (x8 devices)
A0 to A2 (x16 devices)
●
are used to set the start address of the spare area while addresses:
●
●
A4 to A7 (x8 devices)
A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is effective for only one operation, once an operation has been executed
in area B the pointer returns automatically to area A and so another Read B command is
required to start another read operation in area B.
Once a Read command is issued two types of operations are available: random read and
page read.
6.2.1
Random read
Each time the command is issued the first read is random read.
21/53
Device operations
NAND512xxA2D, NAND01GxxA2C
6.2.2
Page read
After the random read access the page data is transferred to the page buffer in a time of
t
(refer to Table 21 for value). Once the transfer is complete the Ready/Busy signal
WHBH
goes High. The data can then be read out sequentially (from selected column address to
last column address) by pulsing the Read Enable signal.
Figure 8.
Read (A,B,C) operations
CL
E
W
AL
R
tBLBH1
(read)
RB
I/O
00h/
Data output (sequentially)
Address input
01h/ 50h
Command
code
Busy
ai07595c
6.2.3
Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed and
Chip Enable remains Low, then the next page is automatically loaded into the page buffer
and the read operation continues. A sequential row read operation can only be used to read
within a block. If the block changes a new read command must be issued. Refer to Figure 9:
Sequential row read operations and Figure 10: Sequential row read block diagrams for
details about sequential row read operations. To terminate a sequential row read operation,
set to High the Chip Enable signal for more than t
. Sequential row read is not available
EHEL
when the Chip Enable don’t care option is enabled.
22/53
NAND512xxA2D, NAND01GxxA2C
Device operations
Figure 9.
Sequential row read operations
tBLBH1
tBLBH1
tBLBH1
(Read busy time)
RB
Busy
Busy
Busy
1st
2nd
page output
Nth
00h/
I/O
Address inputs
page output
page output
01h/ 50h
Command
code
ai07597
Figure 10. Sequential row read block diagrams
Read A command, x8 devices
Read A command, x16 devices
Area B
(2nd half Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
(main area)
Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
Read B command, x8 devices
Read C command, x8/x16 devices
Area B
(2nd half Page)
Area A
(1st half Page)
Area C
(Spare)
Area A
Area A/ B
Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
AI07598
Figure 11. Read block diagrams
Read A command, x8 devices
Read A command, x16 devices
Area B
(2nd half page)
Area A
(1st half page)
Area C
(spare)
Area A
(main area)
Area C
(spare)
(1)
A9-A26
(1)
A9-A26
A0-A7
A0-A7
Read B command, x8 devices
Read C command, x8/x16 devices
Area B
(2nd half page)
Area A/ B
Area A
(1st half page)
Area C
(spare)
Area A
Area C
(spare)
(1)
A9-A26
(1)
A9-A26
A0-A3 (x 8)
A0-A2 (x 16)
A0-A7
A4-A7 (x 8), A3-A7 (x 16) are don't care
AI07596
1. Highest address depends on device density.
23/53
Device operations
NAND512xxA2D, NAND01GxxA2C
6.3
Page program
The page program operation is the standard operation to program data to the memory array.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to the Section 6.1: Pointer operations and Figure 7 for
details.
Each page program operation consists of five steps (see Figure 12):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 6 and
Table 7)
3. The data is then input (up to 528 bytes/264 words) and loaded into the page buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R controller
5. The P/E/R controller then programs the data into the array.
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted, all other commands are ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 12. Page program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Data Input
10h
Address Inputs
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai07566
1. Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1: Pointer operations for
details.
24/53
NAND512xxA2D, NAND01GxxA2C
Device operations
6.4
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails an error is signalled in the status register. However
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 words/528 bytes from the page into the page buffer
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that must be the same for the source and target
pages
3. The Program Confirm command (code 10h) is no more necessary on NAND512xxA2D
and NAND01GxxA2C devices. It is optional and has been maintained for backward
compatibility.
After a copy back program operation, a partial-page program is not allowed in the target
page until the block has been erased.
See Figure 13 for an example of the copy back operation.
Table 10. Copy back program addresses
Density
Same address for source and target pages
512 Mbits
1 Gbit
A25
A25, A26
Figure 13. Copy back operation
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Source
Target
Address Inputs
(1)
I/O
00h
8Ah
10h
70h
SR0
Address Inputs
Read
Code
Copy Back
Code
Read Status Register
ai13187
1. The Program Confirm command (code 10h) is no more necessary on NAND512xxA2D and NAND01GxxA2C devices. It is
optional and has been maintained for backward compatibility.
25/53
Device operations
NAND512xxA2D, NAND01GxxA2C
6.5
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 14):
1. One bus cycle is required to setup the Block Erase command
2. Only three bus cycles are required to input the block address. The first cycle (A0 to A7)
is not required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the
last address cycle I/O2 to I/O7 must be set to V .
IL
3. One bus cycle is required to issue the confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 14. Block erase operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
6.6
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued, refer to Table 21 for the values.
26/53
NAND512xxA2D, NAND01GxxA2C
Device operations
6.7
Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read.
The status register bits are summarized in Table 11: Status register bits. Refer to Table 11 in
conjunction with the following text descriptions.
6.7.1
Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write
protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2
6.7.3
6.7.4
P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are reserved
Table 11. Status register bits
Bit
Name
Logic level
Definition
Not protected
'1'
SR7
Write protection
'0'
Protected
'1'
P/E/R C inactive, device ready
P/E/R C active, device busy
SR6
SR5, SR4, SR3, SR2, SR1
SR0
Program/ erase/ read controller
Reserved
'0'
Don’t care
‘1’
Error – operation failed
Generic error
‘0’
No error – operation successful
27/53
Device operations
NAND512xxA2D, NAND01GxxA2C
6.8
Read electronic signature
The device contains a manufacturer code and device code. To read these codes two steps
are required:
1. first use one bus write cycle to issue the Read Electronic Signature command (90h),
followed by an address input of 00h
2. then perform two bus read operations – the first reads the manufacturer code and the
second, the device code. Further bus read operations are ignored.
Refer to Table 12: Electronic signature, for information on the addresses.
Table 12. Electronic signature
Root part number
Manufacturer code
Device code
NAND512R3A2D
NAND512W3A2D
NAND512R4A2D
NAND512W4A2D
NAND01GR3A2C
NAND01GW3A2C
NAND01GR4A2C
NAND01GW4A2C
36h
76h
20h
0046h
0056h
78h
0020h
20h
79h
0072h
0074h
0020h
28/53
NAND512xxA2D, NAND01GxxA2C
Software algorithms
7
Software algorithms
This section gives information on the software algorithms that Numonyx recommends to
implement to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 14: Program, erase times and program erase endurance cycles for value)
and it is recommended to implement garbage collection, a wear-leveling algorithm and an
error correction code, to extend the number of program and erase cycles and increase the
data retention.
To help integrate a NAND memory into an application Numonyx can provide a full range of
software solutions: file system, sector management, drivers, and code management.
Contact the nearest Numonyx sales office or visit www.numonyx.com for more details.
7.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 6th byte (x8 device)/1st
word (x16 device) in the spare area of the 1st page, does not contain FFh is a bad block.
The bad block information must be read before any erase is attempted as the bad block
information may be erased. For the system to be able to recognize the bad blocks based on
the original information it is recommended to create a bad block table following the flowchart
shown in Figure 15.
7.2
NAND flash memory failure modes
Over the lifetime of the device additional bad blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
●
Program/erase failure: in this case the block has to be replaced by copying the data to a
valid block. These additional bad blocks can be identified as attempts to program or
erase them will give errors in the status register.
As the failure of a page program operation does not affect the data in other pages in the
same block, the block can be replaced by re-programming the current data and copying
the rest of the replaced block to an available valid block. The Copy Back Program
command can be used to copy the data to a valid block. See Section 6.4: Copy back
program for more details
●
Read failure: in this case, ECC correction must be implemented. To efficiently use the
memory space, it is mandatory to recover single-bit errors, which occur during read
operations, by using ECC without replacing the whole block.
Refer to Table 13 for the procedure to follow if an error occurs during an operation.
29/53
Software algorithms
NAND512xxA2D, NAND01GxxA2C
Procedure
Table 13. NAND flash failure modes
Operation
Erase
Program
Read
Block replacement
Block replacement
ECC
Figure 15. Bad block management flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
30/53
NAND512xxA2D, NAND01GxxA2C
Software algorithms
7.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 16).
Figure 16. Garbage collection
Old area
New area (after GC)
Valid
page
Invalid
page
Free
page
(erased)
AI07599B
7.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
●
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
●
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
7.5
Error correction code
An error correction code (ECC) must be implemented in the NAND flash memories to
identify and correct errors in the data.
In this family of devices is required the implementation of an ECC algorithm able to correct
1 bit and to detect 2 bits for every 512 bytes. All the memory array must be covered by ECC,
including the spare area, when in this area sensible data are stored.
31/53
Software algorithms
NAND512xxA2D, NAND01GxxA2C
An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for
more details.
7.6
Hardware simulation models
7.6.1
Behavioral simulation models
Denali software corporation models are platform independent functional models designed to
assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and so allow
software to be developed before hardware.
7.6.2
IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC characteristics, rise/fall times and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
32/53
NAND512xxA2D, NAND01GxxA2C
Program and erase times and endurance cycles
8
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Table 14.
Table 14. Program, erase times and program erase endurance cycles
NAND flash
Parameters
Unit
Min
Typ
Max
Page program time
200
1.5
700
3
µs
ms
Block erase time
Program/erase cycles per block (with ECC)
Data retention
100,000
10
cycles
years
9
Maximum ratings
Stressing the device above the ratings listed in Table 15: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 15. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature under bias
– 50
– 65
125
150
260
2.7
4.6
2.7
4.6
°C
°C
°C
V
Storage temperature
TLEAD
Lead temperature during soldering
1.8 V devices
– 0.6
– 0.6
– 0.6
– 0.6
(1)
VIO
Input or output voltage
Supply voltage
3 V devices
1.8 V devices
3 V devices
V
V
VDD
V
1. Minimum Voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
33/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 16: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 16. Operating and AC measurement conditions
NAND flash
Parameter
Units
Min
Max
1.8 V devices
3 V devices
Grade 6
1.7
2.7
1.95
3.6
85
V
V
Supply voltage (VDD
)
Ambient temperature (TA)
–40
°C
pF
pF
V
1.8 V devices
3 V devices
1.8 V devices
3 V devices
1.8 V devices
3 V devices
30
50
Load capacitance (CL) (1 TTL GATE
and CL)
0
VDD
2.4
Input pulses voltages
0.4
V
0.9
1.5
5
V
Input and output timing ref. voltages
V
Input rise and fall times
ns
kΩ
Output circuit resistors, Rref
8.35
(1)(2)
Table 17. Capacitance
Symbol
Parameter
Test condition
Typ
Max
Unit
CIN
Input capacitance
VIN = 0 V
10
pF
Input/output
capacitance
CI/O
VIL = 0 V
10
pF
1.
TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double on stacked devices.
34/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
(1)
Table 18. DC characteristics, 1.8 V devices
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
read
IDD1
–
8
15
mA
E=VIL, OUT = 0 mA
I
Operating current
IDD2
IDD3
Program
Erase
–
–
–
–
8
8
15
15
mA
mA
E = VDD - 0.2,
WP=0/VDD
IDD5
Standby current (CMOS)
–
10
50
µA
ILI
ILO
Input leakage current
Output leakage current
Input high voltage
VIN = 0 to VDDmax
VOUT = 0 to VDDmax
–
–
–
–
–
–
–
–
4
±10
±10
µA
µA
V
–
0.8 x VDD
-0.3
VIH
VDD + 0.3
0.2 x VDD
–
VIL
Input low voltage
–
V
VOH
VOL
Output high voltage level
Output low voltage level
Output low current (RB)
IOH = -100 µA
IOL = 100 µA
VOL = 0.1 V
VDD-0.1
–
V
0.1
V
IOL (RB)
3
mA
VDD supply voltage (erase and
program lockout)
VLKO
–
–
1.1
–
V
1. Leakage currents double on stacked devices.
Figure 17. Equivalent testing circuit for AC characteristics measurement
V
DD
2R
ref
NAND flash
C
L
2R
ref
GND
GND
Ai11085
35/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
(1)
Table 19. DC characteristics, 3 V devices
Symbol
Parameter
Test conditions
tRLRL minimum
E = VIL, OUT = 0 mA
Min
Typ
Max
Unit
Sequential
read
IDD1
–
15
30
mA
I
Operating current
IDD2
IDD3
IDD4
IDD5
ILI
Program
Erase
–
–
–
15
15
–
30
30
mA
mA
mA
µA
µA
µA
V
–
Standby current (TTL),
Standby current (CMOS)
Input leakage current
Output leakage current
Input high voltage
E=VIH, WP=0V/VDD
E=VDD-0.2, WP=0/VDD
VIN= 0 to VDDmax
VOUT= 0 to VDDmax
–
–
1
–
10
–
50
–
±10
ILO
–
–
±10
VIH
0.8 x VDD
–
VDD+0.3
0.2 x VDD
–
VIL
Input low voltage
–
−0.3
2.4
–
–
V
VOH
VOL
Output high voltage level
Output low voltage level
Output low current (RB)
IOH = −400 µA
IOL = 2.1 mA
VOL = 0.4 V
–
V
–
0.4
V
IOL (RB)
8
10
mA
VDD supply voltage (erase and
program lockout)
VLKO
–
–
1.8
–
V
1. Leakage currents double on stacked devices.
Table 20. AC characteristics for command, address, data input
Alt.
1.8 V
devices devices
3 V
Symbol
Parameter
Unit
ns
symbol
tALLWH
tALHWH
tCLHWH
tCLLWH
tDVWH
Address Latch Low to Write Enable High
Address Latch High to Write Enable High
Command Latch High to Write Enable High
Command Latch Low to Write Enable High
Data Valid to Write Enable High
tALS
AL setup time
CL setup time
Min
Min
25
25
15
15
tCLS
ns
tDS
tCS
Data setup time Min
20
30
15
20
ns
ns
tELWH
Chip Enable Low to Write Enable High
Write Enable High to Address Latch High
Write Enable High to Address Latch Low
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
E setup time
Min
tWHALH
tWHALL
tWHCLH
tWHCLL
tWHDX
tWHEH
tALH
AL hold time
Min
10
10
5
5
ns
ns
tCLH
CL hold time
Min
tDH
tCH
Data hold time
E hold time
Min
Min
10
10
5
5
ns
ns
Write Enable High to Chip Enable High
W High hold
time
tWHWL
tWH
Write Enable High to Write Enable Low
Min
Min
15
10
ns
tWLWH
tWLWL
tWP
tWC
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
W pulse width
25
45
15
30
ns
ns
Write cycle time Min
36/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Table 21. AC characteristics for operations
Alt.
1.8 V
devices devices
3 V
Symbol
Parameter
Unit
symbol
tALLRL1
tALLRL2
tBHRL
Read electronic signature
Read cycle
Min
Min
10
10
20
15
500
3
10
10
20
12
500
3
ns
ns
ns
µs
µs
ms
µs
µs
µs
µs
ns
ns
ns
ns
Address Latch Low to
Read Enable Low
tAR
tRR
Ready/Busy High to Read Enable Low
Read busy time
Min
tBLBH1
tBLBH2
tBLBH3
Max
Max
Max
Max
Max
Max
Max
Min
tPROG
tBERS
Program busy time
Erase busy time
Ready/Busy Low to
Ready/Busy High
Reset busy time, during ready
5
5
Reset busy time, during read
Reset busy time, during program
Reset busy time, during erase
5
5
tBLBH4
tRST
10
500
10
0
10
500
10
0
tCLLRL
tDZRL
tEHQZ
tELQV
tCLR
tIR
tCHZ
tCEA
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Read Enable High to
Min
Max
Max
20
45
20
35
tRHRL
tREH
tRHZ
Read Enable High hold time
Min
15
30
10
30
ns
ns
Read Enable Low
tRHQZ
tEHQX
tRHQX
Read Enable High to Output Hi-Z
Max
TOH
Chip Enable High or Read Enable High to Output Hold
Min
10
10
ns
Read Enable Low to
Read Enable pulse width
Read Enable High
tRLRH
tRLRL
tRP
tRC
Min
Min
25
50
15
30
ns
ns
Read Enable Low to
Read cycle time
Read Enable Low
Read Enable access time
Read Enable Low to
Read ES access time(1)
Output Valid
tRLQV
tREA
Max
Max
30
15
18
12
ns
µs
Write Enable High to
Read busy time
tWHBH
tR
Ready/Busy High
tWHBL
tWHRL
tVHWH
tWB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Max
Min
100
60
100
60
ns
ns
tWHR
tWW
Write protection time
Min
100
100
ns
(2)
tVLWH
1. ES = electronic signature.
2. During a program/erase enable operation, tVHWH is the delay from WP High to W High. During a program/erase disable
operation, tVLWH is the delay from WP Low to W High.
37/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
Figure 18. Command Latch AC waveforms
CL
tCLHWH
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWH
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai13105
Figure 19. Address Latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tWLWL
tWLWL
tWLWL
tELWH
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
ai13106
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 5
Adrress
cycle 1
38/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Figure 20. Data Input Latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai13107
Figure 21. Sequential data output after read AC waveforms
tEHQX
tEHQZ
ai08031b
1. CL = Low, AL = Low, W = High.
39/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
Figure 22. Read status register AC waveforms
tCLHWH
tELWH
tEHQX
ai08032c
Figure 23. Read electronic signature AC waveforms
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
Man.
code
Device
code
I/O
90h
00h
Read Electronic 1st Cycle
Manufacturer and
Device Codes
Signature
Command
Address
ai08039b
1. Refer to Table 12 for the values of the manufacturer and device codes.
40/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Figure 24. Page read A/ read B operation AC waveforms
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
Data
N
Data
N+1
Data
N+2
Data
Last
00h or
01h
Add.N Add.N Add.N
cycle 2 cycle 3 cycle 4
Add.N
cycle 1
Data Output
from Address N to Last Byte or Word in Page
Command
Code
Address N Input
Busy
tRHQX
tEHQX
ai08033c
41/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
Figure 25. Read C operation, one page AC waveforms
CL
E
W
tWHBH
tWHALL
AL
tALLRL2
tBHRL
R
Data
Last
Add. M Add. M Add. M Add. M
cycle 1 cycle 2 cycle 3 cycle 4
I/O
RB
50h
Data M
Command
Code
Data Output from M to
Last Byte or Word in Area C
Address M Input
Busy
ai08035b
1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care.
42/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Figure 26. Page program AC waveforms
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tBLBH2
(Program Busy time)
AL
R
Add.N
Add.N Add.N
cycle 1 cycle 2
Add.N
cycle 3
I/O
RB
80h
Last
N
10h
70h
SR0
cycle 4
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai08037
43/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
Figure 27. Block erase AC waveforms
CL
E
tWLWL
(Write Cycle time)
W
tBLBH3
tWHBL
(Erase Busy time)
AL
R
Add.
Add.
Add.
cycle 3
I/O
60h
D0h
70h
SR0
cycle 1 cycle 2
RB
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038b
Figure 28. Reset AC waveforms
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
44/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Figure 29. Program/erase enable waveforms
W
tVHWH
WP
RB
I/O
80h
10h
ai12477
Figure 30. Program/erase disable waveforms
W
tVLWH
WP
High
RB
I/O
80h
10h
ai12478
10.1
Ready/Busy signal electrical characteristics
Figure 31, Figure 32 and Figure 33 show the electrical characteristics for the Ready/Busy
signal. The value required for the resistor R can be calculated using the following equation:
P
(
–
)
V
V
DDmax
OLmax
+ I
R min= -------------------------------------------------------------
P
I
L
OL
So,
1.85V
R min(1.8V)= ---------------------------
P
+
3mA
I
L
3.2V
R min(3V)= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the Ready/Busy signal. R
L
P
max is determined by the maximum value of t .
r
45/53
DC and AC parameters
NAND512xxA2D, NAND01GxxA2C
Figure 31. Ready/Busy AC waveform
1.8 V device - V : 0.1 V, V
: V
- 0.1 V
OL
OH
OH
DD
3.3 V device - V : 0.4 V, V
OL
: 2.4 V
ready V
DD
V
OH
V
OL
busy
t
t
r
f
NI3087
Figure 32. Ready/Busy load circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
46/53
NAND512xxA2D, NAND01GxxA2C
DC and AC parameters
Figure 33. Resistor value versus waveform timings for Ready/Busy signal
1. T = 25°C.
10.2
Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
Low (V ) to guarantee hardware protection during power transitions as shown in the figure
IL
below (Figure 34).
Figure 34. Data protection
Nominal Range
V
DD
V
LKO
Locked
Locked
WP
Ai13188
47/53
Package mechanical
NAND512xxA2D, NAND01GxxA2C
11
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 35. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 22. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.20
0.15
1.05
0.27
0.21
0.08
12.10
20.20
18.50
–
0.047
0.006
0.041
0.011
0.008
0.003
0.476
0.795
0.728
–
0.10
1.00
0.22
0.05
0.95
0.17
0.10
0.004
0.039
0.009
0.002
0.037
0.007
0.004
C
CP
D1
E
12.00
20.00
18.40
0.50
0.60
0.80
3°
11.90
19.80
18.30
–
0.472
0.787
0.724
0.020
0.024
0.031
3°
0.468
0.779
0.720
–
E1
e
L
0.50
0.70
0.020
0.028
L1
α
0°
5°
0°
5°
48/53
NAND512xxA2D, NAND01GxxA2C
Package mechanical
Figure 36. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package outline
D
D2
D1
FD1
FE
e
SE
b
E
E2 E1
ddd
BALL "A1"
FE1
A
A2
e
SD
FD
A1
BGA-Z75
1. Drawing is not to scale.
49/53
Package mechanical
NAND512xxA2D, NAND01GxxA2C
Table 23. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.05
0.041
0.25
0.010
0.65
0.45
9.00
4.00
7.20
0.026
0.018
0.354
0.157
0.283
0.40
8.90
0.50
9.10
0.016
0.350
0.020
0.358
D
D1
D2
ddd
E
0.10
0.004
0.437
11.00
5.60
8.80
10.90
0.80
11.10
0.433
0.220
0.346
0.429
E1
E2
e
0.031
FD
FD1
FE
FE1
SD
SE
2.50
0.90
2.70
1.10
0.098
0.035
0.106
0.043
0.40
0.40
0.016
0.016
50/53
NAND512xxA2D, NAND01GxxA2C
Ordering information
12
Ordering information
Table 24. Ordering information scheme
Example:
NAND512W3A
2
D
N
6
E
Device type
NAND = NAND flash memory
Density
512 = 512 Mbits
01G = 1 Gbit(1)
Operating voltage
R = VDD = 1.7 to 1.95 V
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
4 = x16
Family identifier
A = 528-byte/ 264-word page
Device options
0 = no option (Chip Enable ‘care’; sequential row read enabled)
2 = Chip Enable don’t care enabled
Product version
C = third version (only for 1-Gbit devices)
D = fourth version (only for 512-Mbit devices)
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA63 9 x 11 x 1.05 mm
Temperature range
6 = –40 to 85 °C
Option
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape & reel packing
1. 1-Gbit devices are only available in the TSOP48 package.
Note:
Not all combinations are necessarily available. For a list of available devices or for further
information on any aspect of these products, please contact your nearest Numonyx sales
office.
51/53
Revision history
NAND512xxA2D, NAND01GxxA2C
13
Revision history
Table 25. Document revision history
Date
Revision
Changes
06-Nov-2008
1
Initial release.
Document status promoted from target specification to preliminary
data. Added NAND01GxxA2C root part numbers throughout the
document.
Modified Figure 31: Ready/Busy AC waveform and Figure 33:
Resistor value versus waveform timings for Ready/Busy signal.
10-Feb-2009
2
Removed Figure 17: Error detection. References to ECOPACK
removed and replaced by information on RoHS compliance
throughout the document.
Removed information about the VFBGA55 package and added
information about the VFBGA63 package throughout the document.
27-Apr-2009
26-May-2009
3
4
Re-added information about VFBGA55 package throughout the
document and modified dimension A2 of the VFBGA63 package in
Table 23: VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch,
package mechanical data.
09-Jun-2009
10-Jul-2009
5
6
Document status promoted from preliminary data to full datasheet.
Removed information about the VFBGA55 package throughout the
document.
Modified: typical and maximum values of IDD1, IDD2 and IDD3 in
Table 18: DC characteristics, 1.8 V devices, tCS minimum value for
1.8 devices in Table 20: AC characteristics for command, address,
data input, and maximum value for tPROG in Table 21: AC
characteristics for operations.
25-Nov-2009
7
52/53
NAND512xxA2D, NAND01GxxA2C
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
53/53
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