NAND512R4B2BV1T [NUMONYX]
Flash, 32MX16, 25000ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, PLASTIC, USOP-48;型号: | NAND512R4B2BV1T |
厂家: | NUMONYX B.V |
描述: | Flash, 32MX16, 25000ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, PLASTIC, USOP-48 光电二极管 |
文件: | 总58页 (文件大小:943K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NAND512-B, NAND01G-B, NAND02G-B,
NAND04G-B, NAND08G-B
512 Mbit, 1 Gbit, 2 Gbit, 4 Gbit, 8 Gbit
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■
HIGH DENSITY NAND FLASH MEMORIES
Figure 1. Packages
–
–
–
Up to 8 Gbit memory array
Up to 64Mbit spare area
Cost effective solutions for mass storage
applications
■
NAND INTERFACE
–
–
–
x8 or x16 bus width
Multiplexed Address/ Data
Pinout compatibility for all densities
TSOP48 12 x 20mm
■
■
■
■
SUPPLY VOLTAGE
–
–
1.8V device: V = 1.7 to 1.95V
DD
3.0V device: V = 2.7 to 3.6V
DD
PAGE SIZE
USOP48 12 x 17 x 0.65mm
–
–
x8 device: (2048 + 64 spare) Bytes
x16 device: (1024 + 32 spare) Words
BLOCK SIZE
FBGA
–
–
x8 device: (128K + 4K spare) Bytes
x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
VFBGA63 9.5 x 12 x 1mm
TFBGA63 9.5 x 12 x 1.2mm
–
–
–
Random access: 25µs (max)
Sequential access: 50ns (min)
Page program time: 300µs (typ)
■
■
DATA PROTECTION
■
■
COPY BACK PROGRAM MODE
Fast page copy without external buffering
–
–
Hardware and Software Block Locking
Hardware Program/Erase locked during
Power transitions
–
CACHE PROGRAM AND CACHE READ
MODES
DATA INTEGRITY
–
Internal Cache Register to improve the
program and read throughputs
–
–
100,000 Program/Erase cycles
10 years Data Retention
RoHS COMPLIANCE
Lead-Free Components are Compliant
with the RoHS Directive
DEVELOPMENT TOOLS
■
FAST BLOCK ERASE
Block erase time: 2ms (typ)
■
■
–
–
■
■
■
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’
–
Error Correction Code software and
hardware models
–
for simple interface with microcontroller
■
SERIAL NUMBER OPTION
–
Bad Blocks Management and Wear
Leveling algorithms
–
–
–
PC Demo board with simulation software
File System OS Native reference software
Hardware simulation models
August 2005
1/58
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 1. Product List
Reference
Part Number
NAND512R3B
NAND512W3B
NAND512R4B
NAND512W4B
NAND01GR3B
NAND01GW3B
NAND01GR4B
NAND01GW4B
NAND02GR3B
NAND02GW3B
NAND02GR4B
NAND02GW4B
NAND04GR3B
NAND04GW3B
NAND04GR4B
NAND04GW4B
NAND08GR3B
NAND08GW3B
NAND08GR4B
NAND08GW4B
NAND512-B
NAND01G-B
NAND02G-B
NAND04G-B
NAND08G-B
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11
Figure 7. FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Memory Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Enable (R).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-Up Read Enable, Lock/Unlock Enable (PRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
DD
V
SS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 8. Address Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Address Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10.Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11.Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13.Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Copy Back Program x8 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Copy Back Program x16 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.Page Copy Back Program with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16.Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P/E/R Controller Bit (SR5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Cache Program Error Bit (SR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Error Bit (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SR4, SR3 and SR2 are Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Electronic Signature Byte/Word 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Blocks Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18.Blocks Unlock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Blocks Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19.Read Block Lock Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20.Block Protection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 38
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 20. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24.DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25.Equivalent Testing Circuit for AC Characteristics Measurement. . . . . . . . . . . . . . . . . . . 40
Table 22. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 26.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 29.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 30.Read Status Register AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 31.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32.Page Read Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 33.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 34.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 35.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 37.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 38.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 50
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 39.Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 40.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . 52
Table 25. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data . 52
Figure 41.USOP48 – lead Plastic Ultra Thin Small Outline,12x17 mm, Package Outline. . . . . . . . 53
Table 26. USOP48 – lead Plastic Ultra Thin Small Outline, 12x17mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 42.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 54
Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data 54
Figure 43.TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 55
Table 28. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data 55
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
SUMMARY DESCRIPTION
The NAND Flash 2112 Byte/ 1056 Word Page is a
family of non-volatile Flash memories that uses
NAND cell technology. The devices range from
512 Mbits to 8 Gbits and operate with either a 1.8V
or 3V voltage supply. The size of a Page is either
2112 Bytes (2048 + 64 spare) or 1056 Words
(1024 + 32 spare) depending on whether the de-
vice has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
throughputs for large files. During Cache Program-
ming, the device loads the data in a Cache Regis-
ter while the previous data is transferred to the
Page Buffer and programmed into the memory ar-
ray. During Cache Reading, the device loads the
data in a Cache Register while the previous data
is transferred to the I/O Buffers to be read.
All devices have the Chip Enable Don’t Care fea-
ture, which allows code to be directly downloaded
by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read oper-
ation.
All devices have the option of a Unique Identifier
(serial number), which allows each device to be
uniquely identified.
The Unique Identifier options is subject to an NDA
(Non Disclosure Agreement) and so not described
in the datasheet. For more details of this option
contact your nearest ST Sales office.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC).
The devices have hardware and software security
features:
■
A Write Protect pin is available to give a
hardware protection against program and
erase operations.
A Block Locking scheme is available to
provide user code and/or data protection.
The devices are available in the following packag-
es:
■
TSOP48 (12 x 20mm) for all products
■
■
USOP48 (12 x 17 x 0.65mm) for 512Mb
and1Gb products
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back Program command is available to
optimize the management of defective blocks.
When a Page Program operation fails, the data
can be programmed in another page without hav-
ing to resend the data to be programmed.
■
■
VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for
512Mb and 1Gb products
TFBGA63 (9.5 x 12 x 1.2mm, 0.8mm pitch) for
2Gb Dual Die products
For information on how to order these options refer
to Table 29., Ordering Information Scheme. De-
vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the de-
vices available in the family.
Each device has Cache Program and Cache Read
features which improve the program and read
7/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 2. Product Description
Timings
Bus
Width
Page
Size
Block
Size
Memory
Array
Operating
Voltage
Random
Access
(max)
Sequential
Access
(min)
Page
Program
(typ)
Reference Part Number Density
Packages
Block
Erase (typ)
NAND512R3B
NAND512W3B
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
1.7 to 1.95V
2.7 to 3.6V
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
25µs
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
60ns
50ns
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
300µs
2048+64 128K+4K
Bytes Bytes
x8
x16
x8
TSOP48
USOP48
VFBGA63
64 Pages x
512 Blocks
NAND512-B
NAND01G-B
NAND02G-B
NAND04G-B
NAND08G-B
512Mbit
1Gbit
2Gbit
4Gbit
8Gbit
2ms
2ms
2ms
2ms
2ms
NAND512R4B
NAND512W4B
NAND01GR3B
NAND01GW3B
NAND01GR4B
NAND01GW4B
NAND02GR3B
NAND02GW3B
NAND02GR4B
NAND02GW4B
NAND04GR3B
NAND04GW3B
NAND04GR4B
NAND04GW4B
NAND08GR3B
NAND08GW3B
NAND08GR4B
NAND08GW4B
1024+32 64K+2K
Words Words
2048+64 128K+4K
Bytes Bytes
TSOP48
USOP48
VFBGA63
64 Pages x
1024 Blocks
1024+32 64K+2K
Words Words
x16
x8
2048+64 128K+4K
Bytes Bytes
64 Pages x
2048 Blocks
TSOP48(1)
TFBGA63(2)
1024+32 64K+2K
Words Words
x16
x8
2048+64 128K+4K
Bytes Bytes
64 Pages x
4096 Blocks
TSOP48
TSOP48
1024+32 64K+2K
Words Words
x16
x8
2048+64 128K+4K
Bytes Bytes
64 Pages x
8192 Blocks
1024+32 64K+2K
Words Words
x16
Note: 1. Both Single and Dual Die devices.
2. Dual Die devices only.
Figure 2. Logic Block Diagram
Address
Register/Counter
AL
CL
W
NAND Flash
Memory Array
P/E/R Controller,
High Voltage
Generator
Command
Interface
Logic
E
WP
R
Page Buffer
Cache Register
Y Decoder
PRL
Command Register
I/O Buffers & Latches
RB
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
AI09373b
8/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 3. Signal Names
Figure 3. Logic Diagram
I/O8-15
Data Input/Outputs for x16 devices
V
Data Input/Outputs, Address Inputs,
or Command Inputs for x8 and x16
devices
DD
I/O0-7
I/O8-I/O15, x16
AL
CL
E
Address Latch Enable
Command Latch Enable
Chip Enable
E
R
I/O0-I/O7, x8/x16
W
R
Read Enable
NAND Flash
AL
RB
RB
W
Ready/Busy (open-drain output)
Write Enable
CL
WP
Write Protect
WP
Power-Up Read Enable, Lock/Unlock
Enable
PRL
PRL
V
Supply Voltage
Ground
DD
V
SS
V
SS
NC
DU
Not Connected Internally
Do Not Use
AI09372b
9/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 4. TSOP48 and USOP48 Connections,
x8 devices
Figure 5. TSOP48 and USOP48 Connections,
x16 devices
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
V
SS
NC
I/O15
I/O7
NC
NC
I/O14
I/O6
I/O7
I/O6
I/O5
I/O4
NC
I/O13
I/O5
I/O12
E
E
I/O4
(1)
(1)
(1)
(1)
NC
NC
NC
NC
V
NC
NC
NC
NC
NAND Flash
(x8)
NAND Flash
(x16)
V
12
13
37
36
V
12
13
37
36
V
DD
DD
DD
DD
V
V
V
NC
NC
SS
SS
SS
NC
NC
NC
NC
CL
AL
W
NC
NC
NC
(1)
(1)
(1)
(1)
NC
CL
AL
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
24
25
V
SS
AI07585C
AI07559C
Note: 1. This pin is DU in the USOP48 package
Note: 1. This pin is DU in the USOP48 package
10/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 6. FBGA63 Connections, x8 devices (Top view through package)
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
AL
V
SS
C
WP
E
W
RB
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
NC
G
H
J
NC
NC
PRL
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI09376
11/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 7. FBGA63 Connections, x16 devices (Top view through package)
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
V
SS
C
WP
AL
E
W
RB
D
E
F
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O1
NC
NC
NC
NC
NC
NC
G
H
J
NC
NC
I/O5
I/O12
I/O7
I/O14
PRL
I/O8
I/O0
I/O10
V
DD
V
I/O9
I/O2
I/O3
I/O6
I/O15
DD
V
K
L
I/O11
I/O4
I/O13
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI09377
12/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures
where 32 cells are connected in series.
The Bad Block Information is written prior to ship-
ping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
The memory array is organized in blocks where
each block contains 64 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a 2048 Byte
main area and a spare area of 64 Bytes. In the x16
devices the pages are split into a 1,024 Word main
area and a 32 Word spare area. Refer to Figure
8., Memory Array Organization.
Table 4. Valid Blocks
Density of Device
8 Gbits
Min
8032
4016
2008
1004
502
Max
8192
4096
2048
1024
512
Bad Blocks
The NAND Flash 2112 Byte/ 1056 Word Page de-
vices may contain Bad Blocks, that is blocks that
contain one or more invalid bits whose reliability is
not guaranteed. Additional Bad Blocks may devel-
op during the lifetime of the device.
4 Gbits
2 Gbits
1Gbit
512 Mbits
Figure 8. Memory Array Organization
x8 DEVICES
x16 DEVICES
Block = 64 Pages
Block = 64 Pages
Page = 2112 Bytes (2,048 + 64)
Page = 1056 Words (1024 + 32)
Main Area
Main Area
Block
Page
Block
Page
8 bits
16 bits
2048 Bytes
64
1024 Words
32
Words
Bytes
Page Buffer, 1056 Words
32
Page Buffer, 2112 Bytes
64
1,024 Words
Words
2,048 Bytes
16 bits
Bytes
8 bits
AI09854
13/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
SIGNAL DESCRIPTIONS
See Figure 3., Logic Diagram, and Table
3., Signal Names, for a brief overview of the sig-
nals connected to this device.
left unconnected (Not Connected) or connected to
V
.
SS
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 10µs (min) is required before the Command In-
terface is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
Write Protect (WP). The Write Protect pin is an
input that gives a hardware protection against un-
wanted program or erase operations. When Write
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Protect is Low, V , the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin
IL
Low, V , during power-up and power-down.
IL
Address Latch Enable (AL). The Address Latch
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write En-
able.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, V , a read, program or
OL
erase operation is in progress. When the operation
Command Latch Enable (CL). The Command
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
completes Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
Refer to the Ready/Busy Signal Electrical Charac-
teristics section for details on how to calculate the
value of the pull-up resistor.
low, V , the device is selected. If Chip Enable
IL
goes high, v , while the device is busy, the device
remains selected and does not go into standby
mode.
IH
V
Supply Voltage. V
provides the power
DD
DD
supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An internal voltage detector disables all functions
whenever V
1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-tran-
sitions.
Read Enable (R). The Read Enable pin, R, con-
trols the sequential data output during Read oper-
is below 2.5V (for 3V devices) or
DD
ations. Data is valid t
after the falling edge of
RLQV
R. The falling edge of R also increments the inter-
nal column address counter by one.
Each device in a system should have V decou-
DD
Power-Up Read Enable, Lock/Unlock Enable
(PRL). The Power-Up Read Enable, Lock/Unlock
Enable input, PRL, is used to enable and disable
pled with a 0.1µF capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
the lock mechanism. When PRL is High, V , the
IH
device is in Block Lock mode.
If the Power-Up Read Enable, Lock/Unlock En-
able input is not required, the PRL pin should be
V
Ground. Ground, V
is the reference for
SS
SS,
the power supply. It must be connected to the sys-
tem ground.
14/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
BUS OPERATIONS
There are six standard bus operations that control
the memory. Each of these is described in this
section, see Table 5., Bus Operations, for a sum-
mary.
Typically, glitches of less than 5 ns on Chip En-
able, Write Enable and Read Enable are ignored
by the memory and do not affect bus operations.
Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See Figure 28. and Table 23. and Table 24. for de-
tails of the timings requirements.
Command Input
Data Output
Command Input bus operations are used to give
commands to the memory. Commands are ac-
cepted when Chip Enable is Low, Command Latch
Enable is High, Address Latch Enable is Low and
Read Enable is High. They are latched on the ris-
ing edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 26. and Table 23. for details of the tim-
ings requirements.
Data Output bus operations are used to read: the
data in the memory array, the Status Register, the
lock status, the Electronic Signature and the
Unique Identifier.
Data is output when Chip Enable is Low, Write En-
able is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read En-
able signal.
Address Input
See Figure 29. and Table 24. for details of the tim-
ings requirements.
Address Input bus operations are used to input the
memory addresses. Four bus cycles are required
to input the addresses for the 512Mb and 1Gb de-
vices whereas five bus cycles are required for the
2Gb, 4Gb and 8Gb devices (refer to Table 6. and
Table 7., Address Insertion).
The addresses are accepted when Chip Enable is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. Only I/O0 to I/O7 are used to input
addresses.
Write Protect
Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be al-
tered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby
See Figure 27. and Table 23. for details of the tim-
ings requirements.
When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.
Data Input
Data Input bus operations are used to input the
data to be programmed.
Table 5. Bus Operations
(1)
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15
(2)
V
V
V
V
Command Input
Address Input
Data Input
Rising
Rising
Rising
Command
Address
Data Input
Data Output
X
X
IL
IL
IL
IL
IL
IH
IH
IH
IH
X
V
V
V
V
IH
V
V
V
X
X
IL
V
V
V
IH
Data Input
IL
IL
V
V
V
IH
Data Output
Write Protect
Falling
X
Data Output
IL
IL
V
IL
X
X
X
X
X
X
X
X
X
X
X
V
IH
V /V
IL DD
Standby
X
Note: 1. Only for x16 devices.
2. WP must be V when issuing a program or erase command.
IH
15/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 6. Address Insertion, x8 Devices
Bus Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A1
I/O0
A0
st
A7
A6
A5
A4
A3
A2
1
nd
V
V
V
V
A11
A15
A23
A10
A14
A22
A30
A9
A8
IL
IL
IL
IL
2
rd
A19
A27
A18
A26
A17
A25
A16
A24
A13
A21
A29
A12
A20
A28
3
th
4
th(2)
V
IL
V
IL
V
V
IL
V
IL
IL
5
Note: 1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb, 4Gb and 8Gb devices. A28 is for 2Gb devices, A29-A28 are for 4Gb devices and A30-A28 for 8Gb
devices only.
Table 7. Address Insertion, x16 Devices
Bus
Cycle
I/O8-
I/O15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
st
X
X
X
X
X
A7
A6
A5
A4
A3
A2
A1
A9
A0
A8
1
nd
V
V
IL
V
V
IL
V
IL
A10
A13
A21
A29
IL
IL
2
rd
A18
A26
A17
A25
A16
A24
A15
A23
A14
A22
A12
A20
A28
A11
A19
A27
3
th
4
th(2)
V
V
IL
V
V
IL
V
IL
IL
IL
5
Note: 1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb, 4Gb and 8Gb devices. A27 is for 2Gb devices, A28-A27 are for 4Gb devices and A29-A27 for 8Gb
devices.
16/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 8. Address Definitions, x8
Address
A0 - A11
Definition
Column Address
Page Address
A12 - A17
A18 - A26
A18 - A27
A18 - A28
A18 - A29
A18 - A30
Block Address
Block Address
Block Address
Block Address
Block Address
512Mb device
1Gb device
2Gb device
4Gb device
8Gb device
Table 9. Address Definitions, x16
Address
Definition
Column Address
Page Address
A0 - A10
A11 - A16
A17 - A25
A17 - A26
A17 - A27
A17 - A28
A17 - A29
Block Address
Block Address
Block Address
Block Address
Block Address
512Mb device
1Gb device
2Gb device
4Gb device
8Gb device
17/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
COMMAND SET
All bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand Register. The two-step command
sequences for program and erase operations are
imposed to maximize data security.
The Commands are summarized in Table
10., Commands.
Table 10. Commands
(1)
Commands
accepted
during busy
Bus Write Operations
Command
st
nd
rd
th
1
CYCLE
2
CYCLE
3
CYCLE
4
CYCLE
(2)
Read
30h
E0h
31h
–
–
–
–
–
–
–
–
–
00h
Random Data Output
Cache Read
05h
00h
34h
(3)
Exit Cache Read
Yes
Page Program
(Sequential Input default)
80h
10h
–
–
Random Data Input
Copy Back Program
Cache Program
Block Erase
85h
00h
80h
60h
FFh
90h
70h
7Ah
23h
2Ah
2Ch
–
35h
15h
D0h
–
–
85h
–
–
10h
–
–
–
Reset
–
–
Yes
Yes
Read Electronic Signature
Read Status Register
Read Block Lock Status
Blocks Unlock
–
–
–
–
–
–
–
–
–
24h
–
–
–
Blocks Lock
–
–
Blocks Lock-Down
–
–
–
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
2. For consecutive Read operations the 00h command does not need to be repeated.
3. Only during Cache Read busy.
18/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
DEVICE OPERATIONS
The following section gives the details of the de-
vice operations.
(refer to Table 24. for value). Once the transfer is
complete the Ready/Busy signal goes High. The
data can then be read out sequentially (from se-
lected column address to last column address) by
pulsing the Read Enable signal.
Read Memory Array
At Power-Up the device defaults to Read mode.
To enter Read mode from another mode the Read
command must be issued, see Table
10., Commands. Once a Read command is is-
sued, subsequent consecutive Read commands
only require the confirm command code (30h).
The device can output random data in a page, in-
stead of the consecutive sequential data, by issu-
ing a Random Data Output command.
The Random Data Output command can be used
to skip some data during a sequential data output.
The sequential operation can be resumed by
changing the column address of the next data to
be output, to the address which follows the Ran-
dom Data Output command.
Once a Read command is issued two types of op-
erations are available: Random Read and Page
Read.
Random Read. Each time the Read command is
issued the first read is Random Read.
The Random Data Output command can be is-
sued as many times as required within a page.
The Random Data Output command is not accept-
ed during Cache Read operations.
Page Read. After the first Random Read access,
the page data (2112 Bytes or 1056 Words) is
transferred to the Page Buffer in a time of t
WHBH
Figure 9. Read Operations
CL
E
W
AL
R
tBLBH1
RB
Address Input
I/O
00h
30h
Data Output (sequentially)
Command
Code
Command
Code
Busy
ai08657b
Note: 1. Highest address depends on device density.
19/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 10. Random Data Output During Sequential Data Output
tBLBH1
(Read Busy time)
RB
Busy
R
Address
Inputs
Address
Inputs
30h
E0h
I/O
00h
05h
Data Output
Data Output
Cmd
Cmd
Cmd
Cmd
Code
Code
Code
Code
5 Add cycles
2Add cycles
Row Add 1,2,3 Col Add 1,2
Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08658
20/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Read
The Cache Read operation is used to improve the
read throughput by reading data using the Cache
Register. As soon as the user starts to read one
page, the device automatically loads the next page
into the Cache Register.
An Cache Read operation consists of three steps
(see Table 10.):
terrupted after the latency time (t
ure 11.
The Ready/Busy signal can be used to monitor the
start of the operation. During the latency period the
Ready/Busy signal goes Low, after this the Ready/
Busy signal goes High, even if the device is inter-
nally downloading page n+1.
), see Fig-
BLBH1
1. One bus cycle is required to setup the Cache
Read command (the same as the standard
Read command)
Once the Cache Read operation has started, the
Status Register can be read using the Read Status
Register command.
2. Four or Five (refer to Table 6. and Table 7.)
bus cycles are then required to input the Start
Address
3. One bus cycle is required to issue the Cache
Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a
page (Column Address = 00h, see Table 8. and
Table 9.). This allows the data to be output unin-
During the operation, SR5 can be read, to find out
whether the internal reading is ongoing (SR5 =
‘0’), or has completed (SR5 = ‘1’), while SR6 indi-
cates whether the Cache Register is ready to
download new data.
To exit the Cache Read operation an Exit Cache
Read command must be issued (see Table 10.).
If the Exit Cache Read command is issued while
the device is internally reading page n+1, page n
will still be output, but not page n+1.
Figure 11. Cache Read Operation
tBLBH1
(Read Busy time)
RB
Busy
Address
last page
34h
I/O
31h
00h
1st page
2nd page 3rd page
Block N
Inputs
Exit
Cache
Read
Code
Read
Setup
Code
Cache
Read
Confirm
Code
Data Output
ai08661
21/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Page Program
5. the P/E/R Controller then programs the data
into the array.
The Page Program operation is the standard oper-
ation to program data to the memory array. Gener-
ally, data is programmed sequentially, however
the device does support Random Input within a
page.
Random Data Input. During a Sequential Input
operation, the next sequential address to be pro-
grammed can be replaced by a random address,
by issuing a Random Data Input command. The
following two steps are required to issue the com-
mand:
The memory array is programmed by page, how-
ever partial page programming is allowed where
any number of Bytes (1 to 2112) or Words (1 to
1056) can be programmed.
The maximum number of consecutive partial page
program operations allowed in the same page is
eight. After exceeding this a Block Erase com-
mand must be issued before any further program
operations can take place in that page.
1. one bus cycle is required to setup the Random
Data Input command (see Table 10.)
2. two bus cycles are then required to input the
new column address (refer to Table 6.)
Random Data Input can be repeated as often as
required in any given page.
Sequential Input. To input data sequentially the
addresses must be sequential and remain in one
block.
For Sequential Input each Page Program opera-
tion consists of five steps (see Figure 12.):
1. one bus cycle is required to setup the Page
Program (Sequential Input) command (see
Table 10.)
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During program operations
the Status Register will only flag errors for bits set
to '1' that have not been successfully programmed
to '0'.
During the program operation, only the Read Sta-
tus Register and Reset commands will be accept-
ed, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to ‘1’ and the Ready/
Busy signal goes High.
The device remains in Read Status Register mode
until another valid command is written to the Com-
mand Interface.
2. four or five bus cycles are then required to
input the program address (refer to Table 6.
and Table 7.)
3. the data is then loaded into the Data Registers
4. one bus cycle is required to issue the Page
Program confirm command to start the P/E/R
Controller. The P/E/R will only start if the data
has been loaded in step 3.
Figure 12. Page Program Operation
tBLBH2
(Program Busy time)
RB
I/O
Busy
Data Input
10h
Address Inputs
80h
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai08659
22/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 13. Random Data Input During Sequential Data Input
tBLBH2
(Program Busy time)
RB
I/O
Busy
Address
Inputs
Address
Inputs
80h
85h
10h
Data Intput
Data Input
70h
SR0
Cmd
Code
Cmd
Confirm
Code
Read Status Register
Code 2 Add cycles
5 Add cycles
Col Add 1,2
Row Add 1,2,3 Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08664
23/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
The Data Input cycle for modifying the source
page is performed as shown in Figure 14. After a
Copy Back Program operation, a partial-page pro-
gram is not allowed in the target page until the
block has been erased.
See Figure 14. for an example of the Copy Back
Program operation.
A data input cycle to modify a portion or a multiple
distant portion of the source page, is shown in Fig-
ure 15.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back Program operation bit error due to
charge loss cannot be detected. For this reason it
is recommended to limit the number of Copy Back
Program operations on the same data and or to
improve the performance of the ECC.
The Copy Back Program operation requires four
steps:
1. The first step reads the source page. The
operation copies all 1056 Words/ 2112 Bytes
from the page into the Data Buffer. It requires:
Table 11. Copy Back Program x8 Addresses
Same Address for Source and
Density
Target Pages
512 Mbit
1 Gbit
no constraint
no constraint
A28
(1)
2 Gbit DD
2 Gbit
no constraint
A29
4 Gbit DD
Note: 1. DD = Dual Die.
–
–
one bus write cycle to setup the command
4 bus write cycles to input the source page
address
Table 12. Copy Back Program x16 Addresses
Same Address for Source and
Density
–
one bus write cycle to issue the confirm
command code
Target Pages
512 Mbit
1 Gbit
no constraint
no constraint
A27
2. When the device returns to the ready state
(Ready/Busy High), the next bus write cycle of
the command is given with the 4 bus cycles to
input the target page address. Refer to Table
11. for the addresses that must be the same
for the Source and Target pages.
(1)
2 Gbit DD
2 Gbit
no constraint
A28
(1)
4 Gbit DD
3. Then the confirm command is issued to start
the P/E/R Controller.
Note: 1. DD = Dual Die.
24/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 14. Copy Back Program
Source
Add Inputs
Target
Add Inputs
I/O
10h
70h
SR0
35h
85h
00h
Read
Code
Copy Back
Code
Read Status Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858b
Note: Copy back program is only permitted between odd address pages or even address pages.
Figure 15. Page Copy Back Program with Random Data Input
2 Cycle
Add Inputs
Target
Add Inputs
Source
Add Inputs
I/O
35h
SR0
00h
85h
Data 85h
Data 10h
70h
Read
Code
Copy Back
Code
Unlimited number of repetitions
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai11001
25/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Program
Cache program command can be issued,
while the internal programming is still
executing.
The Cache Program operation is used to improve
the programming throughput by programming
data using the Cache Register. The Cache Pro-
gram operation can only be used within one block.
The Cache Register allows new data to be input
while the previous data that was transferred to the
Page Buffer is programmed into the memory ar-
ray.
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During Cache Program oper-
ations SR5 can be read to find out whether the in-
ternal programming is ongoing (SR5 = ‘0’) or has
completed (SR5 = ‘1’) while SR6 indicates wheth-
er the Cache Register is ready to accept new data.
If any errors have been detected on the previous
page (Page N-1), the Cache Program Error Bit SR1
will be set to ‘1', while if the error has been detect-
ed on Page N the Error Bit SR0 will be set to '1’.
Each Cache Program operation consists of five
steps (refer to Figure 16.):
1. First of all the program setup command is
issued (one bus cycle to issue the program
setup command then four bus write cycles to
input the address), the data is then input (up to
2112 Bytes/ 1056 Words) and loaded into the
Cache Register.
When the next page (Page N) of data is input with
the Cache Program command, t
is affected
WHBH2
by the pending internal programming. The data will
only be transferred from the Cache Register to the
Page Buffer when the pending program cycle is
finished and the Page Buffer is available.
2. One bus cycle is required to issue the confirm
command to start the P/E/R Controller.
If the system monitors the progress of the opera-
tion using only the Ready/Busy signal, the last
page of data must be programmed with the Page
Program confirm command (10h).
3. The P/E/R Controller then transfers the data to
the Page Buffer. During this the device is busy
for a time of t
.
WHBH2
If the Cache Program confirm command (15h) is
used instead, Status Register bit SR5 must be
polled to find out if the last programming is finished
before starting any other operations.
4. Once the data is loaded into the Page Buffer
the P/E/R Controller programs the data into
the memory array. As soon as the Cache
Registers are empty (after t ) a new
WHBH2
Figure 16. Cache Program Operation
tBLBH5
tBLBH5
tCACHEPG
(Cache Busy time)
RB
Busy
Busy
10h
Busy
Address Data
Address Data
Inputs Inputs
Address Data
I/O
80h
15h
80h
15h
80h
70h SR0
Inputs
Inputs
Inputs
Inputs
Cache Program
Confirm Code
Page
Program
Confirm Code
Read Status
Register
Page
Program
Code
Cache
Page
Program Program
Code
Code
First Page
Second Page
Last Page
(can be repeated up to 63 times)
ai08672
Note: 1. Up to 64 pages can be programmed in one Cache Program operation.
2. t is the program time for the last page + the program time for the (last − 1) page − (Program command cycle time + Last
th
CACHEPG
page data loading time).
26/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Block Erase
3. one bus cycle is required to issue the Block
Erase confirm command to start the P/E/R
Erase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed block to ‘1’. All previous data in the block
is lost.
An erase operation consists of three steps (refer to
Figure 17.):
Controller.
The operation is initiated on the rising edge of
write Enable, W, after the confirm command is is-
sued. The P/E/R Controller handles Block Erase
and implements the verify process.
During the Block Erase operation, only the Read
Status Register and Reset commands will be ac-
cepted, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to ‘1’ and the Ready/
Busy signal goes High. If the operation completed
successfully, the Write Status Bit SR0 is ‘0’, other-
wise it is set to ‘1’.
1. One bus cycle is required to setup the Block
Erase command. Only addresses A18-A27
(x8) or A17-A26 (x16) are used, the other
address inputs are ignored.
2. two or three bus cycles are then required to
load the address of the block to be erased.
Refer to Table 8. and Table 9. for the block
addresses of each device.
Figure 17. Block Erase Operation
tBLBH3
(Erase Busy time)
RB
Busy
Block Address
Inputs
I/O
60h
D0h
70h
SR0
Confirm
Code
Read Status Register
Block Erase
Setup Code
ai07593
Reset
The Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
command is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.
If the device has already been reset then the new
Reset command will not be accepted.
The Ready/Busy signal goes Low for t
after
BLBH4
the Reset command is issued. The value of t
BLBH4
depends on the operation that the device was per-
forming when the command was issued, refer to
Table 24. for the values.
27/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Read Status Register
During Cache Program operations SR6 acts as a
Cache Program Ready/Busy bit, which indicates
whether the Cache Register is ready to accept
new data. When SR6 is set to '0', the Cache Reg-
ister is busy and when SR6 is set to '1', the Cache
Register is ready to accept new data.
During all other operations SR6 acts as a P/E/R Con-
troller bit, which indicates whether the P/E/R Con-
troller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
The device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Register convey information and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is present on the output data bus (I/O0-
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessary to toggle the Chip Enable or Read En-
able signals to update the contents of the Status
Register.
P/E/R Controller Bit (SR5). The Program/Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new Read
command must be issued to continue with a Page
Read operation.
Cache Program Error Bit (SR1). The Cache Pro-
gram Error bit can be used to identify if the previous
page (page N-1) has been successfully pro-
gramed or not in a Cache Program operation. SR1
is set to ’1’ when the Cache Program operation
has failed to program the previous page (page N-
1) correctly. If SR1 is set to ‘0’ the operation has
completed successfully.
The Status Register bits are summarized in Table
13., Status Register Bits, . Refer to Table 13. in
conjunction with the following text descriptions.
The Cache Program Error bit is only valid during
Cache Program operations, during other opera-
tions it is Don’t Care.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to ‘1’ the de-
vice is not protected and program or erase opera-
tions are allowed. If the Write Protection bit is set
to ‘0’ the device is protected and program or erase
operations are not allowed.
Error Bit (SR0). The Error bit is used to identify if
any errors have been detected by the P/E/R Con-
troller. The Error Bit is set to ’1’ when a program or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to ‘0’ the oper-
ation has completed successfully. The Error Bit
SR0, in a Cache Program operation, indicates a
failure on Page N.
P/E/R Controller and Cache Ready/Busy Bit
(SR6). Status Register bit SR6 has two different
functions depending on the current operation.
SR4, SR3 and SR2 are Reserved.
28/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 13. Status Register Bits
Bit
Name
Logic Level
Definition
'1'
Not Protected
Protected
SR7
Write Protection
'0'
'1'
P/E/R C inactive, device ready
Program/ Erase/ Read
Controller
'0'
P/E/R C active, device busy
(1)
SR6
'1'
Cache Register ready (Cache Program only)
Cache Register busy (Cache Program only)
P/E/R C inactive, device ready
Cache Ready/Busy
'0'
'1'
Program/ Erase/ Read
SR5
SR4, SR3, SR2
SR1
(2)
Controller
'0'
P/E/R C active, device busy
Reserved
Don’t Care
'1'
'0'
‘1’
‘0’
‘1’
‘0’
Page N-1 failed in Cache Program operation
Page N-1 programmed successfully
Error – operation failed
(3)
Cache Program Error
Generic Error
No Error – operation successful
(1)
SR0
Page N failed in Cache Program operation
Page N programmed successfully
Cache Program Error
Note: 1. The SR6 bit and SR0 bit have a different meaning during Cache Program and Cache Read operations.
2. Only valid for Cache Program operations, for other operations it is same as SR6.
3. Only valid for Cache Program operations, for other operations it is Don’t Care.
29/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Read Electronic Signature
2. one Bus Write cycle to input the address (00h)
3. four Bus Read Cycles to sequentially output
the data (as shown in Table 14., Electronic
Signature).
The device contains a Manufacturer Code and De-
vice Code. To read these codes three steps are re-
quired:
1. one Bus Write cycle to issue the Read
Electronic Signature command (90h)
Table 14. Electronic Signature
Byte/Word 1
Byte/Word 2
Part Number
Byte/Word 3
Byte/Word 4
Manufacturer Code
Device code
A2h
NAND512R3B
NAND512W3B
NAND512R4B
NAND512W4B
NAND01GR3B
NAND01GW3B
NAND01GR4B
NAND01GW4B
NAND02GR3B
NAND02GW3B
NAND02GR4B
NAND02GW4B
NAND04GR3B
NAND04GW3B
NAND04GR4B
NAND04GW4B
NAND08GR3B
NAND08GW3B
NAND08GR4B
NAND08GW4B
20h
0020h
20h
F2h
B2h
C2h
A1h
F1h
B1h
0020h
20h
C1h
AAh
DAh
BAh
CAh
ACh
DCh
BCh
CCh
A3h
Page Size
Spare Area size
Sequential Access Time
Block Size
Reserved
80h
Organization
(seeTable 15.)
0020h
20h
0020h
20h
D3h
B3h
0020h
C3h
30/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 15. Electronic Signature Byte/Word 4
I/O
Definition
Value
Description
0 0
0 1
1 0
1 1
1K
2K
Reserved
Reserved
Page Size
(Without Spare Area)
I/O1-I/O0
Spare Area Size
(Byte / 512 Byte)
0
1
8
16
I/O2
I/O3
0
1
Standard (50 ns)
Sequential Access Time
Fast
(30 ns)
0 0
0 1
1 0
1 1
64K
128K
256K
Block Size
(Without Spare Area)
I/O5-I/O4
Reserved
0
1
X8
X16
I/O6
I/O7
Organization
Not Used
Reserved
Note: 1. V
is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
DDth
31/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
DATA PROTECTION
The device has both hardware and software fea-
tures to protect against program and erase opera-
tions.
Refer to Figure 26., Command Latch AC Wave-
forms for details on how to issue the command.
Blocks Unlock
It features a Write Protect, WP, pin, which can be
used to protect the device against program and
erase operations. It is recommended to keep WP
A sequence of consecutive locked blocks can be
unlocked, to allow program or erase operations, by
issuing an Blocks Unlock command (see Table
10.).
The Blocks Unlock command consists of four
steps:
at V during power-up and power-down.
IL
In addition, to protect the memory from any invol-
untary program/erase operations during power-
transitions, the device has an internal voltage de-
tector which disables all functions whenever V
CC
■
One bus cycle to setup the command
is below 1.5V.
The device features a Block Lock mode, which is
enabled by setting the Power-Up Read Enable,
Lock/Unlock Enable, PRL, signal to High.
The Block Lock mode has two levels of software
protection.
■
two or three bus cycles to give the Start Block
Address (refer to Table 8. , Table 9. and
Figure 18.)
■
■
one bus cycle to confirm the command
two or three bus cycles to give the End Block
Address (refer to Table 8. , Table 9.and Figure
18.).
■
Blocks Lock/Unlock
Blocks Lock-down
■
Refer to Figure 20. for an overview of the protec-
tion mechanism.
The Start Block Address must be nearer the logi-
cal LSB (Least Significant Bit) than End Block Ad-
dress.
If the Start Block Address is the same as the End
Block Address, only one block is unlocked.
Only one consecutive area of blocks can be un-
locked at any one time. It is not possible to unlock
multiple areas.
Blocks Lock
All the blocks are locked simultaneously by issuing
a Blocks Lock command (see Table 10.).
All blocks are locked after power-up and when the
Write Protect signal is Low.
Once all the blocks are locked, one sequence of
consecutive blocks can be unlocked by using the
Blocks Unlock command.
Figure 18. Blocks Unlock Operation
WP
I/O
Add1
Add3
23h
Add1
Add3
24h
Add2
Add2
End Block Address, 3 cycles
Start Block Address, 3 cycles
Blocks Unlock
Command
ai08670
Note: Three address cycles are required for 2,4 and 8 Gb devices. The 512Mb and 1Gb devices only require two address cycles.
32/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Blocks Lock-Down
Read Block Lock Status command (see Table
10.).
The Lock-Down feature provides an additional lev-
el of protection. A Locked-down block cannot be
unlocked by a software command. Locked-Down
blocks can only be unlocked by setting the Write
Protect signal to Low for a minimum of 100ns.
Only locked blocks can be locked-down. The com-
mand has no affect on unlocked blocks.
The command consists of:
■
one bus cycle to give the command code
three bus cysles to give the block address
■
After this, a read cycle will then output the Block
Lock Status on the I/O pins on the falling edge of
Chip Enable or Read Enable, whichever occurs
last. Chip Enable or Read Enable do not need to
be toggled to update the status.
Refer to Figure 26., Command Latch AC Wave-
forms for details on how to issue the command.
The Read Block Lock Status command will not be
accepted while the device is busy (RB Low).
Block Lock Status
The device will remain in Read Block Lock Status
mode until another command is issued.
In Block Lock mode (PRL High) the Block Lock
Status of each block can be checked by issuing a
Figure 19. Read Block Lock Status Operation
W
tWHRL
R
I/O
Add1
Add3
7Ah
Dout
Add2
Block Lock Status
Block Address, 3 cycles
Read Block Lock
Status Command
ai08669
Note: Three address cycles are required for 2,4 and 8 Gb devices. The 512Mb and 1Gb devices only require two address cycles.
Table 16. Block Lock Status
Status
Locked
I/O7-I/O3
I/O2
I/O1
I/O0
0
X
X
X
0
1
0
1
1
0
Unlocked
Locked-Down
0
1
Unlocked in Locked-
Down Area
X
1
0
1
Note: X = Don’t Care.
33/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 20. Block Protection State Diagram
Power-Up
Block Unlock
Locked
Blocks Lock-Down
Command
Command
(start + end block address)
Blocks Lock
Command
WP V >100ns
IL
WP V >100ns
IL
Unlocked in
Locked Area
Locked-Down
WP V >100ns
IL
Unlocked in
Locked-Down
Area
Blocks Lock-Down
Command
AI08663c
Note: PRL must be High for the software commands to be accepted.
34/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
SOFTWARE ALGORITHMS
This section gives information on the software al-
gorithms that ST recommends to implement to
manage the Bad Blocks and extend the lifetime of
the NAND device.
These additional Bad Blocks can be identified as
attempts to program or erase them will give errors
in the Status Register.
As the failure of a page program operation does
not affect the data in other pages in the same
block, the block can be replaced by re-program-
ming the current data and copying the rest of the
replaced block to an available valid block. The
Copy Back Program command can be used to
copy the data to a valid block.
See the “Copy Back Program” section for more de-
tails.
Refer to Table 17. for the recommended proce-
dure to follow if an error occurs during an opera-
tion.
NAND Flash memories are programmed and
erased by Fowler-Nordheim tunneling using a high
voltage. Exposing the device to a high voltage for
extended periods can cause the oxide layer to be
damaged. For this reason, the number of program
and erase cycles is limited (see Table 18. for val-
ue) and it is recommended to implement Garbage
Collection, a Wear-Leveling Algorithm and an Er-
ror Correction Code, to extend the number of pro-
gram and erase cycles and increase the data
retention.
To help integrate a NAND memory into an applica-
tion ST Microelectronics can provide:
Table 17. Block Failure
■
A Demo board with NAND simulation software
for PCs
Operation
Erase
Recommended Procedure
Block Replacement
Block Replacement or ECC
ECC
■
File System OS Native reference software,
which supports the basic commands of file
management.
Program
Read
Contact the nearest ST Microelectronics sales of-
fice for more details.
Figure 21. Bad Block Management Flowchart
Bad Block Management
START
Devices with Bad Blocks have the same quality
level and the same AC and DC characteristics as
devices where all the blocks are valid. A Bad Block
does not affect the performance of valid blocks be-
cause it is isolated from the bit line and common
source line by a select transistor.
Block Address =
Block 0
Increment
Block Address
The devices are supplied with all the locations in-
side valid blocks erased (FFh). The Bad Block In-
formation is written prior to shipping. Any block,
where the 1st and 6th Bytes, or 1st Word, in the
spare area of the 1st page, does not contain FFh,
is a Bad Block.
The Bad Block Information must be read before
any erase is attempted as the Bad Block Informa-
tion may be erased. For the system to be able to
recognize the Bad Blocks based on the original in-
formation it is recommended to create a Bad Block
table following the flowchart shown in Figure 21.
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
Block Replacement
AI07588C
Over the lifetime of the device additional Bad
Blocks may develop. In this case the block has to
be replaced by copying the data to a valid block.
35/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 22. Garbage Collection
Old Area
New Area (After GC)
Valid
Page
Invalid
Page
Free
Page
(Erased)
AI07599B
Garbage Collection
imum number of write cycles per block reaches a
specific threshold.
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space and allow further pro-
gram operations it is recommended to implement
a Garbage Collection algorithm. In a Garbage Col-
lection software the valid pages are copied into a
free area and the block containing the invalid pag-
es is erased (see Figure 22.).
Error Correction Code
An Error Correction Code (ECC) can be imple-
mented in the Nand Flash memories to identify
and correct errors in the data.
For every 2048 bits in the device it is recommend-
ed to implement 22 bits of ECC (16 bits for line par-
ity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog.
Contact the nearest ST Microelectronics sales of-
fice for more details.
Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
Figure 23. Error Detection
New ECC generated
during read
In memories that do not use a Wear-Leveling Al-
gorithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
XOR previous ECC
with new ECC
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:
NO
NO
>1 bit
All results
= zero?
= zero?
■
First Level Wear-leveling, new data is
programmed to the free blocks that have had
the fewest write cycles
YES
YES
22 bit data = 0
11 bit data = 1
1 bit data = 1
ECC Error
■
Second Level Wear-leveling, long-lived data is
copied to another block so that the original
block can be used for more frequently-
changed data.
Correctable
Error
No Error
The Second Level Wear-leveling is triggered when
the difference between the maximum and the min-
ai08332
36/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Hardware Simulation Models
ior of the I/O buffers and electrical characteristics
of Flash devices.
Behavioral simulation models. Denali Software
Corporation models are platform independent
functional models designed to assist customers in
performing entire system simulations (typical
VHDL/Verilog). These models describe the logic
behavior and timings of NAND Flash devices, and
so allow software to be developed before hard-
ware.
These models provide information such as AC
characteristics, rise/fall times and package me-
chanical data, all of which are measured or simu-
lated at voltage and temperature ranges wider
than those allowed by target specifications.
IBIS models are used to simulate PCB connec-
tions and can be used to resolve compatibility is-
sues when upgrading devices. They can be
imported into SPICETOOLS.
IBIS simulations models. IBIS (I/O Buffer Infor-
mation Specification) models describe the behav-
37/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of
Program/ Erase cycles per block are shown in Ta-
ble 18.
Table 18. Program, Erase Times and Program Erase Endurance Cycles
NAND Flash
Parameters
Unit
Min
Typ
300
2
Max
700
3
Page Program Time
Block Erase Time
µs
ms
Program/Erase Cycles (per block)
Data Retention
100,000
10
cycles
years
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 19., Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 19. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
– 50
– 65
Max
125
150
260
T
Temperature Under Bias
°C
°C
°C
BIAS
T
Storage Temperature
STG
(2)
T
LEAD
Lead temperature during soldering
1.8V devices
3 V devices
1.8V devices
3 V devices
– 0.6
– 0.6
– 0.6
– 0.6
2.7
4.6
2.7
4.6
V
V
V
V
(1)
Input or Output Voltage
Supply Voltage
V
IO
V
DD
Note: 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may over-
shoot to V + 2V for less than 20ns during transitions on I/O pins.
DD
2. Compatibility with Lead-free soldering processes in accordance with ECOPACK 7191395 specifications. Not exceeding 250°C for
more than 10s, and peaking at 260°C.
38/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment
Conditions
summarized
in
Table
20., Operating and AC Measurement Conditions.
Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.
Table 20. Operating and AC Measurement Conditions
NAND Flash
Parameter
Units
Min
Max
1.95
3.6
70
1.8V devices
1.7
2.7
0
V
V
Supply Voltage (V
)
DD
3V devices
Grade 1
°C
°C
pF
pF
V
Ambient Temperature (T )
A
Grade 6
–40
85
1.8V devices
3V devices (2.7 - 3.6V)
1.8V devices
3V devices
30
50
Load Capacitance (C ) (1 TTL GATE and C )
L
L
V
0
DD
Input Pulses Voltages
0.4
2.4
V
1.8V devices
3V devices
0.9
1.5
8.35
5
V
Input and Output Timing Ref. Voltages
V
Output Circuit Resistor R
kΩ
ns
ref
Input Rise and Fall Times
Table 21. Capacitance
Symbol
Parameter
Input Capacitance
Test Condition
Typ
Max
Unit
pF
C
V
= 0V
= 0V
10
10
IN
IN
C
V
IL
Input/Output Capacitance
pF
I/O
Note: T = 25°C, f = 1 MHz. C and C are not 100% tested.
A
IN
I/O
Figure 24. DC Characteristics, 1.8V Devices
Symbol
Parameter
Test Conditions
minimum
Min
Typ
Max
Unit
t
Sequential
Read
RLRL
I
-
8
15
mA
DD1
E=V
I
= 0 mA
IL, OUT
Operating
Current
I
Program
Erase
-
-
-
-
8
8
15
15
mA
mA
DD2
I
DD3
E=V -0.2,
DD
I
Standby Current (CMOS)
-
10
50
µA
DD5
WP=0/V
DD
I
V = 0 to V max
Input Leakage Current
Output Leakage Current
Input High Voltage
-
-
-
-
-
-
±10
±10
µA
µA
V
LI
IN
DD
I
LO
V
= 0 to V max
OUT
DD
V
V
-0.4
V
+0.3
-
-
IH
DD
DD
V
Input Low Voltage
-0.3
0.4
V
IL
39/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Symbol
Parameter
Test Conditions
Min
-0.1
Typ
Max
-
Unit
V
V
OH
I
= -100µA
= 100µA
= 0.1V
V
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
-
-
OH
DD
V
I
OL
-
0.1
4
V
OL
I
OL
(RB)
V
OL
3
-
mA
V
DD
Supply Voltage (Erase and
Program lockout)
V
LKO
-
-
1.1
V
Figure 25. Equivalent Testing Circuit for AC Characteristics Measurement
V
DD
2R
ref
NAND Flash
C
L
2R
ref
GND
GND
Ai11085
40/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 22. DC Characteristics, 3V Devices
Symbol
Parameter
Test Conditions
minimum
Min
Typ
Max
Unit
t
Sequential
Read
RLRL
I
-
15
30
mA
DD1
E=V
I
= 0 mA
IL, OUT
Operating
Current
I
Program
Erase
-
-
-
15
15
30
30
1
mA
mA
mA
DD2
I
-
DD3
E=V , WP=0/V
IDD4
Standby current (TTL)
IH
DD
E=V -0.2,
DD
I
Standby Current (CMOS)
-
10
50
µA
DD5
WP=0/V
DD
I
V = 0 to V max
Input Leakage Current
Output Leakage Current
Input High Voltage
-
-
-
-
-
-
-
-
±10
±10
µA
µA
V
LI
IN
DD
I
LO
V
= 0 to V max
OUT
DD
V
V
+0.8
V
V
+0.3
-
IH
DD
DD
V
+0.2
Input Low Voltage
-
-0.3
2.4
-
V
IL
DD
V
OH
I
= -100µA
= 100µA
Output High Voltage Level
Output Low Voltage Level
Output Low Current (RB)
-
V
OH
V
I
OL
0.4
10
V
OL
I
(RB)
V
OL
= 0.4V
-
8
mA
OL
V
Supply Voltage (Erase and
Program lockout)
DD
V
LKO
-
-
1.7
V
41/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 23. AC Characteristics for Command, Address, Data Input
Alt.
1.8V
3V
Symbol
Parameter
Unit
Symbol
Devices Devices
t
Address Latch Low to Write Enable Low
Address Latch High to Write Enable Low
Command Latch High to Write Enable Low
Command Latch Low to Write Enable Low
Data Valid to Write Enable High
ALLWL
t
AL Setup time
CL Setup time
Min
Min
0
0
0
0
ns
ALS
t
ALHWL
t
CLHWL
t
ns
CLS
t
CLLWL
t
t
Data Setup time
E Setup time
AL Hold time
Min
Min
Min
20
0
20
0
ns
ns
ns
DVWH
DS
t
t
Chip Enable Low to Write Enable Low
Write Enable High to Address Latch High
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
Write Enable High to Chip Enable High
ELWL
CS
t
t
10
10
WHALH
ALH
t
WHCLH
t
CL hold time
Min
10
10
ns
CLH
t
WHCLL
t
t
Data Hold time
E Hold time
Min
Min
10
10
10
10
ns
ns
WHDX
DH
t
t
WHEH
CH
W High Hold
time
t
t
Write Enable High to Write Enable Low
Min
Min
20
20
ns
WHWL
WH
(1)
(1)
t
t
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
W Pulse Width
ns
ns
WLWH
WP
25
60
25
50
t
t
Write Cycle time Min
WLWL
WC
Note: 1. If t
is less than 10ns, t
must be minimum 35ns, otherwise, t
may be minimum 25ns.
ELWL
WLWH
WLWH
42/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 24. AC Characteristics for Operations
Alt.
Symbol
1.8V
3V
Symbol
Parameter
Unit
Devices Devices
t
Read Electronic Signature
Read cycle
Min
Min
10
10
20
25
700
3
10
10
20
25
700
3
ns
ns
ns
µs
µs
ms
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ALLRL1
Address Latch Low to
Read Enable Low
t
AR
t
ALLRL2
t
t
Ready/Busy High to Read Enable Low
Read Busy time
Min
BHRL
RR
t
Max
Max
Max
Max
Typ
BLBH1
t
t
PROG
Program Busy time
BLBH2
t
t
Erase Busy time
BLBH3
BERS
Ready/Busy Low to
Ready/Busy High
t
Reset Busy time, during ready
5
5
BLBH4
3
3
t
t
Cache Busy time
BLBH5
CBSY
Max
Max
Max
Max
Min
700
5
700
5
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
Write Enable High to
Ready/Busy High
t
t
10
500
10
0
10
500
10
0
WHBH1
RST
t
t
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Chip Enable Low to Output Valid
Read Enable High to
CLLRL
CLR
t
t
Min
DZRL
IR
t
t
t
Max
Max
20
45
20
45
EHQZ
CHZ
t
ELQV
CEA
t
t
Read Enable High Hold time
Min
Min
20
15
20
15
ns
ns
RHRL
REH
Read Enable Low
T
T
EHQX
T
Chip Enable high or Read Enable high to Output Hold
OH
RHQX
Read Enable Low to
Read Enable Pulse Width
Read Enable High
t
t
Min
Min
25
60
25
50
ns
ns
RLRH
RP
Read Enable Low to
Read Cycle time
t
t
RLRL
RC
Read Enable Low
Read Enable Access time
Read Enable Low to
t
t
REA
Max
Max
35
25
35
25
ns
µs
RLQV
Output Valid
(3)
Read ES Access time
Write Enable High to
Ready/Busy High
t
t
R
Read Busy time
WHBH
t
t
t
WB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Max
Min
100
60
100
60
ns
ns
WHBL
t
WHRL
WHR
Write Enable Low to
Write Cycle time
t
t
Min
60
50
ns
WLWL
WC
Write Enable Low
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 36, 37 and 38.
2. To break the sequential read cycle, E must be held High for longer than t
3. ES = Electronic Signature.
.
EHEL
43/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 26. Command Latch AC Waveforms
CL
tCLHWL
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWL
(E Setup time)
E
tWLWH
W
tALLWL
tWHALH
(ALSetup time)
(AL Hold time)
AL
I/O
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Command
ai08028
Figure 27. Address Latch AC Waveforms
tCLLWL
(CL Setup time)
CL
tELWL
tWLWL
tWLWL
tWLWL
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHALL
tALHWL
tWHWL
tWHALL
tWHWL
tWHALL
(AL Setup time)
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
tWHDX
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 1
ai08029
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
44/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 28. Data Input Latch AC Waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWL
tWLWL
(ALSetup time)
AL
W
tWLWH
tWLWH
tWLWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai08030
Note: Data In Last is 2112 in x8 devices and 1056 in x16 devices.
Figure 29. Sequential Data Output after Read AC Waveforms
tRLRL
(Read Cycle time)
E
tRHRL
(R High Holdtime)
tEHQZ
R
tRHQZ
tRHQZ
tRLQV
tRLQV
tRLQV
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai08031
Note: 1. CL = Low, AL = Low, W = High.
45/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 30. Read Status Register AC Waveform
tCLLRL
CL
tWHCLL
tCLHWL
tWHEH
E
tELWL
tWLWH
W
R
tELQV
tWHRL
tEHQZ
tRHQZ
tDZRL
tWHDX
tDVWH
(Data Setup time)
tRLQV
(Data Hold time)
70h/ 72h/
73h/ 74h/ 75h
Status Register
Output
I/O
ai08666
Figure 31. Read Electronic Signature AC Waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
00h
Byte1
Byte2
Byte3
00h
Byte4
Man.
code
Device
code
Read Electronic 1st Cycle
Signature
Command
see Note.1
Address
ai08667
Note: 1. Refer to Table 14. for the values of the Manufacturer and Device Codes, and to Table 15. for the information contained in Byte4.
46/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 32. Page Read Operation AC Waveform
CL
tEHEL
tEHQZ
tEHBH
E
tWLWL
W
tWHBL
tWHBH
AL
tALLRL2
tRLRL
tRHQZ
tRHBL
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
Add.N
cycle 4
Data
N
Data
N+1
Data
N+2
Data
Last
Add.N
cycle 1
Add.N
cycle 3
Add.N
cycle 2
00h
30h
Data Output
from Address N to Last Byte or Word in Page
Command Address N Input
Code
Busy
ai08660
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
47/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 33. Page Program AC Waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tBLBH2
(Program Busy time)
AL
R
Add.N
Add.N Add.N
cycle 1 cycle 2
Add.N
cycle 3
I/O
80h
Last
N
10h
70h
SR0
cycle 4
RB
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai08668
Note: A fifth address cycle is required for 2Gb, 4Gb and 8Gb devices.
48/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 34. Block Erase AC Waveform
CL
E
tWLWL
(Write Cycle time)
W
AL
R
tBLBH3
tWHBL
(Erase Busy time)
Add.
Add.
Add.
I/O
70h
SR0
60h
D0h
cycle 1 cycle 2
cycle 3
RB
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038b
Note: Address cycle 3 is required for 2Gb, 4Gb and 8Gb devices only.
Figure 35. Reset AC Waveform
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
49/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Ready/Busy Signal Electrical Characteristics
Figures 37, 36 and 38 show the electrical charac-
teristics for the Ready/Busy signal. The value re-
Figure 37. Ready/Busy Load Circuit
quired for the resistor R can be calculated using
P
the following equation:
(
–
)
V
V
DDmax
OLmax
+ I
R min= -----------------------------------------------------------
P
I
L
OL
ibusy
R
P
V
DD
So,
1.85V
R min(1.8V)= ---------------------------
P
+
3mA
I
DEVICE
L
RB
Open Drain Output
3.2V
R min(3V)= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the
L
devices tied to the Ready/Busy signal. R max is
P
determined by the maximum value of t .
r
Figure 36. Ready/Busy AC Waveform
V
SS
ready V
DD
V
OH
AI07563B
V
OL
busy
t
t
r
f
AI07564B
Figure 38. Resistor Value Versus Waveform Timings For Ready/Busy Signal
V
= 1.8V, C = 30pF
V
= 3.3V, C = 100pF
DD
L
DD
L
400
300
200
400
300
200
4
3
2
4
3
2
400
300
2.4
200
1.2
1.7
120
100
0
1
100
0
1
0.85
0.8
3.6
100
3.6
90
0.57
0.6
3.6
60
1.7
0.43
1.7
30
1.7
3.6
1.7
1
2
3
4
1
2
3
4
R
(KΩ)
R
(KΩ)
P
P
t
t
r
ibusy
f
ai07565B
Note: T = 25°C.
50/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Data Protection
In the V
range from V
to the lower limit of
LKO
DD
nominal range, the WP pin should be kept low
The ST NAND device is designed to guarantee
Data Protection during Power Transitions.
(V ) to guarantee hardware protection during
IL
power transitions as shown in the below figure.
A V
detection circuit disables all NAND opera-
DD
tions, if V is below the V
threshold.
DD
LKO
Figure 39. Data Protection
Nominal Range
V
DD
V
LKO
Locked
Locked
W
Ai11086
51/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
PACKAGE MECHANICAL
Figure 40. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
Note: Drawing is not to scale.
Table 25. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
Symbol
Typ
Min
Max
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
Typ
Min
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
5°
L1
α
0°
5°
0°
52/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 41. USOP48 – lead Plastic Ultra Thin Small Outline,12x17 mm, Package Outline
1
48
e
b
D1
L1
A2
A
24
25
E1
E
θ
A1
L
DIE
c
ddd
WSOP-A
Note: Drawing not to scale.
Table 26. USOP48 – lead Plastic Ultra Thin Small Outline, 12x17mm,
Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
0.48
0.00
0.48
0.13
0.08
11.90
Max
0.65
0.10
0.56
0.23
0.17
12.10
0.06
17.20
15.50
–
Typ
Max
0.026
0.004
0.022
0.009
0.007
0.476
0.002
0.677
0.610
–
A
A1
A2
b
0.019
0.000
0.019
0.005
0.003
0.469
0.52
0.16
0.020
0.006
0.004
0.472
c
0.10
D1
ddd
E
12.00
17.00
15.40
0.50
16.80
15.30
–
0.669
0.606
0.020
0.022
0.010
0.661
0.602
–
E1
e
L
0.55
0.45
–
0.65
–
0.018
–
0.026
–
L1
q
0.25
0
5
0
5
53/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 42. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D2
D1
FD1
SD
FD
e
e
SE
E
E2 E1
ddd
BALL "A1"
FE1
FE
e
b
A
A2
A1
BGA-Z67
Note: Drawing is not to scale
Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.05
0.0413
0.25
0.0098
0.70
0.50
9.60
0.0276
0.0197
0.3780
0.45
9.50
4.00
7.20
0.40
9.40
0.0177
0.3740
0.1575
0.2835
0.0157
0.3701
D
D1
D2
ddd
E
0.10
0.0039
0.4764
12.00
5.60
8.80
0.80
2.75
1.15
3.20
1.60
0.40
0.40
11.90
–
12.10
0.4724
0.2205
0.3465
0.0315
0.1083
0.0453
0.1260
0.0630
0.0157
0.0157
0.4685
E1
E2
e
–
–
–
FD
FD1
FE
FE1
SD
SE
54/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 43. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D
D2
D1
FD1
SD
FD
e
e
SE
E
E2 E1
ddd
BALL "A1"
FE1
FE
e
b
A
A2
A1
BGA-Z67
Note: Drawing is not to scale
Table 28. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.20
0.0472
0.25
0.0098
0.80
0.45
9.50
4.00
7.20
0.0315
0.0177
0.3740
0.1575
0.2835
0.40
9.40
0.50
9.60
0.0157
0.3701
0.0197
0.3780
D
D1
D2
ddd
E
0.10
0.0039
0.4764
12.00
5.60
8.80
0.80
2.75
1.15
3.20
1.60
0.40
0.40
11.90
–
12.10
0.4724
0.2205
0.3465
0.0315
0.1083
0.0453
0.1260
0.0630
0.0157
0.0157
0.4685
–
E1
E2
e
–
–
FD
FD1
FE
FE1
SD
SE
55/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
PART NUMBERING
Table 29. Ordering Information Scheme
Example:
NAND02GR3B
2
A ZA
1
T
Device Type
NAND Flash Memory
Density
512 = 512Mb
01G = 1Gb
02G = 2Gb
04G = 4Gb
08G = 8Gb
Operating Voltage
R = V = 1.7 to 1.95V
DD
W = V = 2.7 to 3.6V
DD
Bus Width
3 = x8
4 = x16
Family Identifier
B = 2112 Bytes/ 1056 Word Page
Device Options
2 = Chip Enable Don't Care Enabled
Product Version
A = First Version
B= Second Version
C= Third Version
Package
N = TSOP48 12 x 20mm (all devices)
V = USOP48 12 x 17 x 0.65mm (512Mb and 1Gb devices)
ZA = VFBGA63 9.5 x 12 x 1mm, 0.8mm pitch (512Mb and 1Gb devices)
ZB = TFBGA63 9.5 x 12 x 1.2mm, 0.8mm pitch (2Gb Dual Die devices)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
E = Lead Free Package, Standard Packing
F = Lead Free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further
information on any aspect of this device, please contact your nearest ST Sales Office.
56/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
REVISION HISTORY
Table 30. Document Revision History
Date
Version
Revision Details
25-Feb-2005
1
First Issue
Automatic Page 0 Read feature removed throughout document.
LFBGA63 package removed throughout document.
Data Protection section and Figure 25., Equivalent Testing Circuit for AC Characteris-
tics Measurement added.
TFBGA63 and VFBGA63 packages updated. Note added to Figure 4., TSOP48 and
USOP48 Connections, x8 devices and Figure 5., TSOP48 and USOP48 Connections,
x16 devices regarding the USOP package.
16-Aug-2005
2
Write Enable (W)., Table 11., Table 12., Table 14., Block Lock Status, Figure 20., Table
20., Figure 24., Table 22., Table 24. and Table 30. modified.
57/58
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
58/58
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