NAND64GAH0KZE5E [NUMONYX]
Flash, 8GX8, PBGA169, 14 X 18 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, TFBGA-169;
| 型号： | NAND64GAH0KZE5E |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 8GX8, PBGA169, 14 X 18 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, TFBGA-169 内存集成电路 |
| 文件： | 总32页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND32GAHOK NAND64GAHOK
NAND128AHOK NAND256AHOK
4-Gbyte, 8-Gbyte, 16-Gbyte, 32-Gbyte, 1.8 V/3.3 V supply,
NAND flash memories with MultiMediaCard™ interface
Preliminary Data
Features
■ Packaged NAND flash memory with
MultiMediaCard interface
FBGA169
■ Up to 32 Gbytes of formatted data storage
■ High capacity memory access
■ eMMC/MultiMediaCard system specification,
compliant with V4.3
■ Full backward compatibility with previous
MultiMediaCard system specification
LFBGA169 14 x 18 x 1.4 mm (ZD)
TFBGA169 14 x 18 x 1.2 mm (ZE)
■ Bus mode
– High-speed MultiMediaCard protocol
– Three different data bus widths:1 bit, 4 bits,
8 bits
– Data transfer rate: up to 52 Mbyte/s
■ Operating voltage range:
■ Error free memory access
– V
=1.8 V/3.3 V
CCQ
– Internal error correction code
– V = 3.3 V
CC
– Internal enhanced data management
algorithm (wear levelling, bad block
management, garbage collection)
■ Multiple block read (x8 at 52 MHz):
up to 28.5 Mbyte/s
■ Multiple block write (x8 at 52 MHz):
– Possibility for the host to make sudden
power failure safe-update operations for
data content
up to 16 Mbyte/s
■ Power dissipation
■ Boot
– Standby current: 150 µA (typ)
– Read current: 70 mA (typ)
– Write current: 80 mA (typ)
– Simple boot sequence method
■ Power save
– Enhanced power saving method by
introducing sleep functionality
■ Security
– Password protection of data
– Built-in write protection
Table 1.
Device summary
Root part number
Package
Operating voltage
NAND32GAH0K
NAND64GAH0K
NAND128AH0K
NAND256AH0K
TFBGA169 14 x 18 x 1.2 mm
LFBGA169 14 x 18 x 1.4 mm
VCC = 3.3 V, VCCQ = 1.8 V/3.3 V
October 2009
Rev 3
1/32
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.numonyx.com
1
Contents
NANDxxxAH0K
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
eMMC Standard Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
System performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MultiMediaCard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Command (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/outputs (DAT0-DAT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
V
V
V
core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
SS
input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CCQ
SSQ
5.2
5.3
5.4
5.5
5.6
5.7
Bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
High speed MultiMediaCard operation . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
6.4
Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/32
NANDxxxAH0K
Contents
6.5
6.6
6.7
6.8
6.9
Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
State transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing diagrams and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.10 Minimum performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Operation conditions register (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Card specific data register (CSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Extended CSD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RCA (relative card address) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DSR (driver stage register) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
10
3/32
List of tables
NANDxxxAH0K
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Communication channel performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OCR register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Card specific data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Extended CSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LFBGA169 14 x 18 x 1.4 mm 132+21+16 3R14 0.50 mm, package mechanical data. . . . 27
TFBGA169 14 x 18 x 1.2 mm 132+21+16 3R14 0.50 mm, package mechanical data. . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/32
NANDxxxAH0K
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LFBGA169 and TFBGA169 package connections (top view through package). . . . . . . . . . 9
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory array structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LFBGA169 14 x 18 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline . . . . . . . . . . . 26
TFBGA169 14 x 18 x 1.2 mm 132+21+16 3R14 0.50 mm, package outline . . . . . . . . . . . 28
5/32
Description
NANDxxxAH0K
1
Description
The NANDxxxAH0K is an embedded flash memory storage solution with MultiMediaCard™
interface (eMMC™). The eMMC™ was developed for universal low cost data storage and
communication media. The NANDxxxAH0K is fully compatible with MMC bus and hosts.
The NANDxxxAH0K communications are made through an advanced 13-pin bus. The bus
can be either 1-bit, 4-bit, or 8-bit in width. The device operates in high-speed mode at clock
frequencies equal to or higher than 20 MHz, which is the MMC standard. The
communication protocol is defined as a part of this MMC standard and referred to as
MultiMediaCard mode.
The device is designed to cover a wide area of applications such as smart phones,
cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They
feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications,
the NANDxxxAH0K supports both 3.3 V supply voltage (V ), and 1.8 V/3.3 V input/output
CC
voltage (V
).
CCQ
The address argument for the NANDxxxAH0K is the sector address (512-byte sectors)
instead of the byte address. This means that NANDxxxAH0K is not backward compatible
with devices of density lower than 2 Gbytes. If there is no indication by the host to the
memory that the host is capable of handling sector type of addressing, the NANDxxxAH0K
will change its state to inactive.
The device has a built-in intelligent controller which manages interface protocols, data
storage and retrieval, wear leveling, bad block management, garbage collection, and
internal ECC.
The NANDxxxAH0K makes available to the host sudden power failure safe-update
operations for the data content, by supporting reliable write features.
The device supports boot operation and sleep/awake commands. In particular, during the
sleep state the host power regulator for V can be switched off, thus minimizing the power
CC
consumption of the NANDxxxAH0K.
The system performance and characteristics are given in Table 2, Table 3, and Table 4.
1.1
eMMC Standard Specification
The NANDxxxAH0K device is fully compatible with the JEDEC Standard Specification No.
JESD84-A43.
This datasheet describes the key and specific features of the NANDxxxAH0K device. Any
additional information required to interface the device to a host system and all the practical
methods for card detection and access can be found in the proper sections of the JEDEC
Standard Specification.
6/32
NANDxxxAH0K
Product specification
2
Product specification
2.1
System performance
Table 2.
System performance
Typical value(1)
NAND64GAH0K,
NAND128AH0K,
System performance
Unit
NAND32GAH0K
NAND256AH0K
Multiple block read sequential(2)
Multiple block write sequential(2)
14
8
28.5
16
Mbyte/s
Mbyte/s
1. Values given for an 8-bit bus width, a clock frequency of 52 MHz, VCC = 3.3 V and VCCQ = 3.3 V.
2. Based on a 4-Mbyte file transfer.
Table 3.
Current consumption
Current consumption(1)
Operation Test conditions
Unit
NAND32GAH0K NAND64GAH0K NAND128AH0K NAND256AH0K
Typ
55
Max
95
Typ
70
Max
100
96
Typ
70
Max
100
96
Typ
70
Max
100
96
Read
VCC= 3.3 V ± 5%
VCCQ = 1.8 V ± 5%
mA
µA
Write
75
95
80
80
80
VCC = 3.3 V ± 5%
25
45
45
165
125
65
165
125
85
165
125
Standby
VCCQ = 1.8 V ± 5%
65
100
65
65
65
1. Values given for an 8-bit bus width and a clock frequency of 26 MHz.
Table 4.
Communication channel performance
MultiMediaCard communication channel performance
Three-wire serial data bus (clock, command, data)
Variable clock rate 0, 26, 52 MHz
Easy card identification
Error protected data transfer
Sequential and single/multiple block oriented data transfer
7/32
Device physical description
NANDxxxAH0K
3
Device physical description
The NANDxxxAH0K contains a single chip controller and flash memory module, see
Figure 1: Device block diagram. The microcontroller interfaces with a host system allowing
data to be written to and read from the flash memory module. The controller allows the host
to be independent from details of erasing and programming the flash memory.
Figure 2 shows the package connections. See Table 5: Signal names for the description of
the signals corresponding to the balls.
Figure 1.
Device block diagram
Data
I/O
Numonyx
single chip
microcontroller
MultiMediaCard
interface
Flash
module
Control
AI13614e
8/32
NANDxxxAH0K
Device physical description
3.1
Package connections
Figure 2.
LFBGA169 and TFBGA169 package connections (top view through package)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
V
NC
SS
CC
V
CC
NC
NC
NC
NC
NC
NC
NC
8
7
NC
NC
NC
NC
V
NC
NC
SS
V
NC
SS
NC
V
NC
V
NC
NC
6
5
4
3
NC
DAT7
V
NC
NC
CLK
CC
SSQ
CCQ
NC
DAT6
NC
V
CMD
V
SSQ
DAT2
DAT1
V
NC
NC
V
CC
SS
CCQ
NC
V
V
NC
DAT5
V
V
CCQ
NC
SSQ
SSQ
NC
CCQ
NC
DAT4
NC
NC
NC
DAT0
NC
NC
NC
NC
NC
NC
NC
V
CCQ
NC
NC
V
NC
NC
NC
V
SSQ
2
1
DAT3
NC
NC
M
NC
NC
NC
NC
NC
AG
CCI
NC
H
NC
N
NC
Y
NC
AE
NC
D
NC
J
NC
K
NC
L
NC
P
NC
R
NC
T
NC
U
NC
V
NC
W
NC
AA
A
B
C
E
F
G
AB
AC
AD
AF
AH
AI13626
1. The ball corresponding to VCCI must be decoupled with an external capacitance.
3.2
Form factor
The ball diameter, d, and the ball pitch, p, for the LFBGA169 and TFBGA169 packages are:
■
■
d = 0.30 mm (solder ball diameter)
p = 0.5 mm (ball pitch)
Figure 3.
Form factor
NC
NC
V
NC
CCQ
d
p
AI13627
9/32
Memory array partitioning
NANDxxxAH0K
4
Memory array partitioning
The basic unit of data transfer to/from the device is one byte. All data transfer
operations which require a block size always define block lengths as integer
multiples of bytes. Some special functions need other partition granularity.
For block oriented commands, the following definitions are used:
■
Block: the unit which is related to the block oriented read and write commands.
Its size is the number of bytes which are transferred when one block command
is issued by the host. The size of a block is either programmable or fixed. The
information about allowed block sizes and the programmability is stored in the
CSD register.
■
■
Erase group: the unit which is related to special erase and write commands
defined for R/W cards. Its size is the smallest number of consecutive write
blocks which can be addressed for erase. The size of the erase group depends
on each device and is stored in the CSD.
Write protect group: the smallest unit that may be individually write protected.
Its size is defined in units of erase groups. The size of a WP-group depends on
each device and is stored in the CSD.
Figure 4 shows the NANDxxxAH0K memory array organization.
Figure 4.
Memory array structure
Write protect group 0
Erase group 0
Block 0
Erase group 1
Erase group n
Write protect group 1
Write protect group 2
Write protect group n
MultiMediaCard
AI13615e
1. n = number of last erase group or last write protect group.
10/32
NANDxxxAH0K
MultiMediaCard interface
5
MultiMediaCard interface
The signal/pin assignments are listed in Table 5. Refer to this table in conjunction with
Figure 2 and Figure 3: Form factor.
5.1
Signals description
5.1.1
Clock (CLK)
The Clock input, CLK, is used to synchronize the memory to the host during command and
data transfers. Each clock cycle gates one bit on the command and on all the data lines. The
Clock frequency, f , may vary between zero and the maximum clock frequency.
PP
5.1.2
5.1.3
Command (CMD)
The CMD signal is a bidirectional command channel used for device initialization and
command transfer. The CMD signal has two operating modes: open-drain and push-pull.
The open-drain mode is used for initialization, while the push-pull mode is used for fast
command transfer. Commands are sent by the MultiMediaCard bus master (or host) to the
device who responds by sending back responses.
Input/outputs (DAT0-DAT7)
DAT0 to DAT7 are bidirectional data channels. The signals operate in push-pull mode. The
NANDxxxAH0K includes internal pull ups for all data lines. These signals cannot be driven
simultaneously by the host and the NANDxxxAH0K device. Right after entering the 4-bit
mode, the card disconnects the internal pull ups of lines DAT1 and DAT2 (DAT3 internal pull
up is left connected due to the SPI mode CS backward compatible usage). Correspondingly
right after entering the 8-bit mode, the card disconnects the internal pull ups of lines DAT1,
DAT2 and DAT4-DAT7.
By default, after power-up or hardware reset, only DAT0 is used for data transfers. The host
can configure the device to use a wider data bus, DAT0, DAT0-DAT3 or DAT0-DAT7, for data
transfer.
5.1.4
5.1.5
V
core supply voltage
CC
V
provides the power supply to the internal core of the memory device. It is the main
CC
power supply for all operations (read, program and erase). The core voltage (V ) can be
within 2.7 V and 3.6 V.
CC
V
ground
SS
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
11/32
MultiMediaCard interface
NANDxxxAH0K
5.1.6
V
input/output supply voltage
CCQ
V
provides the power supply to the I/O pins and enables all outputs to be powered
CCQ
independently from V
.
CC
The input/output voltage (V
) can be either within 1.65/1.7 V and 1.95 V (low voltage
CCQ
range) or 2.7 V and 3.6 V (high voltage range).
5.1.7
V
supply voltage
SSQ
V
ground is the reference for the input/output circuitry driven by V
.
CCQ
SSQ
Table 5.
Name
Signal names
Type(1)
Description
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (OD or PP)
I (PP)
Data
Data
Data
Data
Data
Data
Data
Data
Command
Clock
VCCQ
VCC
Input/output power supply
Core power supply
Input/output ground
VSSQ
VCCI
VSS
I
Must be decoupled with an external capacitance
Ground
NC
NC
Not connected(2)
1. I: input; O: output, OD: open drain, PP: push-pull.
2. NC pins can be connected to ground or left floating.
12/32
NANDxxxAH0K
MultiMediaCard interface
5.2
Bus topology
The NANDxxxAH0K device supports the MMC protocol. For more details, refer to section
6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC
Standard Specification contains a bus circuitry diagram for reference.
5.3
Power-up
The power-up is handled locally in each device and in the bus master. Figure 5: Power-up
shows the power-up sequence. Refer to section 12.3 of the JEDEC Standard Specification
No. JESD84-A43 for specific instructions regarding the power-up sequence.
After power-up, the maximum initial load the NANDxxxAH0K can present on the V line is
CC
C4, in parallel with a minimum of R4. During operation, device capacitance on the V line
CC
must not exceed 10 µF.
5.4
Power cycling
The bus master can execute any sequences of V and V
power-up/power down.
CCQ
CC
However, the master must not issue any commands until V and V
are stable within
CC
CCQ
each operating voltage range. For more information about power cycling see section 12.3.3
of the JEDEC Standard Specification No. JESD84-A43 and Figure 6: Power cycling.
13/32
MultiMediaCard interface
NANDxxxAH0K
Figure 5.
Power-up
Supply
voltage
(3)
V
CCmax
Memory
field
working
voltage
range
(3)
V
CC
(3)
V
CCmin
(3)
V
CCQmax
Control logic
working
voltage range
(3)
V
CCQmin
Time
Power-up
Supply
(2)
First CMD1 to card ready
ramp-up
N
N
CC
CC
Initialization
sequence
CMD2
CMD1
CMD1
CMD1
(1)
CMD1 repeated
until busy flag cleared
Initialization
delay
The longest of: 1 ms,
74 clock cycles,
supply ramp-up time,
or the boot operation period.
AI14104b
1. The length of the initialization sequence is either 1 ms, 74 clocks or the supply ramp up time, whichever is the longest. The
device shall complete its initialization within 1 second from the first CMD1 with a valid V range.
2. NCC is the number of clock cycles.
3. Refer to Section 7.1: Operation conditions register (OCR) for details on voltage ranges.
Figure 6.
Power cycling
Supply
voltage
V
CC
V
CCmin
V
CCQ
V
CCQmin
Command input prohibited
Command input prohibited
Sleep mode
Time
AI14122b
14/32
NANDxxxAH0K
MultiMediaCard interface
5.5
5.6
5.7
Bus operating conditions
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
Bus signal levels
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
Bus timing
Refer to section 12.7 of the JEDEC Standard Specification No. JESD84-A43.
15/32
High speed MultiMediaCard operation
NANDxxxAH0K
6
High speed MultiMediaCard operation
All communication between the host and the device is controlled by the host (master).
The following section provides an overview of the identification and data transfer modes,
commands, dependencies, various operation modes and restrictions for controlling the clock
signal. For detailed information, refer to section 7 of the JEDEC Standard Specification No.
JESD84-A43.
6.1
6.2
6.3
Boot mode
The host can read boot data from NANDxxxAH0K by keeping CMD line Low after power-on
or sending CMD0 with argument + 0xFFFFFFFA (optional for slave), before issuing CMD1.
The data can be read from either boot area or user area depending on the register setting.
Refer to section 7.2 of the JEDEC Standard Specification No. JESD84-A43.
Identification mode
When in card identification mode, the host resets the NANDxxxAH0K, validates the
operating voltage range and the access mode, identifies the device and assigns a relative
address (RCA) to it. For more information see section 7.3 of the JEDEC Standard
Specification No. JESD84-A43.
Data transfer mode
The device enters data transfer mode once an RCA is assigned to it. When the device is in
standby mode, issuing the CMD7 command along with the RCA, selects the device and puts
it into the transfer state. The host enters data transfer mode after identifying the
NANDxxxAH0K on the bus. When the device is in standby state, communication over the
CMD and DAT lines is in push-pull mode.
The section 7.5 of the JEDEC Standard Specification No. JESD84-A43 contains more
detailed information about data read and write, erase, write protect management,
lock/unlock operations, the switch function command, high speed mode selection, and bus
testing procedure. Moreover section 7.5.7 contains a detailed description of the reliable
write features supported by the NANDxxxAH0K.
6.4
6.5
Clock control
Refer to section 7.6 of the JEDEC Standard Specification No. JESD84-A43.
Error conditions
Refer to section 7.7 of the JEDEC Standard Specification No. JESD84-A43.
16/32
NANDxxxAH0K
High speed MultiMediaCard operation
6.6
6.7
6.8
6.9
6.10
Commands
Refer to section 7.9 of the JEDEC Standard Specification No. JESD84-A43.
State transition
Refer to section 7.10 and 7.12 of the JEDEC Standard Specification No. JESD84-A43.
Response
Refer to section 7.11 of the JEDEC Standard Specification No. JESD84-A43.
Timing diagrams and values
Refer to section 7.14 of the JEDEC Standard Specification No. JESD84-A43.
Minimum performance
Refer to section 7.8 of the JEDEC Standard Specification No. JESD84-A43.
17/32
Device registers
NANDxxxAH0K
7
Device registers
There are five different registers within the device interface:
■
■
■
■
■
■
Operation conditions register (OCR)
Card identification register (CID)
Card specific data register (CSD)
Relative card address register (RCA)
DSR (driver stage register)
Extended card specific data register (EXT_CSD).
These registers are used for the serial data communication and can be accessed only using
the corresponding commands (refer to section 7.9 of the JEDEC Standard Specification No.
JESD84-A43. The device does not implement the DSR register.
The MultiMediaCard has a status register to provide information about the device current
state and completion codes for the last host command.
7.1
Operation conditions register (OCR)
The 32-bit operation conditions register stores the V
, the input/output voltage of the
CCQ
flash memory component. The device is capable of communicating (identification procedure
and data transfer) with any MultiMediaCard host using any operating voltage within 1.7 V
and 1.95 V (low-voltage range) or 2.7 V and 3.6 V (high-voltage range) depending on the
voltage range supported by the host. For further details, refer to section 8.1 of the JEDEC
Standard Specification No. JESD84-A43.
If the host tries to change the OCR values during an initialization procedure the changes in
the OCR content will be ignored.
The level coding of the OCR register is as follows:
■
■
Restricted voltage windows = Low
Device busy = Low
Table 6.
OCR register definition
OCR bit
Description
MultiMediaCard
6 to 0
7
Reserved
Low VCCQ
2.0 - 2.6
000 0000b
1b
14 to 8
000 0000b
1 1111 1111b
000 0000b
10b (sector mode)
23 to 15
28 to 24
30 to 29
31
2.7 - 3.6 (High VCCQ range)
Reserved
Access mode
Power-up status bit (busy)(1)
1. This bit is set to Low if the device has not finished the power-up routine.
18/32
NANDxxxAH0K
Device registers
7.2
Card identification (CID) register
The CID register is 16-byte long and contains a unique card identification number used
during the card identification procedure. It is a 128-bit wide register with the content as
defined in Table 7. It is programmed during device manufacturing and can not be changed
by MultiMediaCard hosts. For details, refer to section 8.2 of the JEDEC Standard
Specification No. JESD84-A43.
Table 7.
Card identification (CID) register
Name
Field
Width
CID - slice
CID - value
Note
Manufacturer ID
Reserved
MID
8
6
2
8
[127:120]
[119:114]
[113:112]
[111:104]
0xFE
Card/BGA
CBX
OID
0x01
0x4E
BGA
OEM/application ID
MMC04G, MMC08G,
MMC16G MMC32G
Product name
PNM
48
[103:56]
Product revision
PRV
PSN
MDT
CRC
–
8
32
8
[55:48]
[47:16]
[15:8]
[7:1]
Product serial number
Manufacturing date
CRC7 checksum
TBD
TBD
TBD
1
7
Not used, always ‘1’
1
[0:0]
7.3
Card specific data register (CSD)
All the configuration information required to access the device data is stored in the CSD
register. The MSB bytes of the register contain the manufacturer data and the two least
significant bytes contains the host controlled data (the device copy, write protection and the
user ECC register).
The host can read the CSD register and alter the host controlled data bytes using the
SEND_CSD and PROGRAM_CSD commands.
In Table 8, the cell type column defines the CSD field as read only (R), one time
programmable (R/W) or erasable (R/W/E). The programmable part of the register (entries
marked by W or E) can be changed by command CMD27.
The copy bit in the CSD can be used to mark the device as an original or a copy. Once set it
cannot be cleared. The device can be purchased with the copy bit set (copy) or cleared,
indicating the device is a master.
The one time programmable (OTP) characteristic of the copy bit is implemented in the
MultiMediaCard controller firmware and not with a physical OTP cell.
For details, refer to section 8.3 of the JEDEC Standard Specification No. JESD84-A43.
19/32
Device registers
NANDxxxAH0K
CSD-value
Table 8.
Card specific data register
Width Cell
[bits] type
Name
Field
CSD-slice
CSD structure
CSD_STRUCTURE
SPEC_VERS
2
4
R
R
[127:126]
[125:122]
0x02
0x04
MultiMediaCard protocol
version
Reserved
2
8
R
R
[121:120]
[119:112]
TBD
Data read access-time-1
TAAC
NSAC
0x4F
Data read access-time-2 in
CLK cycles (NSAC*100)
8
R
[111:104]
0x01
Max. data transfer rate
Command classes
TRAN_SPEED
CCC
8
12
4
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
[103:96]
[95:84]
[83:80]
[79:79]
[78:78]
[77:77]
[76:76]
[75:74]
[73:62]
[61:59]
[58:56]
[55:53]
[52:50]
[49:47]
[46:42]
[41:37]
[36:32]
[31:31]
[30:29]
[28:26]
[25:22]
[21:21]
[20:20]
[16:16]
[15:15]
[14:14]
[13:13]
[12:12]
0x32
0xF5
0x09
0x01
0x00
0x00
0x00
TBD
TBD
0x07
0x07
0x07
0x07
0x07
0x1F
0x1F
0x0F
0x01
TBD
0x02
0x09
0x00
TBD
0x00
0x00
0x00
0x00
0x00
Max. read data block length
READ_BL_LEN
Partial blocks for read allowed READ_BL_PARTIAL
1
Write block misalignment
Read block misalignment
DSR implemented
Reserved
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
1
1
1
2
Device size
C_SIZE
12
3
Max. read current at VCC(min) VDD_R_CURR_MIN
Max. read current at VCC(max) VDD_R_CURR_MAX
Max. write current at VCC(min) VDD_W_CURR_MIN
Max. write current at VCC(max) VDD_W_CURR_MAX
3
3
3
Device size multiplier
C_SIZE_MULT
3
Erase group size
ERASE_GRP_SIZE
ERASE_GRP_MULT
WP_GRP_SIZE
WP_GRP_ENABLE
DEFAULT_ECC
5
Erase group size multiplier
Write protect group size
Write protect group enable
Manufacturer default ECC
Write speed factor
5
5
1
2
R2W_FACTOR
3
Max. write data block length
WRITE_BL_LEN
4
Partial blocks for write allowed WRITE_BL_PARTIAL
Reserved
1
Content protection application CONTENT_PROT_APP
1
1
1
1
1
R
File format group
FILE_FORMAT_GROUP
COPY
R/W
R/W
R/W
R/W/E
Copy flag (OTP)
Permanent write protection
Temporary write protection
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
20/32
NANDxxxAH0K
Device registers
CSD-value
Table 8.
Card specific data register (continued)
Width Cell
[bits] type
Name
Field
CSD-slice
Hard disk like file
system with partition
table
File format
FILE_FORMAT
2
R/W
[11:10]
ECC code 2 R/W/E none 0
CRC
ECC
CRC
2
7
1
R/W/E
R/W/E
–
[9:8]
[7:1]
[0:0]
0x00
TBD
TBD
Not used, always ‘1’
7.4
Extended CSD register
The extended CSD register defines the device properties and selected modes. It is 512-byte
long. The 320 most significant bytes are the properties segment that defines the device
capabilities and cannot be modified by the host. The 192 lower bytes are the modes
segment that defines the configuration the device is working in. For details, refer to section
8.4 of the JEDEC Standard Specification No. JESD84-A43.
These modes can be changed by the host by means of the Switch command.
(1)
Table 9.
Extended CSD
CSD-slice
value
Name
Field
Size (bytes)
Cell type
CSD-slice
Properties segment
Reserved(2)
7
1
[511:505]
[504]
TBD
0x01
TBD
0x01
TBD
0x02
0x00
Supported command sets S_CMD_SET
Reserved(2)
R
TBD
R
275
1
[503:229]
[228]
Boot information
Reserved(2)
BOOT_INFO
1
TBD
R
[227]
Boot partition size
Access size
BOOT_SIZE_MULTI
ACC_SIZE
1
[226]
1
R
[225]
High-capacity erase unit
size
HC_ERASE_GRP_SIZE
ERASE_TIMEOUT_MULT
1
R
[224]
0x00
High-capacity erase
timeout
1
1
1
R
R
R
[223]
[222]
[221]
0x03
0x01
0x00
Reliable write sector count REL_WR_SEC_C
High-capacity write protect
HC_WP_GRP_SIZE
group size
Sleep current (VCC
)
S_C_VCC
1
1
1
1
1
R
R
[220]
[219]
[218]
[217]
[216]
0x04
0x08
TBD
0x0B
TBD
Sleep current (VCCQ
Reserved(2)
)
S_C_VCCQ
TBD
R
Sleep/awake timeout
Reserved(2)
S_A_TIMEOUT
TBD
21/32
Device registers
NANDxxxAH0K
CSD-slice
(1)
Table 9.
Extended CSD (continued)
Name Field
Size (bytes)
Cell type
CSD-slice
value
According
to device
density
Sector count
Reserved(2)
SEC_COUNT
4
1
1
R
[215:212]
[211]
TBD
Minimum write
performance for 8 bit at
52 MHz
MIN_PERF_W_8_52
MIN_PERF_R_8_52
R
R
[210]
0x08
Minimum read
performance for 8 bit at
52 MHz
1
1
[209]
[208]
0x08
0x08
Minimum write
performance for 8 bit at
26 MHz, for 4 bit at
52 MHz
MIN_PERF_W_8_26_4_5
2
R
R
Minimum read
performance for 8 bit at
26 MHz, for 4 bit at
52 MHz
MIN_PERF_R_8_26_4_5
2
1
[207]
0x08
Minimum write
performance for 4 bit at
26 MHz
MIN_PERF_W_4_26
MIN_PERF_R_4_26
1
1
R
R
[206]
[205]
0x08
0x08
Minimum read
performance for 4 bit at
26 MHz
Reserved(2)
1
1
[204]
[203]
TBD
0x00
Power class for 26 MHz at
3.6 V
PWR_CL_26_360
PWR_CL_52_360
PWR_CL_26_195
PWR_CL_52_195
R
R
R
R
Power class for 52 MHz at
3.6 V
1
1
1
[202]
[201]
[200]
0x00
0x00
0x00
Power class for 26 MHz at
1.95 V
Power class for 52 MHz at
1.95 V
Reserved(2)
3
1
1
1
1
1
[199:197]
[196]
TBD
0x03
TBD
0x02
TBD
0x03
Card type
CARD_TYPE
R
R
Reserved(2)
[195]
CSD structure version
Reserved(2)
CSD_STRUCTURE
EXT_CSD_REV
CMD_SET
[194]
[193]
Extended CSD revision
Modes segment
Command set
R
[192]
1
1
1
R/W
RO
[191]
[190]
[189]
0x00
TBD
0x00
Reserved(2)
Command set revision
CMD_SET_REV
22/32
NANDxxxAH0K
Device registers
CSD-slice
(1)
Table 9.
Extended CSD (continued)
Name
Field
Size (bytes)
Cell type
CSD-slice
value
Reserved(2)
Power class
Reserved(2)
1
1
1
[188]
[187]
[186]
TBD
0x00
TBD
POWER_CLASS
HS_TIMING
R/W
R/W
High speed interface
timing
1
[185]
0x00
Reserved(2)
1
1
1
1
1
1
1
1
1
[184]
[183]
[182]
[181]
[180]
[179]
[178]
[177]
[176]
TBD
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
Bus width mode
Reserved(2)
BUS_WIDTH
WO
RO
Erased memory content
Reserved(2)
ERASED_MEM_CONT
BOOT_CONFIG
Boot configuration
Reserved(2)
R/W
R/W
Boot bus width 1
Reserved(2)
BOOT_BUS_WIDTH
High-density erase group
definition
ERASE_GROUP_DEF
1
R/W
[175]
0x00
TBD
Reserved(2)
175
[174:0]
1. TBD stands for ‘to be defined’.
2. Reserved bits should read as ‘0’.
23/32
Device registers
NANDxxxAH0K
7.5
RCA (relative card address) register
The writable 16-bit relative card address (RCA) register carries the device address assigned
by the host during the device identification. This address is used for the addressed host-card
communication after the device identification procedure. The default value of the RCA
register is ‘0x0001’. The value ‘0x0000’ is reserved to set all cards into the standby state
with CMD7. For details refer to section 8.5 of the JEDEC Standard Specification No.
JESD84-A43.
7.6
DSR (driver stage register) register
The 16-bit driver stage register (DSR) can be optionally used to improve the bus
performance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of devices on the bus).
The CSD register contains the information concerning the DSR register usage.
The default value of the DSR register is ‘0x404’. For details refer to section 8.6 of the
JEDEC Standard Specification No. JESD84-A43.
7.7
Status register
The status register provides information about the device current state and completion
codes for the last host command. The device status can be explicitly read (polled) with the
SEND_STATUS command. The MultiMediaCard status register structure is defined in
section 7.12 of the JEDEC Standard Specification No. JESD84-A43.
24/32
NANDxxxAH0K
Package mechanical
8
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
25/32
Package mechanical
NANDxxxAH0K
Figure 7.
LFBGA169 14 x 18 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline
D
D1
SD
b
e
SE
E
E4 E3 E2 E1
ddd
FE
FE1
FE2
FE3
FD
e
FD1
FD2
FD3
A2
A
A1
ZD_ME
1. Drawing is not to scale.
26/32
NANDxxxAH0K
Package mechanical
inches
Table 10.
LFBGA169 14 x 18 x 1.4 mm 132+21+16 3R14 0.50 mm, package mechanical data
millimeters
Min
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
–
–
1.40
0.26
1.11
0.35
14.10
–
–
0.055
0.010
0.044
0.014
0.555
0.21
1.06
0.30
14.00
6.50
0.16
1.01
0.25
13.90
0.008
0.042
0.012
0.551
0.256
0.006
0.040
0.010
0.547
D
D1
ddd
E
0.08
0.003
0.705
18.00
6.50
10.50
12.50
13.50
0.50
3.75
4.25
5.25
6.25
5.75
3.75
2.75
2.25
0.25
0.25
17.90
18.10
0.709
0.256
0.413
0.492
0.531
0.020
0.148
0.167
0.207
0.246
0.226
0.148
0.108
0.088
0.010
0.010
0.713
E1
E2
E3
E4
e
–
–
–
–
FD
FD1
FD2
FD3
FE
FE1
FE2
FE3
SD
SE
–
–
–
–
–
–
–
–
27/32
Package mechanical
NANDxxxAH0K
Figure 8.
TFBGA169 14 x 18 x 1.2 mm 132+21+16 3R14 0.50 mm, package outline
D
D1
SD
b
e
SE
E
E4 E3 E2 E1
ddd
FE
FE1
FE2
FE3
FD
e
A
A2
A1
ZE-ME
1. Drawing is not to scale.
28/32
NANDxxxAH0K
Package mechanical
inches
Table 11.
TFBGA169 14 x 18 x 1.2 mm 132+21+16 3R14 0.50 mm, package mechanical data
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
–
–
1.20
–
–
0.047
0.15
0.85
0.35
14.00
6.50
0.006
0.033
0.014
0.551
0.256
0.30
0.40
0.012
0.547
0.016
0.555
D
13.90
14.10
D1
ddd
E
0.08
0.003
0.705
18.00
6.50
10.50
12.50
13.50
0.50
3.75
5.75
3.75
2.75
2.25
0.25
0.25
17.90
18.10
0.709
0.256
0.413
0.492
0.531
0.020
0.148
0.226
0.148
0.108
0.088
0.010
0.010
0.713
E1
E2
E3
E4
e
–
–
–
–
FD
FE
FE1
FE2
FE3
SD
SE
–
–
–
–
–
–
–
–
29/32
Ordering information
NANDxxxAH0K
9
Ordering information
Table 12. Ordering information scheme
Example:
NAND32GAH
0
K
ZE
5
F
Device type
NAND flash memory
Density
32G = 4 Gbytes
64G = 8 Gbytes
128 = 16 Gbytes
256 = 32 Gbytes
Operating voltage
A = VCC= 3.3 V, VCCQ = 1.8 V or 3.3 V
Memory type
H = eMMC
Device options
0 = no option
Product version
K = version K
Package
ZD = LFBGA169 14 x 18 x 1.4 mm (only for 32-Gbyte devices)
ZE = TFBGA169 14 x 18 x 1.2 mm (only for 4-, 8-, and 16-Gbyte devices)
Temperature range
5 = −25 to 85 °C
Packing
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape & reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to ’1’. For further
information on any aspect of these devices, please contact your nearest Numonyx sales
office.
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NANDxxxAH0K
Revision history
10
Revision history
Table 13. Document revision history
Date
Revision
Changes
01-Dec-2008
1
Initial release.
Modified Figure 7: LFBGA169 12 x 16 1.4 mm 132+21+16 3R14
0.50 mm, package outline and Figure 7: LFBGA169 14 x 18 x 1.4 mm
132+21+16 3R14 0.50 mm, package outline.
03-Feb-2009
27-Oct-2009
2
3
Removed references to ECOPACK packages throughout the
document.
Changed datasheet’s name from NANDxxxAH0PK to NANDxxxAH0K
Removed LFBGA169 12 x 16 x 1.4 mm and added TFBGA169
14 x 18 x 1.2 mm package throughout the document.
Modified: Table 2: System performance, Table 3: Current
consumption, Table 8: Card specific data register, Table 9: Extended
CSD, Table 12: Ordering information scheme, and note 1 below
Figure 5: Power-up.
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NANDxxxAH0K
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