PC28F320C3BD70 [NUMONYX]
Flash, 2MX16, 70ns, PBGA64, LEAD FREE, BGA-64;
| 型号： | PC28F320C3BD70 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 2MX16, 70ns, PBGA64, LEAD FREE, BGA-64 内存集成电路 闪存 |
| 文件： | 总70页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Numonyx™ Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3 (x16)
Datasheet
Product Features
Flexible SmartVoltage Technology
— 2.7 V– 3.6 V read/program/erase
— 12 V for fast production programming
1.65 V to 2.5 V or 2.7 V to 3.6 V I/O Option
— Reduces overall system power
High Performance
128-bit Protection Register
— 64 bit unique device identifier
— 64 bit user programmable OTP cells
Extended Cycling Capability
— Minimum 100,000 block erase cycles
Software
— 2.7 V– 3.6 V: 70 ns max access time
— Supported by Numonyx Advanced Flash
File Managers -- Numonyx™ VFM,
Numonyx™ FDI, etc.
Optimized Architecture for Code Plus Data
Storage
— Code and data storage in the same
memory device
— Eight 4 Kword blocks, top or bottom
parameter boot
— Robust Power Loss Recovery for Data Loss
Prevention
— Common Flash Interface
Standard Surface Mount Packaging
— 48-Ball μBGA*/VFBGA
— 64-Ball Easy BGA packages
— 48-TSOP package
Intel ETOX* VIII (0.13 μm) Flash Technology
— 8, 16, 32 Mbit
— Up to 127 x 32 Kword blocks
— Fast program suspend capability
— Fast erase suspend capability
Flexible Block Locking
— Lock/unlock any block
— Full protection on power-up
— Write Protect (WP#) pin for hardware block
protection
Low Power Consumption
Intel ETOX* VII (0.18 μm) Flash Technology
— 16, 32 Mbit
Intel ETOX* VI (0.25 μm) Flash Technology
— 8, 16 and 32 Mbit
— 9 mA typical read
— 7 uA typical standby with Automatic Power
Savings feature
Extended Temperature Operation
— -40 °C to +85 °C
290645-24
March 2008
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet
2
March 2008
290645-24
C3 Discrete
Contents
1.0 Introduction..............................................................................................................7
1.1
1.2
Nomenclature.....................................................................................................7
Conventions .......................................................................................................8
2.0 Functional Overview..................................................................................................9
2.1
2.2
2.3
Product Overview................................................................................................9
Block Diagram .................................................................................................. 10
Memory Map..................................................................................................... 10
3.0 Package Information............................................................................................... 13
3.1
3.2
3.3
mBGA* and VF BGA Package .............................................................................. 13
TSOP Package................................................................................................... 14
Easy BGA Package............................................................................................. 15
4.0 Ballout and Signal Descriptions ............................................................................... 16
4.1
4.2
4.3
48-Lead TSOP Package ...................................................................................... 16
64-Ball Easy BGA Package.................................................................................. 19
Signal Descriptions............................................................................................ 19
5.0 Maximum Ratings and Operating Conditions............................................................ 21
5.1
5.2
Absolute Maximum Ratings................................................................................. 21
Operating Conditions ......................................................................................... 21
6.0 Electrical Specifications........................................................................................... 23
6.1
6.2
Current Characteristics....................................................................................... 23
DC Voltage Characteristics.................................................................................. 24
7.0 AC Characteristics ................................................................................................... 26
7.1
7.2
7.3
7.4
7.5
AC Read Characteristics ..................................................................................... 26
AC Write Characteristics..................................................................................... 30
Erase and Program Timings ................................................................................ 34
AC I/O Test Conditions....................................................................................... 34
Device Capacitance ........................................................................................... 35
8.0 Power and Reset Specifications............................................................................... 36
8.1
8.2
8.3
8.4
8.5
Active Power (Program/Erase/Read) .................................................................... 36
Automatic Power Savings (APS) .......................................................................... 36
Standby Power.................................................................................................. 36
Deep Power-Down Mode..................................................................................... 36
Power and Reset Considerations.......................................................................... 37
8.5.1 Power-Up/Down Characteristics................................................................ 37
8.5.2 RP# Connected to System Reset .............................................................. 37
8.5.3 VCC, VPP and RP# Transitions.................................................................. 37
8.5.4 Reset Specifications................................................................................ 37
Power Supply Decoupling ................................................................................... 38
8.6
9.0 Device Operations ................................................................................................... 39
9.1
Bus Operations ................................................................................................. 39
9.1.1 Read .................................................................................................... 39
9.1.2 Write.................................................................................................... 39
9.1.3 Output Disable....................................................................................... 39
9.1.4 Standby................................................................................................ 39
9.1.5 Reset.................................................................................................... 40
10.0 Modes of Operation ................................................................................................. 41
March 2008
290645-24
Datasheet
3
C3 Discrete
10.1 Read Mode........................................................................................................41
10.1.1 Read Array ............................................................................................41
10.1.2 Read Identifier .......................................................................................41
10.1.3 CFI Query..............................................................................................42
10.1.4 Read Status Register...............................................................................42
10.1.4.1 Clear Status Register.................................................................43
10.2 Program Mode...................................................................................................43
10.2.1 12-Volt Production Programming ..............................................................43
10.2.2 Suspending and Resuming Program ..........................................................44
10.3 Erase Mode.......................................................................................................44
10.3.1 Suspending and Resuming Erase ..............................................................44
11.0 Security Modes ........................................................................................................48
11.1 Flexible Block Locking.........................................................................................48
11.1.1 Locking Operation...................................................................................48
11.1.1.1 Locked State ............................................................................49
11.1.1.2 Unlocked State .........................................................................49
11.1.1.3 Lock-Down State.......................................................................49
11.2 Reading Block-Lock Status..................................................................................49
11.3 Locking Operations during Erase Suspend .............................................................49
11.4 Status Register Error Checking ............................................................................50
11.5 128-Bit Protection Register .................................................................................50
11.5.1 Reading the Protection Register................................................................50
11.5.2 Programming the Protection Register.........................................................51
11.5.3 Locking the Protection Register.................................................................51
11.6 VPP Program and Erase Voltages ..........................................................................51
11.6.1 Program Protection .................................................................................51
Datasheet
4
March 2008
290645-24
C3 Discrete
Revision History
Date of
Version
Revision
Description
05/12/98
-001
Original version
48-Lead TSOP package diagram change
μBGA package diagrams change
32-Mbit ordering information change (Section 6)
CFI Query Structure Output Table Change (Table C2)
CFI Primary-Vendor Specific Extended Query Table Change for Optional Features and
Command Support change (Table C8)
07/21/98
-002
Protection Register Address Change
I
test conditions clarification (Section 4.3)
μBGA package top side mark information clarification (Section 6)
PPD
Byte-Wide Protection Register Address change
V
V
CCS
Specification change (Section 4.3)
IH
IL
Maximum Specification change (Section 4.3)
10/03/98
12/04/98
-003
-004
I
test conditions clarification (Section 4.3)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory
Family.
Added t
/t
and t
(Section 4.6)
QVBL
BHWH BHEH
Programming the Protection Register clarification (Section 3.4.2)
12/31/98
02/24/99
-005
-006
Removed all references to x8 configurations
Removed reference to 40-Lead TSOP from front page
Added Easy BGA package (Section 1.2)
Removed 1.8 V I/O references
06/10/99
-007
Locking Operations Flowchart changed (Appendix B)
Added t
(Section 4.6)
WHGL
CFI Primary Vendor-Specific Extended Query changed (Appendix C)
Max I changed to 25 µA
Table 10, added note indicating V Max = 3.3 V for 32-Mbit device
CC
CCD
03/20/00
04/24/00
-008
-009
Added specifications for 0.18 micron product offerings throughout document Added 64-
Mbit density
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
10/12/00
-010
Changed VccMax=3.3V reference to indicate that the affected product is the 0.25μm
32Mbit device.
Minor text edits throughout document.
Added 1.8v I/O operation documentation where applicable
Added TSOP PCN ‘Pin-1’ indicator information
Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Information
Removed 0.4 µm references in DC characteristics table
Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA
Corrected ‘bottom’ parameter block sizes to on 8Mb device to 8 x 4KWords
Minor text edits throughout document
7/20/01
-011
10/02/01
2/05/02
-012
-013
Added specifications for 0.13 micron product offerings throughout document
Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
Updated 64Mb product offerings.
Updated 16Mb product offerings.
4/05/02
3/06/03
-014
-016
Revised and corrected DC Characteristics Table.
Added mechanicals for Easy BGA.
Minor text edits throughout document.
Complete technical update.
March 2008
290645-24
Datasheet
5
C3 Discrete
Date of
Revision
Version
Description
10/01/03
5/20/04
9/1/04
-017
-018
-019
-020
Corrected information in the Device Geometry Details table, address 0x34.
Updated the layout of the datasheet.
Fixed typo for Standby power on cover page.
9/14/04
Added lead-free line items to Table 38, “Product Information Ordering Matrix” on page 70.
Added specification for 8Mb 0.13 micron device.
Added 0.13 micron to Table 38, “Product Information Ordering Matrix” on page 70.
9/27/04
1/26/05
-021
-022
Converted datasheet to new template. Deleted Description in Table 4. Deleted Note in
Figure 5.
Removed all 64M ordering information, removed VF BGA 8M ordering information.
Removed 64M reference in title page only. Added software verbiage in title page. Corrected
Lead Width (b) measurement in Fig 2., uBGA and VF BGA Package Drawing and
Dimensions, page 12.
5/16/05
-023
24
March 2008
Applied Numnyx branding.
Datasheet
6
March 2008
290645-24
C3 Discrete
1.0
Introduction
This datasheet contains the specifications for the Numonyx™ Advanced+ Boot Block
Flash Memory (C3) device family, hereafter called the C3 flash memory device. These
flash memories add features such as instant block locking and protection registers that
can be used to enhance the security of systems.
The Numonyx™ Advanced+ Book Block Flash Memory (C3) device, manufactured on
Intel’s latest 0.13 μm and 0.18 μm technologies, represents a feature-rich solution for
low-power applications. The C3 device incorporates low-voltage capability (3 V read,
program, and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Numonyx™
Flash Data Integrator (Numonyx™ FDI) software and you have a cost-effective,
flexible, monolithic code plus data storage solution. Numonyx™ Advanced+ Boot Block
Flash Memory (C3) products are available in 48-lead TSOP, 48-ball CSP, and 64-ball
Easy BGA packages. Additional information on this product family can be obtained from
the Numonyx™ Flash website: http://www.Numonyx.com
1.1
Nomenclature
0x
Hexadecimal prefix
Binary prefix
8 bits
0b
Byte
Word
16 bits
KW or Kword 1024 words
Mword
Kb
1,048,576 words
1024 bits
KB
1024 bytes
Mb
1,048,576 bits
MB
1,048,576 bytes
APS
CSP
CUI
OTP
PR
Automatic Power Savings
Chip Scale Package
Command User Interface
One Time Programmable
Protection Register
Protection Register Data
Protection Lock Register
Reserved for Future Use
Status Register
PRD
PLR
RFU
SR
SRD
WSM
Status Register Data
Write State Machine
March 2008
290645-24
Datasheet
7
C3 Discrete
1.2
Conventions
The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package; for chip scale package (CSP) the term ball is used.
Group Membership Brackets: Square brackets will be used to designate group
membership or to define a group of signals with similar function (i.e. A[21:1], SR[4:1])
Set: When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block: A group of bits (or words) that erase simultaneously with one block erase
instruction.
Main Block: A block that contains 32 Kwords.
Parameter Block: A block that contains 4 Kwords.
Datasheet
8
March 2008
290645-24
C3 Discrete
2.0
Functional Overview
This section provides an overview of the Numonyx™ Advanced+ Boot Block Flash
Memory (C3) device features and architecture.
2.1
Product Overview
The C3 flash memory device provides high-performance asynchronous reads in
package-compatible densities with a 16 bit data bus. Individually-erasable memory
blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks
are located in the boot block at either the top or bottom of the device’s memory map.
The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3
V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC
and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O
voltage flexibility, the dedicated VPP input provides complete data protection when VPP
≤ VPPLK
.
The C3 Discrete device features a 128-bit protection register enabling security
techniques and data protection schemes through a combination of factory-programmed
and user-programmable OTP data registers. Zero-latency locking/unlocking on any
memory block provides instant and complete protection for critical system code and
data. Additional block lock-down capability provides hardware protection where
software commands alone cannot change the block’s protection status.
A command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence issued to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS),
standby mode, and deep power-down mode. The device automatically enters APS
mode following read cycle completion. Standby mode begins when the system
deselects the flash memory by deasserting Chip Enable, CE#. The deep power-down
mode begins when Reset Deep Power-Down, RP# is asserted, which deselects the
memory and places the outputs in a high-impedance state, producing ultra-low power
savings. Combined, these three power-savings features significantly enhanced power
consumption flexibility.
March 2008
290645-24
Datasheet
9
C3 Discrete
2.2
Block Diagram
Figure 1: C3 Flash Memory Device Block Diagram
DQ 0-DQ15
V
CCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
RP#
WP#
Y-Decoder
X-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
A[MAX:MIN]
Input Buffer
V
PP
Address
Latch
V
CC
GND
Address
Counter
2.3
Memory Map
The C3 Discrete device is asymmetrically blocked, which enables system code and data
integration within a single flash device. The bulk of the array is divided into 32 Kword
main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage
of boot code or for frequently changing small parameters. See Table 1, “Top Boot
Memory Map” on page 11 and Table 2, “Bottom Boot Memory Map” on page 12 for
details.
Datasheet
10
March 2008
290645-24
C3 Discrete
Table 1:
Top Boot Memory Map
8-Mbit
Size
16-Mbit
Memory
Addressing
(Hex)
32-Mbit
Memory
Addressin
g (Hex)
64-Mbit
Memory
Addressing
(Hex)
Size
(KW Blk
)
Size
(KW Blk
)
Size
(KW Blk
)
Memory
(KW Blk
Addressin
)
g (Hex)
7F000-
1FF000-
1FFFFF
4
4
22
21
20
19
18
17
16
15
14
13
12
4
4
38
37
36
35
34
33
32
31
30
29
28
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
4
4
70
69
68
67
66
65
64
63
62
61
60
4
4
134
133
3FF000-3FFFFF
3FE000-3FEFFF
7FFFF
7E000-
7EFFF
1FE000-
1FEFFF
7D000-
7DFFF
1FD000-
1FDFFF
4
4
4
4
132 3FD000-3FDFFF
7C000-
7CFFF
1FC000-
1FCFFF
4
4
4
4
131
130
129
128
127
126
125
124
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
7B000-
7BFFF
1FB000-
1FBFFF
4
4
4
4
7A000-
7AFFF
1FA000-
1FAFFF
4
4
4
4
79000-
79FFF
1F9000-
1F9FFF
4
4
4
4
78000-
78FFF
1F8000-
1F8FFF
4
4
4
4
70000-
77FFF
1F0000-
1F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
68000-
6FFFF
1E8000-
1EFFFF
60000-
67FFF
1E0000-
1E7FFF
58000-
5FFFF
1D8000-
1DFFFF
32
...
11
...
2
32
...
27
...
2
D8000-DFFFF
...
32
...
59
...
2
32
...
123 3D8000-3DFFFF
...
...
...
2
...
10000-
17FFF
10000-
17FFF
32
32
10000-17FFF
32
32
10000-17FFF
08000-
0FFFF
32
32
1
0
8000-0FFFF
0000-07FFF
32
32
1
0
08000-0FFFF
00000-07FFF
32
32
1
0
32
32
1
0
08000-0FFFF
00000-07FFF
00000-
07FFF
March 2008
290645-24
Datasheet
11
C3 Discrete
Table 2:
Bottom Boot Memory Map
8-Mbit
Memory
Addressin
g (Hex)
16-Mbit
32-Mbit
Memory
Addressing
(Hex)
64-Mbit
Memory
Addressing
(Hex)
Size
(KW Blk
)
Size
(KW Blk
)
Size
(KW Blk
)
Size
(KW Blk
)
Memory
Addressing
(Hex)
78000-
7FFFF
1F8000-
1FFFFF
32
32
32
22
21
20
32
32
32
38
37
36
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
32
32
32
70
69
68
32
32
32
134
133
132
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
70000-
77FFF
1F0000-
1F7FFF
68000-
6FFFF
1E8000-
1EFFFF
60000-
67FFF
1E0000-
1E7FFF
32
...
19
...
32
...
35
...
E0000-E7FFF
...
32
...
67
...
32
.
131
...
3E0000-3E7FFF
...
...
...
18000-
1FFFF
32
10
32
10
18000-1FFFF
32
10
18000-1FFFF
32
10
18000-1FFFF
10000-
17FFF
32
32
4
9
8
7
6
5
4
3
2
1
0
32
32
4
9
8
7
6
5
4
3
2
1
0
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
32
32
4
9
8
7
6
5
4
3
2
1
0
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
32
32
4
9
8
7
6
5
4
3
2
1
0
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
08000-
0FFFF
07000-
07FFF
06000-
06FFF
4
4
4
4
05000-
05FFF
4
4
4
4
04000-
04FFF
4
4
4
4
03000-
03FFF
4
4
4
4
02000-
02FFF
4
4
4
4
01000-
01FFF
4
4
4
4
00000-
00FFF
4
4
4
4
Datasheet
12
March 2008
290645-24
C3 Discrete
3.0
Package Information
3.1
μBGA* and VF BGA Package
Figure 2: μBGA* and VF BGA Package Drawing and Dimensions
C3 Discrete 8/16/32/64M,
.25,.18, .13u ubga/VFBGA
R0
Ball A1
Corner
Ball A1
Corner
D
S1
S2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2 1
A
B
C
D
A
B
C
E
D
E
F
e
E
F
b
Top View - Bump Side down
Bottom View-Bump side up
A
1
A2
A
Seating
Plan
Y
Side View
Note: Drawing not to scale
Millimeters
Inches
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length 8M (.25)
Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13)
Package Body Length 64M (.18)
Package Body Width 8M (.25)
Package Body Width 16M (.25/.18/.13) 32M (.18/.13)
Package Body Width 32M (.25)
Package Body Width 64M (.18)
Pitch
Ball (Lead) Count 8M, 16M
Ball (Lead) Count 32M
Ball (Lead) Count 64M
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D 8M (.25)
Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13S)1
Corner to Ball A1 Distance Along D 64M (.18)
Corner to Ball A1 Distance Along E 8M (.25)
Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.1S32)
Symbol
Min
Nom
Max
1.000
Min
Nom
Max
0.0394
A
A1
A2
b
D
D
D
E
E
E
E
e
N
N
N
Y
S1
0.150
0.0059
0.0128
0.665
0.375
7.910
7.286
7.700
6.500
6.964
0.0262
0.0148
0.325
7.810
7.186
7.600
6.400
6.864
0.425
8.010
7.386
7.800
6.600
7.064
10.860
9.100
0.0167
0.2829
0.2992
0.2520
0.2702
0.4232
0.3504
0.2868
0.3031
0.2559
0.2742
0.4272
0.3543
0.0295
46
0.2908
0.3071
0.2598
0.2781
0.4276
0.3583
10.750 10.850
8.900
9.000
0.750
46
47
48
47
48
0.100
1.430
1.118
1.325
1.475
1.707
3.650
2.725
0.0039
0.0563
0.0440
0.0522
0.0581
0.0672
0.1437
0.1073
1.230
0.918
1.125
1.275
1.507
3.450
2.525
1.330
1.018
1.225
1.375
1.607
3.550
2.625
0.0484
0.0361
0.0443
0.0502
0.0593
0.1358
0.0994
0.0524
0.0401
0.0482
0.0541
0.0633
0.1398
0.1033
S1
S2
Corner to Ball A1 Distance Along E 32M (.25)
Corner to Ball A1 Distance Along E 64M (.18)
S2
S2
March 2008
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Datasheet
13
C3 Discrete
3.2
TSOP Package
Figure 3: TSOP Package Drawing and Dimensions
Z
A
2
See Notes 1, 2, 3 and 4
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
b
0
L
Notes:
1.
2.
3.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Table 3:
TSOP Package Dimensions
Millimeters
Nom
Inches
Nom
Parameter
Symbol
Min
Max
Min
Max
Package Height
A
A1
A2
b
1.200
0.047
Standoff
Package Body Thickness
Lead Width
0.050
0.950
0.150
0.100
18.200
11.800
0.002
0.037
0.006
0.004
0.717
0.465
1.000
0.200
0.150
18.400
12.000
0.500
20.000
0.600
48
1.050
0.300
0.039
0.008
0.006
0.724
0.472
0.0197
0.787
0.024
48
0.041
0.012
0.008
0.732
0.480
Lead Thickness
c
0.200
Package Body Length
Package Body Width
Lead Pitch
D1
E
18.600
12.200
e
Terminal Dimension
Lead Tip Length
D
L
19.800
0.500
20.200
0.700
0.780
0.020
0.795
0.028
Lead Count
N
Lead Tip Angle
Θ
0°
3°
5°
0°
3°
5°
Seating Plane Coplanarity
Lead to Package Offset
Y
0.100
0.350
0.004
0.014
Z
0.150
0.250
0.006
0.010
Datasheet
14
March 2008
290645-24
C3 Discrete
3.3
Easy BGA Package
Figure 4: Easy BGA Package Drawing and Dimension
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
A
B
C
D
E
b
e
E
F
F
G
H
G
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Dimensions Table
Millimeters
Min
Inches
Min
Symbol
A
Nom
Max Notes
1.200
Nom
Max
Package Height
0.0472
1
Ball Height
A
A
0.250
0.0098
2
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
0.780
0.430
10.000
13.000
1.000
64
0.0307
0.0169
0.3937
0.5118
0.0394
64
b
D
E
[e]
N
Y
0.330
9.900
12.900
0.530
10.100
13.100
0.0130
0.3898
0.5079
0.0209
0.3976
0.5157
1
1
0.100
1.600
3.100
0.0039
0.0630
0.1220
1
S
S
1.400
2.900
1.500
3.000
1
1
0.0551
0.1142
0.0591
0.1181
2
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
March 2008
290645-24
Datasheet
15
C3 Discrete
4.0
Ballout and Signal Descriptions
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball μBGA, and Easy
BGA packages. See Figure 5 on page 16, Figure 7 on page 18, and Figure 8 on
page 19, respectively.
4.1
48-Lead TSOP Package
Figure 5: 48-Lead TSOP Package
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
A8
64 M
32 M
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
16 M
Datasheet
16
March 2008
290645-24
C3 Discrete
Figure 6: Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-Mb and 32-Mb TSOP
Current Mark:
New Mark:
Note:
The topside marking on 8 Mb, 16 Mb, and 32 Mb Numonyx™ Advanced and Advanced +
Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator.
Products without the white triangle will continue to use a dimple as a Pin 1 indicator.
There are no other changes in package size, materials, functionality, customer
handling, or manufacturability. Product will continue to meet Numonyx stringent quality
requirements. Products affected are Numonyx Ordering Codes shown in Table 4.
Table 4:
48-Lead TSOP
Extended
Extended 64 Mbit
Extended 32 Mbit
Extended 16 Mbit
TE28F320C3TD70
TE28F320C3BD70
TE28F160C3TD70
TE28F160C3BD70
TE28F800C3TA90
TE28F800C3BA90
TE28F320C3TC70
TE28F320C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC90
TE28F320C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100
TE28F160C3TA110
TE28F160C3BA110
TE28F320C3TA110
TE28F320C3BA110
March 2008
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Datasheet
17
C3 Discrete
Figure 7: 48-Ball µBGA* and 48-Ball VF BGA Chip Scale Package (Top View, Ball
Down)1,2,3
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A13
A11
A8
VPP
WP#
A19
A7
A4
A14
A15
A10
A12
D14
D15
D7
WE#
A9
RP#
A21
D11
D12
D4
A18
A20
D2
A17
A6
A5
A3
A2
A1
64M
32M
A16
D5
D8
CE#
D0
A0
VCCQ
GND
D6
D3
D9
GND
OE#
D13
VCC
D10
D1
Notes:
1.
2.
3.
Shaded connections indicate the upgrade address connections. Numonyx recommends to not use routing in this area.
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
Unused address balls are not populated.
Datasheet
18
March 2008
290645-24
C3 Discrete
4.2
64-Ball Easy BGA Package
Figure 8: 64-Ball Easy BGA Package1,2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A1
A
B
C
A
B
C
A1
A6 A18 VPP VCC GND A10 A15
A15 A10 GND VCC VPP A18 A6
(1)
(1)
(1)
(1)
A2 A17 A19 RP# DU A20
A11 A14
A12 A13
A5 DU DU DU DU A8 A9
A14 A11 A20
DU RP# A19
A17 A2
(1)
(1)
A3
A4
A7 WP# WE# DU A21
A13 A12 A21
DU WE# WP# A7
A3
D
D
A9
A8 DU DU DU DU A5 A4
E
F
E
F
DQ DQ DQ DQ DQ DQ DU DU
DU DU DQ DQ DQ DQ DQ DQ
8
1
9
3
12
6
6
12
3
9
1
8
CE# DQ DQ DQ DQ DQ DU DU
DU DU DQ DQ DQ DQ
DQ
10
CE#
0
10
11
5
14
14
5
11
0
G
H
G
H
A0 VSSQ DQ DQ DQ DQ VSSQ A16
A16 VSSQ D15 D13 DQ DQ VSSQ A0
4 2
2
4
13
15
(2)
(2)
A22 OE# VCCQ VCC VSSQ DQ VCCQ DU
DU VCCQ D7 VSSQ VCC VCCQ OE# A22
7
Top View
- Ball Side
Bottom View - Ball Side
Notes:
1.
2.
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
Unused address balls are not populated.
4.3
Signal Descriptions
Table 5:
Signal Descriptions
Symbol
Type
Description
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
A[MAX:0]
DQ[15:0]
Input
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
Input/
Output
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
CE#
OE#
Input
Input
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
RP#
Input
High-Z, resets the Write State Machine, and minimizes current levels (I
).
CCD
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
March 2008
290645-24
Datasheet
19
C3 Discrete
Table 5:
Signal Descriptions
Symbol
Type
Description
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of the WE# pulse.
WE#
Input
WRITE PROTECT: Active-low input.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be
unlocked through software.
WP#
Input
When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are
now locked and can be unlocked and locked through software. After WP# goes low, any blocks
previously marked lock-down revert to the lock-down state.
See Section 11.0, “Security Modes” on page 48 for details on block locking.
PROGRAM/ERASE Power Supply: Operates as an input at logic levels to control complete device
protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. Do not
leave this pin floating.
Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands.
Input/
Power
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can drop
as low as 1.65 V to allow for resistor or diode drop from the system supply.
VPP
Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5%
to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the boot
blocks. VPP can be connected to 12 V for a total of 80 hours maximum. See Section 11.6 for details
on VPP voltage configurations.
VCC
VCCQ
GND
DU
Power
Power
Power
—
DEVICE CORE Power Supply: Supplies power for device operations.
OUTPUT Power Supply: Output-driven source voltage. This ball can be tied directly to V if
CC
operating within V range.
CC
Ground: For all internal circuitry. All ground inputs must be connected.
Do Not Use: Do not use this ball. This ball must not be connected to any power supplies, signals or
other balls,; it must be left floating.
NC
—
No Connect
Datasheet
20
March 2008
290645-24
C3 Discrete
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These ratings are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended, and extended exposure beyond the “Operating
Conditions” may affect device reliability.
.
NOTICE: Specifications are subject to change without notice. Verify with your local Numonyx Sales office that you have the
latest datasheet before finalizing a design.
Parameter
Maximum Rating
Notes
Extended Operating Temperature
During Read
–40 °C to +85 °C
During Block Erase and Program
Temperature under Bias
–40 °C to +85 °C
–40 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +3.7 V
–0.5 V to +13.5 V
–0.2 V to +3.6 V
100 mA
Storage Temperature
Voltage On Any Pin (except V and V ) with Respect to GND
1
CC
PP
V
V
Voltage (for Block Erase and Program) with Respect to GND
1,2,3
PP
and V
Supply Voltage with Respect to GND
CC
CCQ
Output Short Circuit Current
4
Notes:
1.
Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V
for periods <20 ns. Maximum DC voltage on input/output pins is V +0.5 V which, during transitions, may
CC
overshoot to V +2.0 V for periods <20 ns.
CC
2.
3.
Maximum DC voltage on V may overshoot to +14.0 V for periods <20 ns.
PP
V
Program voltage is normally 1.65 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a
PP
maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/
erase. V may be connected to 12 V for a total of 80 hours maximum.
Output shorted for no more than one second. No more than one output shorted at a time.
PP
4.
5.2
Operating Conditions
Table 6:
Temperature and Voltage Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
T
Operating Temperature
Supply Voltage
–40
2.7
+85
3.6
3.6
3.6
2.5
2.5
3.6
°C
A
V
V
V
V
V
V
V
1, 2
1, 2
1
Volts
CC1
CC
3.0
CC2
2.7
CCQ1
CCQ2
CCQ3
PP1
I/O Supply Voltage
Supply Voltage
1.65
1.8
Volts
Volts
1
1.65
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Datasheet
21
C3 Discrete
Table 6:
Temperature and Voltage Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
V
1, 3
3
11.4
12.6
Volts
PP2
Cycling
Block Erase Cycling
and V
100,000
Cycles
Notes:
1.
2.
3.
V
V
must share the same supply when they are in the V
range.
CC
CC
CCQ
CC1
Max = 3.3 V for 0.25μm 32-Mbit devices.
Applying V = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of
PP
PP
80 hours maximum.
Datasheet
22
March 2008
290645-24
C3 Discrete
6.0
Electrical Specifications
6.1
Current Characteristics
Table 7:
DC Current Characteristics (Sheet 1 of 2)
2.7 V–3.6
V
2.7 V–2.85 V 2.7 V–3.3 V
1.65 V–2.5 V 1.8 V–2.5 V
CC
V
Sym
Parameter
2.7 V–3.6
V
Unit
Test Conditions
V
CCQ
Note
Typ
Max
Typ
Max
Typ
Max
V
V
V
= V Max
CC
CC
I
Input Load Current
1,2
± 1
± 1
± 1
µA
µA
µA
µA
µA
µA
mA
= V
Max
LI
CCQ
= V
CCQ
CCQ
or GND
IN
V
V
V
= V Max
CC
CC
Output Leakage
Current
I
1,2
1
± 10
15
± 10
50
± 10
250
250
20
= V
CCQ
Max
LO
CCQ
CCQ
= V
or GND
IN
V
Standby Current
CC
V
= V Max
CC
CC
for 0.13 and 0.18
Micron Product
7
10
7
20
20
7
150
150
7
CE# = RP# = V
or during Program/ Erase
Suspend
CCQ
I
CCS
V
Standby Current
CC
for 0.25 Micron
Product
1
25
50
WP# = V
or GND
CCQ
V
Power-Down
CC
Current for 0.13 and
0.18 Micron Product
1,2
1,2
1,2,3
15
20
V
V
V
= V Max
CC
CC
= V
CCQ
Max
CCQ
CCQ
I
CCD
= V
or GND
IN
V
Power-Down
CC
RP# = GND ± 0.2 V
Current for 0.25
Product
7
25
7
25
7
25
V
Read Current for
CC
V
V
= V Max
CC
CC
0.13 and 0.18 Micron
Product
9
18
8
15
9
15
= V
Max
CCQ
CCQ
I
OE# = V , CE# =V
f = 5 MHz, I
Inputs = V or V
CCR
IH IL
OUT
IL
=0 mA
V
Read Current for
CC
1,2,3
1
10
0.2
18
8
18
5
8
15
5
9
15
5
mA
µA
IH
0.25 Micron Product
V
Deep Power-Down
RP# = GND ± 0.2 V
V
PP
I
0.2
18
10
21
16
0.2
18
10
21
16
PPD
Current
≤ V
PP
CC
V
=V
PP
PP1,
55
22
45
15
55
30
45
45
55
30
45
45
mA
mA
mA
mA
Program in Progress
I
V
Program Current
1,4
1,4
CCW
CC
V
= V
PP2 (12v)
PP
Program in Progress
V
= V
PP
PP1,
16
8
Erase in Progress
I
V
V
Erase Current
Erase Suspend
CCE
CC
V
= V
PP
PP2 (12v) ,
Erase in Progress
CC
Current for 0.13 and
0.18 Micron Product
7
15
25
50
50
200
200
50
50
200
200
µA
µA
I
/
CE# = V
Progress
Erase Suspend in
IH,
CCES
CCWS
1,4,5
1,4
I
V
Erase Suspend
CC
Current for 0.25
Micron Product
10
2
±15
2
±15
2
±15
µA
µA
V
V
≤ V
CC
PP
PP
I
V
Read Current
PPR
PP
50
200
50
200
50
200
> V
CC
March 2008
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Datasheet
23
C3 Discrete
Table 7:
DC Current Characteristics (Sheet 2 of 2)
2.7 V–3.6
V
2.7 V–2.85 V 2.7 V–3.3 V
1.65 V–2.5 V 1.8 V–2.5 V
CC
V
Sym
Parameter
2.7 V–3.6
V
Unit
Test Conditions
V
CCQ
Note
Typ
Max
Typ
Max
Typ
Max
V
=V
PP1,
PP
0.05
0.1
0.05
0.1
0.05
0.1
mA
mA
mA
mA
Program in Progress
I
V
V
Program Current
Erase Current
1,4
PPW
PP
PP
V
= V
PP
PP2 (12v)
8
0.05
8
22
0.1
22
8
22
0.1
45
8
22
0.1
45
Program in Progress
V
= V
PP
PP1,
0.05
16
0.05
16
Erase in Progress
I
1,4
1,4
PPE
V
= V
PP
PP2 (12v) ,
Erase in Progress
V
= V
PP
PP1,
0.2
50
5
0.2
50
5
0.2
50
5
µA
µA
Program or Erase Suspend in
Progress
I
I
/
V
Erase Suspend
PPES
PPWS
CC
Current
V
= V
PP2 (12v) ,
PP
200
200
200
Program or Erase Suspend in
Progress
Notes:
1.
2.
All currents are in RMS unless otherwise noted. Typical values at nominal V , T = +25 °C.
CC A
The test conditions V Max, V
Max, V Min, and V
Min refer to the maximum or minimum V or V
voltage
CC
CCQ
CC
CCQ
CC
CCQ
listed at the top of each column. V Max = 3.3 V for 0.25μm 32-Mbit devices.
CC
3.
4.
5.
Automatic Power Savings (APS) reduces I
to approximately standby levels in static operation (CMOS inputs).
CCR
Sampled, not 100% tested.
I
or I
CCR
is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I
CCWS CCES
CCES
and I
. If the device is read while in program suspend, current draw is the sum of I
and I
.
CCWS
CCR
6.2
DC Voltage Characteristics
Table 8:
DC Voltage Characteristics (Sheet 1 of 2)
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit
Test Conditions
CCQ
Note
Min
Max
Min
Max
0.4
Min
Max
0.4
Input Low
Voltage
V
*
CC
V
V
–0.4
2.0
–0.4
–0.4
V
V
IL
0.22 V
Input High
Voltage
V
V
V
–
–
V
V
V
–
–
V
CCQ
+0.3V
CCQ
CCQ
0.4V
CCQ
CCQ
0.4V
IH
+0.3V
+0.3V
V
V
OL
= V Min
CC
CC
Output Low
Voltage
V
–0.1
0.1
-0.1
0.1
-0.1
0.1
V
V
= V
Min
OL
CCQ
CCQ
I
= 100 μA
V
V
= V Min
CC
CC
Output High
Voltage
V
CCQ
–0.1V
CCQ
0.1V
CCQ
0.1V
V
= V Min
OH
CCQ
CCQ
I
= –100 μA
OH
V
Lock-
Complete Write
Protection
PP
V
V
V
1
1
1.0
3.6
1.0
3.6
1.0
3.6
V
V
V
PPLK
Out Voltage
V
during
1.65
11.4
1.65
11.4
1.65
11.4
PP1
PP
Program /
Erase
1,2
12.6
12.6
12.6
PP2
Operations
Datasheet
24
March 2008
290645-24
C3 Discrete
Table 8:
DC Voltage Characteristics (Sheet 2 of 2)
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit
Test Conditions
CCQ
Note
Min
Max
Min
Max
0.4
Min
Max
0.4
Input Low
Voltage
V
*
CC
V
V
–0.4
2.0
–0.4
–0.4
V
V
IL
0.22 V
Input High
Voltage
V
V
–
V
V
–
V
CCQ
+0.3V
CCQ
CCQ
0.4V
CCQ
CCQ
0.4V
IH
+0.3V
+0.3V
V
V
OL
= V Min
CC
CC
Output Low
Voltage
V
V
–0.1
1.5
0.1
-0.1
1.5
0.1
-0.1
1.5
0.1
V
V
= V
Min
OL
CCQ
CCQ
I
= 100 μA
V
Prog/
CC
Erase
Lock
LKO
Voltage
V
Prog/
CCQ
Erase
Lock
Voltage
V
1.2
1.2
1.2
V
LKO2
Notes:
1.
2.
Erase and Program are inhibited when V < V
and not guaranteed outside the valid V ranges of V
and V
.
PP2
PP
PPLK
PP
PP1
Applying V = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
PP
and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum.
PP
March 2008
290645-24
Datasheet
25
C3 Discrete
7.0
AC Characteristics
7.1
AC Read Characteristics
Table 9:
Read Operations—8-Mbit Density
Density
8 Mbit
Product
70 ns
90 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
110 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
Paramete
r
#
Sym
V
2.7 V – 3.6 V
CC
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Note
R1
t
t
Read Cycle Time
3,4
3,4
70
80
90
100
110
AVAV
AVQV
Address to
Output Delay
R2
R3
R4
R5
R6
R7
R8
R9
70
70
80
80
90
90
100
100
30
110
110
30
CE# to Output
Delay
t
t
t
t
t
t
t
1,3,4
1,3,4
3,4
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OE# to Output
Delay
20
30
30
RP# to Output
Delay
150
150
150
150
150
CE# to Output in
Low Z
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
0
0
0
0
0
0
OE# to Output in
Low Z
CE# to Output in
High Z
20
20
20
20
20
20
20
20
20
20
OE# to Output in
High Z
Output Hold from
Address, CE#, or
OE# Change,
Whichever
R10
t
2,3,4
0
0
0
0
0
OH
Occurs First
Notes:
1.
2.
3.
4.
OE# may be delayed up to t
Sampled, but not 100% tested.
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
See Figure 9, “Read Operation Waveform” on page 29.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
Datasheet
26
March 2008
290645-24
C3 Discrete
Table 10: Read Operations—16-Mbit Density
Densit
y
16 Mbit
90 ns
Produ
ct
70 ns
80 ns
110 ns
Paramet
er
Note
s
#
Sym
2.7 V–3.6
V
2.7 V–3.6
V
3.0 V–3.6
2.7 V–3.6
V
3.0 V–
3.6V
2.7 V–
3.6V
V
CC
V
Ma
Ma
Min
(ns
)
Min
(ns
)
Min
Max
Min
Max
Min Max Min
Max
x
(ns
)
x
(ns
)
(ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
R1
R2
R3
R4
R5
R6
t
Read Cycle Time
70
80
80
90
100
110
3,4
3,4
AVAV
Address to Output
Delay
t
70
70
80
80
80
80
90
90
100
100
30
110
AVQV
t
CE# to Output Delay
110 1,3,4
ELQV
GLQV
PHQV
OE# to Output
Delay
t
t
20
20
30
30
30
1,3,4
3,4
RP# to Output Delay
150
150
150
150
150
150
CE# to Output in
Low Z
t
0
0
0
0
0
0
0
0
0
0
0
0
2,3,4
ELQX
GLQX
EHQZ
GHQZ
OE# to Output in
Low Z
R7
R8
R9
t
2,3,4
2,3,4
2,3,4
CE# to Output in
High Z
t
20
20
20
20
20
20
20
20
20
20
20
20
OE# to Output in
High Z
t
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First
R10
t
0
0
0
0
0
0
2,3,4
OH
Notes:
1.
2.
3.
4.
OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV
ELQV– GLQV
Sampled, but not 100% tested.
See Figure 9, “Read Operation Waveform” on page 29.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
March 2008
290645-24
Datasheet
27
C3 Discrete
Table 11: Read Operations—32-Mbit Density
Densit
y
32 Mbit
100 ns
Produc
70 ns
90 ns
110 ns
t
Paramet
er
Note
s
#
Sym
2.7 V–3.6
V
2.7 V–3.6
V
3.0 V–3.3
2.7 V–3.3
V
3.0 V–3.3
2.7 V–3.3
V
V
CC
V
V
Min Max
Min Max Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Min Max
(ns) (ns)
(ns
)
(ns
)
R1
R2
t
Read Cycle Time
70
90
90
100
100
110
110
3,4
3,4
AVAV
Address to Output
Delay
t
70
90
90
100
100
AVQV
R3
R4
R5
t
CE# to Output Delay
OE# to Output Delay
RP# to Output Delay
70
20
90
20
90
30
100
30
100
30
110 1,3,4
ELQV
GLQV
PHQV
t
t
30
1,3,4
3,4
150
150
150
150
150
150
CE# to Output in
Low Z
R6
R7
R8
R9
t
0
0
0
0
0
0
0
0
0
0
0
0
2,3,4
2,3,4
2,3,4
2,3,4
ELQX
GLQX
EHQZ
GHQZ
OE# to Output in
Low Z
t
t
CE# to Output in
High Z
20
20
20
20
20
20
20
20
20
20
20
20
OE# to Output in
High Z
t
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First
R10
t
0
0
0
0
0
0
2,3,4
OH
Notes:
1.
2.
3.
4.
OE# may be delayed up to t
t
after the falling edge of CE# without impact on t
.
ELQV– GLQV
ELQV
Sampled, but not 100% tested.
See Figure 9, “Read Operation Waveform” on page 29.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements
and maximum allowable input slew rate.
Datasheet
28
March 2008
290645-24
C3 Discrete
Table 12: Read Operations — 64-Mbit Density
Density
Product
64 Mbit
70 ns
2.7 V–3.6 V
80 ns
#
Sym
Parameter
Unit
V
2.7 V–3.6 V
CC
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
Read Cycle Time
3,4
3,4
70
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address to Output Delay
CE# to Output Delay
70
70
80
80
AVQV
t
1,3,4
1,3,4
3,4
ELQV
GLQV
PHQV
t
t
OE# to Output Delay
RP# to Output Delay
20
20
150
150
t
CE# to Output in Low Z
OE# to Output in Low Z
CE# to Output in High Z
OE# to Output in High Z
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
ELQX
GLQX
EHQZ
GHQZ
t
t
20
20
20
20
t
Output Hold from Address, CE#, or OE# Change,
Whichever Occurs First
R10
t
2,3,4
0
0
ns
OH
Notes:
1.
2.
3.
4.
OE# may be delayed up to t
Sampled, but not 100% tested.
t
after the falling edge of CE# without impact on t
.
ELQV
ELQV– GLQV
See Figure 9, “Read Operation Waveform” on page 29.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
Figure 9: Read Operation Waveform
R1
R2
Address [A]
R3
R8
CE# [E]
R4
R9
OE# [G]
WE# [W]
R7
R6
R10
Data [D/Q]
R5
RST# [P]
March 2008
290645-24
Datasheet
29
C3 Discrete
7.2
AC Write Characteristics
Table 13: Write Operations—8-Mbit Density
Density
Product
3.0 V – 3.6 V
8 Mbit
90 ns
70ns
70
110 ns
80
100
#
Sym
Parameter
V
CC
2.7 V – 3.6 V
Note
90
110
Min
(ns)
Min
(ns)
Min
(ns)
Min
(ns)
Min
(ns)
t
t
/
PHWL
PHEL
W1
W2
W3
W4
W5
W6
W7
W8
W9
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
4,5
150
0
150
0
150
0
150
0
150
0
t
t
/
ELWL
WLEL
t
t
/
WLWH
ELEH
4,5
45
40
50
0
50
50
50
0
60
50
60
0
70
60
70
0
70
60
70
0
t
t
/
/
/
/
/
DVWH
DVEH
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
2,4,5
2,4,5
4,5
t
t
AVWH
AVEH
t
t
WHEH
EHWH
t
t
WHDX
EHDX
2,4,5
2,4,5
2,4,5
0
0
0
0
0
t
t
WHAX
EHAX
0
0
0
0
0
t
t
WHWL /
EHEL
25
30
30
30
30
t
t
/
VPWH
VPEH
W10
W11
W12
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
200
0
PP
t
QVVL
PP
t
t
/
BHWH
BHEH
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
0
W13
W14
t
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
QVBL
t
WE# High to OE# Going Low
30
30
30
30
30
WHGL
Notes:
1.
Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
WP
(whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, write pulse width high (t
) is
WP
WLWH
ELEH
WLEH
ELWH
WPH
defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last).
Hence, t
= t
= t
= t
= t
.
WPH
EHEL
WHEL
EHWL
2.
3.
4.
Refer to TableW2H3W,L“Command Bus Operations” on page 45 for valid A or D
.
IN
IN
Sampled, but not 100% tested.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
5.
See Figure 10, “Write Operations Waveform” on page 33.
Datasheet
30
March 2008
290645-24
C3 Discrete
Table 14: Write Operations—16-Mbit Density
Density
Product
16 Mbit
90 ns
80
70 ns
80 ns
110 ns
100
3.0 V – 3.6 V
2.7 V – 3.6 V
#
Sym
Parameter
Unit
V
CC
70
80
90
110
Min
Not
e
Min
Min
Min
Min
Min
t
t
/
RP# High Recovery to WE# (CE#) Going
Low
PHWL
PHEL
W1
4,5
150
0
150
0
150
0
150
0
150
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
/
ELWL
WLEL
W2
W3
W4
W5
W6
W7
W8
W9
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
t
t
/
1,4,
5
WLWH
ELEH
45
40
50
0
50
40
50
0
50
50
50
0
60
50
60
0
70
60
70
0
70
60
70
0
t
t
/
/
/
/
/
2,4,
5
DVWH
DVEH
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
t
t
2,4,
5
AVWH
AVEH
t
t
CE# (WE#) Hold Time from WE# (CE#)
High
WHEH
EHWH
4,5
t
t
2,4,
5
WHDX
EHDX
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
0
0
0
0
0
0
t
t
2,4,
5
WHAX
EHAX
0
0
0
0
0
0
t
t
1,4,
5
WHWL /
EHEL
25
30
30
30
30
30
t
t
/
3,4,
5
VPWH
VPEH
W10
W11
W12
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
ns
PP
t
3,4
3,4
QVVL
PP
t
t
/
BHWH
BHEH
WP# Setup to WE# (CE#) Going High
0
0
0
0
0
0
W13
W14
t
t
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
QVBL
WE# High to OE# Going Low
30
30
30
30
30
30
WHGL
Notes:
1.
Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
WP
(whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, write pulse width high (t
) is
WP
WLWH
ELEH
WLEH
ELWH
WPH
defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last).
Hence, t
= t
= t
= t
= t
.
WPH
EHEL
WHEL
EHWL
2.
3.
4.
Refer to TableW2H3W,L“Command Bus Operations” on page 45 for valid A or D
.
IN
IN
Sampled, but not 100% tested.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
5.
See Figure 10, “Write Operations Waveform” on page 33.
March 2008
290645-24
Datasheet
31
C3 Discrete
Table 15: Write Operations—32-Mbit Density
Density
32 Mbit
100 ns
Product
70 ns
90 ns
110 ns
3.0 V – 3.6
#
Sym
Parameter
90
100
Unit
6
V
V
CC
2.7 V – 3.6 V
Note
70
90
100
Min
110
Min
Min
Min
Min
Min
t
t
/
RP# High Recovery to WE# (CE#)
Going Low
PHWL
PHEL
W1
W2
4,5
4,5
150
0
150
0
150
150
0
150
150
0
ns
ns
t
t
/
CE# (WE#) Setup to WE# (CE#)
Going Low
ELWL
WLEL
0
0
t
/
WLWH
W3
WE# (CE#) Pulse Width
1,4,5
45
60
60
70
70
70
ns
t
ELEH
t
t
/
DVWH
DVEH
W4
W5
W6
W7
W8
W9
Data Setup to WE# (CE#) Going High
2,4,5
2,4,5
4,5
40
50
0
40
60
0
50
60
0
60
70
0
60
70
0
60
70
0
ns
ns
ns
ns
ns
ns
t
t
/
Address Setup to WE# (CE#) Going
High
AVWH
AVEH
t
t
/
/
/
CE# (WE#) Hold Time from WE#
(CE#) High
WHEH
EHWH
t
t
Data Hold Time from WE# (CE#)
High
WHDX
EHDX
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
t
t
Address Hold Time from WE# (CE#)
High
WHAX
EHAX
0
0
0
0
0
0
t
t
WHWL /
EHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
t
t
/
VPWH
VPEH
W10
W11
W12
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
ns
PP
PP
t
QVVL
t
t
/
BHWH
BHEH
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
0
0
W13
W14
t
t
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
QVBL
WE# High to OE# Going Low
30
30
30
30
30
30
WHGL
Notes:
1.
Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
WP
(whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, write pulse width high (t
) is
WP
WLWH
ELEH
WLEH
ELWH
WPH
defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last).
Hence, t
= t
= t
= t
= t
.
WPH
EHEL
WHEL
EHWL
2.
3.
4.
Refer to TableW2H3W,L“Command Bus Operations” on page 45 for valid A or D
.
IN
IN
Sampled, but not 100% tested.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
5.
6.
See Figure 10, “Write Operations Waveform” on page 33.
V
Max = 3.3 V for 32-Mbit 0.25 Micron product.
CC
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Table 16: Write Operations—64-Mbit Density
Density
Product
64 Mbit
80 ns
#
Symbol
Parameter
Unit
2.7 V – 3.6
V
V
Note
Min
CC
W1
W2
t
t
/ t
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
4,5
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHWL
PHEL
/ t
ELWL
WLEL
W3
t
/ t
1,4,5
2,4,5
2,4,5
4,5
60
40
60
0
WLWH
DVWH
ELEH
DVEH
AVEH
EHWH
W4
t
/ t
/ t
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
W5
t
AVWH
W6
t
/ t
WHEH
W7
t
/ t
/ t
2,4,5
2,4,5
1,4,5
3,4,5
3,4
0
WHDX
EHDX
EHAX
W8
t
0
WHAX
W9
t
t
30
200
0
WHWL / EHEL
W10
W11
W12
W13
W14
t
/ t
V
V
Setup to WE# (CE#) Going High
Hold from Valid SRD
VPWH
VPEH
PP
PP
t
QVVL
t
/ t
WP# Setup to WE# (CE#) Going High
WP# Hold from Valid SRD
3,4
0
BHWH
BHEH
t
3,4
0
QVBL
t
WE# High to OE# Going Low
3,4
30
WHGL
Notes:
1.
Write pulse width (t ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
WP
(whichever goes high first). Hence, t
= t
= t
= t
= t
. Similarly, write pulse width high (t
) is
WP
WLWH
ELEH
WLEH
ELWH
WPH
defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last).
Hence, t
= t
= t
= t
= t
.
WPH
EHEL
WHEL
EHWL
2.
3.
4.
Refer to TableW2H3W,L“Command Bus Operations” on page 45 for valid A or D
.
IN
IN
Sampled, but not 100% tested.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements and
maximum allowable input slew rate.
5.
See Figure 10, “Write Operations Waveform” on page 33.
Figure 10: Write Operations Waveform
W5
W8
Address [A]
CE# [E]
W6
W3
W2
W9
WE# [W]
OE# [G]
W4
W7
Data [D/Q]
RP# [P]
W1
W10
Vpp [V]
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7.3
Erase and Program Timings
Table 17: Erase and Program Timings
V
1.65 V–3.6 V
11.4 V–12.6 V
PP
Symbol
Parameter
Unit
Note
Typ
Max
Typ
Max
4-KW Parameter Block
Word Program Time
t
t
1, 2, 3
0.10
0.30
2.4
200
200
4
0.03
0.12
s
s
BWPB
32-KW Main Block
Word Program Time
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.8
12
22
0.5
1
0.24
8
1
185
185
4
BWMB
Word Program Time for 0.13 and
0.18 Micron Product
µs
µs
s
t
/ t
EHQV1
WHQV1
Word Program Time for 0.25
Micron Product
8
4-KW Parameter Block
Erase Time
t
t
/ t
/ t
0.4
0.6
WHQV2
EHQV2
EHQV3
32-KW Main Block
Erase Time
5
5
s
WHQV3
t
t
/ t
/ t
Program Suspend Latency
Erase Suspend Latency
1,3
1,3
5
5
10
20
5
5
10
20
µs
µs
WHRH1
EHRH1
EHRH2
WHRH2
Notes:
1.
2.
3.
Typical values measured at T = +25 °C and nominal voltages.
A
Excludes external system-level overhead.
Sampled, but not 100% tested.
7.4
AC I/O Test Conditions
Figure 11: AC Input/Output Reference Waveform
VCCQ
Input
VCCQ/2
Test Points
VCCQ/2
Output
0V
Note: Input timing begins, and output timing ends, at V
/2. Input rise and fall times (10% to 90%) < 5 ns. Worst-case speed
CCQ
conditions are when V = V Min.
CC
CC
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Figure 12: Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 17 for component values.
Table 18: Test Configuration Component Values for Worst-Case Speed Conditions
Test Configuration
Min Standard Test
C
(pF)
R
(kΩ)
R (kΩ)
2
L
1
V
50
25
25
CCQ
Note: C includes jig capacitance.
L
7.5
Device Capacitance
TA = 25 °C, f = 1 MHz
Table 19: Device Capacitance
§
Symbol
Parameter
Typ
Max
Unit
Condition
C
Input Capacitance
Output Capacitance
6
8
8
pF
pF
V
= 0.0 V
= 0.0 V
IN
IN
C
§
12
V
OUT
OUT
Sampled, not 100% tested.
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C3 Discrete
8.0
Power and Reset Specifications
Numonyx™ flash devices have a tiered approach to power savings that can significantly
reduce overall system power consumption. The Automatic Power Savings (APS) feature
reduces power consumption when the device is selected but idle. If CE# is deasserted,
the flash enters its standby mode, where current consumption is even lower. If RP# is
deasserted, the flash enter deep power-down mode for ultra-low current consumption.
The combination of these features can minimize memory power consumption, and
therefore, overall system power consumption.
8.1
Active Power (Program/Erase/Read)
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active
mode. Refer to the DC Characteristic tables for ICC current values. Active power is the
largest contributor to overall system power consumption. Minimizing the active current
could have a profound effect on system power consumption, especially for battery-
operated devices.
8.2
8.3
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is
read from the memory array and the address lines are idle, APS circuitry places the
device in a mode where typical current is comparable to ICCS. The flash stays in this
static state with outputs valid until a new location is read.
Standby Power
When CE# is at a logic-high level (VIH), the flash memory is in standby mode, which
disables much of the device’s circuitry and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE#
signal. If CE# transitions to a logic-high level during Erase or Program operations, the
device will continue to perform the operation and consume corresponding active power
until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time
and quantify the respective power consumption in each mode for their specific
application. This approach will provide a more accurate measure of application-specific
power and energy requirements.
8.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL. During read modes, RP#
going low de-selects the memory and places the outputs in a high-impedance state.
Recovery from deep power-down requires a minimum time of tPHQV for read operations,
and tPHWL/tPHEL for write operations.
During program or erase modes, RP# transitioning low aborts the in-progress
operation. The memory contents of the address being programmed or the block being
erased are no longer valid as the data integrity has been compromised by the abort.
During deep power-down, all internal circuits are switched to a low-power savings
mode (RP# transitioning to VIL or turning off power to the device clears the Status
Register).
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8.5
Power and Reset Considerations
Power-Up/Down Characteristics
8.5.1
To prevent any condition that may result in a spurious write or erase operation,
Numonyx recommends to power-up VCC and VCCQ together. Conversely, VCC and
VCCQ must power-down together.
Numonyx also recommends that you power-up VPP with or after VCC has reached
VCCmin. Conversely, VPP must powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCmin
before applying VCCQ and VPP. Device inputs must not be driven before supply voltage
reaches VCCmin
.
Power supply transitions must only occur when RP# is low.
8.5.2
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase
devices since the system reads from the flash memory when it comes out of reset. If a
CPU reset occurs without a flash memory reset, proper CPU initialization will not occur
because the flash memory may be providing status information instead of array data.
Numonyx recommends connecting RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above
VLKO. Because both WE# and CE# must be low for a command write, driving either
signal to VIH will inhibit writes to the device. The CUI architecture provides additional
protection since alteration of memory contents can only occur after successful
completion of the two-step command sequences. The device is also disabled until RP#
is brought to VIH, regardless of the state of its control inputs. By holding the device in
reset during power-up/down, invalid bus conditions during power-up can be masked,
providing yet another level of memory protection.
8.5.3
8.5.4
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or
CE# transitions or WSM actions. Its default state upon power-up, after exit from reset
mode or after VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions
down to VPPLK), the CUI must be reset to read-array mode by the Read Array command
if access to the flash-memory array is desired.
Reset Specifications
Table 20: Reset Specifications
V
2.7 V – 3.6 V
Max
CC
Symbol
Parameter
Unit
Notes
Min
RP# Low to Reset during Read
t
(If RP# is tied to V , this specification is not
100
ns
1, 2
PLPH
CC
applicable)
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C3 Discrete
Table 20: Reset Specifications
V
2.7 V – 3.6 V
Max
CC
Symbol
Parameter
Unit
Notes
Min
t
t
RP# Low to Reset during Block Erase
RP# Low to Reset during Program
22
12
µs
µs
3
3
PLRH1
PLRH2
Notes:
1.
2.
If t
is < 100 ns the device may still reset but this is not guaranteed.
PLPH
If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset will
complete within 100 ns.
Sampled, but not 100% tested.
3.
Figure 13: Reset Operations Waveforms
VIH
R P # (P )
tP H Q V
tP H W L
tP H E L
V IL
t P L P H
(A ) R e se t d u rin g R e a d M o de
A b o rt
C o m p le te
t P L R H
t P H Q V
t P H W L
t P H E L
V IH
V IL
R P # (P )
t
P L P H
t P L P H
t P L R H
<
(B ) R e se t d u rin g P ro gram o r B lock E ra se ,
A b o rt D e e p
C o m p le te P o w e r-
t P H Q V
t P H W L
t P H E L
D o w n
t P L R H
V IH
V IL
R P # (P )
t
P L P H
(C ) R e se t P rog ra m o r B lo ck E rase, t P L P H
>
t P L R H
8.6
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling.
System designers should consider the following three supply current issues:
• Standby current levels (ICCS
• Read current levels (ICCR
)
)
• Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive
loading. Two-line control and proper decoupling capacitor selection will suppress these
transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor
connected between each VCC and GND, and between its VPP and VSS. These high-
frequency, inherently low-inductance capacitors should be placed as close as possible
to the package leads.
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9.0
Device Operations
The C3 Discrete device uses a CUI and automated algorithms to simplify Program and
Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power
supplies during erasure and programming.
The internal WSM completely automates Program and Erase operations while the CUI
signals the start of an operation and the Status Register reports device status. The CUI
handles the WE# interface to the data and address latches as well as system status
requests during WSM operation.
9.1
Bus Operations
The C3 Discrete device performs read, program, and erase operations in-system
through the local CPU or microcontroller. Four control pins (CE#, OE#, WE#, and RP#)
manage the data flow in and out of the flash device. Table 21 on page 39 summarizes
these bus operations.
Table 21: Bus Operations
Mode
RP#
CE#
OE#
WE#
DQ[15:0]
Read
V
V
V
V
V
V
V
V
V
D
OUT
IH
IH
IH
IH
IL
IL
IL
IH
IL
IH
IH
IH
Write
V
V
V
D
IN
IL
Output Disable
Standby
Reset
V
High-Z
High-Z
High-Z
IH
V
X
X
V
X
X
X
IL
Note: X = Don’t Care (V or V
)
IH
IL
9.1.1
Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be
deasserted. CE# is the device selection control; when active low, it enables the flash
memory device. OE# is the data output control; when low, data is output on DQ[15:0].
See Figure 9, “Read Operation Waveform” on page 29.
9.1.2
Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high.
Commands are issued to the Command User Interface (CUI). The CUI does not occupy
an addressable memory location. Address and data are latched on the rising edge of
the WE# or CE# pulse, whichever occurs first. See Figure 10, “Write Operations
Waveform” on page 33.
9.1.3
9.1.4
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. DQ[15:0] are
placed in a high-impedance state.
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in
standby mode, which substantially reduces device power consumption without any
latency for subsequent read accesses. In standby, outputs are placed in a high-
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C3 Discrete
impedance state independent of OE#. If deselected during a Program or Erase
operation, the device continues to consume active power until the Program or Erase
operation is complete.
9.1.5
Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers
in a high-impedance state, and turns off all internal circuits. After return from reset, a
time tPHQV is required until the initial read-access outputs are valid. A delay (tPHWL or
tPHEL) is required after return from reset before a write cycle can be initiated. After this
wake-up interval, normal operation is restored. The CUI resets to read-array mode, the
Status Register is set to 0x80, and all blocks are locked. See Figure 13, “Reset
Operations Waveforms” on page 38.
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation
will be aborted; the memory contents at the aborted location (for a program) or block
(for an erase) are no longer valid, since the data may be partially erased or written.
The abort process goes through the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process
which takes time tPLRH to complete.
2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted
during tPLRH) or enter reset mode (if RP# is deasserted after tPLRH). See Figure 13,
“Reset Operations Waveforms” on page 38.
In both cases, after returning from an aborted operation, the relevant time tPHQV or
tPHWL/tPHEL must be observed before a Read or Write operation is initiated, as discussed
in the previous paragraph. However, in this case, these delays are referenced to the
end of tPLRH rather than when RP# goes high.
As with any automated device, it is important to assert RP# during a system reset.
When the system comes out of reset, the processor reads from the flash memory.
Automated flash memories provide status information when read during Program or
Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx™ flash memories allow proper CPU
initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
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10.0
Modes of Operation
10.1
Read Mode
The flash memory has four read modes (read array, read identifier, read status, and CFI
query) and two write modes (program and erase). Three additional modes (erase
suspend to program, erase suspend to read, and program suspend to read) are
available only during suspended operations. Table 23, “Command Bus Operations” on
page 45 and Table 24, “Command Codes and Descriptions” on page 46 summarize the
commands used for these modes.
Appendix A, “Write State Machine States” on page 53 is a comprehensive chart
showing the state transitions.
10.1.1
Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode
and will respond to the read-control inputs (CE#, address inputs, and OE#) without any
additional CUI commands.
When the device is in read array mode, four control signals control data output.
• WE# must be logic high (VIH)
• CE# must be logic low (VIL)
• OE# must be logic low (VIL)
• RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If
the device is not in read-array mode, as would be the case after a Program or Erase
operation, the Read Array command (0xFF) must be issued to the CUI before array
reads can occur.
10.1.2
Read Identifier
The read-identifier mode outputs three types of information: the manufacturer/device
identifier, the block locking status, and the protection register. The device is switched to
this mode by issuing the Read Identifier command (0x90). Once in this mode, read
cycles from addresses shown in Table 22 retrieve the specified information. To return to
read-array mode, issue the Read Array command (0xFF).
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Table 22: Device Identification Codes
1
Address
Item
Data
Description
Base
Offset
Manufacturer ID
Block
0x00
0x0089
0x88C0
8-Mbit Top Boot Device
0x88C1
8-Mbit Bottom Boot Device
16-Mbit Top Boot Device
16-Mbit Bottom Boot Device
32-Mbit Top Boot Device
32-Mbit Bottom Boot Device
64-Mbit Top Boot Device
64-Mbit Bottom Boot Device
Block is unlocked
0x88C2
0x88C3
Device ID
Block
0x01
0x02
0x88C4
0x88C5
0x88CC
0x88CD
DQ0 = 0b0
DQ0 = 0b1
DQ1 = 0b0
DQ1 = 0b1
Lock Data
2
Block Lock Status
Block
Block
Block is locked
Block is not locked-down
Block is locked down
2
Block Lock-Down Status
0x02
0x80
Protection Register Lock Status
Protection Register
Notes:
Block
Block
Multiple reads required to read the
entire 128-bit Protection Register.
0x81 - 0x88
Register Data
1.
The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block
number 38 in a bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i.e. 0x0F8002. Then examine
DQ0 of the data to determine if the block is locked.
See Section 11.2, “Reading Block-Lock Status” on page 49 for valid lock status.
2.
10.1.3
10.1.4
CFI Query
The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read
Query Command (0x98). The CFI data structure contains information such as block
size, density, command set, and electrical specifications. Once in this mode, read cycles
from addresses shown in Appendix C, “Common Flash Interface,” retrieve the specified
information. To return to read-array mode, issue the Read Array command (0xFF).
Read Status Register
The Status Register indicates the status of device operations and the success/failure of
that operation. The Read Status Register (0x70) command causes subsequent reads to
output data from the Status Register until another command is issued. To return to
reading from the array, issue a Read Array (0xFF) command.
The Status Register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs
0x00 when a Read Status Register command is issued.
The contents of the Status Register are latched on the falling edge of OE# or CE#
(whichever occurs last) which prevents possible bus errors that might occur if Status
Register contents change while being read. CE# or OE# must be toggled with each
subsequent status read, or the Status Register will not indicate completion of a
Program or Erase operation.
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When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits
in the Status Register indicate whether the WSM was successful in performing the
preferred operation See Table 25, “Status Register Bit Definition” on page 47.
10.1.4.1
Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7, but
the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5
indicate various error conditions, these bits can be cleared only through the Clear
Status Register (0x50) command. By allowing the system software to control the
resetting of these bits, several operations may be performed (such as cumulatively
programming several addresses or erasing multiple blocks in sequence) before reading
the Status Register to determine if an error occurred during that series. Clear the
Status Register before beginning another command or sequence. The Read Array
command must be issued before data can be read from the memory array. Resetting
the device also clears the Status Register.
10.2
Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup
command (0x40) is issued to the CUI, followed by a second write that specifies the
address and data to be programmed. The WSM will execute a sequence of internally
timed events to program preferred bits of the addressed location, then verify the bits
are sufficiently programmed. Programming the memory results in specific bits within an
address location being changed to a “0.” If users attempt to program “1”s, the memory
cell contents do not change and no error occurs.
The Status Register indicates programming status. While the program sequence
executes, status bit 7 is “0.” The Status Register can be polled by toggling either CE#
or OE#. While programming, the only valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the program-status bits must be checked. If the
programming operation was unsuccessful, SR[4] is set to indicate a program failure. If
SR[3] is set, then VPP was not within acceptable limits, and the WSM did not execute
the program command. If SR[1] is set, a program operation was attempted on a locked
block and the operation was aborted.
The Status Register should be cleared before attempting the next operation. Any CUI
instruction can follow after programming is completed; however, to prevent inadvertent
Status Register reads, be sure to reset the CUI to read-array mode.
10.2.1
12-Volt Production Programming
When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through
the VCC pin.
Note:
If VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above
1.65 V to perform in-system flash modifications.
When VPP is connected to a 12 V power supply, the device draws program and erase
current directly from the VPP pin. This eliminates the need for an external switching
transistor to control VPP. Figure 16 on page 52 shows examples of how the flash power
supplies can be configured for various usage models.
The 12 V VPP mode enhances programming performance during the short period of
time typically found in manufacturing processes; however, it is not intended for
extended use. You cna apply 12 V to VPP during Program and Erase operations for a
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C3 Discrete
maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks.
VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device
beyond these limits may cause permanent damage.
10.2.2
Suspending and Resuming Program
The Program Suspend command halts an in-progress program operation so that data
can be read from other locations of memory. Once the programming process starts,
issuing the Program Suspend command to the CUI requests that the WSM suspend the
program sequence at predetermined points in the program algorithm. The device
continues to output Status Register data after the Program Suspend command is
issued. Polling SR[7] and SR[2] will determine when the program operation has been
suspended (both will be set to “1”). The program-suspend latency is specified with
tWHRH1/tEHRH1.
A Read-Array command can now be issued to the CUI to read data from blocks other
than that which is suspended. The only other valid commands while program is
suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume.
After the Program Resume command is issued to the flash memory, the WSM will
continue with the programming process and SR[2] and SR[7] will automatically be
cleared. The device automatically outputs Status Register data when read (see
Figure 18, “Program Suspend / Resume Flowchart” on page 57) after the Program
Resume command is issued. VPP must remain at the same VPP level used for program
while in program-suspend mode. RP# must also remain at VIH.
10.3
Erase Mode
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI,
along with an address identifying the block to be erased. This address is latched
internally when the Erase Confirm command is issued. Block erasure results in all bits
within the block being set to “1.” Only one block can be erased at a time. The WSM will
execute a sequence of internally timed events to program all bits within the block to
“0,” erase all bits within the block to “1,” then verify that all bits within the block are
sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the Status Register indicates that erasure is complete, check the erase-status bit
to verify that the Erase operation was successful. If the Erase operation was
unsuccessful, SR[5] of the Status Register will be set to a “1,” indicating an erase
failure. If VPP is not within acceptable limits after the Erase Confirm command was
issued, the WSM will not execute the erase sequence; instead, SR[5] of the Status
Register is set to indicate an erase error, and SR[3] is set to a “1” to identify that VPP
supply voltage is not within acceptable limits.
After an Erase operation, clear the Status Register (0x50) before attempting the next
operation. Any CUI instruction can follow after erasure is completed; however, to
prevent inadvertent status- register reads, Numonyx recommends that you place the
flash in read-array mode after the erase is complete.
10.3.1
Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase
Suspend command is provided to allow erase-sequence interruption to read data
from—or program data to— another block in memory. Once the erase sequence is
started, issuing the Erase Suspend command to the CUI suspends the erase sequence
at a predetermined point in the erase algorithm. The Status Register indicates if/when
the Erase operation has been suspended. Erase-suspend latency is specified by tWHRH2
/
tEHRH2
.
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A Read Array or Program command can now be issued to the CUI to read/program data
from/to blocks other than that which is suspended. This nested Program command can
subsequently be suspended to read yet another location. The only valid commands
while Erase is suspended are Read Status Register, Read Identifier, CFI Query, Program
Setup, Program Resume, Erase Resume, Lock Block, Unlock Block, and Lock-Down
Block. During erase-suspend mode, the device can be placed in a pseudo-standby
mode by taking CE# to VIH, which reduces active current consumption.
Erase Resume continues the erase sequence when CE# = VIL. Similar to the end of a
standard Erase operation, the Status Register must be read and cleared before the next
instruction is issued.
Table 23: Command Bus Operations
First Bus Cycle
Addr
Second Bus Cycle
Addr
Command
Notes
Oper
Data
Oper
Data
Read Array
1,3
1,3
1,3
1,3
1,3
2,3
1,3
1,3
1,3
1,3
1,3
1,3
1,3
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
X
X
X
X
X
0xFF
0x90
Read Identifier
Read
Read
Read
IA
QA
X
ID
QD
CFI Query
0x98
Read Status Register
Clear Status Register
Program
0x70
SRD
0x50
0x40/0x10
0x20
Write
Write
PA
BA
PD
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
Lock Block
D0H
0xB0
0xD0
0x60
Write
Write
Write
Write
BA
BA
BA
PA
0x01
0xD0
0x2F
PD
Unlock Block
0x60
Lock-Down Block
Protection Program
0x60
0xC0
X = "Don’t Care"
PA = Prog Addr
PD = Prog Data
BA = Block Addr
IA = Identifier Addr.
QA = Query Addr.
QD = Query Data
SRD = Status Reg.
Data
ID = Identifier Data
Notes:
1.
Following the Read Identifier or CFI Query commands, read operations output device identification data or CFI query
information, respectively. See Section 10.1.2 and Section 10.1.3.
2.
3.
Either 0x40 or 0x10 command is valid, but the Numonyx standard is 0x40.
When writing commands, the upper data bus [DQ8-DQ15] should be either V or V , to minimize current draw.
IL
IH
Bus operations are defined in Table 21, “Bus Operations” on page 39.
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C3 Discrete
Table 24: Command Codes and Descriptions
Code
Device Mode
(HEX)
Command Description
FF
Read Array
This command places the device in read-array mode, which outputs array data on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second
cycle latches addresses and data information and initiates the WSM to execute the Program
algorithm. The flash outputs Status Register data when CE# or OE# is toggled. A Read Array
command is required after programming to read array data. See Section 10.2, “Program
Mode” on page 43.
40
Program Set-Up
This is a two-cycle command. It prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 to “1,”
(b) place the device into the read-Status Register mode, and (c) wait for another command. See
Section 10.3, “Erase Mode” on page 44.
20
Erase Set-Up
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will close the address and
data latches and begin erasing the block indicated on the address pins. During program/erase, the
device will respond only to the Read Status Register, Program Suspend and Erase Suspend
commands, and will output Status Register data when CE# or OE# is toggled.
If a Program or Erase operation was previously suspended, this command will resume that
operation.
Program/Erase
Resume
D0
If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock the
block indicated on the address pins. If the block had been previously set to Lock-Down, this
operation will have no effect. (See Section 11.1)
Unlock Block
Issuing this command will begin to suspend the currently executing Program/Erase operation. The
Status Register will indicate when the operation has been successfully suspended by setting either
the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit SR[7] to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input-
control pins except RP#, which will immediately shut down the WSM and the remainder of the chip
Program Suspend
Erase Suspend
B0
70
if RP# is driven to V . See Sections 3.2.5.1 and 3.2.6.1.
IL
This command places the device into read-Status Register mode. Reading the device will output
the contents of the Status Register, regardless of the address presented to the device. The device
automatically enters this mode after a Program or Erase operation has been initiated. See
Section 10.1.4, “Read Status Register” on page 42.
Read Status
Register
The WSM can set the block-lock status SR[1], V Status SR[3], program status SR[4], and erase-
PP
status SR[5] bits in the Status Register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
Clear Status
Register
50
90
This command puts the device into the read-identifier mode so that reading the device will output
the manufacturer/device codes or block-lock status. See Section 10.1.2, “Read Identifier”
on page 41.
Read Identifier
Block Lock,
Block Unlock,
Block Lock-Down
Set-Up
This command prepares the CUI for block-locking changes. If the next command is not Block
Unlock, Block Lock, or Block Lock-Down, then the CUI will set both the program and erase-Status
Register bits to indicate a command-sequence error. See Section 11.0, “Security Modes”
on page 48.
60
If the previous command was Lock Set-Up, the CUI will latch the address and lock the block
indicated on the address pins. (See Section 11.1)
01
2F
Lock-Block
Lock-Down
If the previous command was a Lock-Down Set-Up command, the CUI will latch the address and
lock-down the block indicated on the address pins. (See Section 11.1)
This command puts the device into the CFI-Query mode so that reading the device will output
Common Flash Interface information. See Section 10.1.3 and Appendix C, “Common
Flash Interface”.
98
C0
CFI Query
This is a two-cycle command. The first cycle prepares the CUI for a program operation to the
protection register. The second cycle latches addresses and data information and initiates the WSM
to execute the Protection Program algorithm to the protection register. The flash outputs Status
Register data when CE# or OE# is toggled. A Read Array command is required after programming
to read array data. See Section 11.5.
Protection
Program
Set-Up
10
00
Alt. Prog Set-Up
Operates the same as Program Set-up command. (See 0x40/Program Set-Up)
Invalid/
Reserved
Unassigned commands should not be used. Numonyx reserves the right to redefine these codes
for future functions.
Note: See Appendix A, “Write State Machine States” for mode transition information.
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Table 25: Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
SR[7] WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Before checking program or erase- status bits, check the Write
State Machine bit first to determine Word Program or Block
Erase completion.
SR[6] = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
SR[5] = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to verify
successful block erasure.
SR[4] = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
The V status bit does not provide continuous indication of V
PP
PP
level. The WSM interrogates V level only after the Program or
PP
SR[3] = V STATUS (VPPS)
Erase command sequences have been entered and informs the
PP
1 = V Low Detect, Operation Abort
system if V has not been switched on. The V is also
PP
PP PP
0 = V OK
checked before the operation is verified by the WSM. The V
status bit is not guaranteed to report accurate feedback
PP
PP
between V
and V Min.
PPLK
PP1
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR[1] = BLOCK LOCK STATUS
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
1 = Prog/Erase attempted on a locked block; Operation
aborted.
0 = No operation to locked blocks
This bit is reserved for future use and should be masked out
when polling the Status Register.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
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C3 Discrete
11.0
Security Modes
11.1
Flexible Block Locking
The C3 Discrete device offers an instant, individual block-locking scheme that allows
any block to be locked or unlocked with no latency, enabling instant code and data
protection.
This locking scheme offers two levels of protection. The first level allows software-only
control of block locking (useful for data blocks that change frequently), while the
second level requires hardware interaction before locking can be changed (useful for
code blocks that change infrequently).
The following sections will discuss the operation of the locking system. The term “state
[abc]” will be used to specify locking states; for example, “state [001],” where
a = value of WP#, b = bit D1 of the Block Lock Status Register, and c = bit D0 of the
Block Lock Status Register. Figure 14, “Block Locking State Diagram” on page 48
displays all of the possible locking states.
Figure 14: Block Locking State Diagram
Locked-
Down4,5
Hardware
Locked5
Locked
Power-Up/Reset
[X01]
[011]
[011]
WP# Hardware Control
Software
Locked
Unlocked
Unlocked
[111]
[110]
[X00]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
Notes:
1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to
this block. D1 = ‘1’, Lock-down has been issued to this block.
3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference
between Hardware Locked and Locked-Down states.
11.1.1
Locking Operation
The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of
which will be described in the following sections. See Figure 14, “Block Locking State
Diagram” on page 48 and Figure 21, “Locking Operations Flowchart” on page 60.
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The following paragraph concisely summarizes the locking functionality.
11.1.1.1
Locked State
The default state of all blocks upon power-up or reset is locked (states [001] or [101]).
Locked blocks are fully protected from alteration. Any Program or Erase operations
attempted on a locked block will return an error on bit SR[1]. The state of a locked
block can be changed to Unlocked or Lock Down using the appropriate software
commands. An Unlocked block can be locked by writing the Lock command sequence,
0x60 followed by 0x01.
11.1.1.2
11.1.1.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All
unlocked blocks return to the Locked state when the device is reset or powered down.
The status of an unlocked block can be changed to Locked or Locked Down using the
appropriate software commands. A Locked block can be unlocked by writing the Unlock
command sequence, 0x60 followed by 0xD0.
Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from Program and Erase
operations (just like Locked blocks), but their protection status cannot be changed
using software commands alone. A Locked or Unlocked block can be Locked Down by
writing the Lock-Down command sequence, 0x60 followed by 0x2F. Locked-Down
blocks revert to the Locked state when the device is reset or powered down.
The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock
Down [011] are protected from program, erase, and lock status changes. When
WP# = 1, the Lock-Down function is disabled ([111]), and Locked-Down blocks can be
individually unlocked by software command to the [110] state, where they can be
erased and programmed. These blocks can then be relocked [111] and unlocked [110]
as required while WP# remains high. When WP# goes low, blocks that were previously
Locked Down return to the Lock-Down state [011], regardless of any changes made
while WP# was high. Device reset or power-down resets all blocks, including those in
Lock-Down, to Locked state.
11.2
Reading Block-Lock Status
The Lock status of each block can be read in read-identifier mode of the device by
issuing the read-identifier command (0x90). Subsequent reads at Block Address +
0x00002 will output the Lock status of that block. The Lock status is represented by
DQ0 and DQ1:
• DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and
cleared by the Unlock command. It is also automatically set when entering Lock
Down.
• DQ1 indicates Lock-Down status and is set by the Lock-Down command. It cannot
be cleared by software—only by device reset or power-down.
See Table 22, “Device Identification Codes” on page 42 for block-status information.
11.3
Locking Operations during Erase Suspend
Changes to block-lock status can be performed during an erase-suspend by using the
standard locking command sequences to Unlock, Lock, or Lock Down a block. This
operation is useful in the case when another block needs to be updated while an Erase
operation is in progress.
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To change block locking during an Erase operation, first issue the Erase Suspend
command (0xB0), and then check the Status Register until it indicates that the Erase
operation has been suspended. Next, write the preferred Lock command sequence to a
block and the Lock status will be changed. After completing any preferred Lock, Read,
or Program operations, resume the Erase operation with the Erase Resume command
(0xD0).
If a block is Locked or Locked Down during a Suspended Erase of the same block, the
locking status bits will be changed immediately. But when the Erase is resumed, the
Erase operation will complete.
Locking operations cannot be performed during a Program Suspend. Refer to Appendix
A, “Write State Machine States” on page 53 for detailed information on which
commands are valid during Erase Suspend.
11.4
Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can
introduce ambiguity into Status Register results.
Since locking changes are performed using a two-cycle command sequence, for
example, 0x60 followed by 0x01 to lock a block. Following the Block Lock, Block
Unlock, or Block Lock-Down Setup command (0x60) with an invalid command will
produce a Lock-Command error (SR[4] and SR[5] will be set to 1) in the Status
Register. If a Lock-Command error occurs during an Erase Suspend, SR[4] and SR[5]
will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is
complete, any possible error during the Erase cannot be detected by the Status
Register because of the previous Lock-Command error.
A similar situation happens if an error occurs during a Program-Operation error nested
within an Erase Suspend.
11.5
128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to
increase the security of a system design. For example, the number contained in the
protection register can be used to “match” the flash component with other system
components, such as the CPU or ASIC, preventing device substitution. Application note,
AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains
additional application information.
The 128 bits of the protection register are divided into two 64-bit segments. One of the
segments is programmed at the Numonyx factory with a unique 64-bit number, which
is unchangeable. The other segment is left blank for customer designs to program, as
preferred. Once the customer segment is programmed, it can be locked to prevent
further programming.
11.5.1
Reading the Protection Register
The protection register is read in the Read-Identifier mode. The device is switched to
this mode by issuing the Read Identifier command (0x90). Once in this mode, read
cycles from addresses shown in Figure 15, “Protection Register Mapping” retrieve the
specified information. To return to Read-Array mode, issue the Read Array command
(0xFF).
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11.5.2
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program
command. The 64-bit number is programmed 16 bits at a time. First, issue the
Protection Program Setup command, 0xC0. The next write to the device will latch in
address and data and program the specified location. The allowable addresses are
listed in Table 22, “Device Identification Codes” on page 42. See Figure 22, “Protection
Register Programming Flowchart” on page 61. Attempting to program to a previously
locked protection register segment will result in a Status Register error (Program Error
bit SR[4] and Lock Error bit SR[1] will be set to 1).
Note:
Do not attempt to address Protection Program commands outside the defined
protection register address space; status register can be indeterminate.
11.5.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming
bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. This bit is set using the
Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in
the protection register. Protection Program commands to a locked section will result in
a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to
1). Protection register lockout state is not reversible.
Figure 15: Protection Register Mapping
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Intel Factory-Programmed)
0x81
0x80
PR Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
11.6
V
Program and Erase Voltages
PP
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range.
For fast production programming, 12 V programming can be used.
11.6.1
Program Protection
In addition to the flexible block locking, the VPP programming voltage can be held low
for absolute hardware write protection of all blocks in the flash device. When VPP is
below or equal to VPPLK, any Program or Erase operation will result in an error,
prompting the corresponding Status Register bit (SR[3]) to be set.
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Figure 16: Example Power Supply Configurations
System Supply
System Supply
VCC
VPP
VCC
12 V Supply
VPP
Prot#
(Logic Signal)
10
≤ KΩ
12 V Fast Programming
Low-Voltage Programming
Absolute Write Protection With V
≤
VPPLK
Absolute Write Protection via Logic Signal
PP
System Supply
(Note 1)
System Supply
VCC
VCC
VPP
VPP
12 V Supply
Low Voltage and 12 V Fast Programming
Low-Voltage Programming
Note:
1.
A resistor can be used if the V supply can sink adequate current based on resistor value. See AP-657 Designing with the
Advanced+ Boot Block Flash Memory Architecture for details.
CC
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Appendix A Write State Machine States
Table 26 and Table 27 show the Write State Machine command state transitions based
on incoming commands.
Table 26: Write State Machine States (Sheet 1 of 2)
Command Input (and Next State)
Program
Setup
(10/
Prog/
Ers
Resume
(D0)
Data
When
Read
Read
Array
(FFH)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Read
Status
(70H)
Clear
Status
(50H)
SR.
7
Current State
40H)
Read
Array
Prog.
Ers.
Read
Array
Read Array
Read Status
Read Config.
Read Query
“1”
“1”
“1”
“1”
Array
Status
Config
CFI
Read Array
Read Array
Read Array
Read Array
Read Sts.
Read Sts.
Read Sts.
Read Sts.
Setup
Setup
Read
Array
Prog.
Setup
Ers.
Setup
Read
Array
Read
Array
Prog.
Setup
Ers.
Setup
Read
Array
Read
Array
Prog.
Setup
Ers.
Setup
Read
Array
Lock
Cmd.
Error
Lock
(Done)
Lock
(Done)
Lock Setup
“1”
Status
Lock Command Error
Lock Cmd. Error
Read
Read
Array
Prog.
Setup
Ers.
Setup
Lock Cmd. Error
“1”
“1”
“1”
“0”
Status
Status
Status
Status
Read Array
Read Array
Read Sts.
Array
Lock Oper.
(Done)
Read
Array
Prog.
Setup
Ers.
Setup
Read
Array
Read Sts.
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(Not Done)
Protection Register Program (Not Done)
Prot. Prog.
(Done)
Read
Array
Prog.
Ers.
Read
Array
“1”
“1”
“0”
Status
Status
Status
Read Array
Setup
Read Sts.
Setup
Prog. Setup
Program
Program (Not
Done)
Prog. Sus.
Status
Program (Not Done)
Program (Not Done)
Prog.
Sus.
Read
Array
Prog.
(Not
Program
Prog.
Sus.
Prog.
Sus. Rd.
Array
Prog. Susp.
Status
Program Suspend
Read Array
Prog. Sus.
Rd. Array
“1”
“1”
“1”
“1”
Status
Array
Config
CFI
(Not
Done)
Done)
Status
Prog.
Sus.
Read
Array
Prog.
(Not
Done)
Program
(Not
Done)
Prog.
Sus.
Status
Prog.
Sus. Rd.
Array
Prog. Susp.
Read Array
Program Suspend
Read Array
Prog. Sus.
Rd. Array
Prog.
Sus.
Read
Array
Prog.
(Not
Done)
Program
(Not
Done)
Prog.
Sus.
Status
Prog.
Sus. Rd.
Array
Prog. Susp.
Read Config
Program Suspend
Read Array
Prog. Sus.
Rd. Array
Prog.
Sus.
Read
Array
Prog.
(Not
Done)
Program
(Not
Done)
Prog.
Sus.
Status
Prog.
Sus. Rd.
Array
Prog. Susp.
Read Query
Program Suspend
Read Array
Prog. Sus.
Rd. Array
Program
(Done)
Read
Array
Prog.
Setup
Ers.
Setup
Read
Status
Read
Array
“1”
“1”
Status
Status
Read Array
Erase
(Not
Done)
Erase
Cmd.
Error
Erase
(Not
Done)
Erase Command
Error
Erase Setup
Erase Command Error
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Table 26: Write State Machine States (Sheet 2 of 2)
Erase Cmd.
Error
Read
Array
Prog.
Setup
Ers.
Setup
Read
Status
Read
Array
“1”
“0”
Status
Status
Read Array
Erase (Not
Done)
Erase Sus.
Status
Erase (Not Done)
Erase (Not Done)
Erase
Sus.
Read
Array
Ers. Sus.
Erase
Sus.
Status
Ers. Susp.
Status
Prog.
Rd.
Ers. Sus.
Rd. Array
Ers. Sus.
“1”
“1”
“1”
Status
Array
Erase
Erase
Erase
Erase
Erase
Erase
Erase
Erase
Setup
Array
Rd. Array
Erase
Sus.
Read
Array
Ers. Sus.
Erase
Sus.
Status
Erase Susp.
Array
Prog.
Rd.
Ers. Sus.
Rd. Array
Ers. Sus.
Rd. Array
Setup
Array
Erase
Sus.
Read
Array
Ers. Sus.
Erase
Sus.
Status
Ers. Susp. Read
Config
Prog.
Rd.
Ers. Sus.
Rd. Array
Ers. Sus.
Rd. Array
Config
Setup
Array
Erase
Sus.
Read
Array
Ers. Sus.
Erase
Sus.
Status
Ers. Susp. Read
Query
Prog.
Rd.
Ers. Sus.
Rd. Array
Ers. Sus.
Rd. Array
“1”
“1”
CFI
Setup
Array
Read
Array
Prog.
Setup
Ers.
Setup
Read
Array
Erase (Done)
Status
Read Array
Read Sts.
Table 27: Write State Machine States, Continued
Command Input (and Next State)
Lock Setup
(60H)
Lock
Confirm
(01H)
Lock Down
Confirm
(2FH)
Unlock
Confirm
(D0H)
Current
State
Read Config
(90H)
Read Query
(98H)
Prot. Prog.
Setup (C0H)
Prot. Prog.
Setup
Read Array
Read Status
Read Config.
Read Config.
Read Config.
Read Config.
Read Config.
Read Query
Read Query
Read Query
Read Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Read Array
Read Array
Read Array
Prot. Prog.
Setup
Prot. Prog.
Setup
Prot. Prog.
Setup
Read Query
Lock Setup
Read Array
Lock Operation (Done)
Read Array
Locking Command Error
Lock Cmd.
Error
Prot. Prog.
Setup
Read Config.
Read Config.
Read Query
Read Query
Lock Setup
Lock Setup
Lock Oper.
(Done)
Prot. Prog.
Setup
Read Array
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(Not Done)
Protection Register Program (Not Done)
Prot. Prog.
(Done)
Prot. Prog.
Lock Setup
Read Config.
Read Query
Read Array
Setup
Prog. Setup
Program
Program
(Not Done)
Program (Not Done)
Prog. Susp.
Status
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program Suspend Read Array
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Table 27: Write State Machine States, Continued
Prog. Susp.
Read Array
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Prog. Susp.
Read Config.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Prog. Susp.
Read Query.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program
(Done)
Prot. Prog.
Setup
Read Config.
Read Config.
Read Query
Read Query
Lock Setup
Read Array
Read Array
Erase
Setup
Erase
(Not Done)
Erase Command Error
Erase Cmd.
Error
Prot. Prog.
Lock Setup
Setup
Erase
(Not Done)
Erase (Not Done)
Erase
Erase Susp.
Status
Ers. Susp.
Erase
Suspend
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
Read Config.
(Not Done)
Read Query
Erase
Suspend
Array
Erase
Suspend
Read Query
Ers. Susp.
Read Config.
Erase
(Not Done)
Erase Suspend Read Array
Erase
Suspend
Read Config.
Erase
Suspend
Read Query
Eras Sus.
Read Config
Erase
(Not Done)
Erase Suspend Read Array
Erase Suspend Read Array
Erase
Suspend
Read Config.
Erase
Suspend
Read Query
Eras Sus.
Read Query
Erase
(Not Done)
Lock Setup
Lock Setup
Prot. Prog.
Setup
Ers.(Done)
Read Config.
Read Query
Read Array
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C3 Discrete
Appendix B Flow Charts
Figure 17: Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0x40
Write
Write
Read
Write 0x40,
Word Address
Setup
Addr = Location to program
(Setup)
Data = Data to program
Addr = Location to program
Data
Write Data,
Word Address
(Confirm)
Status register data: Toggle CE# or
OE# to update Status Register
None
None
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle
No
Suspend?
Yes
0
SR[7] =
1
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Error
Idle
Idle
None
None
1
1
1
VPP Range
Error
SR[3] =
0
Check SR[4]:
1 = Data Program Error
Program
Error
Check SR[1]:
1 = Block locked; operation aborted
SR[4] =
0
Idle
None
SR[3] MUST be cleared before the Write State Machine will
allow further program attempts.
Device
SR[1] =
0
Protect Error
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Program
Successful
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Figure 18: Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Status
Data = 0x70
Addr = Any address
Write
Write
Write 0xB0
Any Address
(Program Suspend)
(Read Status)
Program Data = 0xB0
Suspend Addr = Any address
Write 0x70
Any Address
Status register data
Toggle CE# or OE# to update Status
register
Read
None
Read Status
Register
Addr = Any address
Check SR[7]:
Idle
Idle
None
None
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[2]:
1 = Program suspended
0 = Program completed
0
Program
Completed
SR[2] =
1
Read
Array
Data = 0xFF
Addr = Any address
Write
Read
Write
Write 0xFF
(Read Array)
Read array data from block other than
the one being programmed
None
Read Array
Data
(Read
Array)
Write 0xFF
Program Data = 0xD0
Resume Addr = Any address
Read Array
Data
Done
Reading
No
Yes
Write 0xD0
Any Address
(Program Resume)
Program
Resumed
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Figure 19: Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Status
Data = 0x70
Addr = Any address
Write
Write
Write 0xB0,
Any Address
(Erase Suspend)
(Read Status)
Erase
Data = 0xB0
Suspend Addr = Any address
Write 0x70,
Any Address
Status Register data. Toggle CE# or
Read
Idle
None
None
None
OE# to update Status register;
Addr = Any Address
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
Idle
0 = Erase completed
0
Erase
Completed
SR[6] =
1
Read Array Data = 0xFF or 0x40
or Program Addr = Any address
Write
Write 0xFF
Read or
Write
Read array or program data from/to
block other than the one being erased
None
Read Array
Data
Program Data = 0xD0
Resume Addr = Any address
Write
(Read Array)
Done
0
Reading
1
Write 0xD0,
Any Address
(Erase Resume)
(Read Array)
Write 0xFF
Erase
Resumed
Read Array
Data
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Figure 20: Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Start
Command
Operation
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write
Read
Write 0x20,
(Block Erase)
Block Address
Erase Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write 0xD0,
(Erase Confirm)
Block Address
Status Register data. Toggle CE# or
None
OE# to update Status register data
Suspend
Erase
Loop
Read Status
Register
Check SR[7]:
Idle
None
1 = WSM ready
0 = WSM busy
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = PP Range Error
Idle
Idle
Idle
None
None
None
V
1
VPP Range
Error
SR[3] =
0
Check SR[4,5]:
Both 1 = Command Sequence Error
1,1
1
Command
Sequence Error
Check SR[5]:
1 = Block Erase Error
SR[4,5] =
0
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
Block Erase
Error
Idle
None
SR[5] =
0
SR[1,3] must be cleared before the Write State Machine will
allow further erase attempts.
1
Block Locked
Error
SR[1] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
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C3 Discrete
Figure 21: Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x60,
Block Address
Lock
Setup
Data = 0x60
Addr = Any Address
(Lock Setup)
Write
Lock,
Unlock, or
Lock-Down
Data = 0x01 (Block Lock)
0xD0 (Block Unlock)
Write either
0x01/0xD0/0x2F,
Block Address
(Lock Confirm)
(Read Device ID)
Write
Write
0x2F (Lock-Down Block)
Confirm Addr = Block to lock/unlock/lock-down
Read Data = 0x90
(Optional) Device ID Addr = Any Address
Write 0x90
Read
(Optional)
Block Lock Block Lock status data
Read Block
Lock Status
Status
Addr = Block address + offset 2
Idle
(Optional)
None
Confirm locking change on D[1,0] .
Locking
No
Change?
Yes
Read
Array
Data = 0xFF
Addr = Any address
Write
Write 0xFF
Any Address
(Read Array)
Lock Change
Complete
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Figure 22: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup)
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
Status Register Data. Toggle CE# or
None
OE# to Update Status Register Data
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
None
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[1], SR[3], SR[4]:
0,1,1 = VPP Range Error
Idle
Idle
Idle
None
1
SR[3], SR[4] =
0
VPP Range Error
Program Error
Check SR[1], SR[3], SR[4]:
0,0,1 = Programming Error
None
None
Check SR[1], SR[3], SR[4]:
1,0,1 = Block locked; operation aborted
1
1
SR[3], SR[4] =
SR[3] must be cleared before the Write State Machine will
allow further program attempts.
0
Only the Clear Staus Register command clears SR[1, 3, 4].
Register Locked;
Program Aborted
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
SR[3], SR[4] =
0
Program
Successful
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C3 Discrete
Appendix C Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash
Interface (CFI) Query command. System software should parse this structure to gain
critical information such as block size, density, x8/x16, and electrical specifications.
Once this information has been obtained, the software detects which command sets to
use to enable flash writes, block erases, and otherwise control the flash component.
The Query is part of an overall specification for multiple command set and control
interface descriptions called Common Flash Interface, or CFI.
C.1
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-DQ7) only. The
numerical offset value is the address relative to the maximum bus width supported by
the device. On this family of devices, the Query table device starting address is a 0x10,
which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 0x10 and 0x11. This CFI-compliant device
outputs 0x00 data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ0-
DQ7) and 0x00 in the high byte (DQ8-DQ15).
At Query addresses containing two or more bytes of information, the least-significant
data byte is presented at the lower address, and the most-significant data byte is
presented at the higher address.
For tables in this appendix, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “0x00,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 0x00 on the upper byte in this mode.
Table 28: Summary of Query Structure Output as a Function of Device and Mode
Device
Hex Offset
Hex Code
ASCII Value
00010:
00011:
00012:
51
52
59
"Q"
"R"
"Y"
Device Addresses
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Table 29: Example of Query Structure Output of x16 Devices
Word Addressing:
Offset
Hex Code
Value
A[X-0]
DQ[16:0]
0x00010
0x00011
0x00012
0x00013
0x00014
0x00015
0x00016
0x00017
0x00018
...
0051
0052
0059
"Q"
"R"
"Y"
P_IDLO
P_IDHI
PLO
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PHI
A_IDLO
A_IDHI
...
...
C.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash
Interface (CFI) Query structure or “database.” Table 30 summarizes the structure sub-
sections and address locations.
Table 30: Query Structure
1
Offset
0x00000
Sub-Section Name
Description
Manufacturer Code
Device Code
0x00001
2
0x(BA+2)
Block Status register
Block-specific information
0x00004-0xF
0x00010
Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
CFI query identification string
System interface information
Device geometry definition
0x0001B
0x00027
Primary Numonyx-specific
Extended Query Table
Vendor-defined additional information specific to the Primary Vendor
Algorithm
3
P
Notes:
1.
Refer to the Query Structure Output section and offset 0x28 for the detailed definition of offset address as a function of
device bus width and mode.
2.
3.
BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word).
Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
C.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations. See Table 31.
Block Erase Status (BSR[1]) allows system software to determine the success of the
last block erase operation. BSR[1] can be used just after power-up to verify that the
VCC supply was not accidentally removed during an erase operation.
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Table 31: Block Status Register
Offset
Length
Description
Add.
Value
Block Lock Status Register
BA+2
--00 or --01
BSR[0] Block lock status
0 = Unlocked
BA+2
(bit 0): 0 or 1
1 = Locked
1
0x(BA+2)
1
BSR[1] Block lock-down status
0 = Not locked down
1 = Locked down
BA+2
BA+2
(bit 1): 0 or 1
(bit 2-7): 0
BSR[7:2]: Reserved for future use
Notes:
1.
BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word).
C.4
CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s). See Table 32.
Table 32: CFI Identification
Offset
Length
Description
Add.
Hex Code
Value
10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
0x10
3
Query-unique ASCII string “QRY“
Primary vendor command set and control interface ID code
16-bit ID code for vendor-specified algorithms
13:
14:
--03
--00
0x13
0x15
0x17
0x19
2
2
2
2
15:
16:
--35
--00
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code
0x0000 means no second vendor-specified algorithm exists
17:
18:
--00
--00
Secondary algorithm Extended Query Table address
0x0000 means none exists
19:
1A:
--00
--00
Table 33: System Interface Information
Offset
Length
Description
Add.
Hex Code
Value
V
V
V
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
0x1B
1
1B:
--27
2.7 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
0x1C
0x1D
1
1
1C:
1D:
--36
--B4
3.6 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
11.4 V
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
0x1E
0x1F
1
1
1E:
1F:
--C6
--05
12.6 V
32 µs
n
“n” such that typical single word program time-out =2 µs
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Table 33: System Interface Information
Offset
Length
Description
Add.
Hex Code
Value
n
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1
1
1
1
1
1
1
“n” such that typical max. buffer write time-out = 2 µs
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
--04
--00
--03
--00
NA
1 s
n
“n” such that typical block erase time-out = 2 ms
n
“n” such that typical full chip erase time-out = 2 ms
NA
n
“n” such that maximum word program time-out = 2 times typical
512µs
NA
n
“n” such that maximum buffer write time-out = 2 times typical
n
“n” such that maximum block erase time-out = 2 times typical
8s
n
“n” such that maximum chip erase time-out = 2 times typical
NA
C.5
Device Geometry Definition
Table 34: Device Geometry Definition
Hex
Code
Offset
Length
Description
Add.
Value
See Table 35,
“Device
n
0x27
1
“n” such that device size = 2 in number of bytes
27
Geometry
Details” on
page 66
x8 async
28:00,29:0
0
x16 async
28:01,29:00 28:02,29:00
x8/x16 async
28:
29:
--01
x16
0x28
0x2A
2
2
Flash device interface:
--00
2A:
2B:
--00
0
n
“n” such that maximum number of bytes in write buffer = 2
--00
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
0x2C
1
2C:
--02
2
See Table 35,
“Device
2D:
2E:
2F:
30:
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
0x2D
0x2D
4
Geometry
Details” on
page 66
See Table 35,
“Device
31:
32:
33:
34:
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
14
Geometry
Details” on
page 66
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C3 Discrete
Table 35: Device Geometry Details
16 Mbit
Address
32 Mbit
64 Mbit
-B
-T
-B
-T
-B
-T
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
-15
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
-16
--01
-00
--17
--01
-00
--17
--01
-00
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
-00
-00
-00
-00
-00
-00
--02
--3E
-00
--02
--07
-00
--02
--7E
-00
-00
--20
--00
--7E
-00
--00
--01
--07
-00
--01
--07
-00
--20
--00
--00
--01
--20
--00
C.6
Numonyx-Specific Extended Query Table
Certain flash features and commands are optional as shown in Table 36, “Primary-
Vendor Specific Extended Query” on page 66. The Numonyx-specific Extended Query
table specifies these features as well as other similar types of information.
Table 36: Primary-Vendor Specific Extended Query (Sheet 1 of 2)
1
Offset
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
P = 0x15
0x(P+0)
0x(P+1)
0x(P+2)
35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
Primary extended query table
Unique ASCII string “PRI”
3
0x(P+3)
0x(P+4)
1
1
Major version number, ASCII
Minor version number, ASCII
38:
39:
--31
--30
“1”
“0”
Optional feature and command support (1=yes,
0=no)
bits 9–31 are reserved; undefined bits are “0.” If
bit 31 is “1” then another 31 bit field of optional
features follows at the end of the bit-30 field.
3A:
3B:
3C:
3D:
--66
--00
--00
--00
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8)
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
No
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
4
No
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Page mode read supported
bit 8 Synchronous read supported
Yes
Yes
No
No
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Table 36: Primary-Vendor Specific Extended Query (Sheet 2 of 2)
1
Offset
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
P = 0x15
Supported functions after suspend: Read Array,
Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3E:
--01
0x(P+9)
1
bit 0 Program supported after erase suspend
bit 0 = 1
Yes
3F:
40:
--03
--00
Block Status Register mask
0x(P+A)
0x(P+B)
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status Register active
bit 1 Block Lock-Down Bit Status active
2
bit 0 = 1
Yes
Yes
bit 1 = 1
V
logic supply highest performance program/
CC
erase voltage
0x(P+C)
1
1
41:
42:
--33
--C0
3.3 V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
V
optimum program/erase supply voltage
PP
0x(P+D)
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
12.0 V
Notes:
1.
The variable P is a pointer which is defined at CFI offset 0x15.
Table 37: Protection Register Information
1
Offset
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Address
Value
P = 0x35
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
0x(P+E)
1
43:
--01
01
0x(P+F)
0x(P+10)
(0xP+11)
44:
45:
46:
--80
--00
--03
80h
00h
8 byte
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15
point to the Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-
programmable.
4
0x(P+12)
47:
48:
--03
8 byte
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
n
n
bits 16–23 = “n” such that 2 = factory pre-programmed bytes
bits 24–31 = “n” such that 2 = user programmable bytes
0x(P+13)
Reserved for future use
Notes:
1.
The variable P is a pointer which is defined at CFI offset 0x15.
March 2008
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C3 Discrete
Appendix D Additional Information
Order Number
Document/Tool
297938
292216
292215
3 Volt Advanced+ Boot Block Flash Memory Specification Update
AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture
Contact your Numonyx
Representative
Numonyx™ Flash Data Integrator (Numonyx™ FDI) Software Developer’s Kit
IFDI Interactive: Play with Numonyx™ Flash Data Integrator on Your PC
297874
Notes:
1.
To request Numonyx documentation or tools, contact your local Numonyx or distribution sales office.
Datasheet
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Appendix E Ordering Information
Figure 23: Component Ordering Information
T E 2 8 F 3 2 0 C 3 T C 7 0
Package
TE = 48-Lead TSOP
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
RC = Easy BGA
PC = Pb Free Easy BGA
PH = Pb Free VFBGA
JS = Pb Free TSOP
Access Speed (ns)
(70, 80, 90, 100, 110)
Lithography
A = 0.25 µm
C = 0.18 µm
D = 0.13 µm
Product line designator
for all Inte®l Flash products
T = Top Blocking
B = Bottom Blocking
Device Density
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
Product Family
C3 = 3 Volt Advanced+ Boot Block
V
V
CC = 2.7 V–3.6 V
PP = 2.7 V–3.6 V or
1.14 V–12.6 V
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Table 38: Product Information Ordering Matrix
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP
48-Ball µBGA* CSP
48-Ball VF BGA
Easy BGA
Extended
64 Mbit
TE28F320C3TD70
TE28F320C3BD70
RC28F320C3TD70
RC28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
GE28F320C3TD70
GE28F320C3BD70
RC28F320C3TD90
RC28F320C3BD90
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
TE28F320C3TA110
TE28F320C3BA110
JS28F320C3BD70
JS28F320C3TD70
JS28F320C3BD90
JS28F320C3TD90
GE28F320C3TC70
GE28F320C3BC70
GE28F320C3TC90
GE28F320C3BC90
PH28F320C3BD70
PH28F320C3TD70
PH28F320C3BD90
PH28F320C3TD90
RC28F320C3TC90
RC28F320C3BC90
RC28F320C3TA100
RC28F320C3BA100
RC28F320C3TA110
RC28F320C3BA110
PC28F320C3BD70
PC28F320C3TD70
PC28F320C3BD90
PC28F320C3TD90
GT28F320C3TA100
GT28F320C3BA100
GT28F320C3TA110
GT28F320C3BA110
Extended
32 Mbit
TE28F160C3TD70
TE28F160C3BD70
TE28F160C3TC70
TE28F160C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TC90
TE28F160C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
JS28F160C3BD70
JS28F160C3TD70
RC28F160C3TD70
RC28F160C3BD70
RC28F160C3TC70
RC28F160C3BC70
RC28F160C3TC80
RC28F160C3BC80
RC28F160C3TC90
RC28F160C3BC90
RC28F160C3TA90
RC28F160C3BA90
RC28F160C3TA110
RC28F160C3BA110
PC28F160C3BD70
PC28F160C3TD70
GE28F160C3TD70
GE28F160C3BD70
GE28F160C3TC70
GE28F160C3BC70
GE28F160C3TC80
GE28F160C3BC80
GE28F160C3TC90
GE28F160C3BC90
GT28F160C3TA90
GT28F160C3BA90
GT28F160C3TA110
GT28F160C3BA110
Extended
16 Mbit
PH28F160C3BD70
PH28F160C3TD70
TE28F800C3TD70
TE28F800C3BD70
RC28F800C3TD70
RC28F800C3BD70
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
JS28F800C3BD70
JS28F800C3TD70
RC28F800C3TA90
RC28F800C3BA90
RC28F800C3TA110
RC28F800C3BA110
PC28F800C3BD70
PC28F800C3TD70
Extended
8 Mbit
Note: The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first
character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other assembly codes
without an “E” or “S” as the first character are production units.
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