PC28F640P30T85_技术文档

®

Numonyx™ StrataFlash Embedded Memory

(P30)

Datasheet

Product Features

High performance

Security

— One-Time Programmable Registers:

— 85 ns initial access

• 64 unique factory device identifier bits

• 2112 user-programmable OTP bits

— Selectable OTP Space in Main Array:

• Four pre-defined 128-KByte blocks (top or bottom

configuration)

— 52 MHz with zero wait states, 17ns clock-to-data output

synchronous-burst read mode

— 25 ns asynchronous-page read mode

— 4-, 8-, 16-, and continuous-word burst mode

— Buffered Enhanced Factory Programming (BEFP) at 5 μs/

byte (Typ)

• Up to Full Array OTP Lockout

— Absolute write protection: V = V

PP

SS

— 1.8 V buffered programming at 7 μs/byte (Typ)

— Power-transition erase/program lockout

— Individual zero-latency block locking

— Individual block lock-down

Architecture

— Multi-Level Cell Technology: Highest Density at Lowest

Cost

Software

— Asymmetrically-blocked architecture

— Four 32-KByte parameter blocks: top or bottom

configuration

— 20 μs (Typ) program suspend

— 20 μs (Typ) erase suspend

— Numonyx™ Flash Data Integrator optimized

— Basic Command Set and Extended Command Set

compatible

— 128-KByte main blocks

Voltage and Power

— V (core) voltage: 1.7 V – 2.0 V

CC

— Common Flash Interface capable

— V

(I/O) voltage: 1.7 V – 3.6 V

CCQ

Density and Packaging

— Standby current: 20μA (Typ) for 64-Mbit

— 4-Word synchronous read current:

13 mA (Typ) at 40 MHz

— 56- Lead TSOP package (64, 128, 256,

512- Mbit)

— 64- Ball Numonyx™ Easy BGA package (64,

128, 256, 512- Mbit)

— Numonyx™ QUAD+ SCSP (64, 128, 256,

512- Mbit)

Quality and Reliability

— Operating temperature: –40 °C to +85 °C

— Minimum 100,000 erase cycles per block

— ETOX™ VIII process technology

— 16-bit wide data bus

Order Number: 306666-11

November 2007

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND

CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx

products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.

Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented

subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or

otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting

Numonyx's website at http://www.numonyx.com.

Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

2

November 2007

Order Number: 306666-11

P30

Contents

1.0 Introduction..............................................................................................................6

1.1

1.2

1.3

Nomenclature.....................................................................................................6

Acronyms...........................................................................................................6

Conventions .......................................................................................................7

2.0 Functional Overview..................................................................................................8

2.1 Virtual Chip Enable Description..............................................................................8

3.0 Package Information...............................................................................................10

3.1

3.2

3.3

56-Lead TSOP................................................................................................... 10

64-Ball Easy BGA Package.................................................................................. 11

QUAD+ SCSP Packages...................................................................................... 13

4.0 Ballout and Signal Descriptions ...............................................................................16

4.1

4.2

4.3

4.4

Signal Ballout ................................................................................................... 16

Signal Descriptions............................................................................................ 19

Dual-Die Configurations ..................................................................................... 21

Memory Maps ................................................................................................... 22

5.0 Maximum Ratings and Operating Conditions............................................................ 25

5.1

5.2

Absolute Maximum Ratings.................................................................................25

Operating Conditions .........................................................................................25

6.0 Electrical Specifications........................................................................................... 26

6.1

6.2

DC Current Characteristics.................................................................................. 26

DC Voltage Characteristics.................................................................................. 27

7.0 AC Characteristics ................................................................................................... 28

7.1

7.2

7.3

7.4

7.5

AC Test Conditions ............................................................................................ 28

Capacitance......................................................................................................29

AC Read Specifications.......................................................................................29

AC Write Specifications ...................................................................................... 36

Program and Erase Characteristics....................................................................... 39

8.0 Power and Reset Specifications...............................................................................41

8.1

8.2

8.3

Power-Up and Power-Down.................................................................................41

Reset Specifications........................................................................................... 41

Power Supply Decoupling ................................................................................... 42

9.0 Device Operations ................................................................................................... 43

9.1

Bus Operations .................................................................................................43

9.1.1 Reads................................................................................................... 43

9.1.2 Writes................................................................................................... 44

9.1.3 Output Disable.......................................................................................44

9.1.4 Standby................................................................................................44

9.1.5 Reset.................................................................................................... 44

Device Commands............................................................................................. 45

Command Definitions.........................................................................................46

9.2

9.3

10.0 Read Operations......................................................................................................48

10.1 Asynchronous Page-Mode Read........................................................................... 48

10.2 Synchronous Burst-Mode Read............................................................................ 48

10.3 Read Configuration Register................................................................................49

10.3.1 Read Mode ............................................................................................ 50

10.3.2 Latency Count........................................................................................50

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Datasheet

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P30

10.3.3 WAIT Polarity.........................................................................................52

10.3.4 Data Hold ..............................................................................................53

10.3.5 WAIT Delay............................................................................................53

10.3.6 Burst Sequence......................................................................................54

10.3.7 Clock Edge.............................................................................................54

10.3.8 Burst Wrap ............................................................................................55

10.3.9 Burst Length..........................................................................................55

10.3.10End of Word Line (EOWL) Considerations ...................................................55

11.0 Programming Operations.........................................................................................56

11.1 Word Programming............................................................................................56

11.1.1 Factory Word Programming......................................................................57

11.2 Buffered Programming .......................................................................................57

11.3 Buffered Enhanced Factory Programming..............................................................58

11.3.1 BEFP Requirements and Considerations .....................................................58

11.3.2 BEFP Setup Phase...................................................................................59

11.3.3 BEFP Program/Verify Phase......................................................................59

11.3.4 BEFP Exit Phase......................................................................................60

11.4 Program Suspend ..............................................................................................60

11.5 Program Resume ...............................................................................................60

11.6 Program Protection ............................................................................................61

12.0 Erase Operations......................................................................................................62

12.1 Block Erase.......................................................................................................62

12.2 Erase Suspend ..................................................................................................62

12.3 Erase Resume ...................................................................................................63

12.4 Erase Protection ................................................................................................63

13.0 Security Modes ........................................................................................................64

13.1 Block Locking....................................................................................................64

13.1.1 Lock Block .............................................................................................64

13.1.2 Unlock Block ..........................................................................................64

13.1.3 Lock-Down Block ....................................................................................64

13.1.4 Block Lock Status ...................................................................................65

13.1.5 Block Locking During Suspend..................................................................65

13.2 Selectable One-Time Programmable Blocks ...........................................................66

13.3 Protection Registers ...........................................................................................66

13.3.1 Reading the Protection Registers...............................................................67

13.3.2 Programming the Protection Registers .......................................................68

13.3.3 Locking the Protection Registers ...............................................................68

14.0 Special Read States..................................................................................................69

14.1 Read Status Register..........................................................................................69

14.1.1 Clear Status Register ..............................................................................70

14.2 Read Device Identifier ........................................................................................70

14.3 CFI Query.........................................................................................................71

A

B

C

D

E

F

Write State Machine.................................................................................................72

Flowcharts...............................................................................................................79

Common Flash Interface..........................................................................................87

Additional Information.............................................................................................97

Ordering Information for Discrete Products .............................................................98

Ordering Information for SCSP Products..................................................................99

Datasheet

4

November 2007

Order Number: 306666-11

P30

Revision History

Revision Date

Revision

Description

April 2005

-001

Initial Release

Revised discrete memory maps in Section 4.4, “Memory Maps” on page 22

Added memory maps for 512-Mbit top parameter devices in Section 4.4, “Memory

Maps” on page 22

Fixed size of Programming Region for 256-Mbit to be 8-Mbit in Section 4.4, “Memory

Maps” on page 22 and Section 11.0, “Programming Operations” on page 56

August 2005

-002

Removed power supply sequencing requirement in Section 8.1, “Power-Up and Power-

Down” on page 41

Updated conditions for Table 15, “Capacitance” on page 29

Updated CFI table in Appendix C, “Common Flash Interface”

Added note to Table 34, “Device ID codes” on page 71 for stacked Device ID codes

Synchronous burst read operation is currently not supported for the TSOP package

Updated 512-Mbit Easy BGA Ball Height (symbol A1) in Figure 2, “Easy BGA Mechanical

Specifications” on page 11

September 2005

-003

November 2005

February 2006

-004

-005

Updated read access speed for 265M TSOP package

Removed all references to 1 Gigabit.

•

Added 52 MHz capabilities,

Added TSOP Package information for 512 Mb throughout the document,

Added Section 2.1, “Virtual Chip Enable Description” on page 8,

Modified figures in Section 4.3, “Dual-Die Configurations” on page 21,

Modified Table 9, “512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and

QUAD+ SCSP)” on page 23,

April 2006

-006

•

Modified Notes 5 & 6 to Reset Specifications table in Section 8.2, “Reset

Specifications” on page 41,

Added additional note on 512 Mb capability in Table 31, “Selectable OTP Block

Mapping” on page 66.

•

Updated the following tables to 52 MHz: Table 16, “AC Read Specifications for 64/

128- Mbit Densities” on page 29 and Table 17, “AC Read Specifications for 256/512-Mbit

Densities” on page 30.

May 2006

May-2006

-007

-008

•

Added notes 1, 2, and 3 to Table 15, “Capacitance” on page 29.

•

Correct typos and add clarifications

Enabled specific burst operation on TSOP packages.

Updated device commands table.

Updaed description on synchronous burst operation.

Added EOWL description.

June - 2007

-009

Updated flowcharts

•

Updated for 65nm lithography

Added W602 - Erase to Suspend

November 2007

-010

11

•

Applied Numonyx branding.

November 2007

Order Number: 306666-11

Datasheet

5

P30

1.0

Introduction

This document provides information about the Numonyx™ StrataFlash^®Embedded

Memory (P30) product and describes its features, operation, and specifications.

The Numonyx™ StrataFlash^®Embedded Memory (P30) product is the latest generation

of Numonyx™ StrataFlash^®memory devices. Offered in 64-Mbit up through 512-Mbit

densities, the P30 device brings reliable, two-bit-per-cell storage technology to the

embedded flash market segment. Benefits include more density in less space, high-

speed interface, lowest cost-per-bit NOR device, and support for code and data

storage. Features include high-performance synchronous-burst read mode, fast

asynchronous access times, low power, flexible security options, and three industry

standard package choices. The P30 product family is manufactured using Intel^*130 nm

ETOX™ VIII process technology.

The P30 product family is also planned on the Intel^*65nm process lithography. 65nm

AC timing changes are noted in this datasheet, and should be taken into account for all

new designs.

1.1

Nomenclature

1.8 V:

3.0 V:

9.0 V:

V_CC(core) voltage range of 1.7 V – 2.0 V

V_CCQ(I/O) voltage range of 1.7 V – 3.6 V

V_PPvoltage range of 8.5 V – 9.5 V

A group of bits, bytes, or words within the flash memory array that erase simultaneously

when the Erase command is issued to the device. The P30 has two block sizes: 32-KByte

and 128-KByte.

Block:

An array block that is usually used to store code and/or data. Main blocks are larger than

parameter blocks.

Main block:

An array block that is usually used to store frequently changing data or small system

parameters that traditionally would be stored in EEPROM.

Parameter block:

A device with its parameter blocks located at the highest physical address of its memory

map.

Top parameter device:

A device with its parameter blocks located at the lowest physical address of its memory

map.

Bottom parameter device:

1.2

Acronyms

BEFP:

CUI:

MLC:

OTP:

PLR:

PR:

Buffer Enhanced Factory Programming

Command User Interface

Multi-Level Cell

One-Time Programmable

Protection Lock Register

Protection Register

RCR:

Read Configuration Register

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November 2007

Order Number: 306666-11

P30

RFU:

Reserved for Future Use

Status Register

SR:

WSM:

Write State Machine

1.3

Conventions

VCC:

Signal or voltage connection

V_CC

0x:

0b:

:

Signal or voltage level

Hexadecimal number prefix

Binary number prefix

SR[4]:

A[15:0]:

A5:

Denotes an individual register bit.

Denotes a group of similarly named signals, such as address or data bus.

Denotes one element of a signal group membership, such as an individual address bit.

Bit:

Binary unit

Byte:

Eight bits

Word:

Kbit:

Two bytes, or sixteen bits

1024 bits

KByte:

KWord:

Mbit:

1024 bytes

1024 words

1,048,576 bits

1,048,576 bytes

1,048,576 words

MByte:

MWord:

November 2007

Order Number: 306666-11

Datasheet

7

P30

2.0

Functional Overview

This section provides an overview of the features and capabilities of the P30.

The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family

of devices provides high performance at low voltage on a 16-bit data bus. Individually

erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the Read Configuration Register enables synchronous burst-

mode reads. In synchronous burst mode, output data is synchronized with a user-

supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory

synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast factory program and erase operations. Designed for low-

voltage systems, the

P30 supports read operations with V_CCat 1.8 V, and erase and program operations with

V_PPat 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the

fastest flash array programming performance with V_PPat 9.0 V, which increases factory

throughput. With V_PPat 1.8 V, VCC and VPP can be tied together for a simple, ultra low

power design. In addition to voltage flexibility, a dedicated VPP connection provides

complete data protection when V_PP≤ V_PPLK

.

A Command User Interface (CUI) is the interface between the system processor and all

internal operations of the device. An internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for block erase and program. A Status

Register indicates erase or program completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each

erase operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

The P30 protection register allows unique flash device identification that can be used to

increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. In addition, the P30 device also has four pre-defined spaces in

the main array that can be configured as One-Time Programmable (OTP).

2.1

Virtual Chip Enable Description

The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit

die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and

TSOP packages. (Refer to Figure 9 on page 21 and Figure 10 on page 21). Address A24

(Quad+ package) or A25 (Easy BGA and TSOP packages) is then used to select

between the die pair with F1-CE# / CE# asserted depending upon the package option

used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (V_IL),

The lower parameter die is selected; when chip enable is asserted and QUAD+ A24

(Easy BGA/TSOP A25) is high (V_IH), the upper parameter die is selected. Refer to

Table 1 and Table 2 for additional details.

Table 1:

Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)

Die Selected

F1-CE#

A24

Lower Param Die

Upper Param Die

L

H

Datasheet

8

November 2007

Order Number: 306666-11

P30

Table 2:

Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages)

Die Selected

CE#

A25

Lower Param Die

Upper Param Die

L

H

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Order Number: 306666-11

Datasheet

9

P30

3.0

Package Information

3.1

56-Lead TSOP

Figure 1: TSOP Mechanical Specifications

Z

A

2

See Note 2

See Notes 1 and 3

Pin 1

e

See Detail B

E

Y

D

1

A

1

D

Seating

Plane

See Detail A

A

Detail A

Detail B

C

0

b

L

Table 3:

TSOP Package Dimensions (Sheet 1 of 2)

Millimeters

Nom

Inches

Nom

Product Information

Symbol

Notes

Min

Max

Min

Max

Package Height

Standoff

A

A₁

A₂

b

-

1.200

-

0.047

-

0.050

0.965

0.100

18.200

13.800

-

0.002

0.038

0.004

0.717

0.543

-

Package Body Thickness

Lead Width

0.995

0.150

18.400

14.000

0.500

20.00

1.025

0.200

18.600

14.200

-

0.039

0.006

0.724

0.551

0.0197

0.787

0.040

0.008

0.732

0.559

-

Lead Thickness

Package Body Length

Package Body Width

Lead Pitch

c

D₁

E

e

Terminal Dimension

D

19.800

20.200

0.780

0.795

Datasheet

10

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P30

Table 3:

TSOP Package Dimensions (Sheet 2 of 2)

Millimeters

Inches

Nom

Product Information

Symbol

Notes

Min

Nom

Max

Min

Max

Lead Tip Length

Lead Count

L

N

ý

0.500

0.600

56

0.700

-

0.020

0.024

56

0.028

-

0°

-

0°

Lead Tip Angle

3°

5°

3°

5°

Seating Plane Coplanarity

Lead to Package Offset

Notes:

Y

Z

-

0.100

0.350

-

0.004

0.014

0.150

0.250

0.006

0.010

1.

2.

3.

4.

One dimple on package denotes Pin 1.

If two dimples, then the larger dimple denotes Pin 1.

Pin 1 will always be in the upper left corner of the package, in reference to the product mark.

Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology

http://developer.Numonyx.com/design/flash/packtech.

3.2

64-Ball Easy BGA Package

Figure 2: Easy BGA Mechanical Specifications

Ball A1

Corner

Ball A1

Corner

D

S1

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

S2

A

B

C

D

E

F

A

B

C

D

E

F

b

e

E

G

H

G

H

Top View - Ball side down

A1

Bottom View - Ball Side Up

A2

A

Seating

Plane

Y

Note: Drawing not to scale

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Datasheet

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P30

Table 4:

Easy BGA Package Dimensions

Millimeters

Nom

Inches

Nom

Product Information

Symbol

Notes

Min

Max

Min

Max

Package Height (64/128/256-Mbit)

Package Height (512-Mbit)

Ball Height

A

-

1.200

1.300

-

0.0472

0.0512

-

A1

0.250

0.0098

Package Body Thickness (64/128/256-

Mbit)

A2

-

0.780

-

0.0307

-

Package Body Thickness (512-Mbit)

Ball (Lead) Width

A2

b

-

0.330

9.900

12.900

-

0.910

0.430

10.000

13.000

1.000

64

-

0.0358

0.0169

0.3937

0.5118

0.0394

64

-

0.530

10.100

13.100

-

0.0130

0.3898

0.5079

-

0.0209

0.3976

0.5157

-

Package Body Width

Package Body Length

Pitch

D

E

[e]

N

Ball (Lead) Count

-

Seating Plane Coplanarity

Corner to Ball A1 Distance Along D

Corner to Ball A1 Distance Along E

Notes:

Y

-

0.100

1.600

3.100

-

0.0039

0.0630

0.1220

S1

S2

1.400

2.900

1.500

3.000

0.0551

0.1142

0.0591

0.1181

1.

Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology

http://developer.Numonyx.com/design/flash/packtech.

Datasheet

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November 2007

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P30

3.3

QUAD+ SCSP Packages

Figure 3: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)

A1 Index

Mark

S₁

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

S₂

A

B

C

D

E

F

A

B

C

D

E

F

D

e

G

H

J

H

J

K

L

M

b

E

Top View - Ball

Down

Bottom View - Ball Up

A

A₂

A₁

Y

Drawing not to scale.

Millimeters

Nom

-

Inches

Nom

-

Dimens ions

Package Height

Ball Height

Package Body Thickness

Ball (Lead) Width

Package Body Width

Package Body Length

Pitch

Ball (Lead) Count

Seating Plane Coplanarity

Corner to Ball A1 Distance Along E

Corner to Ball A1 Distance Along D

S ymbol

A

Min

-

0.200

-

0.325

9.900

7.900

-

Max

1.200

-

Min

-

Max

0.0472

-

1

A

-

0.0079

-

0.0128

0.3898

0.3110

-

2

0.860

0.375

10.000

8.000

0.800

88

-

0.0339

0.0148

0.3937

0.3150

0.0315

88

-

b

D

E

e

N

Y

0.425

10.100

8.100

-

0.0167

0.3976

0.3189

-

0.100

1.300

0.700

-

0.0039

0.0512

0.0276

1

S

1.100

0.500

1.200

0.600

0.0433

0.0197

0.0472

0.0236

2

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Datasheet

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P30

Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm)

S1

A1 Index

Mark

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

S2

A

B

C

D

E

F

A

B

C

D

E

F

D

e

G

H

J

H

J

K

L

M

b

E

Bottom View - Ball Up

A

Top View - Ball Down

A2

A1

Y

Drawing not to scale.

Note: Dimensions A1, A2, and b are preliminary

Millimeters

Inches

Dimensions

Package Height

Ball Height

Package Body Thickness

Ball (Lead) Width

Package Body Length

Package Body Width

Pitch

Symbol

Min

Nom

-

0.740

0.350

11.00

8.00

0.80

88

Max

1.000

-

Min

-

Nom

-

0.0291

0.0138

0.4331

0.3150

0.0315

88

Max

0.0394

-

A

A1

A2

b

D

E

-

0.117

-

0.300

10.900

7.900

-

0.0046

-

0.0118

0.4291

0.3110

-

0.400

11.100

8.100

-

0.0157

0.4370

0.3189

-

e

N

Ball (Lead) Count

-

Seating Plane Coplanarity

Corner to Ball A1 Distance Along E

Corner to Ball A1 Distance Along D

Y

S1

S2

-

0.100

1.300

1.200

-

0.0039

0.0512

0.0472

1.100

1.000

1.200

1.100

0.0433

0.0394

0.0472

0.0433

Datasheet

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November 2007

Order Number: 306666-11

P30

Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)

S1

A1 Index

Mark

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

S2

A

B

C

D

E

F

A

B

C

D

E

F

D

e

G

H

J

H

J

K

L

M

b

E

Bottom View - Ball Up

A

Top View - Ball Down

A2

A1

Y

Drawing not to scale.

Millimeters

Nom

-

Inches

Nom

-

Dimensions

Package Height

Ball Height

Package Body Thickness

Ball (Lead) Width

Package Body Length

Package Body Width

Pitch

Symbol

Min

Max

1.200

-

Min

-

Max

0.0472

-

A

A1

A2

b

D

E

-

0.200

-

0.325

10.900

7.900

-

0.0079

-

0.0128

0.4291

0.3110

-

0.860

0.375

11.000

8.000

0.800

88

-

0.0339

0.0148

0.4331

0.3150

0.0315

88

-

0.425

11.100

8.100

-

0.0167

0.4370

0.3189

-

e

N

Ball (Lead) Count

-

Seating Plane Coplanarity

Corner to Ball A1 Distance Along E

Corner to Ball A1 Distance Along D

Y

S1

S2

-

0.100

1.300

1.200

-

0.0039

0.0512

0.0472

1.100

1.000

1.200

1.100

0.0433

0.0394

0.0472

0.0433

November 2007

Order Number: 306666-11

Datasheet

15

P30

4.0

Ballout and Signal Descriptions

4.1

Signal Ballout

Figure 6: 56-Lead TSOP Pinout (64/128/256/512- Mbit)

WAIT

A17

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

A16

A15

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

ADV#

CLK

A14

A13

A12

A11

A10

A9

A23

A22

A21

VSS

VCC

WE#

WP#

A20

A19

A18

A8

A7

A6

A5

A4

A3

A2

A24

A25

VSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Intel StrataFlash®

Embedded Memory (P30)

RST#

VPP

56-Lead TSOP Pinout

14 mm x 20 mm

DQ11

DQ3

DQ10

DQ2

VCCQ

DQ9

DQ1

DQ8

DQ0

VCC

OE#

Top View

VSS

CE#

A1

Notes:

1.

2.

3.

4.

5.

A1 is the least significant address bit.

A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).

A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).

A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).

Please refer to the latest specification update for synchronous read operation with the TSOP package. The synchronous read

^{input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See}Section 4.2, “Signal Descriptions”

on page 19.

Datasheet

16

November 2007

Order Number: 306666-11

P30

Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit)

5

8

5

1

2

3

4

6

7

6

4

3

2

1

A

B

C

D

A

B

C

D

E

A1

A6

A8

VPP A13 VCC A18 A22

A22 A18 VCC A13 VPP A8

RFU A19 A25 A14 CE# A9

A21 A20 WP# A15 A12 A10

A17 A16 VCCQ VCCQ RST# A11

A6

VSS

A7

A1

A2

A3

A4

A2 VSS

A9 CE# A14 A25 A19 RFU

A10 A12 A15 WP# A20 A21

A11 RST# VCCQ VCCQ A16 A17

A3

A4

A7

A5

E

F

DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU

RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#

A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE#

RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8

OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU

WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23

F

G

H

RFU VSS VCC VSS DQ13 VSS DQ7 A24

A24 DQ7 VSS DQ13 VSS VCC VSS RFU

Easy BGA

Top View- Ball side down

Bottom View- Ball side up

Notes:

1.

2.

3.

4.

A1 is the least significant address bit.

A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).

A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).

A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).

November 2007

Order Number: 306666-11

Datasheet

17

P30

Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout

Pin 1

1

DU

A4

2

3

4

5

6

7

8

DU

Depop

A19

Depop

VSS

Depop

VCC

RFU

Depop

VCC

CLK

RFU

A20

DU

A

B

C

D

E

F

A

B

C

D

E

F

A18

RFU

A17

A7

A21

A22

A9

A11

A5

A23

VSS

A12

A3

A24

VPP

RFU

A13

A2

RFU

DQ2

DQ1

WP#

RST#

DQ10

DQ3

ADV#

WE#

DQ5

A10

A14

WAIT

DQ7

A15

A1

A6

A8

A16

A0

DQ8

DQ0

DQ13

DQ14

F2-CE#

F2-OE#

G

H

G

H

RFU

DQ12

J

K

L

RFU

F1-CE#

VSS

DU

F1-OE#

RFU

VSS

DU

DQ9

RFU

VCCQ

Depop

3

DQ11

RFU

VCC

Depop

4

DQ4

RFU

VSS

Depop

5

DQ6

VCC

VSS

Depop

6

DQ15

VCCQ

VSS

DU

VCCQ

RFU

VSS

DU

J

K

L

M

1

2

7

8

Notes:

1.

2.

3.

4.

A22 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).

A23 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).

A24 is valid for 512-Mbit densities and above; otherwise, it is a no connect (NC).

F2-CE# and F2-OE# are no connect (NC) for all densities.

Datasheet

18

November 2007

Order Number: 306666-11

P30

4.2

Signal Descriptions

This section has signal descriptions for the various P30 packages.

Table 5:

TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit:

A[24:1]; 512-Mbit: A[25:1]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the

dual-die 512-Mbit configuration is accomplished by setting A[25] high (V_IH).

A[MAX:1]

DQ[15:0]

Input

DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float

when the CE# or OE# are deasserted. Data is internally latched during writes.

Input/

Output

ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on

the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

ADV#

Input

In asynchronous mode, the address is latched when ADV# going high or continuously flows through

if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When

deasserted, the associated flash die is deselected, power is reduced to standby levels, data and

WAIT outputs are placed in high-Z state.

CE#

CLK

Input

WARNING: Chip enable must be driven high when device is not in use.

CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During

synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid

CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

OE#

Input

cycles. OE# high places the data outputs and WAIT in High-Z.

RESET: Active low input. RST# resets internal automation and inhibits write operations. This

provides data protection during power transitions. RST# high enables normal operation. Exit from

reset places the device in asynchronous read array mode.

RST#

WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration

Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V_OLor

V_OHwhen CE# and OE# are V_IL. WAIT is high-Z if CE# or OE# is V_IH

.

WAIT

Output

•

In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and

valid data when deasserted.

•

In asynchronous page mode, and all write modes, WAIT is deasserted.

WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched

on the rising edge of WE#.

WE#

WP#

Input

WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory

contents cannot be altered when V_PP≤ V_PPLK. Block erase and program at invalid V_PPvoltages should

not be attempted.

Set V_PP= V_PPLfor in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, the V_IHlevel of V_PPcan be as low as V_PPLmin. V_PPmust remain above V_PPL

min to perform in-system flash modification. VPP may be 0 V during read operations.

Power/

Input

VPP

V_PPHcan be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500

cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycling capability.

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited

when V_CC≤ V_LKO. Operations at invalid V_CCvoltages should not be attempted.

VCC

Power

VCCQ

VSS

Power

Output Power Supply: Output-driver source voltage.

Ground: Connect to system ground. Do not float any VSS connection.

November 2007

Order Number: 306666-11

Datasheet

19

P30

Table 5:

TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)

Symbol

Type

Name and Function

Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.

These should be treated in the same way as a Do Not Use (DU) signal.

RFU

—

DU

NC

—

Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

No Connect: No internal connection; can be driven or floated.

Table 6:

QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit:

A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the

dual-die 512-Mbit configuration is accomplished by setting A[25] high (V_IH).

A[MAX:0]

DQ[15:0]

Input

DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float

when the CE# or OE# are deasserted. Data is internally latched during writes.

Input/

Output

ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on

the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

ADV#

Input

In asynchronous mode, the address is latched when ADV# going high or continuously flows through

if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When

deasserted, the associated flash die is deselected, power is reduced to standby levels, data and

WAIT outputs are placed in high-Z state.

F1-CE#

CLK

Input

WARNING: Chip enable must be driven high when device is not in use.

CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During

synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid

CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high places the data outputs and WAIT in High-Z.

F1-OE#

RST#

Input

RESET: Active low input. RST# resets internal automation and inhibits write operations. This

provides data protection during power transitions. RST# high enables normal operation. Exit from

reset places the device in asynchronous read array mode.

WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration

Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V_OLor

V_OHwhen CE# and OE# are V_IL. WAIT is high-Z if CE# or OE# is V_IH

.

WAIT

Output

•

In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and

valid data when deasserted.

In asynchronous page mode, and all write modes, WAIT is deasserted.

WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched

WE#

WP#

Input

on the rising edge of WE#.

WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory

contents cannot be altered when V_PP≤ V_PPLK. Block erase and program at invalid V_PPvoltages should

not be attempted.

Set V_PP= V_PPLfor in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, the V_IHlevel of V_PPcan be as low as V_PPLmin. V_PPmust remain above V_PPL

min to perform in-system flash modification. VPP may be 0 V during read operations.

Power/

lnput

VPP

V_PPHcan be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500

cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycling capability.

Datasheet

20

November 2007

Order Number: 306666-11

P30

Table 6:

QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)

Symbol

Type

Name and Function

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited

when V_CC≤ V_LKO. Operations at invalid V_CCvoltages should not be attempted.

VCC

Power

VCCQ

VSS

Power

Output Power Supply: Output-driver source voltage.

Ground: Connect to system ground. Do not float any VSS connection.

Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.

These should be treated in the same way as a Do Not Use (DU) signal.

RFU

—

DU

NC

—

Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

No Connect: No internal connection; can be driven or floated.

4.3

Dual-Die Configurations

Figure 9: 512-Mbit Easy BGA and TSOP Top or Bottom Parameter Block Diagram

Easy BGA & TSOP 512-Mbit (Dual-Die) Top or Bottom Parameter

Configuration

CE#

Top Param Die

RST#

WP#

OE#

WE#

(256-Mbit)

VCC

VPP

VCCQ

VSS

CLK

ADV#

Bottom Param Die

(256-Mbit)

DQ[15:0]

WAIT

A[MAX:1]

Figure 10: 512-Mbit QUAD+ SCSP Top or Bottom Parameter Block Diagram

QUAD+ 512-Mbit (Dual-Die) Top or Bottom Parameter

Configuration

F1-CE#

Top Param Die

RST#

WP#

OE#

WE#

(256-Mbit)

VCC

VPP

VCCQ

VSS

CLK

ADV#

Bottom Param Die

(256-Mbit)

DQ[15:0]

WAIT

A[MAX:0]

Note: A_max= V_ihselects the Top parameter Die; A_max= V_ilselects the Bottom Parameter Die.

November 2007

Order Number: 306666-11

Datasheet

21

P30

4.4

Memory Maps

Table 7 through Table 9 show the P30 memory maps. The memory array is divided into

multiple 8-Mbit Programming Regions (see Section 11.0, “Programming Operations” on

page 56).

Table 7:

Discrete Top Parameter Memory Maps (all packages)

Size

(KB)

Size

(KB)

Blk

64-Mbit

Blk

128-Mbit

32

66

3FC000 - 3FFFFF

32

130

7FC000 - 7FFFFF

32

63

62

3F0000 - 3F3FFF

3E0000 - 3EFFFF

32

127

126

7F0000 - 7F3FFF

7E0000 - 7EFFFF

128

56

55

54

380000 - 38FFFF

370000 - 37FFFF

360000 - 36FFFF

128

120

119

118

780000 - 78FFFF

770000 - 77FFFF

760000 - 76FFFF

128

1

0

010000 - 01FFFF

000000 - 00FFFF

128

1

0

010000 - 01FFFF

000000 - 00FFFF

Size

(KB)

Blk

256-Mbit

32

258

FFC000 - FFFFFF

32

255

254

FF0000 - FF3FFF

FE0000 - FEFFFF

128

248

247

246

F80000 - F8FFFF

F70000 - F7FFFF

F60000 - F6FFFF

128

1

0

010000 - 01FFFF

000000 - 00FFFF

Table 8:

Discrete Bottom Parameter Memory Maps (all packages)

Size

(KB)

Size

(KB)

Blk

64-Mbit

Blk

128-Mbit

128

66

65

3F0000 - 3FFFFF

3E0000 - 3EFFFF

128

130

129

7F0000 - 7FFFFF

7E0000 - 7EFFFF

128

12

11

090000 - 09FFFF

080000 - 08FFFF

128

12

11

090000 - 09FFFF

080000 - 08FFFF

Datasheet

22

November 2007

Order Number: 306666-11

P30

Table 8:

Discrete Bottom Parameter Memory Maps (all packages)

Size

(KB)

Size

(KB)

Blk

64-Mbit

Blk

128-Mbit

128

10

070000 - 07FFFF

128

10

070000 - 07FFFF

128

32

4

3

010000 - 01FFFF

00C000 - 00FFFF

128

32

4

3

010000 - 01FFFF

00C000 - 00FFFF

32

0

000000 - 003FFF

32

0

000000 - 003FFF

Size

(KB)

Blk

256-Mbit

128

258

257

FF0000 - FFFFFF

FE0000 - FEFFFF

128

12

11

10

090000 - 09FFFF

080000 - 08FFFF

070000 - 07FFFF

128

32

4

3

010000 - 01FFFF

00C000 - 00FFFF

32

0

000000 - 003FFF

Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-

Words where a Word is the size of the flash output bus (16 bits).

Note: The Dual- Die P30 memory maps are the same for both parameter options because the

devices employ virtual chip enable (Refer to Section 2.1). The parameter option only defines

the placement of bottom parameter die.

Table 9:

512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP)

(Sheet 1 of 2)

512-Mbit Flash (2x256-Mbit w/ 1CE)

Size

(KB)

Die Stack Config

Blk

Address Range

32

517

1FFC000 - 1FFFFFF

256-Mbit

32

514

513

1FF0000 - 1FF3FFF

1FE0000 - 1FEFFFF

Top Parameter Die

128

259

258

1000000 - 100FFFF

FF0000 - FFFFFF

November 2007

Order Number: 306666-11

Datasheet

23

P30

Table 9:

512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP)

(Sheet 2 of 2)

512-Mbit Flash (2x256-Mbit w/ 1CE)

Size

(KB)

Die Stack Config

Blk

Address Range

256-Mbit

128

32

4

3

010000 - 01FFFF

00C000 - 00FFFF

Bottom Parameter Die

32

0

000000 - 003FFF

Note: Refer to the appropriate 256-Mbit Memory Map (Table 7 or Table 8) for Programming Region information; Block size

is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of

the flash output bus (16 bits).

Datasheet

24

November 2007

Order Number: 306666-11

P30

5.0

Maximum Ratings and Operating Conditions

5.1

Absolute Maximum Ratings

Warning:

Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent

damage. These are stress ratings only.

Table 10:

Parameter

Maximum Rating

Notes

Temperature under bias

Storage temperature

–40 °C to +85 °C

–65 °C to +125 °C

–0.5 V to +4.1 V

–0.2 V to +10 V

–0.2 V to +2.5 V

–0.2 V to +4.1 V

100 mA

Voltage on any signal (except V_CC, VPP and VCCQ)

1

VPP voltage

1,2,3

VCC voltage

1

4

VCCQ voltage

Output short circuit current

Notes:

1.

Voltages shown are specified with respect to V_SS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on

V_CC, V_CCQ, and V_PP. During transitions, this level may undershoot to –2.0 V for periods less than 20 ns. Maximum DC

voltage on V_CCis V_CC+ 0.5 V, which, during transitions, may overshoot to V_CC+ 2.0 V for periods less than 20 ns.

Maximum DC voltage on input/output signals and V_CCQis V_CCQ+ 0.5 V, which, during transitions, may overshoot to

V_CCQ+ 2.0 V for periods less than 20 ns.

2.

3.

Maximum DC voltage on V_PPmay overshoot to +11.5 V for periods less than 20 ns.

Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for

1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.

4.

Output shorted for no more than one second. No more than one output shorted at a time.

5.2

Operating Conditions

Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure

beyond the “Operating Conditions” may affect device reliability.

Table 11: Operating Conditions

Symbol

Parameter

Min

Max

Units

Notes

T_C

Operating Temperature

V_CCSupply Voltage

–40

+85

2.0

3.6

9.5

80

°C

1

3

V_CC

1.7

CMOS inputs

TTL inputs

1.7

V_CCQ

I/O Supply Voltage

2.4

V

V_PPL

V_PPH

t_PPH

V_PPVoltage Supply (Logic Level)

Factory word programming V_PP

Maximum V_PPHours

0.9

8.5

V_PP= V_PPH

V_PP= V_PPL

V_PP= V_PPH

-

Hours

Cycles

2

Main and Parameter Blocks

Main Blocks

100,000

-

Block

Erase

Cycles

-

1000

2500

Parameter Blocks

Notes:

1.

2.

3.

T

_C= Case Temperature.

In typical operation VPP program voltage is V_PPL

.

40Mhz burst operation on the TSOP package has a min V_ccvalue of 1.85V. Please refer to the latest Specification Update

regarding synchronous burst operation with the TSOP package

November 2007

Order Number: 306666-11

Datasheet

25

P30

6.0

Electrical Specifications

6.1

DC Current Characteristics

Table 12: DC Current Characteristics (Sheet 1 of 2)

CMOS

TTL Inputs

Inputs

(V_CCQ

2.4 V - 3.6

V)

=

(V_CCQ

1.7 V - 3.6

V)

=

Sym

Parameter

Unit

Test Conditions

Notes

Typ

Max

Typ

Max

V_CC= V_CCMax

V_CCQ= V_CCQMax

V_IN= V_CCQor V_SS

I_LI

Input Load Current

-

±1

-

±2

µA

1

Output

V_CC= V_CCMax

V_CCQ= V_CCQMax

V_IN= V_CCQor V_SS

I_LO

Leakage

Current

DQ[15:0],

-

±1

-

±10

WAIT

64-Mbit

20

30

35

75

20

30

35

75

V_CC= V_CCMax

V_CCQ= V_CCQMax

CE# = V_CCQ

RST# = V_CCQ(for I_CCS

RST# = V_SS(for I_CCD

WP# = V_IH

128-Mbit

256-Mbit

512-Mbit

I_CCS

I_CCD

,

V_CCStandby,

Power Down

µA

1,2

)

55

115

230

55

200

400

)

110

Asynchronous Single-

Word f = 5 MHz (1 CLK)

14

9

16

10

14

9

16

10

mA

1-Word Read

Page-Mode Read

f = 13 MHz (5 CLK)

4-Word Read

BL = 4W

13

15

17

21

16

19

22

23

36

26

20

30

55

110

17

19

21

26

19

23

26

28

51

33

35

75

115

230

n/a

36

n/a

51

mA

Average

V_CC

V_CC= V_CCMax

CE# = V_IL

OE# = V_IH

Inputs: V_ILor

V_IH

BL = 8W

Synchronous Burst

f = 40 MHz

I_CCR

Read

1

BL = 16W

BL = Cont.

BL = 4W

Current

BL = 8W

Synchronous Burst

f = 52MHz

BL = 16W

BL = Cont.

V_PP= V_PPL, pgm/ers in progress

V_PP= V_PPH, pgm/ers in progress

1,3,5

I_CCW,

I_CCE

V_CCProgram Current,

V_CCErase Current

mA

26

33

64-Mbit

128-Mbit

256-Mbit

512-Mbit

20

35

V_CCProgram Suspend

30

75

I_CCWS,Current,

CE# = V_CCQ; suspend in

progress

µA

1,3,4

I_CCES

V_CCErase

55

200

400

Suspend Current

110

I_PPS,

V_PPStandby Current,

I_PPWS,V_PPProgram Suspend Current,

0.2

5

0.2

5

µA

V_PP= V_PPL, suspend in progress

1,3

V_PPErase Suspend Current

IPPES

I_PPR

V_PPRead

2

0.05

8

15

0.10

22

2

0.05

8

15

0.10

22

µA

V_PP= V_PPL

V_PP= V_PPL,program in progress

V_PP= V_PPH,program in progress

I_PPW

V_PPProgram Current

mA

Datasheet

26

November 2007

Order Number: 306666-11

P30

Table 12: DC Current Characteristics (Sheet 2 of 2)

CMOS

TTL Inputs

Inputs

(V_CCQ

2.4 V - 3.6

V)

=

(V_CCQ

1.7 V - 3.6

V)

=

Sym

Parameter

Unit

Test Conditions

Notes

Typ

Max

Typ

Max

0.05

8

0.10

22

0.05

8

0.10

22

V_PP= V_PPL,erase in progress

I_PPE

V_PPErase Current

mA

V

_PP= V_PPH,erase in progress

Notes:

1.

2.

3.

4.

5.

All currents are RMS unless noted. Typical values at typical V_CC, T_C= +25 °C.

I_CCSis the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.

Sampled, not 100% tested.

I_CCESis specified with the device deselected. If device is read while in erase suspend, current is I_CCESplus I_CCR

I_CCW, I_CCEmeasured over typical or max times specified in Section 7.5, “Program and Erase

Characteristics” on page 39.

.

6.2

DC Voltage Characteristics

Table 13: DC Voltage Characteristics

(1)

CMOS Inputs

(VCCQ = 1.7 V – 3.6 V)

TTL Inputs

(VCCQ = 2.4 V – 3.6 V)

Sym

Parameter

Unit

Test Condition

Notes

Min

Max

Min

Max

V_IL

Input Low Voltage

Input High Voltage

0

0.4

0

0.6

V

2

V_IH

V_CCQ– 0.4 V

V_CCQ

2.0

V_CCQ

V_CC= V_CCMin

V_CCQ= V_CCQMin

I_OL= 100 µA

V_OL

Output Low Voltage

Output High Voltage

-

0.1

-

0.1

-

V

V_CC= V_CCMin

V_CCQ= V_CCQMin

I_OH= –100 µA

V_OH

V_CCQ– 0.1

V_PPLK

V_LKO

V_PPLock-Out Voltage

V_CCLock Voltage

-

0.4

-

0.4

V

3

1.0

0.9

-

1.0

0.9

-

V_LKOQ

V_CCQLock Voltage

Notes:

1.

2.

3.

Synchronous read mode is not supported with TTL inputs.

V_ILcan undershoot to –0.4 V and V_IHcan overshoot to V_CCQ+ 0.4 V for durations of 20 ns or less.

V_PP≤ V_PPLKinhibits erase and program operations. Do not use V_PPLand V_{PPH outside their valid ranges.}

November 2007

Order Number: 306666-11

Datasheet

27

P30

7.0

AC Characteristics

7.1

AC Test Conditions

Figure 11: AC Input/Output Reference Waveform

V_CCQ

Input V_CCQ/2

Test Points

V_CCQ/2 Output

0V

IO_REF.WMF

Note: AC test inputs are driven at V_CCQfor Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at V_CCQ/2. Input rise

and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V_CC= V_CCMin.

Figure 12: Transient Equivalent Testing Load Circuit

Device

Out

Under Test

C_L

Notes:

1.

2.

See the following table for component values.

Test configuration component value for worst-case speed conditions.

C_Lincludes jig capacitance.

3.

.

Table 14: Test Configuration Component Value For Worst Case Speed Conditions

Test Configuration

_CCQMin Standard Test

C_L(pF)

V

30

Figure 13: Clock Input AC Waveform

R201

V_IH

CLK [C]

V_IL

R202

R203

Datasheet

28

November 2007

Order Number: 306666-11

P30

7.2

Capacitance

Table 15: Capacitance

Parameter

Signals

Min

Typ

Max

Unit

Condition

Notes

Address, Data,

CE#, WE#, OE#,

RST#, CLK, ADV#,

WP#

Typ temp = 25 °C,

Max temp = 85 °C,

V_CC= (0 V - 2.0 V),

V_CCQ= (0 V - 3.6 V),

Discrete silicon die

Input Capacitance

Output Capacitance

2

6

4

7

5

pF

1,2,3

Data, WAIT

Notes:

1.

Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of

dies in the stack.

2.

3.

Sampled, but not 100% tested.

Silicon die capacitance only; add 1 pF for discrete packages.

7.3

AC Read Specifications

Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 1 of 2)

Num

Symbol

Parameter

Min

Max

Unit

Notes

Asynchronous Specifications

R1

R2

R3

R4

R5

R6

R7

R8

R9

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_PHQV

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

Read cycle time

85

-

85

25

150

-

ns

Address to output valid

CE# low to output valid

OE# low to output valid

-

1,2

1

RST# high to output valid

CE# low to output in low-Z

OE# low to output in low-Z

CE# high to output in high-Z

OE# high to output in high-Z

-

0

-

1,3

1,2,3

-

24

-

1,3

Output hold from first occurring address, CE#, or

OE# change

R10

t_OH

0

-

ns

R11

R12

R13

R15

t_EHEL

t_ELTV

t_EHTZ

t_GLTV

CE# pulse width high

20

-

ns

1

CE# low to WAIT valid

CE# high to WAIT high-Z

OE# low to WAIT valid

OE# low to WAIT in low-Z

OE# high to WAIT in high-Z

17

20

17

-

1,3

1

-

R16

R17

t_GLTX

t_GHTZ

0

-

1,3

20

Latching Specifications

R101

R102

R103

R104

R105

R106

t_AVVH

t_ELVH

t_VLQV

t_VLVH

t_VHVL

t_VHAX

Address setup to ADV# high

CE# low to ADV# high

10

-

ns

ADV# low to output valid

ADV# pulse width low

85

-

1

10

9

ADV# pulse width high

Address hold from ADV# high

-

1,4

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Datasheet

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P30

Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2)

Num

Symbol

Parameter

Min

Max

Unit

Notes

R108

R111

t_APA

t_phvh

Page address access

-

25

-

ns

1

RST# high to ADV# high

30

Clock Specifications

-

52

40

-

MHz

ns

R200

R201

f_CLK

CLK frequency

CLK period

TSOP

19.2

25

5

t_CLK

1,3,5,6

-

ns

R202

R203

t_CH/CL

CLK high/low time

CLK fall/rise time

-

ns

t_FCLK/RCLK

-

3

ns

Synchronous Specifications^(5,6)

R301

R302

R303

R304

R305

R306

R307

R311

R312

t_AVCH/L

t_VLCH/L

t_ELCH/L

t_{CHQV / tCLQV}

t_CHQX

Address setup to CLK

ADV# low setup to CLK

CE# low setup to CLK

CLK to output valid

9

-

ns

1

9

-

17

-

Output hold from CLK

Address hold from CLK

CLK to WAIT valid

3

1,7

1,4,7

1,7

1

t_CHAX

10

-

t_CHTV

17

-

t_CHVL

CLK Valid to ADV# Setup

WAIT Hold from CLK

3

t_CHTX

3

-

1,7

Notes:

1.

See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max

allowable input slew rate.

2.

3.

4.

5.

6.

7.

OE# may be delayed by up to t_ELQV– t_GLQVafter CE#’s falling edge without impact to t_ELQV.

Sampled, not 100% tested.

Address hold in synchronous burst mode is t_CHAXor t_VHAX, whichever timing specification is satisfied first.

Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.

Synchronous read mode is not supported with TTL level inputs.

Applies only to subsequent synchronous reads.

Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3)

Num

Symbol

Parameter

Speed

Min

Max

Unit

Notes

Asynchronous Specifications

V_CC= 1.8 V – 2.0

85

88

95

-

V

V_CC= 1.7 V – 2.0

V

R1

R2

t_AVAV

Read cycle time

ns

256/512-Mb TSOP

packages

V_CC= 1.8 V – 2.0

V

85

88

95

V_CC= 1.7 V – 2.0

V

t_AVQV

Address to output valid

-

ns

256/512-Mb TSOP

packages

-

Datasheet

30

November 2007

Order Number: 306666-11

P30

Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 2 of 3)

Num

Symbol

Parameter

Speed

Min

Max

Unit

Notes

V_CC= 1.8 V – 2.0

V

-

85

V_CC= 1.7 V – 2.0

R3

t_ELQV

CE# low to output valid

-

88

95

ns

V

256/512-Mb TSOP

packages

R4

R5

R6

R7

R8

R9

t_GLQV

t_PHQV

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

OE# low to output valid

-

25

150

-

ns

1,2

1

RST# high to output valid

CE# low to output in low-Z

OE# low to output in low-Z

CE# high to output in high-Z

OE# high to output in high-Z

0

-

1,3

1,2,3

-

24

-

1,3

Output hold from first occurring address, CE#, or OE#

change

R10

t_OH

0

-

ns

R11

R12

R13

R15

t_EHEL

t_ELTV

t_EHTZ

t_GLTV

CE# pulse width high

20

-

ns

1

CE# low to WAIT valid

CE# high to WAIT high-Z

OE# low to WAIT valid

OE# low to WAIT in low-Z

OE# high to WAIT in high-Z

17

20

17

-

1,3

1

-

R16

R17

t_GLTX

t_GHTZ

0

-

1,3

20

Latching Specifications

R101

R102

t_AVVH

t_ELVH

Address setup to ADV# high

CE# low to ADV# high

10

-

ns

V

_CC= 1.8 V – 2.0

-

85

88

95

V

V_CC= 1.7 V – 2.0

V

R103

t_VLQV

ADV# low to output valid

ns

1

256/512-Mb TSOP

packages

R104

R105

R106

R108

R111

t_VLVH

t_VHVL

t_VHAX

t_APA

ADV# pulse width low

ADV# pulse width high

Address hold from ADV# high

Page address access

10

9

-

ns

-

1,4

1

-

25

-

t_phvh

RST# high to ADV# high

30

Clock Specifications

-

52

40

-

MHz

ns

1,3,5,6

R200

R201

f_CLK

CLK frequency

CLK period

TSOP Package

19.2

25

5

t_CLK

-

ns

R202

R203

t_CH/CL

CLK high/low time

CLK fall/rise time

-

ns

t_FCLK/RCLK

-

3

ns

Synchronous Specifications^(5,6)

November 2007

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Datasheet

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P30

Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 3 of 3)

Num

R301

Symbol

t_AVCH/L

Parameter

Address setup to CLK

Speed

Min

Max

Unit

Notes

9

-

ns

R302

R303

R304

R305

R306

R307

R311

R312

t_VLCH/L

t_ELCH/L

t_{CHQV / tCLQV}

t_CHQX

ADV# low setup to CLK

CE# low setup to CLK

CLK to output valid

1

9

-

17

-

Output hold from CLK

Address hold from CLK

CLK to WAIT valid

3

1,7

1,4,7

1,7

1

t_CHAX

10

-

t_CHTV

17

-

t_CHVL

CLK Valid to ADV# Setup

WAIT Hold from CLK

3

t_CHTX

3

-

1,7

Notes:

1.

See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max

allowable input slew rate.

2.

3.

4.

5.

6.

7.

OE# may be delayed by up to t_ELQV– t_GLQVafter CE#’s falling edge without impact to t_ELQV.

Sampled, not 100% tested.

Address hold in synchronous burst mode is t_CHAXor t_VHAX, whichever timing specification is satisfied first.

Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.

Synchronous read mode is not supported with TTL level inputs.

Applies only to subsequent synchronous reads.

Table 18: AC Read Specification differences for 65nm

Num

Symbol

Parameter

Min

Max

Unit

Notes

Asynchronous Specifications

100

110

-

ns

2

R1

R2

t_AVAV

t_AVQV

t_ELQV

Read cycle time

TSOP

100

110

100

110

100

110

2

Address to output valid

2

-

2

R3

CE# low to output valid

t_VLQV

2

1,2

2

R103

ADV# low to output valid

Notes:

1.

See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and

max allowable input slew rate.

2.

This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs

that will use the 65nm lithography.

Datasheet

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P30

Figure 14: Asynchronous Single-Word Read (ADV# Low)

R1

R2

Address [A]

ADV#

R3

R8

CE# [E}

R4

R9

OE# [G]

R15

R17

WAIT [T]

R7

R6

Data [D/Q]

R5

RST# [P]

Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

Figure 15: Asynchronous Single-Word Read (ADV# Latch)

R1

R2

Address [A]

A[1:0][A]

R101

R105

R106

ADV#

CE# [E}

OE# [G]

WAIT [T]

R3

R8

R4

R9

R15

R17

R7

R6

R10

Data [D/Q]

Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

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Figure 16: Asynchronous Page-Mode Read Timing

R1

R2

A[Max:2] [A]

A[1:0]

R101

R105

R106

ADV#

CE# [E]

R3

R8

R4

R10

OE# [G]

R15

R17

WAIT [T]

R7

R9

R108

DATA [D/Q]

Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).

Figure 17: Synchronous Single-Word Array or Non-array Read Timing

R301

R306

CLK [C]

R2

Address [A]

R101

R104

R106

R105

ADV# [V]

R303

R102

R3

R8

CE# [E]

OE# [G]

WAIT [T]

R7

R9

R15

R307

R304

R17

R312

R4

R305

Data [D/Q]

1.

2.

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either

during or one data cycle before valid data.

This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by

CE# deassertion after the first word in the burst.

Datasheet

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November 2007

Order Number: 306666-11

P30

Figure 18: Continuous Burst Read, Showing An Output Delay Timing

R301

R302

R306

R304

CLK [C]

Address [A]

ADV# [V]

R2

R101

R106

R105

R303

R102

R3

CE# [E]

OE# [G]

R15

R307

R304

R312

WAIT [T]

R4

R7

R305

Data [D/Q]

Notes:

1.

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either

during or one data cycle before valid data.

At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is

not 4-word boundary aligned.

2.

Figure 19: Synchronous Burst-Mode Four-Word Read Timing

R302

R301

R306

CLK [C]

Address [A]

ADV# [V]

R2

R101

A

R105

R102

R106

R303

R3

R8

CE# [E]

OE# [G]

WAIT [T]

R9

R15

R17

R307

R4

R304

R305

Q0

R7

R304

R10

Data [D/Q]

Q1

Q2

Q3

Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and

deasserted during valid data (RCR[10] = 0, Wait asserted low).

November 2007

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Datasheet

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P30

7.4

AC Write Specifications

Table 19: AC Write Specifications

Num

W1

Symbol

t_PHWL

Parameter

Min

Max

Unit

Notes

RST# high recovery to WE# low

CE# setup to WE# low

150

-

ns

1,2,3

1,2,4

W2

t_ELWL

0

W3

t_WLWH

t_DVWH

t_AVWH

t_WHEH

t_WHDX

t_WHAX

t_WHWL

t_VPWH

t_QVVL

WE# write pulse width low

Data setup to WE# high

Address setup to WE# high

CE# hold from WE# high

Data hold from WE# high

Address hold from WE# high

WE# pulse width high

50

W4

50

W5

50

W6

0

1,2

W7

0

W8

0

W9

20

1,2,5

W10

W11

W12

W13

W14

W16

V_PPsetup to WE# high

200

1,2,3,7

V_PPhold from Status read

WP# hold from Status read

WP# setup to WE# high

WE# high to OE# low

0

t_QVBL

0

200

t_BHWH

t_WHGL

t_WHQV

0

1,2,9

WE# high to read valid

t_AVQV+ 35

1,2,3,6,10

Write to Asynchronous Read Specifications

W18 t_WHAVWE# high to Address valid

Write to Synchronous Read Specifications

0

-

ns

1,2,3,6,8

W19

W20

t_WHCH/L

t_WHVH

WE# high to Clock valid

WE# high to ADV# high

19

-

ns

1,2,3,6,10

Write Specifications with Clock Active

W21

W22

t_VHWL

t_CHWL

ADV# high to WE# low

Clock high to WE# low

-

20

ns

1,2,3,11

Notes:

1.

2.

3.

4.

Write timing characteristics during erase suspend are the same as write-only operations.

A write operation can be terminated with either CE# or WE#.

Sampled, not 100% tested.

Write pulse width low (t_WLWHor t_ELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high

(whichever occurs first). Hence, t_WLWH= t_ELEH= t_WLEH= t_ELWH

.

5.

Write pulse width high (t_WHWLor t_EHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low

(whichever occurs last). Hence, t_WHWL= t_EHEL= t_WHEL= t_EHWL).

6.

7.

8.

t_WHVHor t_WHCH/Lmust be met when transitioning from a write cycle to a synchronous burst read.

V_PPand WP# should be at a valid level until erase or program success is determined.

This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and

W20 for synchronous read.

When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.

Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect

this change.

9.

10.

11.

These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.

Datasheet

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P30

Figure 20: Write-to-Write Timing

W5

W8

W5

W8

Address [A]

W2

W6

W2

W6

CE# [E}

W3

W9

W3

WE# [W]

OE# [G]

W4

W7

W4

W7

Data [D/Q]

W1

RST# [P]

Figure 21: Asynchronous Read-to-Write Timing

R1

R2

W5

W8

Address [A]

R3

R8

R9

CE# [E}

R4

OE# [G]

W2

W3

W6

WE# [W]

R15

R17

WAIT [T]

R7

R6

W7

R10

W4

Data [D/Q]

RST# [P]

Q

D

R5

Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.

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Figure 22: Write-to-Asynchronous Read Timing

W5

W8

R1

Address [A]

ADV# [V]

W2

W6

R10

CE# [E}

WE# [W]

OE# [G]

WAIT [T]

W3

W18

W14

R15

R17

R4

R2

R3

R8

W4

W7

R9

Data [D/Q]

RST# [P]

D

Q

W1

Figure 23: Synchronous Read-to-Write Timing

Latency Count

R301

R302

R306

CLK [C]

R2

W5

R101

W18

Address [A]

R105

R102

R106

R104

ADV# [V]

R303

R11

R13

R3

W6

CE# [E]

OE# [G]

R4

R8

W21

W22

W21

W22

W2

W8

W15

W3

W9

WE#

R16

R307

R304

R312

WAIT [T]

R7

R305

W7

Q

D

Data [D/Q]

Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is

ignored during write operation.

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Figure 24: Write-to-Synchronous Read Timing

R302

R301

R2

CLK

W5

W8

R306

R106

Address [A]

R104

R303

ADV#

W6

W2

R11

CE# [E}

W18

W19

W20

W3

WE# [W]

OE# [G]

WAIT [T]

R4

R15

R3

R307

W7

R304

R305

R304

W4

D

Q

Data [D/Q]

RST# [P]

W1

Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low).

7.5

Program and Erase Characteristics

Table 20:

V_PPL

V_PPH

Typ

Num

Symbol

Parameter

Units

Notes

Min

Typ

Max

Min

Max

Conventional Word Programming

Single word - 130nm

Single word - 65nm

Single cell

-

90

125

30

200

150

60

-

85

125

30

190

150

60

Program

Time

W200

t_PROG/W

µs

1

Buffered Programming

W200

W251

t_PROG/W

t_BUFF

Single word

-

90

440

200

880

-

85

190

680

Program

Time

µs

32-word buffer

340

Buffered Enhanced Factory Programming

W451

W452

t_BEFP/W

Single word

BEFP Setup

n/a

-

10

-

1,2

1

Program

t_BEFP/Setup

5

Erasing and Suspending

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Table 20:

V_PPL

Typ

V_PPH

Typ

Num

Symbol

Parameter

Units

Notes

Min

Max

Min

Max

W500

W501

W600

W601

W602

t_ERS/PB

t_ERS/MB

t_SUSP/P

t_SUSP/E

t_ERS/SUSP

32-KByte Parameter

128-KByte Main

Program suspend

Erase suspend

-

0.4

1.2

20

2.5

4.0

25

-

0.4

1.0

20

2.5

4.0

25

-

Erase Time

s

1

Suspend

Latency

20

µs

Erase to Suspend

500

1,3

Notes:

1.

Typical values measured at T_C= +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system

overhead. Sampled, but not 100% tested.

2.

3.

Averaged over entire device.

W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend

command. Violating the specification repeatedly during any particular block erase may cause erase failures.

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8.0

Power and Reset Specifications

8.1

Power-Up and Power-Down

Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise

V_CCand V_CCQshould attain their minimum operating voltage before applying V_PP.

Power supply transitions should only occur when RST# is low. This protects the device

from accidental programming or erasure during power transitions.

8.2

Reset Specifications

Asserting RST# during a system reset is important with automated program/erase

devices because systems typically expect to read from flash memory when coming out

of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization

may not occur. This is because the flash memory may be providing status information,

instead of array data as expected. Connect RST# to the same active low reset signal

used for CPU initialization.

Also, because the device is disabled when RST# is asserted, it ignores its control inputs

during power-up/down. Invalid bus conditions are masked, providing a level of memory

protection.

Table 21:

Num

Symbol

t_PLPH

t_PLRH

Parameter

RST# pulse width low

Min

Max

Unit

Notes

P1

100

-

25

-

ns

1,2,3,4

1,3,4,7

1,4,5,6

RST# low to device reset during erase

P2

P3

RST# low to device reset during program

V_CCPower valid to RST# de-assertion (high) 130nm

-

µs

60

300

t_VCCPH

V

_CCPower valid to RST# de-assertion (high) 65nm

-

Notes:

1.

2.

3.

4.

5.

6.

7.

These specifications are valid for all device versions (packages and speeds).

The device may reset if t_PLPHis < t_{PLPH MIN}, but this is not guaranteed.

Not applicable if RST# is tied to Vcc.

Sampled, but not 100% tested.

When RST# is tied to the V_CCsupply, device will not be ready until t_VCCPHafter V_CC≥ V_CCMIN

When RST# is tied to the V_CCQsupply, device will not be ready until t_VCCPHafter V_CC≥ V_CCMIN

Reset completes within t_PLPHif RST# is asserted while no erase or program operation is executing.

.

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Figure 25: Reset Operation Waveforms

P1

P2

P3

R5

V_IH

V_IL

(

A) Reset during

RST# [P]

V_CC

read mode

Abort

Complete

R5

(B) Reset during

V_IH

V_IL

program or block erase

P1

≤ P2

Abort

Complete

R5

(C) Reset during

V_IH

V_IL

program or block erase

P1

≥ P2

V_CC

0V

(D) VCC Power-up to

RST# high

8.3

Power Supply Decoupling

Flash memory devices require careful power supply de-coupling. Three basic power

supply current considerations are 1) standby current levels, 2) active current levels,

and 3) transient peaks produced when CE# and OE# are asserted and deasserted.

When the device is accessed, many internal conditions change. Circuits within the

device enable charge-pumps, and internal logic states change at high speed. All of

these internal activities produce transient signals. Transient current magnitudes depend

on the device outputs’ capacitive and inductive loading. Two-line control and correct

de-coupling capacitor selection suppress transient voltage peaks.

Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from

VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to

ground. High-frequency, inherently low-inductance capacitors should be placed as close

as possible to package leads.

Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor

should be placed between power and ground close to the devices. The bulk capacitor is

meant to overcome voltage droop caused by PCB trace inductance.

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9.0

Device Operations

This section provides an overview of device operations. The system CPU provides

control of all in-system read, write, and erase operations of the device via the system

bus. The on-chip Write State Machine (WSM) manages all block-erase and word-

program algorithms.

Device commands are written to the Command User Interface (CUI) to control all flash

memory device operations. The CUI does not occupy an addressable memory location;

it is the mechanism through which the flash device is controlled.

9.1

Bus Operations

CE# low and RST# high enable device read operations. The device internally decodes

upper address inputs to determine the accessed block. ADV# low opens the internal

address latches. OE# low activates the outputs and gates selected data onto the I/O

bus.

In asynchronous mode, the address is latched when ADV# goes high or continuously

flows through if ADV# is held low. In synchronous mode, the address is latched by the

first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#

and RST# must be V_IH; CE# must be V_IL).

Bus cycles to/from the P30 device conform to standard microprocessor bus operations.

Table 22 summarizes the bus operations and the logic levels that must be applied to

the device control signal inputs.

Table 22: Bus Operations Summary

DQ[15:0

]

Bus Operation

RST#

CLK

ADV#

CE#

OE#

WE#

WAIT

Notes

Asynchronous

V_IH

V_IL

X

L

H

L

Output

Input

Deasserted

Driven

Read

Write

Synchronous

Running

X

L

H

X

High-Z

1

2

Output Disable

Standby

Reset

X

L

H

X

High-Z

H

X

2

2,3

Notes:

1.

Refer to the Table 23, “Command Bus Cycles” on page 45 for valid DQ[15:0] during a write

operation.

2.

3.

X = Don’t Care (H or L).

RST# must be at V_SS± 0.2 V to meet the maximum specified power-down current.

9.1.1

Reads

To perform a read operation, RST# and WE# must be deasserted while CE# and OE#

are asserted. CE# is the device-select control. When asserted, it enables the flash

memory device. OE# is the data-output control. When asserted, the addressed flash

memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on

page 48 for details on the available read modes, and see Section 14.0, “Special Read

States” on page 69 for details regarding the available read states.

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9.1.2

Writes

To perform a write operation, both CE# and WE# are asserted while RST# and OE# are

deasserted. During a write operation, address and data are latched on the rising edge

of WE# or CE#, whichever occurs first. Table 23, “Command Bus Cycles” on page 45

shows the bus cycle sequence for each of the supported device commands, while

Table 24, “Command Codes and Definitions” on page 46 describes each command. See

Section 7.0, “AC Characteristics” on page 28 for signal-timing details.

Note: Write operations with invalid V_CCand/or V_PPvoltages can produce spurious results and should

not be attempted.

9.1.3

9.1.4

Output Disable

When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-

impedance (High-Z) state, WAIT is also placed in High-Z.

Standby

When CE# is deasserted the device is deselected and placed in standby, substantially

reducing power consumption. In standby, the data outputs are placed in High-Z,

independent of the level placed on OE#. Standby current, I_CCS, is the average current

measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,

average current is measured over the same time interval 5 μs after CE# is deasserted.

When the device is deselected (while CE# is deasserted) during a program or erase

operation, it continues to consume active power until the program or erase operation is

completed.

9.1.5

Reset

As with any automated device, it is important to assert RST# when the system is reset.

When the system comes out of reset, the system processor attempts to read from the

flash memory if it is the system boot device. If a CPU reset occurs with no flash

memory reset, improper CPU initialization may occur because the flash memory may

be providing status information rather than array data. Flash memory devices from

Numonyx allow proper CPU initialization following a system reset through the use of the

RST# input. RST# should be controlled by the same low-true reset signal that resets

the system CPU.

After initial power-up or reset, the device defaults to asynchronous Read Array mode,

and the Status Register is set to 0x80. Asserting RST# de-energizes all internal

circuits, and places the output drivers in High-Z. When RST# is asserted, the device

shuts down the operation in progress, a process which takes a minimum amount of

time to complete. When RST# has been deasserted, the device is reset to

asynchronous Read Array state.

Note: If RST# is asserted during a program or erase operation, the operation is terminated and the

memory contents at the aborted location (for a program) or block (for an erase) are no longer

valid, because the data may have been only partially written or erased.

When returning from a reset (RST# deasserted), a minimum wait is required before the

initial read access outputs valid data. Also, a minimum delay is required after a reset

before a write cycle can be initiated. After this wake-up interval passes, normal

operation is restored. See Section 7.0, “AC Characteristics” on page 28 for details

about signal-timing.

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9.2

Device Commands

Device operations are initiated by writing specific device commands to the Command

User Interface (CUI). See Table 23, “Command Bus Cycles” on page 45. Several

commands are used to modify array data including Word Program and Block Erase

commands. Writing either command to the CUI initiates a sequence of internally-timed

functions that culminate in the completion of the requested task. However, the

operation can be aborted by either asserting RST# or by issuing an appropriate

suspend command.

Table 23: Command Bus Cycles

First Bus Cycle

Second Bus Cycle

Bus

Mode

Command

Cycles

Oper

Addr⁽¹⁾

Data⁽²⁾

Oper

Addr⁽¹⁾

Data⁽²⁾

Read Array

1

≥ 2

2

Write

DnA

0xFF

0x90

0x98

0x70

0x50

-

DBA + IA

DBA + QA

DnA

-

ID

Read Device Identifier

CFI Query

Read

-

Read

QD

SRD

-

Read Status Register

Clear Status Register

1

-

0x40/

0x10

Word Program

2

Write

WA

Write

WA

WD

Program

Buffered Program⁽³⁾

> 2

0xE8

0x80

N - 1

0xD0

Buffered Enhanced Factory

Program (BEFP)⁽⁴⁾

Erase

Block Erase

2

Write

BA

0x20

Write

BA

0xD0

Program/Erase Suspend

Program/Erase Resume

Lock Block

1

2

Write

DnA

BA

0xB0

0xD0

0x60

0xC0

-

Suspend

-

Write

BA

PRA

LRA

0x01

0xD0

0x2F

PD

Block

Locking/

Unlocking

Unlock Block

BA

Lock-down Block

BA

PRA

LRA

Program Protection Register

Program Lock Register

Protection

LRD

Program Read Configuration

Register

Configuration

2

Write

RCD

0x60

Write

RCD

0x03

Notes:

1.

First command cycle address should be the same as the operation’s target address.

DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device)

DnA = Address within the device.

IA = Identification code address offset.

QA = CFI Query address offset.

WA = Word address of memory location to be written.

BA = Address within the block.

PRA = Protection Register address.

LRA = Lock Register address.

RCD = Read Configuration Register data on QUAD+ A[15:0] or EASY BGA A[16:1].

ID = Identifier data.

QD = Query data on DQ[15:0].

2.

SRD = Status Register data.

WD = Word data.

N = Word count of data to be loaded into the write buffer.

PD = Protection Register data.

LRD = Lock Register data.

3.

4.

The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This

is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming

operation.

The confirm command (0xD0) is followed by the buffer data.

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9.3

Command Definitions

Valid device command codes and descriptions are shown in Table 24.

Table 24: Command Codes and Definitions (Sheet 1 of 2)

Mode

Code

Device Mode

Read Array

Description

0xFF

Places the device in Read Array mode. Array data is output on DQ[15:0].

Places the device in Read Status Register mode. The device enters this mode

after a program or erase command is issued. Status Register data is output

on DQ[7:0].

Read Status

Register

0x70

0x90

Read Device ID

or Configuration

Register

Places device in Read Device Identifier mode. Subsequent reads output

manufacturer/device codes, Configuration Register data, Block Lock status,

or Protection Register data on DQ[15:0].

Read

Places the device in Read Query mode. Subsequent reads output Common

Flash Interface information on DQ[7:0].

0x98

0x50

Read Query

Clear Status

Register

The WSM can only set Status Register error bits. The Clear Status Register

command is used to clear the SR error bits.

First cycle of a 2-cycle programming command; prepares the CUI for a write

operation. On the next write cycle, the address and data are latched and the

WSM executes the programming algorithm at the addressed location. During

program operations, the device responds only to Read Status Register and

Program Suspend commands. CE# or OE# must be toggled to update the

Status Register in asynchronous read. CE# or ADV# must be toggled to

update the Status Register Data for synchronous Non-array reads. The Read

Array command must be issued to read array data after programming has

finished.

Word Program

Setup

Write

0x40

Alternate Word

Program Setup

0x10

0xE8

Equivalent to the Word Program Setup command, 0x40.

This command loads a variable number of words up to the buffer size of 32

words onto the program buffer.

Buffered Program

The confirm command is Issued after the data streaming for writing into the

buffer is done. This instructs the WSM to perform the Buffered Program

algorithm, writing the data from the buffer to the flash memory array.

Buffered Program

Confirm

0xD0

Write

First cycle of a 2-cycle command; initiates Buffered Enhanced Factory

Program mode (BEFP). The CUI then waits for the BEFP Confirm command,

0xD0, that initiates the BEFP algorithm. All other commands are ignored

when BEFP mode begins.

0x80

0xD0

BEFP Setup

If the previous command was BEFP Setup (0x80), the CUI latches the

address and data, and prepares the device for BEFP mode.

BEFP Confirm

First cycle of a 2-cycle command; prepares the CUI for a block-erase

operation. The WSM performs the erase algorithm on the block addressed by

the Erase Confirm command. If the next command is not the Erase Confirm

(0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and

places the device in read status register mode.

0x20

0xD0

Block Erase Setup

Erase

If the first command was Block Erase Setup (0x20), the CUI latches the

address and data, and the WSM erases the addressed block. During block-

erase operations, the device responds only to Read Status Register and Erase

Suspend commands. CE# or OE# must be toggled to update the Status

Register in asynchronous read. CE# or ADV# must be toggled to update the

Status Register Data for synchronous Non-array reads

Block Erase Confirm

This command issued to any device address initiates a suspend of the

currently-executing program or block erase operation. The Status Register

indicates successful suspend operation by setting either SR[2] (program

suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write

State Machine remains in the suspend mode regardless of control signal

states (except for RST# asserted).

Program or Erase

Suspend

0xB0

0xD0

Suspend

This command issued to any device address resumes the suspended program

or block-erase operation.

Suspend Resume

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Table 24: Command Codes and Definitions (Sheet 2 of 2)

Mode

Code

Device Mode

Description

First cycle of a 2-cycle command; prepares the CUI for block lock

configuration changes. If the next command is not Block Lock (0x01), Block

Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits

SR[4] and SR[5], indicating a command sequence error.

0x60

Lock Block Setup

If the previous command was Block Lock Setup (0x60), the addressed block

is locked.

0x01

0xD0

0x2F

0xC0

Lock Block

Block Locking/

Unlocking

If the previous command was Block Lock Setup (0x60), the addressed block

is unlocked. If the addressed block is in a lock-down state, the operation has

no effect.

Unlock Block

Lock-Down Block

If the previous command was Block Lock Setup (0x60), the addressed block

is locked down.

First cycle of a 2-cycle command; prepares the device for a Protection

Register or Lock Register program operation. The second cycle latches the

register address and data, and starts the programming algorithm

Program Protection

Register Setup

Protection

First cycle of a 2-cycle command; prepares the CUI for device read

configuration. If the Set Read Configuration Register command (0x03) is not

the next command, the CUI sets Status Register bits SR[4] and SR[5],

indicating a command sequence error.

Read Configuration

Register Setup

0x60

0x03

Configuration

If the previous command was Read Configuration Register Setup (0x60), the

CUI latches the address and writes A[15:0] to the Read Configuration

Register. Following a Configure Read Configuration Register command,

subsequent read operations access array data.

Read Configuration

Register

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10.0

Read Operations

The device supports two read modes: asynchronous page mode and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a

reset. The Read Configuration Register must be configured to enable synchronous burst

reads of the flash memory array (see Section 10.3, “Read Configuration Register” on

page 49).

The device can be in any of four read states: Read Array, Read Identifier, Read Status

or Read Query. Upon power-up, or after a reset, the device defaults to Read Array. To

change the read state, the appropriate read command must be written to the device

(see Section 9.2, “Device Commands” on page 45). See Section 14.0, “Special Read

States” on page 69 for details regarding Read Status, Read ID, and CFI Query modes.

The following sections describe read-mode operations in detail.

10.1

Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read

mode and the device is set to Read Array. However, to perform array reads after any

other device operation (e.g. write operation), the Read Array command must be issued

in order to read from the flash memory array.

Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit

RCR[15] is set (see Section 10.3, “Read Configuration Register” on page 49).

To perform an asynchronous page-mode read, an address is driven onto the Address

bus, and CE# and ADV# are asserted. WE# and RST# must already have been

deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven

high to latch the address, or it must be held low throughout the read cycle. CLK is not

used for asynchronous page-mode reads, and is ignored. If only asynchronous reads

are to be performed, CLK should be tied to a valid V_IHlevel, WAIT signal can be floated

and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial

access time t_AVQVdelay. (see Section 7.0, “AC Characteristics” on page 28).

In asynchronous page mode, four data words are “sensed” simultaneously from the flash

memory array and loaded into an internal page buffer. The buffer word corresponding

to the initial address on the Address bus is driven onto DQ[15:0] after the initial access

delay. The lowest two address bits determine which word of the 4-word page is output

from the data buffer at any given time.

10.2

Synchronous Burst-Mode Read

To perform a synchronous burst-read, an initial address is driven onto the Address bus, and

CE# and ADV# are asserted. WE# and RST# must already have been deasserted.

ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can

remain asserted throughout the burst access, in which case the address is latched on

the next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay (see Section

10.3.2, “Latency Count” on page 50). Subsequent data is output on valid CLK edges

following a minimum delay. However, for a synchronous non-array read, the same word

of data will be output on successive clock edges until the burst length requirements are

satisfied. Refer to the following waveforms for more detailed information:

• Figure 17, “Synchronous Single-Word Array or Non-array Read Timing” on page 34

• Figure 18, “Continuous Burst Read, Showing An Output Delay Timing” on page 35

• Figure 19, “Synchronous Burst-Mode Four-Word Read Timing” on page 35

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10.3

Read Configuration Register

The Read Configuration Register (RCR) is used to select the read mode (synchronous or

asynchronous), and it defines the synchronous burst characteristics of the device. To

modify RCR settings, use the Configure Read Configuration Register command (see

Section 9.2, “Device Commands” on page 45).

RCR contents can be examined using the Read Device Identifier command, and then

reading from offset 0x05 (see Section 14.2, “Read Device Identifier” on page 70).

The RCR is shown in Table 25. The following sections describe each RCR bit.

Table 25: Read Configuration Register Description

Read Configuration Register (RCR)

Data

Hold

WAIT

Delay

Burst

Wrap

Read

Mode

WAIT

Polarity

Burst

Seq

CLK

Edge

RES

Latency Count

LC[2:0]

RES

Burst Length

RM

15

Bit

R

WP

10

DH

9

WD

8

BS

7

CE

6

R

5

R

4

BW

3

BL[2:0]

1

14

13

12

11

2

0

Name

Description

0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

15

Read Mode (RM)

Reserved (R)

14

Reserved bits should be cleared (0)

010 =Code 2

011 =Code 3

100 =Code 4

101 =Code 5

Latency Count (LC[2:0])

13:11

110 =Code 6

111 =Code 7 (default)

(Other bit settings are reserved)

0 =WAIT signal is active low

1 =WAIT signal is active high (default)

Wait Polarity (WP)

Data Hold (DH)

10

9

0 =Data held for a 1-clock data cycle

1 =Data held for a 2-clock data cycle (default)

0 =WAIT deasserted with valid data

1 =WAIT deasserted one data cycle before valid data (default)

8

Wait Delay (WD)

Burst Sequence (BS)

0 =Reserved

1 =Linear (default)

7

Clock Edge (CE)

0 = Falling edge

1 = Rising edge (default)

6

5:4

3

Reserved (R)

Reserved bits should be cleared (0)

Burst Wrap (BW)

0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]

1 =No Wrap; Burst accesses do not wrap within burst length (default)

001 =4-word burst

010 =8-word burst

011 =16-word burst

111 =Continuous-word burst (default)

2:0

Burst Length (BL[2:0])

(Other bit settings are reserved)

Note: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0).

Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)

combination is not supported. Table 25, “Read Configuration Register Description” on page 49 is

shown using the QUAD+ package. For EASY BGA and TSOP packages, the table reference should be adjusted using

address bits A[16:1].

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10.3.1

10.3.2

Read Mode

The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode

operation for the device. When the RM bit is set, asynchronous page mode is selected

(default). When RM is cleared, synchronous burst mode is selected.

Latency Count

The Latency Count (LC) bits tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the

first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to

determine this value and Figure 26 shows the data output latency for the different

settings of LC. The maximum Latency Count for P30 would be Code 4 based on the Max

Clock frequency specification of 52 mhz, and there will be zero WAIT States when

bursting within the word line. Please also refer to “End of Word Line (EOWL)

Considerations” on page 55 for more information on EOWL.

Refer to Table 26, “Latency Count (LC) and Frequency Support” on page 51 for Latency

Code Settings.

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Figure 26: First-Access Latency Count

CLK [C]

Valid

Address

Address [A]

ADV# [V]

Code 0 (Reserved)

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

DQ_15-0[D/Q]

Code 1

(Reserved

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 2

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 3

Code 4

Code 5

Code 6

Code 7

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Table 26: Latency Count (LC) and Frequency Support

Latency Count Settings

Frequency Support (MHz)

2

3

4

£ 27

£ 40

£ 52

Note: Synchronous burst read operation is currently not supported for the TSOP package.

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Figure 27: Example Latency Count Setting using Code 3

t_Data

0

1

2

3

4

CLK

CE#

ADV#

Address

A[MAX:0]

Code 3

High-Z

Data

D[15:0]

R103

10.3.3

WAIT Polarity

The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V_OHor V_OL) of

WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is

asserted low. WAIT changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# deasserted).

10.3.3.1

WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read

status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid

on the bus.

WAIT behavior during synchronous non-array reads at the end of word line works

correctly only on the first data access.

When the device is operating in asynchronous page mode, asynchronous single word

read mode, and all write operations, WAIT is set to a deasserted state as determined

by RCR[10]. See Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on

page 33, and Figure 16, “Asynchronous Page-Mode Read Timing” on page 34.

Table 27: WAIT Functionality Table (Sheet 1 of 2)

Condition

WAIT

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

CE# =’0’, OE# = ‘0’

High-Z

Active

1

Synchronous Array Reads

Synchronous Non-Array Reads

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Table 27: WAIT Functionality Table (Sheet 2 of 2)

Condition

WAIT

Notes

All Asynchronous Reads

All Writes

Deasserted

High-Z

1

1,2

Notes:

1.

2.

Active: WAIT is asserted until data becomes valid, then deasserts

When OE# = V_IHduring writes, WAIT = High-Z

10.3.4

Data Hold

For burst read operations, the Data Hold (DH) bit determines whether the data output

remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the

“data cycle”. When DH is set, output data is held for two clocks (default). When DH is

cleared, output data is held for one clock (see Figure 28). The processor’s data setup

time and the flash memory’s clock-to-data output delay should be considered when

determining whether to hold output data for one or two clocks. A method for

determining the Data Hold configuration is shown below:

To set the device at one clock data hold for subsequent reads, the following condition

must be satisfied:

t_{CHQV (ns) +}t_DATA(ns) ≤ One CLK Period (ns)

t_DATA= Data set up to Clock (defined by CPU)

For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming

t

_CHQV= 20 ns and t_DATA= 4 ns. Applying these values to the formula above:

20 ns + 4 ns ≤ 25 ns

The equation is satisfied and data will be available at every clock period with data hold

setting at one clock. If t_{CHQV (ns) +}t_DATA(ns) >One CLK Period (ns), data hold setting of

2 clock periods must be used.

Figure 28: Data Hold Timing

CLK [C]

1 CLK

Data Hold

Valid

Output

Valid

Output

Valid

Output

D[15:0] [Q]

2 CLK

Valid

Output

Valid

Output

D[15:0] [Q]

Data Hold

10.3.5

WAIT Delay

The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during

synchronous burst reads. WAIT can be asserted either during or one data cycle before

valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle

before valid data (default). When WD is cleared, WAIT is deasserted during valid data.

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10.3.6

Burst Sequence

The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst

sequence is supported. Table 28 shows the synchronous burst sequence for all burst

lengths, as well as the effect of the Burst Wrap (BW) setting.

Table 28: Burst Sequence Word Ordering

Burst Addressing Sequence (DEC)

Start

Addr.

(DEC)

Burst

Wrap

(RCR[3])

4-Word Burst

(BL[2:0] =

0b001)

8-Word Burst

(BL[2:0] = 0b010)

16-Word Burst

(BL[2:0] = 0b011)

Continuous Burst

(BL[2:0] = 0b111)

0

1

2

3

4

5

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

0-1-2-3-4…14-15

1-2-3-4-5…15-0

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

2-3-4-5-6…15-0-1

3-4-5-6-7…15-0-1-2

4-5-6-7-8…15-0-1-2-3

5-6-7-8-9…15-0-1-2-3-4

6-7-8-9-10…15-0-1-2-3-4-

5

6

7

0

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

6-7-8-9-10-11-12-…

7-8-9-10-11-12-13…

7-8-9-10…15-0-1-2-3-4-5-

6

14

15

0

14-15-0-1-2…12-13

15-0-1-2-3…13-14

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

0

1

2

3

4

5

6

1

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

0-1-2-3-4…14-15

1-2-3-4-5…15-16

2-3-4-5-6…16-17

3-4-5-6-7…17-18

4-5-6-7-8…18-19

5-6-7-8-9…19-20

6-7-8-9-10…20-21

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12-…

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-

14

7

1

7-8-9-10-11…21-22

7-8-9-10-11-12-13…

14

15

1

14-15-16-17-18…28-29

15-16-17-18-19…29-30

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

10.3.7

Clock Edge

The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.

This clock edge is used at the start of a burst cycle, to output synchronous data, and to

assert/deassert WAIT.

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10.3.8

Burst Wrap

The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length

accesses wrap within the selected word-length boundaries or cross word-length

boundaries. When BW is set, burst wrapping does not occur (default). When BW is

cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may

occur when the burst sequence crosses its first device-row (16-word) boundary. If the

burst sequence’s start address is 4-word aligned, then no delay occurs. If the start

address is at the end of a 4-word boundary, the worst case output delay is one clock

cycle less than the first access Latency Count. This delay can take place only once, and

doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT

informs the system of this delay when it occurs.

10.3.9

Burst Length

The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst

reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and

continuous word.

Continuous-burst accesses are linear only, and do not wrap within any word length

boundaries (see Table 28, “Burst Sequence Word Ordering” on page 54). When a burst

cycle begins, the device outputs synchronous burst data until it reaches the end of the

“burstable” address space.

10.3.10

End of Word Line (EOWL) Considerations

When performing synchronous burst reads with BW set (no wrap) and DH reset (1 clock

cycle), an output “delay” requiring additions clock Wait States may occur when the

burst sequence crosses its first device-row (16-word) boundary. The delay would take

place only once, and will not occur if the burst sequence does not cross a device-row

boundary. The WAIT signal informs the system of this delay when it occurs. If the burst

sequence’s start address is 4-word aligned (i.e. 0x00h, 0x04h, 0x08h, 0x0Ch) then no

delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h,

0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States required) will be

one clock cycle less than the first access Latency Count (LC-1) when crossing the first

device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalignments may require

wait states depending upon the LC setting and the starting address alignment. For

example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but

the same LC setting of 3 with a starting address of 0xFE would require 1 wait state

when crossing the first device row boundary.

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11.0

Programming Operations

The device supports three programming methods: Word Programming (40h/10h),

Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,

D0h). See

Section 9.0, “Device Operations” on page 43 for details on the various programming

commands issued to the device. The following sections describe device programming in

detail.

Successful programming requires the addressed block to be unlocked. If the block is

locked down, WP# must be deasserted and the block must be unlocked before

attempting to program the block. Attempting to program a locked block causes a

program error (SR[4] and SR[1] set) and termination of the operation. See Section

13.0, “Security Modes” on page 64 for details on locking and unlocking blocks.

The Product Name is segmented into multiple 8-Mbit Programming Regions. See

Section 4.4, “Memory Maps” on page 22 for complete addressing. Execute in Place

(XIP) applications must partition the memory such that code and data are in separate

programming regions. XIP is executing code directly from flash memory. Each

Programming Region should contain only code or data but not both. The following

terms define the difference between code and data. System designs must use these

definitions when partitioning their code and data for the P30 device.

• Code: Execution code ran out of the flash device on a continuous basis in the

system.

• Data: Information periodically programmed into the flash device and read back

(e.g. execution code shadowed and executed in RAM, pictures, log files, etc.).

11.1

Word Programming

Word programming operations are initiated by writing the Word Program Setup

command to the device (see Section 9.0, “Device Operations” on page 43). This is

followed by a second write to the device with the address and data to be programmed.

The device outputs Status Register data when read. See Figure 38, “Word Program

Flowchart” on page 79. V_PPmust be above V_PPLK, and within the specified V_PPLmin/

max values.

During programming, the Write State Machine (WSM) executes a sequence of

internally-timed events that program the desired data bits at the addressed location,

and verifies that the bits are sufficiently programmed. Programming the flash memory

array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to

ones only by erasing the block (see Section 12.0, “Erase Operations” on page 62).

The Status Register can be examined for programming progress and errors by reading

at any address. The device remains in the Read Status Register state until another

command is written to the device.

Status Register bit SR[7] indicates the programming status while the sequence

executes. Commands that can be issued to the device during programming are

Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read

Array (this returns unknown data).

When programming has finished, Status Register bit SR[4] (when set) indicates a

programming failure. If SR[3] is set, the WSM could not perform the word

programming operation because V_PPwas outside of its acceptable limits. If SR[1] is set,

the word programming operation attempted to program a locked block, causing the

operation to abort.

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Before issuing a new command, the Status Register contents should be examined and

then cleared using the Clear Status Register command. Any valid command can follow,

when word programming has completed.

11.1.1

Factory Word Programming

Factory word programming is similar to word programming in that it uses the same

commands and programming algorithms. However, factory word programming

enhances the programming performance with V_PP= V_PPH. This can enable faster

programming times during OEM manufacturing processes. Factory word programming

is not intended for extended use. See Section 5.2, “Operating Conditions” on page 25

for limitations when V_PP= V_PPH

.

Note: When V_PP= V_PPL, the device draws programming current from the V_CCsupply. If V_PPis driven

by a logic signal, V_PPLmust remain above V_PPLMIN to program the device. When V_PP= V_PPH

,

the device draws programming current from the V_PPsupply. Figure 29, “Example VPP Supply

Connections” on page 61 shows examples of device power supply configurations.

11.2

Buffered Programming

The device features a 32-word buffer to enable optimum programming performance.

For Buffered Programming, data is first written to an on-chip write buffer. Then the

buffer data is programmed into the flash memory array in buffer-size increments. This

can improve system programming performance significantly over non-buffered

programming.

When the Buffered Programming Setup command is issued (see Section 9.2, “Device

Commands” on page 45), Status Register information is updated and reflects the

availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is

available; if cleared, the buffer is not available. To retry, issue the Buffered

Programming Setup command again, and re-check SR[7]. When SR[7] is set, the

buffer is ready for loading. (see Figure 40, “Buffer Program Flowchart” on page 81).

On the next write, a word count is written to the device at the buffer address. This tells

the device how many data words will be written to the buffer, up to the maximum size

of the buffer.

On the next write, a device start address is given along with the first data to be written

to the flash memory array. Subsequent writes provide additional device addresses and

data. All data addresses must lie within the start address plus the word count.

Optimum programming performance and lower power usage are obtained by aligning

the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing

a 32-word boundary during programming will double the total programming time.

After the last data is written to the buffer, the Buffered Programming Confirm command

must be issued to the original block address. The WSM begins to program buffer

contents to the flash memory array. If a command other than the Buffered

Programming Confirm command is written to the device, a command sequence error

occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the

array, the device stops programming, and Status Register bits SR[7,4] are set,

indicating a programming failure.

When Buffered Programming has completed, additional buffer writes can be initiated by

issuing another Buffered Programming Setup command and repeating the buffered

program sequence. Buffered programming may be performed with V_PP= V_PPLor V_PPH

(see Section 5.2, “Operating Conditions” on page 25 for limitations when operating the

device with V_PP= V_PPH).

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If an attempt is made to program past an erase-block boundary using the Buffered

Program command, the device aborts the operation. This generates a command

sequence error, and Status Register bits SR[5,4] are set.

If Buffered programming is attempted while V_PPis below V_PPLK, Status Register bits

SR[4,3] are set. If any errors are detected that have set Status Register bits, the

Status Register should be cleared using the Clear Status Register command.

11.3

Buffered Enhanced Factory Programming

Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash

programming. The enhanced programming algorithm used in BEFP eliminates

traditional programming elements that drive up overhead in device programmer

systems.

BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 41, “BEFP

Flowchart” on page 82). It uses a write buffer to spread MLC program performance

across 32 data words. Verification occurs in the same phase as programming to

accurately program the flash memory cell to the correct bit state.

A single two-cycle command sequence programs the entire block of data. This

enhancement eliminates three write cycles per buffer: two commands and the word

count for each set of 32 data words. Host programmer bus cycles fill the device’s write

buffer followed by a status check. SR[0] indicates when data from the buffer has been

programmed into sequential flash memory array locations.

Following the buffer-to-flash array programming sequence, the Write State Machine

(WSM) increments internal addressing to automatically select the next 32-word array

boundary. This aspect of BEFP saves host programming equipment the address-bus

setup overhead.

With adequate continuity testing, programming equipment can rely on the WSM’s

internal verification to ensure that the device has programmed properly. This eliminates

the external post-program verification and its associated overhead.

11.3.1

BEFP Requirements and Considerations

Table 29: BEFP Requirements

Parameter/Issue

Requirement

Notes

Case Temperature

T_C= 25 °C ± 5 °C

V_CC

Within operating range

Driven to V_PPH

VPP

Setup and Confirm

Target block unlocked before issuing the BEFP Setup and Confirm commands

The first-word address (WA0) of the block to be programmed must be held constant

from the setup phase through all data streaming into the target block, until transition

to the exit phase is desired

Programming

Buffer Alignment

Note:

WA0 must align with the start of an array buffer boundary

1

1.

Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =

0x00.

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Table 30: BEFP Considerations

Parameter/Issue

Requirement

Notes

Cycling

For optimum performance, cycling must be limited below 100 erase cycles per block.

BEFP programs one block at a time; all buffer data must fall within a single block

BEFP cannot be suspended

1

2

Programming blocks

Suspend

Programming the flash

memory array

Programming to the flash memory array can occur only when the buffer is full.

3

Note:

1.

2.

3.

Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work

properly.

If the internal address counter increments beyond the block's maximum address, addressing wraps around to the

beginning of the block.

If the number of words is less than 32, remaining locations must be filled with 0xFFFF.

11.3.2

BEFP Setup Phase

After receiving the BEFP Setup and Confirm command sequence, Status Register bit

SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup.

A delay before checking SR[7] is required to allow the WSM enough time to perform all

of its setups and checks (Block-Lock status, V_PPlevel, etc.). If an error is detected,

SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1]

is also set. SR[3] is set if the error occurred due to an incorrect V_PPlevel.

Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs

Status Register data. Do not issue the Read Status Register command; it will be interpreted

as data to be loaded into the buffer.

11.3.3

BEFP Program/Verify Phase

After the BEFP Setup Phase has completed, the host programming system must check

SR[7,0] to determine the availability of the write buffer for data streaming. SR[7]

cleared indicates the device is busy and the BEFP program/verify phase is activated.

SR[0] indicates the write buffer is available.

Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer

data programming to the array. For BEFP, the count value for buffer loading is always

the maximum buffer size of 32 words. During the buffer-loading sequence, data is

stored to sequential buffer locations starting at address 0x00. Programming of the

buffer contents to the flash memory array starts as soon as the buffer is full. If the

number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.

Caution:

The buffer must be completely filled for programming to occur. Supplying an

address outside of the current block's range during a buffer-fill sequence

causes the algorithm to exit immediately. Any data previously loaded into the

buffer during the fill cycle is not programmed into the array.

The starting address for data entry must be buffer size aligned, if not the BEFP

algorithm will be aborted and the program fails and (SR[4]) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the

flash memory array; programming continues from where the previous buffer sequence

ended. The host programming system must poll SR[0] to determine when the buffer

program sequence completes. SR[0] cleared indicates that all buffer data has been

transferred to the flash array; SR[0] set indicates that the buffer is not available yet for

the next fill cycle. The host system may check full status for errors at any time, but it is

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only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write

cycles should be issued to the device until SR[0] = 0 and the device is ready for the

next buffer fill.

Note: Any spurious writes are ignored after a buffer fill operation and when internal program is

proceeding.

The host programming system continues the BEFP algorithm by providing the next

group of data words to be written to the buffer. Alternatively, it can terminate this

phase by changing the block address to one outside of the current block’s range.

The Program/Verify phase concludes when the programmer writes to a different block

address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the

device enters the BEFP Exit phase.

11.3.4

11.4

BEFP Exit Phase

When SR[7] is set, the device has returned to normal operating conditions. A full status

check should be performed at this time to ensure the entire block programmed

successfully. When exiting the BEFP algorithm with a block address change, the read

mode will not change. After BEFP exit, any valid command can be issued to the device.

Program Suspend

Issuing the Program Suspend command while programming suspends the

programming operation. This allows data to be accessed from the device other than the

one being programmed. The Program Suspend command can be issued to any device

address. A program operation can be suspended to perform reads only. Additionally, a

program operation that is running during an erase suspend can be suspended to

perform a read operation (see Figure 39, “Program Suspend/Resume Flowchart” on

page 80).

When a programming operation is executing, issuing the Program Suspend command

requests the WSM to suspend the programming algorithm at predetermined points. The

device continues to output Status Register data after the Program Suspend command is

issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend

latency is specified in Section 7.5, “Program and Erase Characteristics” on page 39.

To read data from the device, the Read Array command must be issued. Read Array,

Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid

commands during a program suspend.

During a program suspend, deasserting CE# places the device in standby, reducing

active current. V_PPmust remain at its programming level, and WP# must remain

unchanged while in program suspend. If RST# is asserted, the device is reset.

11.5

Program Resume

The Resume command instructs the device to continue programming, and

automatically clears Status Register bits SR[7,2]. This command can be written to any

address. If error bits are set, the Status Register should be cleared before issuing the

next instruction. RST# must remain deasserted (see Figure 39, “Program Suspend/

Resume Flowchart” on page 80).

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11.6

Program Protection

When V_PP= V_IL, absolute hardware write protection is provided for all device blocks. If

V

_PPis at or below V_PPLK, programming operations halt and SR[3] is set indicating a V_PP-

level error. Block lock registers are not affected by the voltage level on V_PP; they may

still be programmed and read, even if V_PPis less than V_PPLK

.

Figure 29: Example VPP Supply Connections

V_CC

V_PP

VCC

VPP

VCC

VPP

PROT #

≤ 10K Ω

• Low-voltage Programming only

• Logic Control of Device Protection

• Factory Programming with V_PP= V_PPH

• Complete write/Erase Protection when V_PP≤ V_PPLK

V_CC

VCC

VPP

V_PP=V_PPH

VPP

• Low Voltage Programming Only

• Full Device Protection Unavailable

• Low Voltage and Factory Programming

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12.0

Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an

erase command sequence is issued, and only one block is erased at a time. When a

block is erased, all bits within that block read as logical ones. The following sections

describe block erase operations in detail.

12.1

Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to

be erased (see Section 9.2, “Device Commands” on page 45). Next, the Block Erase Confirm

command is written to the address of the block to be erased. If the device is placed in standby (CE#

deasserted) during an erase operation, the device completes the erase operation before

entering standby.V_PPmust be above V_PPLKand the block must be unlocked (see Figure 42, “Block

Erase Flowchart” on page 83).

During a block erase, the Write State Machine (WSM) executes a sequence of

internally-timed events that conditions, erases, and verifies all bits within the block.

Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are

ones can be changed to zeros only by programming the block (see Section 11.0,

“Programming Operations” on page 56).

The Status Register can be examined for block erase progress and errors by reading

any address. The device remains in the Read Status Register state until another

command is written. SR[0] indicates whether the addressed block is erasing. Status

Register bit SR[7] is set upon erase completion.

Status Register bit SR[7] indicates block erase status while the sequence executes.

When the erase operation has finished, Status Register bit SR[5] indicates an erase

failure if set. SR[3] set would indicate that the WSM could not perform the erase

operation because V_PPwas outside of its acceptable limits. SR[1] set indicates that the

erase operation attempted to erase a locked block, causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and

then cleared using the Clear Status Register command. Any valid command can follow

once the block erase operation has completed.

12.2

Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation.

This allows data to be accessed from memory locations other than the one being

erased. The Erase Suspend command can be issued to any device address. A block

erase operation can be suspended to perform a word or buffer program operation, or a

read operation within any block except the block that is erase suspended (see

Figure 39, “Program Suspend/Resume Flowchart” on page 80).

When a block erase operation is executing, issuing the Erase Suspend command

requests the WSM to suspend the erase algorithm at predetermined points. The device

continues to output Status Register data after the Erase Suspend command is issued.

Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is

specified in Section 7.5, “Program and Erase Characteristics” on page 39.

To read data from the device (other than an erase-suspended block), the Read Array

command must be issued. During Erase Suspend, a Program command can be issued

to any block other than the erase-suspended block. Block erase cannot resume until

program operations initiated during erase suspend complete. Read Array, Read Status

Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands

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during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,

Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase

Suspend.

During an erase suspend, deasserting CE# places the device in standby, reducing

active current. V_PPmust remain at a valid level, and WP# must remain unchanged

while in erase suspend. If RST# is asserted, the device is reset.

12.3

12.4

Erase Resume

The Erase Resume command instructs the device to continue erasing, and

automatically clears status register bits SR[7,6]. This command can be written to any

address. If status register error bits are set, the Status Register should be cleared

before issuing the next instruction. RST# must remain deasserted (see Figure 39,

“Program Suspend/Resume Flowchart” on page 80).

Erase Protection

When V_PP= V_IL, absolute hardware erase protection is provided for all device blocks. If

V_PPis below V_PPLK, erase operations halt and SR[3] is set indicating a V_PP-level error.

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13.0

Security Modes

The device features security modes used to protect the information stored in the flash

memory array. The following sections describe each security mode in detail.

13.1

Block Locking

Individual instant block locking is used to protect user code and/or data within the flash

memory array. All blocks power up in a locked state to protect array data from being

altered during power transitions. Any block can be locked or unlocked with no latency.

Locked blocks cannot be programmed or erased; they can only be read.

Software-controlled security is implemented using the Block Lock and Block Unlock

commands. Hardware-controlled security can be implemented using the Block Lock-

Down command along with asserting WP#. Also, V_PPdata security can be used to

inhibit program and erase operations (see Section 11.6, “Program Protection” on

page 61 and Section 12.4, “Erase Protection” on page 63).

The P30 device also offers four pre-defined areas in the main array that can be

configured as One-Time Programmable (OTP) for the highest level of security. These

include the four 32 KB parameter blocks together as one and the three adjacent 128 KB

main blocks. This is available for top or bottom parameter devices.

13.1.1

Lock Block

To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command

issued to the desired block’s address (see Section 9.2, “Device Commands” on page 45 and

Figure 44, “Block Lock Operations Flowchart” on page 85). If the Set Read Configuration

Register command is issued after the Block Lock Setup command, the device

configures the RCR instead.

Block lock and unlock operations are not affected by the voltage level on V_PP. The block

lock bits may be modified and/or read even if V_PPis at or below V_PPLK

.

13.1.2

13.1.3

Unlock Block

The Unlock Block command is used to unlock blocks (see Section 9.2, “Device

Commands” on page 45). Unlocked blocks can be read, programmed, and erased.

Unlocked blocks return to a locked state when the device is reset or powered down. If a

block is in a lock-down state, WP# must be deasserted before it can be unlocked (see

Figure 30, “Block Locking State Diagram” on page 65).

Lock-Down Block

A locked or unlocked block can be locked-down by writing the Lock-Down Block

command sequence (see Section 9.2, “Device Commands” on page 45). Blocks in a

lock-down state cannot be programmed or erased; they can only be read. However,

unlike locked blocks, their locked state cannot be changed by software commands

alone. A locked-down block can only be unlocked by issuing the Unlock Block command

with WP# deasserted. To return an unlocked block to locked-down state, a Lock-Down

command must be issued prior to changing WP# to V_IL. Locked-down blocks revert to

the locked state upon reset or power up the device (see Figure 30, “Block Locking State

Diagram” on page 65).

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13.1.4

Block Lock Status

The Read Device Identifier command is used to determine a block’s lock status (see

Section 14.2, “Read Device Identifier” on page 70). Data bits DQ[1:0] display the

addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the

addressed block’s lock-down bit.

Figure 30: Block Locking State Diagram

Locked-

Down^4,5

[011]

Hardware

Locked⁵

[011]

Locked

Power-Up/Reset

[X01]

WP# Hardware Control

Software

Locked

Unlocked

[X00]

[111]

[110]

Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)

Software Block Lock-Down (0x60/0x2F)

WP# hardware control

Notes:

1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care.

2. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued

to this block. DQ1 = ‘1’, Lock-Down has been issued to this block.

3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is

locked.

4. Locked-down = Hardware + Software locked.

5. [011] states should be tracked by system software to determine difference between

Hardware Locked and Locked-Down states.

13.1.5

Block Locking During Suspend

Block lock and unlock changes can be performed during an erase suspend. To change

block locking during an erase operation, first issue the Erase Suspend command.

Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is

suspended and ready to accept another command.

Next, write the desired lock command sequence to a block, which changes the lock

state of that block. After completing block lock or unlock operations, resume the erase

operation using the Erase Resume command.

Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,

or Lock-Down Block produces a command sequence error and set Status Register bits SR[4]

and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5]

remains set, even after the erase operation is resumed. Unless the Status Register is cleared

using the Clear Status Register command before resuming the erase operation, possible erase

errors may be masked by the command sequence error.

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If a block is locked or locked-down during an erase suspend of the same block, the lock

status bits change immediately. However, the erase operation completes when it is

resumed. Block lock operations cannot occur during a program suspend. See Appendix

A, “Write State Machine” on page 72, which shows valid commands during an erase

suspend.

13.2

Selectable One-Time Programmable Blocks

Any of four pre-defined areas from the main array (the four 32-KB parameter blocks

together as one and three adjacent 128 KB main blocks) can be configured as OTP so

further program and erase operations are not allowed. This option is available for top or

bottom parameter devices.

Table 31: Selectable OTP Block Mapping

Density

Top Parameter Configuration

Bottom Parameter Configuration

blocks 258:255 (parameters)

block 254 (main)

blocks 3:0 (parameters)

block 4 (main)

256-Mbit

block 253 (main)

block 5 (main)

block 252 (main)

block 6 (main)

blocks 130:127 (parameters)

block 126 (main)

blocks 3:0 (parameters)

block 4 (main)

128-Mbit

block 125 (main)

block 5 (main)

block 124 (main)

block 6 (main)

blocks 66:63 (parameters)

block 62 (main)

blocks 3:0 (parameters)

block 4 (main)

64-Mbit

block 61 (main)

block 5 (main)

block 60 (main)

block 6 (main)

Notes:

1.

The 512-Mbit devices will have multiple die and selectable OTP areas depending on the placement of the parameter

blocks.

2.

When programming the OTP bits for a Top Parameter Device, the following upper address bits must also be driven

properly: A[Max:17] driven high (V_IH) for TSOP and Easy BGA packages, and A[Max:16] driven high (V_IH) for QUAD+

SCSP.

Note: Please see your local Numonyx representative for details about the Selectable OTP

implementation.

13.3

Protection Registers

The device contains 17 Protection Registers (PRs) that can be used to implement

system security measures and/or device identification. Each Protection Register can be

individually locked.

The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The

lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit

number. The other 64-bit segment, as well as the other sixteen 128-bit Protection

Registers, are blank. Users can program these registers as needed. When programmed,

users can then lock the Protection Register(s) to prevent additional bit programming

(see Figure 31, “Protection Register Map” on page 67).

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The user-programmable Protection Registers contain one-time programmable (OTP)

bits; when programmed, register bits cannot be erased. Each Protection Register can

be accessed multiple times to program individual bits, as long as the register remains

unlocked.

Each Protection Register has an associated Lock Register bit. When a Lock Register bit

is programmed, the associated Protection Register can only be read; it can no longer be

programmed. Additionally, because the Lock Register bits themselves are OTP, when

programmed, Lock Register bits cannot be erased. Therefore, when a Protection

Register is locked, it cannot be unlocked.

.

Figure 31: Protection Register Map

0x109

128-bit Protection Register 16

(User-Programmable)

0x102

0x91

128-bit Protection Register 1

(User-Programmable)

0x8A

0x89

Lock Register 1

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x88

64-bit Segment

(User-Programmable)

0x85

0x84

128-Bit Protection Register 0

64-bit Segment

(Factory-Programmed)

0x81

0x80

Lock Register 0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

13.3.1

Reading the Protection Registers

The Protection Registers can be read from any address. To read the Protection Register,

first issue the Read Device Identifier command at any address to place the device in the

Read Device Identifier state (see Section 9.2, “Device Commands” on page 45). Next,

perform a read operation using the address offset corresponding to the register to be

read. Table 33, “Device Identifier Information” on page 70 shows the address offsets of

the Protection Registers and Lock Registers. Register data is read 16 bits at a time.

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13.3.2

Programming the Protection Registers

To program any of the Protection Registers, first issue the Program Protection Register

command at the parameter’s base address plus the offset to the desired Protection

Register (see Section 9.2, “Device Commands” on page 45). Next, write the desired

Protection Register data to the same Protection Register address (see Figure 31,

“Protection Register Map” on page 67).

The device programs the 64-bit and 128-bit user-programmable Protection Register

data 16 bits at a time (see Figure 45, “Protection Register Programming Flowchart” on

page 86). Issuing the Program Protection Register command outside of the Protection

Register’s address space causes a program error (SR[4] set). Attempting to program a

locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]

set).

Note: When programming the OTP bits for a Top Parameter Device, the following upper address

bits must also be driven properly: A[Max:17] driven high (V_IH) for TSOP and Easy BGA

packages, and A[Max:16] driven high (V_IH) for QUAD+ SCSP.

13.3.3

Locking the Protection Registers

Each Protection Register can be locked by programming its respective lock bit in the

Lock Register. To lock a Protection Register, program the corresponding bit in the Lock

Register by issuing the Program Lock Register command, followed by the desired Lock

Register data (see Section 9.2, “Device Commands” on page 45). The physical

addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These

addresses are used when programming the lock registers (see Table 33, “Device

Identifier Information” on page 70).

Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-

programmed 64-bit region of the first 128-bit Protection Register containing the unique

identification number of the device. Bit 1 of Lock Register 0 can be programmed by the

user to lock the user-programmable, 64-bit region of the first 128-bit Protection

Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’

such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers.

Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit

Protection Registers. Programming a bit in Lock Register 1 locks the corresponding

128-bit Protection Register.

Caution:

After being locked, the Protection Registers cannot be unlocked.

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14.0

Special Read States

The following sections describe non-array read states. Non-array reads can be

performed in asynchronous read or synchronous burst mode. A non-array read

operation occurs as asynchronous single-word mode. When non-array reads are performed in

asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-

array read operation occurs as synchronous burst mode, the same word of data

requested will be output on successive clock edges until the burst length requirements

are satisfied.

Refer to the following waveforms for more detailed information:

• Figure 14, “Asynchronous Single-Word Read (ADV# Low)” on page 33

• Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on page 33

• Figure 17, “Synchronous Single-Word Array or Non-array Read Timing” on page 34

14.1

Read Status Register

To read the Status Register, issue the Read Status Register command at any address.

Status Register information is available to which the Read Status Register, Word

Program, or Block Erase command was issued. Status Register data is automatically

made available following a Word Program, Block Erase, or Block Lock command

sequence. Reads from the device after any of these command sequences outputs the

device’s status until another valid command is written (e.g. Read Array command).

The Status Register is read using single asynchronous-mode or synchronous burst

mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on

DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs

first) updates and latches the Status Register contents. However, reading the Status

Register in synchronous burst mode, CE# or ADV# must be toggled to update status

data.

The Device Write Status bit (SR[7]) provides overall status of the device. Status

register bits SR[6:1] present status and error information about the program, erase,

suspend, V_PP, and block-locked operations.

Table 32: Status Register Description (Sheet 1 of 2)

Status Register (SR)

Default Value = 0x80

Program

Suspend

Status

Device Write EraseSuspend

Program

Status

Block-Locked

BEFP

Status

Erase Status

V_PPStatus

Status

DWS

7

ESS

6

ES

5

PS

4

VPPS

3

PSS

2

BLS

1

BWS

0

Bit

Name

Description

0 = Device is busy; program or erase cycle in progress; SR[0] valid.

1 = Device is ready; SR[6:1] are valid.

7

6

5

4

Device Write Status (DWS)

Erase Suspend Status (ESS)

Erase Status (ES)

0 = Erase suspend not in effect.

1 = Erase suspend in effect.

0 = Erase successful.

1 = Erase fail or program sequence error when set with SR[4,7].

0 = Program successful.

Program Status (PS)

1 = Program fail or program sequence error when set with SR[5,7]

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Table 32: Status Register Description (Sheet 2 of 2)

Status Register (SR)

Default Value = 0x80

0 = VPP within acceptable limits during program or erase operation.

3

2

1

V_PPStatus (VPPS)

1 = VPP < VPPLK during program or erase operation.

0 = Program suspend not in effect.

1 = Program suspend in effect.

Program Suspend Status (PSS)

Block-Locked Status (BLS)

0 = Block not locked during program or erase.

1 = Block locked during program or erase; operation aborted.

After Buffered Enhanced Factory Programming (BEFP) data is loaded into the

buffer:

0 = BEFP complete.

0

BEFP Status (BWS)

1 = BEFP in-progress.

Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register

ambiguity when issuing commands during Erase Suspend. If a command sequence error

occurs during an erase-suspend state, the Status Register contains the command sequence

error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors

during the erase operation cannot be detected via the Status Register because it contains the

previous error status.

14.1.1

Clear Status Register

The Clear Status Register command clears the status register. It functions independent

of V_PP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits

SR[5:3,1] without clearing them. The Status Register should be cleared before starting

a command sequence to avoid any ambiguity. A device reset also clears the Status

Register.

14.2

Read Device Identifier

The Read Device Identifier command instructs the device to output manufacturer code,

device identifier code, block-lock status, protection register data, or configuration

register data (see Section 9.2, “Device Commands” on page 45 for details on issuing

the Read Device Identifier command). Table 33, “Device Identifier Information” on

page 70 and Table 34, “Device ID codes” on page 71 show the address offsets and data

values for this device.

Table 33: Device Identifier Information (Sheet 1 of 2)

Item

Address⁽¹⁾

Data

Manufacturer Code

0x00

0x01

0089h

ID (see Table 34)

Lock Bit:

Device ID Code

Block Lock Configuration:

• Block Is Unlocked

DQ₀= 0b0

• Block Is Locked

BBA + 0x02

DQ₀= 0b1

• Block Is not Locked-Down

• Block Is Locked-Down

Read Configuration Register

Lock Register 0

DQ₁= 0b0

DQ₁= 0b1

0x05

0x80

RCR Contents

PR-LK0

64-bit Factory-Programmed Protection Register

64-bit User-Programmable Protection Register

0x81–0x84

0x85–0x88

Factory Protection Register Data

User Protection Register Data

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Table 33: Device Identifier Information (Sheet 2 of 2)

Item

Address⁽¹⁾

Data

Lock Register 1

0x89

PR-LK1

128-bit User-Programmable Protection Registers

0x8A–0x109

Protection Register Data

Notes:

1.

BBA = Block Base Address.

Table 34: Device ID codes

Device Identifier Codes

ID Code Type

Device Density

–T

–B

(Top Parameter)

(Bottom Parameter)

64-Mbit

128-Mbit

256-Mbit

8817

8818

8919

881A

881B

891C

Device Code

Note: The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by

either of the 256-Mbit Device ID codes depending on its parameter option.

14.3

CFI Query

The CFI Query command instructs the device to output Common Flash Interface (CFI)

data when read. See Section 9.2, “Device Commands” on page 45 for details on issuing

the CFI Query command. Appendix C, “Common Flash Interface” on page 87 shows CFI

information and address offsets within the CFI database.

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Appendix A Write State Machine

Figure 32 through Figure 37 show the command state transitions (Next State Table)

based on incoming commands. Only one partition can be actively programming or

erasing at a time. Each partition stays in its last read state (Read Array, Read Device

ID, CFI Query or Read Status Register) until a new command changes it. The next WSM

state does not depend on the partition’s output state.

Figure 32: Write State Machine—Next State Table (Sheet 1 of 6)

Command Input to Chip and resulting Chip Next State

BE Confirm,

Buffered

Enhanced

P/E

Resume,

ULB,

Clear

Status

Register ⁽⁵⁾

Lock, Unlock,

Lock-down,

CR setup ⁽⁴⁾

Buffered

Program

(BP)

BP / Prg /

Erase

Suspend

Read

Word

Program ^(3,4)

Erase

Setup ^(3,4)

Read

Status

Read

ID/Query

(2)

Current Chip

State ⁽⁷⁾

Factory Pgm

Array

Setup ^{(3, 4)}

Confirm ⁽⁸⁾

(FFH)

(10H/40H)

(E8H)

(20H)

(80H)

(D0H)

(B0H)

(70H)

(50H)

(90H, 98H)

(60H)

Program

Setup

Erase

Setup

Lock/CR

Setup

Ready

BP Setup

BEFP Setup

Ready

(Unlock

Block)

Lock/CR Setup

Ready (Lock Error)

Setup

OTP

Busy

OTP Busy

Word Program Busy

Word

Setup

Program Busy

Word Program Busy

Busy

Program

Suspend

Word

Program

Word

Program

Busy

Word Program Suspend

Suspend

BP Load 1

BP Load 2

Setup

BP Load 1

BP Confirm if Data load into Program Buffer is complete; Else BP Load 2

BP Load 2

BP

Confirm

Ready (Error)

BP Busy

BP Suspend

Ready (Error)

Erase Busy

BP Busy

BP Suspend

BP

Suspend

BP Suspend

Ready (Error)

BP Busy

Setup

Erase Busy

Erase

Suspend

Erase Busy

Busy

Erase

Word

Program

Setup in

Erase

Lock/CR

Setup in

Erase

BP Setup in

Erase

Suspend

Erase

Suspend

Erase Suspend

Suspend

Erase Busy

Suspend

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Figure 33: Write State Machine—Next State Table (Sheet 2 of 6)

Chip

Command Input to Chip and resulting

Next State

BE Confirm,

Buffered

Enhanced

Factory Pgm

Setup ^{(3, 4)}

P/E

Resume,

ULB,

Confirm ⁽⁸⁾

Clear

Status

Register ⁽⁵⁾

Lock, Unlock,

Lock-down,

CR setup ⁽⁴⁾

Buffered

Program

(BP)

BP / Prg /

Erase

Suspend

Read

Word

Program ^(3,4)

Erase

Setup ^(3,4)

Read

Status

Read

ID/Query

(2)

Current Chip

State ⁽⁷⁾

Array

(FFH)

(10H/40H)

(E8H)

(20H)

(80H)

(D0H)

(B0H)

(70H)

(50H)

(90H, 98H)

(60H)

Word Program Busy in Erase Suspend

Setup

Word

Program

Word Program Busy in Erase Suspend

Word Program Busy in Erase Suspend Busy

Word Program Suspend in Erase Suspend

Busy

Suspend in

Erase

Suspend

Word

Program in

Erase

Word

Program

Busy in

Erase

Suspend

Word Program Suspend in Erase Suspend

Suspend

BP Load 1

BP Load 2

Setup

BP Load 1

BP Confirm if Data load into Program Buffer is complete; Else BP Load 2

BP Load 2

BP Busy in

Erase

Suspend

BP in Erase

Suspend

BP

Confirm

Erase Suspend (Error)

Ready (Error in Erase Suspend)

BP Suspend

in Erase

BP Busy in Erase Suspend

BP Busy

Suspend

BP Busy in

Erase

Suspend

BP

Suspend

BP Suspend in Erase Suspend

Erase

Suspend

(Unlock

Block)

Lock/CR Setup in Erase

Suspend

Erase Suspend (Lock Error)

Ready (Error)

Erase Suspend (Lock Error [Botch])

Ready (Error)

BEFP

Loading

Buffered

Setup

Enhanced

Factory

Data (X=32)

Program

BEFP

Mode

BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)

Busy

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Figure 34: Write State Machine—Next State Table (Sheet 3 of 6)

Chip

Command Input to Chip and resulting

Next State

Lock

Block

Confirm ⁽⁸⁾Confirm

Lock-Down

OTP

Setup ⁽⁴⁾

Write RCR

Block Address

Illegal Cmds or

BEFP Data ⁽¹⁾

Block

WSM

Operation

Completes

Current Chip

State ⁽⁷⁾

(8)

9

Confirm

(?WA0)

(8)

(C0H)

(01H)

(2FH)

(03H)

(XXXXH)

(all other codes)

OTP

Setup

Ready

(Lock

Error)

Ready

(Lock

Block)

Ready

(Lock Down

Blk)

Ready

(Set CR)

N/A

Lock/CR Setup

Ready (Lock Error)

Setup

OTP Busy

OTP

Busy

Ready

N/A

Word Program Busy

Setup

Ready

Busy

Word

Program

Word Program Suspend

BP Load 1

Suspend

Setup

BP Load 2

Ready (BP Load 2 BP Load 2

BP Load 1

BP Confirm if

Data load into

Program Buffer is

complete; ELSE

BP Load 2

N/A

BP Confirm if Data load into Program Buffer is

complete; ELSE BP load 2

BP Load 2

Ready

BP

Ready (Error)

(Proceed if

unlocked or lock

error)

BP

Confirm

Ready (Error)

BP Busy

BP Suspend

Ready (Error)

Erase Busy

Ready

N/A

BP

Suspend

Setup

Busy

Ready

Erase

Suspend

Erase Suspend

N/A

Datasheet

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Figure 35: Write State Machine—Next State Table (Sheet 4 of 6)

Chip

Command Input to Chip and resulting

Next State

Lock

Block

Confirm ⁽⁸⁾Confirm

Lock-Down

OTP

Setup ⁽⁴⁾

Write RCR

Block Address

Illegal Cmds or

BEFP Data ⁽¹⁾

Block

WSM

Operation

Completes

(8)

9

Current Chip

State ⁽⁷⁾

Confirm

(?WA0)

(8)

(C0H)

(01H)

(2FH)

(03H)

(XXXXH)

(all other codes)

Word Program Busy in Erase Suspend

Setup

NA

Word Program Busy in Erase Suspend Busy

Busy

Erase Suspend

Word

Program in

Erase

Suspend

Word Program Suspend in Erase Suspend

BP Load 1

Suspend

N/A

Setup

BP Load 2

Ready (BP Load 2 BP Load 2

BP Load 1

BP Confirm if

Data load into

Program Buffer is

complete; Else

BP Load 2

BP Confirm if Data load into Program Buffer is

complete; Else BP Load 2

N/A

Ready

BP Load 2

BP in Erase

Suspend

BP

Ready (Error)

(Proceed if

unlocked or lock

error)

Ready (Error in Erase Suspend)

Ready (Error)

Confirm

BP Busy in Erase Suspend

Erase Suspend

BP Busy

BP

Suspend

BP Suspend in Erase Suspend

Erase

Suspend Suspend

(Lock

Error)

Erase

Suspend

Lock/CR Setup in Erase

Suspend

Erase Suspend (Lock Error)

Suspend

(Set CR)

N/A

(Lock

Block)

(Lock Down

Block)

Ready (BEFP

Ready (Error)

Loading Data)

Ready (Error)

Buffered

Enhanced

Factory

Program

Mode

Setup

BEFP Program and Verify Busy (if Block Address

given matches address given on BEFP Setup

command). Commands treated as data. (7)

BEFP

Busy

Ready

BEFP Busy

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Figure 36: Write State Machine—Next State Table (Sheet 5 of 6)

Output Next State Table

Output

Command Input to Chip and resulting

Mux Next State

BE Confirm,

Buffered

P/E

Clear

Status

Register ⁽⁵⁾

Lock, Unlock,

Lock-down,

Word

Program

Setup (3,4)

Program/

Erase

Suspend

Read

Erase

Enhanced

Factory Pgm

Setup ^{(3, 4)}

Read

Status

Read

ID/Query

Resume,

BP Setup

(E8H)

(2)

Array

Setup ^(3,4)

Current chip state

CR setup ⁽⁴⁾

ULB Confirm

(8)

(FFH)

(10H/40H)

(20H)

(30H)

(D0H)

(B0H)

(70H)

(50H)

(90H, 98H)

(60H)

BEFP Setup,

BEFP Pgm & Verify

Busy,

Erase Setup,

OTP Setup,

BP: Setup, Load 1,

Load 2, Confirm,

Word Pgm Setup,

Word Pgm Setup in

Erase Susp,

Status Read

BP Setup, Load1,

Load 2, Confirm in

Erase Suspend

Lock/CR Setup,

Lock/CR Setup in

Erase Susp

Status Read

Status

Read

OTP Busy

Ready,

Erase Suspend,

BP Suspend

BP Busy,

Word Program

Busy,

Erase Busy,

BP Busy

Output mux

does not

change.

Read Array

Status Read

Output does not change.

Status Read

ID Read

BP Busy in Erase

Suspend

Word Pgm

Suspend,

Word Pgm Busy in

Erase Suspend,

Pgm Suspend In

Erase Suspend

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Figure 37: Write State Machine—Next State Table (Sheet 6 of 6)

Output Next State Table

Output

Command Input to Chip and resulting

Mux Next State

Lock

Block

Confirm ⁽⁸⁾Confirm

Lock-Down

OTP

Setup ⁽⁴⁾

Write CR

Illegal Cmds or

BEFP Data ⁽¹⁾

Block Address

(?WA0)

Block

WSM

(8)

Confirm

(8)

Operation

Completes

Current chip state

(C0H)

(01H)

(2FH)

(03H)

(FFFFH)

(all other codes)

BEFP Setup,

BEFP Pgm & Verify

Busy,

Erase Setup,

OTP Setup,

BP: Setup, Load 1,

Load 2, Confirm,

Word Pgm Setup,

Word Pgm Setup in

Erase Susp,

Status Read

BP Setup, Load1,

Load 2, Confirm in

Erase Suspend

Lock/CR Setup,

Lock/CR Setup in

Erase Susp

Array

Read

Status Read

Output does

not change.

OTP Busy

Ready,

Erase Suspend,

BP Suspend

BP Busy,

Word Program

Busy,

Erase Busy,

BP Busy

Status

Read

Output does not

change.

Output does not change.

Array Read

BP Busy in Erase

Suspend

Word Pgm

Suspend,

Word Pgm Busy in

Erase Suspend,

Pgm Suspend In

Erase Suspend

Notes:

1.

"Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase],

etc.)

2.

3.

4.

If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at

different locations in the address map.

1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will

occur.

To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle

command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an

erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be

ignored because it is unclear whether the user intends to erase the block or resume the program operation.

The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM

running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).

BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.

5.

6.

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7.

The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI

or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on

where the partition's output mux is presently pointing to.

8.

9.

Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then

move to the Ready State.

WA0 refers to the block address latched during the first write cycle of the current operation.

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Appendix B Flowcharts

Figure 38: Word Program Flowchart

WORD PROGRAM PROCEDURE

Bus

Operation

Start

Command

Comments

Program Data = 0x40

Setup Addr = Location to program

Write

Read

Write 0x40,

Word Address

(Setup)

Data = Data to program

Data

Addr = Location to program

Write Data,

Word Address

(Confirm)

None

Status register data

Program

Suspend

Loop

Read Status

Register

Check SR[7]

1 = WSM Ready

0 = WSM Busy

Idle

No

Suspend?

Yes

0

SR[7] =

1

Repeat for subsequent Word Program operations.

Full Status Register check can be done after each program, or

after a sequence of program operations.

Full Status

Check

(if desired)

Write 0xFF after the last operation to set to the Read Array

state.

Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status

Register

Bus

Command

Operation

Comments

Check SR[3]:

1 = V_PPError

Idle

None

1

V_PPRange

Error

SR[3] =

0

Check SR[4]:

1 = Data Program Error

Program

Error

Check SR[1]:

1 = Block locked; operation aborted

SR[4] =

0

Idle

None

If an error is detected, clear the Status Register before

continuing operations - only the Clear Staus Register

command clears the Status Register error bits.

Device

Protect Error

SR[1] =

0

Program

Successful

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Datasheet

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Figure 39: Program Suspend/Resume Flowchart

PROGRAM SUSPEND / RESUME PROCEDURE

Bus

Operation

Start

Command

Comments

Read Status

Write 70h

Read

Data = 70h

Write

Status Addr = Block to suspend(BA)

Program Data = B0h

Suspend Addr = X

Program Suspend

Write B0h

Any Address

Status register data

Initiate a read cycle to update Status

register

Addr = Suspended block (BA)

Read

Read Status

Register

Check SR.7

Standby

1 = WSM ready

0 = WSM busy

0

SR.7 =

1

Check SR.2

1 = Program suspended

0 = Program completed

Program

Completed

SR.2 =

1

Read

Array

Data = FFh

Addr = Block address to read (BA)

Write

Read

Write

Read Array

Write FFh

Read array data from block other than

the one being programmed

Read Array

Data

Program Data = D0h

Resume Addr = Suspended block (BA)

Done

No

Reading

Yes

Program Resume

Read Array

Write FFh

Write D0h

Any Address

Program

Resumed

Read Array

Data

PGM_SUS.WMF

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Figure 40: Buffer Program Flowchart

Bus

Operation

Command

Comments

Data = E8H

Write to

Buffer

Write

Read

Addr = Block Address

Start

SR.7 = Valid

Addr = Block Address

Device

Check SR.7

1 = Device WSM is Busy

0 = Device WSM is Ready

Use Single Word

Supports Buffer

Standby

No

Programming

Writes?

Yes

Data = N-1 = Word Count

N = 0 corresponds to count = 1

Addr = Block Address

Write

(Notes1, 2)

Set Timeout or

Loop Counter

Write

(Notes3, 4)

Data = Write Buffer Data

Addr = Start Address

Get Next

Target Address

Write

(Notes5, 6)

Data = Write Buffer Data

Addr = Block Address

Issue Write to Buffer

Command E8h and

Block Address

Program

Confirm

Data = D0H

Addr = Block Address

Write

Read

Status register Data

CE# and OE# low updates SR

Addr = Block Address

Read Status Register

(at Block Address)

Check SR.7

1 = WSM Ready

0 = WSM Busy

No

Standby

Timeout

or Count

Expired?

0 = No

Is WSM Ready?

SR.7 =

1. Word count values on DQ₀-DQ₇are loaded into the Count

register. Count ranges for this device are N = 0000h to 0001Fh.

2. The device outputs the status register when read.

3. Write Buffer contents will be programmed at the device start

address or destination flash address.

Yes

1 = Yes

Write Word Count,

Block Address

4. Align the start address on a Write Buffer boundary for

maximum programming performance(i.e., A₄–A₀of the start

address = 0).

Write Buffer Data,

Start Address

5. The device aborts the Buffered Program command if the

current address is outside the original block address.

6. The Status register indicates an "improper command

sequence" if the Buffered Program command is aborted. Follow

this with a Clear Status Register command.

X = X + 1

Write Buffer Data,

Block Address

X = 0

Full status check can be done after all erase and write

sequences complete. Write FFh after the last operation to reset

the device to read array mode.

No

Abort Bufferred

Program?

X = N?

Yes

Write Confirm D0h

and Block Address

Write to another

Block Address

Buffered Program

Aborted

Read Status Register

No

Suspend

Program

Loop

Yes

0

Suspend

Program

SR.7 =?

Full Status

Check if Desired

1

Yes

Another Buffered

Programming?

No

Program Complete

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Datasheet

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Figure 41: BEFP Flowchart

BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE

Setup Phase

Program & Verify Phase

Exit Phase

Read

Status Reg.

Read

Status Reg.

Start

V_PPapplied

Block Unlocked

No (SR[7]=0)

BEFP

Exited?

No (SR[0]=1)

Data Stream

Ready?

Yes (SR[0]=0)

Yes (SR[7]=1)

Write 80h @

1^stWord Address

Initialize Count:

X = 0

Full Status Check

Procedure

Write D0h @

1^stWord Address

Write Data @ 1^st

Word Address

Program

Complete

BEFP Setup delay

Increment Count:

X = X+1

Read

Status Reg.

N

Check

X = 32?

Yes (SR[7]=0)

Y

BEFP Setup

Done?

Read

No (SR[7]=1)

Status Reg.

No (SR[0]=1)

Check V_PP, Lock

errors (SR[3,1])

Program

Done?

Yes (SR[0]=0)

Exit

N

Last

Data?

Y

Write 0xFFFF,

Address Not within

Current Block

BEFP Setup

BEFP Program & Verify

BEFP Exit

Operation Comments

Bus

State

Bus

State

Bus

State

Operation

Comments

Operation

Comments

Unlock

Block

Status

Register

Data = Status Register Data

Address = 1^stWord Addr.

Status

Register

Data = Status Register Data

Address = 1^stWord Addr.

Read

Write

V_PPHapplied to VPP

Read

Write

(Note 1)

BEFP

Setup

Data = 0x80 @ 1^stWord

Address

Data = 0x80 @ 1^stWord

Address¹

Check SR[0]:

0 = Ready for Data

1 = Not Ready for Data

Check

Exit

Status

Check SR[7]:

0 = Exit Not Completed

1 = Exit Completed

Data Stream

Ready?

Standby

BEFP

Confirm

Write

Read

Initialize

Count

Repeat for subsequent blocks ;

X = 0

Status

Register

Data = Status Register Data

Address = 1^stWord Addr.

After BEFP exit, a full Status Register check can

determine if any program error occurred;

Write

(note 2)

Load

Buffer

Data = Data to Program

Address = 1^stWord Addr.

BEFP

Setup

Done?

Check SR[7]:

0 = BEFP Ready

1 = BEFP Not Ready

Standby

Increment

Count

See full Status Register check procedure in the

Word Program flowchart.

Standby

Read

X = X+1

X = 32?

Yes = Read SR[0]

No = Load Next Data Word

Error

Condition

Check

If SR[7] is set, check:

SR[3] set = V_PPError

SR[1] set = Locked Block

Buffer

Full?

Write 0xFF to enter Read Array state.

Status

Register

Data = Status Reg. Data

Address = 1^stWord Addr.

Check SR[0]:

0 = Program Done

1 = Program in Progress

Program

Done?

Standby

Last

Data?

No = Fill buffer again

Yes = Exit

Standby

Write

Exit Prog & Data = 0xFFFF @ address

Verify Phase not in current block

NOTES:

1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary.

2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing).

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Figure 42: Block Erase Flowchart

BLOCK ERASE PROCEDURE

Bus

Operation

Start

Command

Comments

Block

Erase

Setup

Data = 0x20

Addr = Block to be erased (BA)

Write

Read

Write 0x20,

Block Address

(Block Erase)

Erase Data = 0xD0

Confirm Addr = Block to be erased (BA)

Write 0xD0,

Block Address

(Erase Confirm)

None

Status Register data.

Suspend

Erase

Loop

Read Status

Register

Check SR[7]:

1 = WSM ready

0 = WSM busy

Idle

No

Suspend

Erase

0

Yes

SR[7] =

1

Repeat for subsequent block erasures.

Full Status register check can be done after each block erase

or after a sequence of block erasures.

Full Erase

Status Check

(if desired)

Write 0xFF after the last operation to enter read array mode.

Block Erase

Complete

FULL ERASE STATUS CHECK PROCEDURE

Read Status

Register

Bus

Command

Operation

Comments

Check SR[3]:

1 = V_PPRange Error

Idle

None

1

V_PPRange

Error

SR[3] =

0

Check SR[4,5]:

Both 1 = Command Sequence Error

1,1

1

Command

Sequence Error

Check SR[5]:

1 = Block Erase Error

SR[4,5] =

0

Check SR[1]:

1 = Attempted erase of locked block;

erase aborted.

Block Erase

Error

Idle

None

SR[5] =

0

Only the Clear Status Register command clears SR[1, 3, 4, 5].

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

1

Block Locked

Error

SR[1] =

0

Block Erase

Successful

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Datasheet

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Figure 43: Erase Suspend/Resume Flowchart

ERASE SUSPEND / RESUME PROCEDURE

Bus

Operation

Start

Command

Comments

Read Status

Write 70h

Any Address

Read

Data = 70h

Write

Status Addr = Any device address

Data = B0h

Addr = Same partition address as

Erase

Suspend

above

Erase Suspend

Write B0h

Any Address

Status register data. Toggle CE# or

OE# to update Status register

Addr =X

Read

Read Status

Register

Check SR.7

Standby

1 = WSM ready

0 = WSM busy

0

SR.7 =

1

Check SR.6

1 = Erase suspended

0 = Erase completed

Standby

Write

Erase

Completed

SR.6 =

1

Read Array Data = FFh or 40h

or Program Addr = Block to program or read

Read or

Write

Read array or program data from/to

block other than the one being erased

Read

Program

Read or

Program ?

Read Array

Data

Program

Loop

Program Data = D0h

Resume Addr = Any address

No

Write

Done?

Yes

Erase Resume

Read Array

Write D0h

Write FFh

Any Address

Any Addres

Erase

Resumed

Read Array

Data

Read Status

Write 70h

Any Address

ERAS_SUS.WMF

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Figure 44: Block Lock Operations Flowchart

LOCKING OPERATIONS PROCEDURE

Bus

Operation

Start

Command

Comments

Lock Setup

Write 60h

Block Address

Lock

Setup

Data = 60h

Addr = Block to lock/unlock/lock-down (BA)

Write

Lock,

Unlock, or

Lockdown

Data = 01h (Lock block)

D0h (Unlock block)

Lock Confirm

Write 01,D0,2Fh

Block Address

2Fh (Lockdown block)

Confirm Addr = Block to lock/unlock/lock-down (BA)

Read ID Plane

Write 90h

Write

(Optional)

Read ID Data = 90h

Plane

Addr = Block address offset+2 (BA+2)

Read

(Optional)

Block Lock Block Lock status data

Status Addr = Block address offset+2 (BA+2)

Read Block Lock

Status

Confirm locking change on DQ , DQ₀.

(See Block Locking State Transitions Table

for valid combinations.)

1

Standby

(Optional)

Locking

No

Change?

Yes

Read

Array

Data = FFh

Addr = Block address (BA)

Write

Read Array

Write FFh

Any Address

Lock Change

Complete

LOCK_OP.WMF

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Datasheet

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Figure 45: Protection Register Programming Flowchart

PROTECTION REGISTER PROGRAMMING PROCEDURE

Bus

Operation

Start

Command

Comments

Program Data = 0xC0

PR Setup Addr = First Location to Program

Write

Write 0xC0,

PR Address

(Program Setup)

(Confirm Data)

Protection Data = Data to Program

Program Addr = Location to Program

Write

Read

Write PR

Address & Data

None

Status Register Data.

Read Status

Register

Check SR[7]:

1 = WSM Ready

0 = WSM Busy

Idle

Program Protection Register operation addresses must be

within the Protection Register address space. Addresses

outside this space will return an error.

0

SR[7] =

1

Repeat for subsequent programming operations.

Full Status

Check

(if desired)

Full Status Register check can be done after each program, or

after a sequence of program operations.

Write 0xFF after the last operation to set Read Array state.

Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status

Register Data

Bus

Operation

Command

Comments

Check SR[3]:

1 =V_PPRange Error

Idle

None

1

SR[3] =

0

V_PPRange Error

Check SR[4]:

1 =Programming Error

None

Check SR[1]:

1 =Block locked; operation aborted

SR[4] =

0

Program Error

Only the Clear Staus Register command clears SR[1, 3, 4].

If an error is detected, clear the Status register before

attempting a program retry or other error recovery.

Register Locked;

Program Aborted

SR[1] =

0

Program

Successful

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Appendix C Common Flash Interface

The Common Flash Interface (CFI) is part of an overall specification for multiple

command-set and control-interface descriptions. This appendix describes the database

structure containing the data returned by a read operation after issuing the CFI Query

command (see Section 9.2, “Device Commands” on page 45). System software can

parse this database structure to obtain information about the flash device, such as

block size, density, bus width, and electrical specifications. The system software will

then know which command set(s) to use to properly perform flash writes, block erases,

reads and otherwise control the flash device.

C.1

Query Structure Output

The Query database allows system software to obtain information for controlling the

flash device. This section describes the device’s CFI-compliant interface that allows

access to Query data.

Query data are presented on the lowest-order data outputs (DQ_7-0) only. The numerical

offset value is the address relative to the maximum bus width supported by the device.

On this family of devices, the Query table device starting address is a 10h, which is a

word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device

outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ_7-0

)

and 00h in the high byte (DQ_15-8).

At Query addresses containing two or more bytes of information, the least significant

data byte is presented at the lower address, and the most significant data byte is

presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal

notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-

wide devices is always “00h,” the leading “00” has been dropped from the table

notation and only the lower byte value is shown. Any x16 device outputs can be

assumed to have 00h on the upper byte in this mode.

Table 35: Summary of Query Structure Output as a Function of Device and Mode

Hex

Code

51

52

59

ASCII

Value

"Q"

"R"

"Y"

Device

Offset

00010:

00011:

00012:

Device Addresses

November 2007

Order Number: 306666-11

Datasheet

87

P30

Table 36: Example of Query Structure Output of x16- Devices

Word Addressing:

Byte Addressing:

Offset

A_X–A₀

Hex Code

Value

Offset

A_X–A₀

Hex Code

Value

D₁₅–D₀

D₇–D₀

00010h

00011h

00012h

00013h

00014h

00015h

00016h

00017h

00018h

...

0051

0052

0059

P_ID_LO

P_ID_HI

P_LO

"Q"

"R"

"Y"

00010h

00011h

00012h

00013h

00014h

00015h

00016h

00017h

00018h

...

51

52

59

P_ID_LO

P_ID_HI

...

"Q"

"R"

"Y"

PrVendor

ID #

PrVendor

TblAdr

AltVendor

ID #

PrVendor

ID #

P_HI

...

A_ID_LO

A_ID_HI

...

C.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash

Interface (CFI) Query structure or “database.” The structure sub-sections and address

locations are summarized below.

Table 37: Query Structure

Description⁽¹⁾

Offset

Sub-Section Name

00001-Fh Reserved

Reserved for vendor-specific information

Command set ID and vendor data offset

Device timing & voltage information

Flash device layout

00010h

0001Bh

00027h

CFI query identification string

System interface information

Device geometry definition

Vendor-defined additional information specific

to the Primary Vendor Algorithm

P⁽³⁾

Primary Intel-specific Extended Query Table

Notes:

1.

Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of

device bus width and mode.

2.

3.

BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).

Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.

C.3

CFI Query Identification String

The Identification String provides verification that the component supports the

Common Flash Interface specification. It also indicates the specification version and

supported vendor-specified command set(s).

Table 38: CFI Identification

Hex

Offset Length

Description

Query-unique ASCII string “QRY“

Add. Code Value

3

10:

11:

12:

13:

14:

15:

16:

17:

18:

19:

1A:

10h

--51

--52

--59

--01

--00

--0A

--01

--00

"Q"

"R"

"Y"

2

Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specified algorithms

Extended Query Table primary algorithm address

13h

15h

17h

19h

Alternate vendor command set and control interface ID code.

0000h means no second vendor-specified algorithm exists

Secondary algorithm Extended Query Table address.

0000h means none exists

Datasheet

88

November 2007

Order Number: 306666-11

P30

Table 39: System Interface Information

Hex

Code

--17

Offset

Length

Description

Add.

1B:

Value

1.7V

1Bh

1

V

_CClogic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1Ch

1Dh

1Eh

1

V_CClogic supply maximum program/erase voltage

1C:

1D:

1E:

--20

--85

--95

2.0V

8.5V

9.5V

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

V

_PP[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

V_PP[programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

“n” such that typical single word program time-out = 2ⁿμ-sec

“n” such that typical max. buffer write time-out = 2ⁿμ-sec

“n” such that typical block erase time-out = 2ⁿm-sec

“n” such that typical full chip erase time-out = 2ⁿm-sec

“n” such that maximum word program time-out = 2ⁿtimes typical

“n” such that maximum buffer write time-out = 2ⁿtimes typical

“n” such that maximum block erase time-out = 2ⁿtimes typical

“n” such that maximum chip erase time-out = 2ⁿtimes typical

1Fh

20h

21h

22h

23h

24h

25h

26h

1

1F:

20:

21:

22:

23:

24:

25:

26:

--08 256μs

--09 512μs

--0A

--00

1s

NA

--01 512μs

--01 1024μs

--02

--00

4s

NA

November 2007

Order Number: 306666-11

Datasheet

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P30

C.4

Device Geometry Definition

Table 40: Device Geometry Definition

Offset

27h

Length

Description

Code

See table below

“n” such that device size = 2ⁿin number of bytes

Flash device interface code assignment:

1

27:

28:

"n" such that n+1 specifies the bit field that represents the flash

device width capabilities as described in the table:

7

6

5

4

3

2

1

x16

9

0

x8

8

28h

2

—

15

—

14

—

13

—

12

—

x64

11

x32

10

--01

x16

64

—

29:

2A:

2B:

2C:

--00

--06

--00

“n” such that maximum number of bytes in write buffer = 2ⁿ

2

1

2Ah

2Ch

Number of erase block regions (x) within device:

1. x = 0 means no erase blocking; the device erases in bulk

2. x specifies the number of device regions with one or

more contiguous same-size erase blocks.

See table below

3. Symmetrically blocked partitions have one blocking region

Erase Block Region 1 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

4

2Dh

31h

35h

2D:

2E:

2F:

30:

31:

32:

33:

34:

35:

36:

37:

38:

See table below

Erase Block Region 2 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

Reserved for future erase block region information

Address

64-Mbit

128-Mbit

256-Mbit

–B

–T

–B

–T

–B

–T

27:

28:

29:

2A:

2B:

2C:

2D:

2E:

2F:

30:

31:

32:

33:

34:

35:

36:

37:

38:

--17

--01

--00

--06

--00

--02

--03

--00

--80

--00

--3E

--00

--02

--00

--17

--01

--00

--06

--00

--02

--3E

--00

--02

--03

--00

--80

--00

--18

--01

--00

--06

--00

--02

--03

--00

--80

--00

--7E

--00

--02

--00

--18

--01

--00

--06

--00

--02

--7E

--00

--02

--03

--00

--80

--00

--19

--01

--00

--06

--00

--02

--03

--00

--80

--00

--FE

--00

--02

--00

--19

--01

--00

--06

--00

--02

--FE

--00

--02

--03

--00

--80

--00

Datasheet

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Order Number: 306666-11

P30

C.5

Numonyx-Specific Extended Query Table

Table 41: Primary Vendor-Specific Extended Query

Offset⁽¹⁾

Hex

Length

Description

P = 10Ah

(Optional flash features and commands)

Add. Code Value

(P+0)h

(P+1)h

(P+2)h

(P+3)h

(P+4)h

(P+5)h

(P+6)h

(P+7)h

(P+8)h

3

Primary extended query table

Unique ASCII string “PRI“

10A

10B:

10C:

10D:

10E:

10F:

110:

111:

--50

--52

--49

--31

--34

--E6

--01

--00

"P"

"R"

"I"

"1"

"4"

1

4

Major version number, ASCII

Minor version number, ASCII

Optional feature and command support (1=yes, 0=no)

bits 11–29 are reserved; undefined bits are “0.” If bit 31 is

“1” then another 31 bit field of Optional features follows at

the end of the bit–30 field.

112: See table below

bit 0 Chip erase supported

bit 1 Suspend erase supported

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

bit 5 Instant individual block locking supported

bit 6 Protection bits supported

bit 7 Pagemode read supported

bit 8 Synchronous read supported

bit 9 Simultaneous operations supported

bit 10 Extended Flash Array Blocks supported

bit 0 = 0

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 1

bit 8 = 1

bit 9 = 0

bit 10 = 0

No

Yes

No

Yes

No

See

table

below

bit 30 CFI Link(s) to follow

bit 30

bit 31

bit 31 Another "Optional Features" field to follow

(P+9)h

1

2

Supported functions after suspend: read Array, Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

bit 0 Program supported after erase suspend

Block status register mask

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status register active

bit 1 Block Lock-Down Bit Status active

bit 4 EFA Block Lock-Bit Status register active

bit 5 EFA Block Lock-Down Bit Status active

V_CClogic supply highest performance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

113:

--01

bit 0 = 1

114:

115:

Yes

(P+A)h

(P+B)h

--03

--00

bit 0 = 1

Yes

No

1.8V

bit 1 = 1

bit 4 = 0

bit 5 = 0

(P+C)h

(P+D)h

1

116:

--18

V_PPoptimum program/erase supply voltage

117:

--90

9.0V

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

Discrete

512-Mbit

Address

112:

–B

–T

–-

–B

die 1 (B) die 2 (T) die 1 (T) die 2 (B)

--40 --00 --40 --00

–T

–-

--00

November 2007

Order Number: 306666-11

Datasheet

91

P30

Table 42: Protection Register Information

Offset⁽¹⁾

Length

P = 10Ah

Hex

Add. Code Value

Description

(Optional flash features and commands)

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection fields are available

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) Protection register bytes. Some are pre-programmed

with device-unique serial numbers. Others are user

programmable. Bits 0–15 point to the Protection register Lock

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

(P+E)h

1

4

118: --02

2

(P+F)h

(P+10)h

(P+11)h

(P+12)h

119: --80

11A: --00

80h

00h

11B: --03 8 byte

11C: --03 8 byte

bits 0–7 = Lock/bytes Jedec-plane physical low address

bits 8–15 = Lock/bytes Jedec-plane physical high address

bits 16–23 = “n” such that 2ⁿ= factory pre-programmed bytes

bits 24–31 = “n” such that 2ⁿ= user programmable bytes

(P+13)h

(P+14)h

(P+15)h

(P+16)h

(P+17)h

(P+18)h

(P+19)h

(P+1A)h

(P+1B)h

(P+1C)h

10

Protection Field 2: Protection Description

Bits 0–31 point to the Protection register physical Lock-word

address in the Jedec-plane.

Following bytes are factory or user-programmable.

bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte)

bits 40–47 = “n” ∴ n = factory pgm'd groups (high byte)

bits 48–55 = “n” \ 2n = factory programmable bytes/group

bits 56–63 = “n” ∴ n = user pgm'd groups (low byte)

11D: --89

11E: --00

11F: --00

120: --00

89h

00h

0

16

0

16

--00

121:

122:

123:

124: --10

--00

125:

126:

∴

bits 64–71 = “n” n = user pgm'd groups (high byte)

n

∴

bits 72–79 = “n” 2 = user programmable bytes/group

--04

Table 43: Burst Read Information

Offset⁽¹⁾

Hex

Length

Description

P = 10Ah

(Optional flash features and commands)

Add. Code Value

(P+1D)h

1

Page Mode Read capability

127: --03 8 byte

bits 0–7 = “n” such that 2ⁿHEX value represents the number of

read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capability.

Synchronous mode read capability configuration 1

Bits 3–7 = Reserved

(P+1E)h

(P+1F)h

1

128: --04

129: --01

4

bits 0–2 “n” such that 2ⁿ⁺¹HEX value represents the

maximum number of continuous synchronous reads when

the device is configured for its maximum word width. A value

of 07h indicates that the device is capable of continuous

linear bursts that will output data until the internal burst

counter reaches the end of the device’s burstable address

space. This field’s 3-bit value can be written directly to the

Read Configuration Register bits 0–2 if the device is

configured for its maximum word width. See offset 28h for

word width to determine the burst data output width.

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Synchronous mode read capability configuration 4

(P+20)h

(P+21)h

(P+22)h

1

12A: --02

12B: --03

12C: --07

8

16

Cont

Datasheet

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P30

Table 44: Partition and Erase Block Region Information

Offset⁽¹⁾

P = 10Ah

See table below

Address

Description

Bot

Top

Bottom

Top

(Optional flash features and commands)

Len

Number of device hardware-partition regions within the device.

x = 0: a single hardware partition device (no fields follow).

x specifies the number of device partition regions containing

one or more contiguous erase block regions.

1

12D:

(P+23)h (P+23)h

Table 45: Partition Region 1 Information

Offset⁽¹⁾

P = 10Ah

See table below

Address

Description

Bot

12E:

12F

130:

131:

132:

Top

Bottom

(P+24)h (P+24)h

Top

(Optional flash features and commands)

Len

2

Data size of this Parition Region Information field

(P+25)h (P+25)h (# addressable locations, including this field)

12E

12F

130:

131:

132:

Number of identical partitions within the partition region

2

1

(P+26)h (P+26)h

(P+27)h (P+27)h

(P+28)h (P+28)h Number of program or erase operations allowed in a partition

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

(P+29)h (P+29)h Simultaneous program or erase operations allowed in other partitions while a

partition in this region is in Program mode

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

(P+2A)h (P+2A)h Simultaneous program or erase operations allowed in other partitions while a

partition in this region is in Erase mode

1

133:

134:

135:

133:

134:

135:

bits 0–3 = number of simultaneous Program operations

bits 4–7 = number of simultaneous Erase operations

(P+2B)h (P+2B)h Types of erase block regions in this Partition Region.

x = 0 = no erase blocking; the Partition Region erases in bulk

x = number of erase block regions w/ contiguous same-size

erase blocks. Symmetrically blocked partitions have one

blocking region. Partition size = (Type 1 blocks)x(Type 1

block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+

(Type n blocks)x(Type n block sizes)

November 2007

Order Number: 306666-11

Datasheet

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P30

Table 46: Partition Region 1 Information (continued)

Offset⁽¹⁾

P = 10Ah

See table below

Address

Description

Bot

Top

136:

137:

138:

139:

13A:

13B:

13C:

Bottom

Top

(Optional flash features and commands)

Len

4

(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information

(P+2D)h (P+2D)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition

(P+2E)h (P+2E)h

(P+2F)h (P+2F)h

(P+30)h (P+30)h

(P+31)h (P+31)h

136:

137:

138:

139:

13A:

13B:

13C:

bits 16–31 = z, region erase block(s) size are z x 256 bytes

Partition 1 (Erase Block Type 1)

Block erase cycles x 1000

2

1

(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC

bits 0–3 = bits per cell in erase region

bit 4 = internal EDAC used (1=yes, 0=no)

bits 5–7 = reserve for future use

(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities

defined in Table 10.

1

6

13D:

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = synchronous host writes permitted (1=yes, 0=no)

bits 3–7 = reserved for future use

Partition Region 1 (Erase Block Type 1) Programming Region Information

(P+34)h (P+34)h

(P+35)h (P+35)h

(P+36)h (P+36)h

(P+37)h (P+37)h

(P+38)h (P+38)h

(P+39)h (P+39)h

13E:

13F:

140:

141:

142:

143:

144:

145:

146:

147:

148:

149:

14A:

bits 0–7 = x, 2^x = Programming Region aligned size (bytes)

bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)

bits 16–23 = y = Control Mode valid size in bytes

13E:

13F:

140:

141:

142:

143:

144:

145:

146:

147:

148:

149:

14A:

bits 24-31 = Reserved

bits 32-39 = z = Control Mode invalid size in bytes

bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)

(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information

(P+3B)h (P+3B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition

(P+3C)h (P+3C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes

(P+3D)h (P+3D)h

(P+3E)h (P+3E)h

(P+3F)h (P+3F)h

4

Partition 1 (Erase Block Type 2)

Block erase cycles x 1000

2

1

(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC

bits 0–3 = bits per cell in erase region

bit 4 = internal EDAC used (1=yes, 0=no)

bits 5–7 = reserve for future use

(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities

defined in Table 10.

1

6

14B:

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bit 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = synchronous host writes permitted (1=yes, 0=no)

bits 3–7 = reserved for future use

Partition Region 1 (Erase Block Type 2) Programming Region Information

(P+42)h (P+42)h

(P+43)h (P+43)h

(P+44)h (P+44)h

(P+45)h (P+45)h

(P+46)h (P+46)h

(P+47)h (P+47)h

14C:

14D:

14E:

14F:

150:

151:

bits 0–7 = x, 2^x = Programming Region aligned size (bytes)

bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)

bits 16–23 = y = Control Mode valid size in bytes

14C:

14D:

14E:

14F:

150:

151:

bits 24-31 = Reserved

bits 32-39 = z = Control Mode invalid size in bytes

bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)

Datasheet

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November 2007

Order Number: 306666-11

P30

Table 47: Partition and Erase Block Region Information

Address

64-Mbit

128-Mbit

256-Mbit

–B

–T

–B

–T

–B

–T

12D:

12E:

12F:

130:

131:

132:

133:

134:

135:

136:

137:

138:

139:

13A:

13B:

13C:

13D:

13E:

13F:

140:

141:

142:

143:

144:

145:

146:

147:

148:

149:

14A:

14B:

14C:

14D:

14E:

14F:

150:

151:

--01

--24

--00

--01

--00

--11

--00

--02

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--3E

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--01

--24

--00

--01

--00

--11

--00

--02

--3E

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--01

--24

--00

--01

--00

--11

--00

--02

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--7E

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--01

--24

--00

--01

--00

--11

--00

--02

--7E

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--01

--24

--00

--01

--00

--11

--00

--02

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--FE

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--01

--24

--00

--01

--00

--11

--00

--02

--FE

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

November 2007

Order Number: 306666-11

Datasheet

95

P30

Table 48: CFI Link Information

Offset⁽¹⁾

Length

Hex

Description

P = 10Ah

(Optional flash features and commands)

CFI Link Field bit definitions

Add.

152:

153:

154:

155:

Code

Value

(P+48)h

(P+49)h

(P+4A)h

(P+4B)h

4

Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table

Bits 10–27 = nth 32Mbit segment of referenced CFI table

Bits 28–30 = Memory Type

Bit 31 = Another CFI Link field immediately follows

CFI Link Field Quantity Subfield definitions

Bits 0–3 = Quantity field (n such that n+1 equals quantity)

Bit 4 = Table & Die relative location

See table below

(P+4C)h

1

156:

Bit 5 = Link Field & Table relative location

Bits 6–7 = Reserved

Discrete

512-Mbit

Address

–B

–-

–T

–-

–B

–T

die 1 (B)

--10

--20

--00

die 2 (T)

die 1 (T)

--10

--20

--00

die 2 (B)

--FF

152:

153:

154:

155:

156:

--FF

--10

--FF

Datasheet

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November 2007

Order Number: 306666-11

P30

Appendix D Additional Information

Order/Document

Document/Tool

Number

309045

308291

300783

290667

P30 Family Specification Update

Schematic Review Checklist for Numonyx™ StrataFlash^®Embedded Memory (P30)

Using Numonyx™ Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode

Numonyx™ StrataFlash^®Memory (J3) Datasheet

Migration Guide for Numonyx™ StrataFlash^®Memory (J3) to Numonyx™ StrataFlash^®Embedded

Memory (P30/P33) Application Note 812

306667

Numonyx™ StrataFlash^®Memory (P30) to Numonyx™ StrataFlash^®Embedded Memory (P33)

Conversion Guide Application Note 867

314750

290737

306669

Numonyx™ StrataFlash^®Synchronous Memory (K3/K18) Datasheet

Migration Guide for Numonyx™ StrataFlash^®Synchronous Memory (K3/K18) to Numonyx™

StrataFlash^®Embedded Memory (P30) Application Note 825

290701

290702

252802

298161

253418

296514

297833

298136

Numonyx™ Wireless Flash Memory (W18) Datasheet

Numonyx™ Wireless Flash Memory (W30) Datasheet

Numonyx™ Flash Memory Design for a Stacked Chip Scale Package (SCSP)

Numonyx™ Flash Memory Chip Scale Package User’s Guide

Numonyx™ Wireless Communications and Computing Package User's Guide

Numonyx™ Small Outline Package Guide

Numonyx™ Flash Data Integrator (Numonyx™ FDI) User Guide

Numonyx™ Persistent Storage Manager (Numonyx™ PSM) User Guide

Migration Guide for Spansion* S29GLxxxN to Numonyx™ StrataFlash^®Embedded Memory (P30/P33)

Application Note 813

306668

Note: Contact your local Numonyx or distribution sales office or visit Numonyx’s World Wide Web home page at http://

www.numonyx.com for technical documentation, tools, or the most current information on Numonyx™ Flash Memory.

November 2007

Order Number: 306666-11

Datasheet

97

P30

Appendix E Ordering Information for Discrete Products

Figure 46: Decoder for Discrete P30

T E 2 8 F 6 4 0 P 3 0 B 8 5

Access Speed

Package Designator

85 ns

TE = 56-Lead TSOP, leaded

JS = 56-Lead TSOP, lead-free

RC = 64-Ball Easy BGA, leaded

PC = 64-Ball Easy BGA, lead-free

Parameter Location

B = Bottom Parameter

T = Top Parameter

Product Line Designator

28F = Intel® Flash Memory

Product Family

P30 = Intel StrataFlash® Embedded Memory

V_CC= 1.7 – 2.0 V

V_CCQ= 1.7 – 3.6 V

Device Density

640 = 64-Mbit

128 = 128-Mbit

256 = 256-Mbit

Table 49: Valid Combinations for Discrete Products

64-Mbit

128-Mbit

256-Mbit

TE28F640P30B85

TE28F640P30T85

JS28F640P30B85

JS28F640P30T85

RC28F640P30B85

RC28F640P30T85

PC28F640P30B85

PC28F640P30T85

TE28F128P30B85

TE28F128P30T85

JS28F128P30B85

JS28F128P30T85

RC28F128P30B85

RC28F128P30T85

PC28F128P30B85

PC28F128P30T85

TE28F256P30B95

TE28F256P30T95

JS28F256P30B95

JS28F256P30T95

RC28F256P30B85

RC28F256P30T85

PC28F256P30B85

PC28F256P30T85

Datasheet

98

November 2007

Order Number: 306666-11

P30

Appendix F Ordering Information for SCSP Products

Figure 47: Decoder for SCSP P30

R D 4 8 F 4 0 0 0 P 0 Z B Q 0

Package Designator

RD = Intel^®SCSP, leaded

Device Details

PF = Intel^®SCSP, lead-free

0 = Original version of the product

RC = 64-Ball Easy BGA, leaded

PC = 64-Ball Easy BGA, lead-free

datasheet for details)

TE = 56-Lead TSOP, leaded

(refer to the latest version of the

JS = 56-Lead TSOP, lead-free

Ballout Designator

Q = QUAD+ ballout

Group Designator

48F = Flash Memory only

0 = Discrete ballout

Flash Density

0 = No die

2 = 64-Mbit

Parameter, Mux Configuration

B = Bottom Parameter, Non Mux

T = Top Parameter, Non Mux

3 = 128-Mbit

4 = 256-Mbit

I/O Voltage, CE# Configuration

Z = Individual Chip Enable(s)

V = Virtual Chip Enable(s)

V_CC= 1.7 V – 2.0 V

Product Family

P = Intel StrataFlash® Embedded Memory

0 = No die

V_CCQ= 1.7 V – 3.6 V

Note: For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations.

Table 50: Valid Combinations for Dual- Die Products

64-Mbit

128-Mbit

256-Mbit

512-Mbit^*

RD48F2000P0ZBQ0

RD48F2000P0ZTQ0

PF48F2000P0ZBQ0

PF48F2000P0ZTQ0

RD48F3000P0ZBQ0

RD48F3000P0ZTQ0

PF48F3000P0ZBQ0

PF48F3000P0ZTQ0

RD48F4000P0ZBQ0

RD48F4000P0ZTQ0

PF48F4000P0ZBQ0

PF48F4000P0ZTQ0

RD48F4400P0VBQ0

PF48F4400P0VBQ0

RC48F4400P0VB00

PC48F4400P0VB00

TE48F4400P0VB00

JS48F4400P0VB00

Note: * The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density.

November 2007

Order Number: 306666-11

Datasheet

99


型号：	PC28F640P30T85
厂家：	NUMONYX B.V
描述：	Numonyx StrataFlash Embedded Memory 恒忆的StrataFlash嵌入式存储器存储
文件：	总99页 (文件大小：1401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC28F640P30T85 [NUMONYX]

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