PF38F5070M0R0C0 [NUMONYX]
StrataFlash㈢ Cellular Memory; StrataFlash㈢蜂窝内存
| 型号： | PF38F5070M0R0C0 |
| 厂家： | 
NUMONYX B.V |
| 描述： | StrataFlash㈢ Cellular Memory |
| 文件： | 总139页 (文件大小：2135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Numonyx™ StrataFlash Cellular Memory
(M18)
Datasheet
Product Features
High-Performance Read, Program and Erase
Power
— Core voltage: 1.7 V - 2.0 V
— 96 ns initial read access
— 108 MHz with zero wait-state synchronous
burst reads: 7 ns clock-to-data output
— 133 MHz with zero wait-state synchronous
burst reads: 5.5 ns clock-to-data output
— 8-, 16-, and continuous-word
synchronous-burst Reads
— Programmable WAIT configuration
— Customer-configurable output driver
impedance
— Buffered Programming:
— I/O voltage: 1.7 V - 2.0 V
— Standby current: 60 µA (typ) for 512-Mbit,
65 nm
— Deep Power-Down mode: 2 µA (typ)
— Automatic Power Savings mode
— 16-word synchronous-burst read current:
23 mA (typ) @ 108 MHz; 24 mA (typ) @
133 MHz
Software
— Numonyx™ Flash Data Integrator
(Numonyx™ FDI) optimized
— Basic Command Set and Extended
Command Set compatible
2.0 µs/Word (typ), 512-Mbit 65 nm;
Block Erase: 0.9 s per block (typ)
— 20 µs (typ) program/erase suspend
Architecture
— Common Flash Interface
— 16-bit wide data bus
— Multi-Level Cell Technology
Security
— OTP Registers:
— Symmetrically-Blocked Array Architecture
— 256-Kbyte Erase Blocks
64 unique pre-programmed bits
2112 user-programmable bits
— Absolute write protection with VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— 1-Gbit device: Eight 128-Mbit partitions
— 512-Mbit device: Eight 64-Mbit partitions
— 256-Mbit device: Eight 32-Mbit partitions.
— 128-Mbit device: Eight 16-Mbit partitions.
— Read-While-Program and Read-While-Erase
— Status Register for partition/device status
— Blank Check feature
Density and Packaging
— Density: 128-, 256-, and 512-Mbit, and 1-
Gbit
— Address-data multiplexed and non-
multiplexed interfaces
— x16D (105-ball) Flash SCSP
— x16C (107-ball) Flash SCSP
— 0.8 mm pitch lead-free solder-ball
Quality and Reliability
— Expanded temperature: –30 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ X Process Technology (65 nm)
— ETOX™ IX Process Technology (90 nm)
Order Number: 309823-11
April 2008
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet
2
April 2008
Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
Contents
1.0 Introduction..............................................................................................................8
1.1
1.2
1.3
1.4
Document Purpose ..............................................................................................8
Nomenclature.....................................................................................................8
Acronyms...........................................................................................................8
Conventions .......................................................................................................9
2.0 Functional Description............................................................................................. 10
2.1
2.2
2.3
Product Overview.............................................................................................. 10
Configuration and Memory Map........................................................................... 11
Device ID......................................................................................................... 12
3.0 Package Information...............................................................................................13
4.0 Ballouts and Signal Descriptions.............................................................................. 23
4.1
Ballouts, x16D .................................................................................................. 23
4.1.1 x16D (105-Ball) Ballout, Non-Mux ............................................................ 23
4.1.2 x16D (105-Ball) Ballout, AD-Mux.............................................................. 24
4.1.3 x16D Mux (105-Ball) Ballout, AA/D Mux .................................................... 25
Signal Descriptions, x16D................................................................................... 26
Ballouts, x16C .................................................................................................. 29
4.3.1 x16C (107-Ball) Ballout, Non-Mux ............................................................ 29
4.3.2 x16C (107-Ball) Ballout, AD-Mux.............................................................. 31
4.3.3 x16C (107-Ball) Ballout, AA/D-Mux...........................................................32
Signal Descriptions x16C.................................................................................... 33
Ballouts, x16 Split Bus.......................................................................................37
4.5.1 x16 Split Bus (165-Ball) Ballout, Non-Mux .................................................37
Signal Descriptions, x16 Split Bus........................................................................38
4.2
4.3
4.4
4.5
4.6
5.0 Maximum Ratings and Operating Conditions............................................................ 42
5.1
5.2
Absolute Maximum Ratings.................................................................................42
Operating Conditions .........................................................................................42
6.0 Electrical Characteristics .........................................................................................43
6.1
Initialization ..................................................................................................... 43
6.1.1 Power-Up/Down Characteristics................................................................43
6.1.2 Reset Characteristics .............................................................................. 43
6.1.3 Power Supply Decoupling ........................................................................43
DC Current Specifications................................................................................... 44
DC Voltage Specifications................................................................................... 46
Capacitance......................................................................................................47
6.2
6.3
6.4
7.0 NOR Flash AC Characteristics................................................................................... 48
7.1
7.2
AC Test Conditions ............................................................................................ 48
Read Specifications............................................................................................ 49
7.2.1 Read Timing Waveforms..........................................................................52
7.2.2 Timings: Non-Mux Device, Async Read...................................................... 53
7.2.3 Timings: Non-Mux Device, Sync Read ....................................................... 54
7.2.4 Timings: AD-Mux Device, Async Read ....................................................... 57
7.2.5 Timings: AD-Mux Device, Sync Read.........................................................58
Write Specifications........................................................................................... 60
7.3.1 Write Timing Waveforms .........................................................................61
7.3.2 Timings: Non Mux Device ........................................................................62
7.3.3 Timings: AD-Mux Device .........................................................................65
Program and Erase Characteristics....................................................................... 68
7.3
7.4
April 2008
Order Number: 309823-11
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.5
7.6
Reset Specifications ...........................................................................................69
Deep Power Down Specifications..........................................................................69
8.0 NOR Flash Bus Interface ..........................................................................................71
8.1
Bus Reads ........................................................................................................71
8.1.1 Asynchronous single-word reads...............................................................72
8.1.2 Asynchronous Page Mode (Non-multiplexed devices only) ............................72
8.1.3 Synchronous Burst Mode .........................................................................72
Bus Writes........................................................................................................73
Reset ...............................................................................................................73
Deep Power-Down .............................................................................................73
Standby ...........................................................................................................74
Output Disable ..................................................................................................74
Bus Cycle Interleaving........................................................................................74
8.7.1 Read Operation During Program Buffer fill..................................................75
Read-to-Write and Write-to-Read Bus Transitions...................................................75
8.8.1 Write to Asynchronous read transition .......................................................75
8.8.2 Write to synchronous read transition .........................................................75
8.8.3 Asynchronous/Synchronous read to write transition.....................................75
8.8.4 Bus write with active clock.......................................................................75
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9.0 NOR Flash Operations ..............................................................................................76
9.1
9.2
9.3
Status Register..................................................................................................76
9.1.1 Clearing the Status Register.....................................................................77
Read Configuration Register................................................................................77
9.2.1 Latency Count........................................................................................78
Enhanced Configuration Register..........................................................................79
9.3.1 Output Driver Control..............................................................................80
9.3.2 Programming the ECR .............................................................................80
Read Operations................................................................................................81
9.4.1 Read Array ............................................................................................81
9.4.2 Read Status Register...............................................................................82
9.4.3 Read Device Information .........................................................................82
9.4.4 CFI Query..............................................................................................83
Programming Modes ..........................................................................................83
9.5.1 Control Mode .........................................................................................84
9.5.2 Object Mode ..........................................................................................85
Programming Operations ....................................................................................88
9.6.1 Single-Word Programming .......................................................................88
9.6.2 Buffered Programming ............................................................................89
9.6.3 Buffered Enhanced Factory Programming (BEFP).........................................90
Block Erase Operations.......................................................................................92
Blank Check Operation .......................................................................................93
Suspend and Resume.........................................................................................93
9.4
9.5
9.6
9.7
9.8
9.9
9.10 Simultaneous Operations....................................................................................95
9.11 Security ...........................................................................................................95
9.11.1 Block Locking.........................................................................................95
9.11.2 One-Time Programmable (OTP) Registers ..................................................97
9.11.3 Global Main-Array Protection....................................................................99
10.0 Device Command Codes .........................................................................................100
11.0 Flow Charts............................................................................................................101
12.0 Common Flash Interface........................................................................................110
12.1 Query Structure Output ....................................................................................110
12.2 Block Status Register .......................................................................................111
Datasheet
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April 2008
Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
12.3 CFI Query Identification String.......................................................................... 111
12.4 Device Geometry Definition .............................................................................. 113
12.5 Numonyx-Specific Extended Query Table............................................................ 114
13.0 Next State ............................................................................................................. 120
A
B
C
AADM Mode ........................................................................................................... 128
Additional Information .......................................................................................... 136
Ordering Information ............................................................................................ 136
April 2008
Order Number: 309823-11
Datasheet
5
Numonyx™ StrataFlash® Cellular Memory (M18)
Revision History
Date
Revision Description
14-April-06
001
002
Initial Release
Updated the template (naming and branding).
On the cover page, changed BEFP from 1.6 µs/byte (typ) to 3.2 µs/Word (typ).
28-April-06
Correced the BEFP on the cover page to read 3.2 µs/Word and synchronized the BEFP on the
cover with that in Section 7.4, “Program and Erase Characteristics” on page 68.
Added Figure 1, “Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)” on page 14 and
Figure 5, “Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2 mm)” on page 18.
Added the following line item part numbers:
—PF48F6000M0Y0BE
—PF38F6070M0Y0BE
20-June-06
003
004
—PF38F6070M0Y0VE
—PF48F6000M0Y1BE
Removed information on the 90 nm Extended Flash Array (EFA) feature that is no longer
supported.
October 2006
Revised to include 65 nm, 1-Gbit device information. Moved sections for Device ID, Additional
Information, and Order Information to Functional Description chapter. Created a separate M18
Developer’s Manual to include the following information:
—Bus Interface
—Flash Operations
—Device Command Codes
—Flow Charts
—Common Flash Interface
—Next State Table
Removed line item PF5566MMY0C0 (512+512 M18 + 128 + 128 PSRAM) and its accompanying
package (8x11x1.4, x16C 107 ball).
Added the following line items:
—PF48F6000M0Y0BE, 65 nm
—PF38F6070M0Y0BE, 65 nm
—PF38F4060M0Y0B0
November 2006
005
—PF58F0031M0Y1BE, 65 nm
—PF38F6070M0Y0C0, 65 nm
—PF38F4060M0Y0C0
—PF38F4060M0Y1C0
—PF38F6070M0Y0VE, 65 nm
Added the following packages to support new line items:
—8x10x1.0, x16D 105 ball
—11x15x1.2, x16D 105 ball
—11x11x1.2, x16C 107 ball
—8x10x1.2, x16C 107 ball
—10x11x1.2, x16SB 165 ball
November 2006
February 2007
006
007
Updated line item information.
Added the following line items and package as applicable:
PF48F4000M0Y0CE, 8x10x1.0 x16C
June 2007
March 2008
March 2007
008
009
008
Merged the Developer Manual and Datasheet content into a single document.
Updated the Performance specifications for 133MHz Capulet 1G improvements.
Updated timing diagrams in AC Characteristics section.
Datasheet
6
April 2008
Order Number: 309823-11
Numonyx™ StrataFlash® Cellular Memory (M18)
Date
Revision Description
Added note stating the value of RCR8 in timing diagrams inSection 7.2.1, “Read Timing Waveforms”
on page 52.
July 2007
009
Resized several timing diagrams in AC Characteristics section.
Updated timing diagrams Figure 31, “Async Read to Write (Non-Mux)” on page 62, Figure 36, “Async Read
to Write (AD-Mux)” on page 66 and Figure 37, “Write to Async Read (AD-Mux)” on page 66
March 2008
April 2008
010
11
Updated Program performance specs with Capulet improved performance values.
Applied Numonyx branding.
April 2008
Order Number: 309823-11
Datasheet
7
Numonyx™ StrataFlash® Cellular Memory (M18)
1.0
Introduction
Numonyx™ StrataFlash® Cellular Memory is the sixth generation Numonyx™
StrataFlash® memory with multi-level cell (MLC) technology. It provides high-
performance, low-power synchronous-burst read mode and asynchronous read mode
at 1.8 V. It features flexible, multi-partition read-while-program and read-while-erase
capability, enabling background programming or erasing in one partition
simultaneously with code execution or data reads in another partition. The eight
partitions allow flexibility for system designers to choose the size of the code and data
segments. The Numonyx™ StrataFlash® Cellular Memory is manufactured using Intel*
65 nm ETOX* X and 90 nm ETOX* IX process technology and is available in industry-
standard chip-scale packaging.
1.1
Document Purpose
This document describes the specifications of the Numonyx™ StrataFlash® Cellular
Memory device.
1.2
Nomenclature
Table 1:
Definition of Terms
Term
Definition
1.8 V
Refers to VCC and VCCQ voltage range of 1.7 V to 2.0 V
Block
A group of bits that erase with one erase command
Main Array
A group of 256-KB blocks used for storing code or data
Partition
A group of blocks that share common program and erase circuitry and command status register
Programming Region
An aligned 1-KB section within the main array
Segment
Byte
Word
Kb
A 32-byte section within the programming region
8 bits
2 bytes = 16 bits
1024 bits
KB
1024 bytes
KW
1024 words
1,048,576 bits
1,048,576 bytes
Mb
MB
1.3
Acronyms
Table 2:
List of Acronyms
Acronym
Meaning
APS
CFI
DU
Automatic Power Savings
Common Flash Interface
Don’t Use
ECR
Enhanced Configuration Register (Flash)
Datasheet
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April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 2:
List of Acronyms
Acronym
Meaning
ETOX
FDI
EPROM Tunnel Oxide
Numonyx™ Flash Data Integrator
Read Configuration Register (Flash)
Reserved for Future Use
RCR
RFU
SCSP
Stacked Chip Scale Package
1.4
Conventions
Table 3:
Datasheet Conventions
Convention
Meaning
Square brackets are used to designate group membership or to define a group of signals with a
similar function, such as A[21:1].
Group Membership Brackets
VCC vs. VCC
When referring to a signal or package-connection name, the notation used is VCC. When
referring to a voltage level, the notation used is subscripted such as VCC
.
This term is used interchangeably throughout this document to denote either a particular die, or
all die in the package.
Device
This is the method used to refer to more than one chip-enable or output enable. When each is
referred to individually, the reference is F1-CE# and F1-OE# (for die #1), and F2-CE# and F2-
OE# (for die #2).
F[3:1]-CE#,
F[2:1]-OE#
When referencing flash memory signals, the notation used is F-VCC or F-VCC, respectively. When
the reference is to PSRAM signals or timings, the notation is prefixed with “P-” (for example, P-
VCC, P-VCC).
When referencing SRAM signals or timings, the notation is prefixed with “S-” (for example, S-
VCC or S-VCC).
F-VCC P-VCC, S-VCC
P-VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM.
Used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between two or
more RAM die. R-OE#, R-LB#, R-UB# and R-WE# are RFU for stacked combinations that do not
include PSRAM or SRAM.
R-OE#, R-LB#,
R-UB#, R-WE#
00FFh
Denotes 16-bit hexadecimal numbers
Denotes 32-bit hexadecimal numbers
00FF 00FFh
April 2008
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Datasheet
9
Numonyx™ StrataFlash® Cellular Memory (M18)
2.0
Functional Description
2.1
Product Overview
The Numonyx™ StrataFlash® Cellular Memory (M18) device provides high read and
write performance at low voltage on a 16-bit data bus.
The flash memory device has a multi-partition architecture with read-while-program
and read-while-erase capability.
The device supports synchronous burst reads up to 108 MHz using ADV# and CLK
address-latching on some litho/density combinations and up to 133 MHz using CLK
address-latching only on some litho/density combinations. It is listed below in the
following table.
Table 4:
M18 Product Litho/Density/Frequency Combinations
Litho (nm)
Density (Mbit)
Supports frequency up to (MHz)
Sync read address-latching
CLK-latching
256
512
133
108
133
133
133
108
133
90
ADV#- and CLK-latching
CLK-latching
128
256
CLK-latching
65
512
CLK-latching
1024
1024
ADV#- and CLK-latching
CLK-latching
In continuous-burst mode, a data Read can traverse partition boundaries.
Upon initial power-up or return from reset, the device defaults to asynchronous array-
read mode. Synchronous burst-mode reads are enabled by programming the Read
Configuration Register. In synchronous burst mode, output data is synchronized with a
user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory
synchronization.
Designed for low-voltage applications, the device supports read operations with VCC at
1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. VCC and VPP can
be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when VPP is less than
VPPLK
.
A Status Register provides status and error conditions of erase and program
operations.
One-Time-Programmable (OTP) registers allow unique flash device identification that
can be used to increase flash content security. Also, the individual block-lock feature
provides zero-latency block locking and unlocking to protect against unwanted program
or erase of the array.
The flash memory device offers three power savings features:
• Automatic Power Savings (APS) mode: The device automatically enters APS
following a read-cycle completion.
• Standby mode: Standby is initiated when the system deselects the device by
deasserting CE#.
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Numonyx™ StrataFlash® Cellular Memory (M18)
• Deep Power-Down (DPD) mode: DPD provides the lowest power consumption and
is enabled by programming in the Enhanced Configuration Register. DPD is initiatied
by asserting the DPD pin.
2.2
Configuration and Memory Map
The Numonyx™ StrataFlash® Cellular Memory device features a symmetrical block
architecture. The flash device main array is divided as follows:
• The main array of the 128-Mbit device is divided into eight 16-Mbit partitions. Each
parition is divided into eight 256-KByte blocks: 8 x 8 = 64 blocks in the main array
of a 128-Mbit device.
• The main array of the 256-Mbit device is divided into eight 32-Mbit partitions. Each
parition is divided into sixteen 256-KByte blocks: 8 x 16 = 128 blocks in the main
array of a 256-Mbit device.
• The main array of the 512-Mbit device is divided into eight 64-Mbit partitions. Each
parition is divided into thirty-two 256-KByte blocks: 8 x 32 = 256 blocks in the
main array of a 256-Mbit device.
• The main array of the 1-Gbit device is divided into eight 128-Mbit partitions. Each
parition is divided into sixty-four 256-KByte blocks: 8 x 64 = 512 blocks in the
main array of a 1-Gbit device.
Each block is divided into as many as two-hundred-fifty-six 1-KByte programming
regions. Each region is divided into as many as thirty-two 32-Byte segments.
Table 5:
Main Array Memory Map (Sheet 1 of 2)
128-Mbit Device
256-Mbit Device
512-Mbit Device
1-Gbit Device
Partition
Mbit
Mbit
Mbit
Mbit
Blk
#
Address
Range
Blk
#
Address
Range
Blk
#
Address
Range
Blk
#
Address
Range
07E0000-
07FFFFF
0FE0000-
0FFFFFF
1FE0000-
1FFFFFF
3FE0000-
3FFFFFF
63
127
255
511
7
6
5
4
16
32
64
128
0700000-
071FFFF
0E00000-
0E1FFFF
1C00000-
1C1FFFF
3800000-
381FFFF
56
55
112
111
224
223
448
447
06E0000-
06FFFFF
0DE0000-
0DFFFFF
1BE0000-
1BFFFFF
37E0000-
37FFFFF
16
16
16
32
32
32
64
64
64
128
128
128
0600000-
061FFFF
0C00000-
0C1FFFF
1800000-
181FFFF
3000000-
301FFFF
48
47
96
95
192
191
384
383
05E0000-
05FFFFF
0BE0000-
0BFFFFF
17E0000-
17FFFFF
2FE0000-
2FFFFFF
0500000-
051FFFF
0A00000-
0A1FFFF
1400000-
141FFFF
2800000-
281FFFF
40
39
80
79
160
159
320
319
04E0000-
04FFFFF
09E0000-
09FFFFF
13E0000-
13FFFFF
27E0000-
27FFFFF
0400000-
041FFFF
0800000-
081FFFF
1000000-
101FFFF
2000000-
201FFFF
32
64
128
256
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Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 5:
Main Array Memory Map (Sheet 2 of 2)
128-Mbit Device
256-Mbit Device
512-Mbit Device
1-Gbit Device
Partition
Mbit
Mbit
Mbit
Mbit
Blk
#
Address
Range
Blk
#
Address
Range
Blk
#
Address
Range
Blk
#
Address
Range
03E0000-
03FFFFF
07E0000-
07FFFFF
0FE0000-
0FFFFFF
1FE0000-
1FFFFFF
31
63
127
255
3
2
1
0
16
32
64
128
0300000-
031FFFF
0600000-
061FFFF
0C00000-
0C1FFFF
1800000-
181FFFF
24
23
48
47
96
95
192
191
02E0000-
02FFFFF
05E0000-
05FFFFF
0BE0000-
0BFFFFF
17E0000-
17FFFFF
16
16
16
32
32
32
64
64
64
128
128
128
0200000-
021FFFF
0400000-
041FFFF
0800000-
081FFFF
1000000-
101FFFF
16
15
32
31
64
63
128
127
01E0000-
01FFFFF
03E0000-
03FFFFF
07E0000-
07FFFFF
0FE0000-
0FFFFFF
0100000-
011FFFF
0200000-
021FFFF
0400000-
041FFFF
0800000-
081FFFF
8
7
16
15
32
31
64
63
00E0000-
00FFFFF
01E0000-
01FFFFF
03E0000-
03FFFFF
07E0000-
07FFFFF
0000000-
001FFFF
0000000-
001FFFF
0000000-
001FFFF
0000000-
001FFFF
0
0
0
0
2.3
Device ID
Table 6:
Device ID codes
Device Identifier Code
(Hex)
Density
Litho (nm)
65
Product
Non-Mux
8900
8903
8901
8904
887E
8881
88B0
88B1
128 Mbit
256 Mbit
512 Mbit
1024 Mbit
AD-Mux
Non-Mux
AD-Mux
Non-Mux
AD-Mux
Non-Mux
AD-Mux
65, 90
65, 90
65
Note: To order parts listed above and to obtain a datasheet for the M18 SCSP parts, please contact your local Numonyx sales
office.
Datasheet
12
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
3.0
Package Information
The following figures show the ballout package information for the device:
• Figure 1, “Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)”
• Figure 2, “Mechanical Specifications: x16D (105-ball) package (8x10x1.4 mm)” on
page 15
• Figure 3, “Mechanical Specifications: x16D (105-ball) package (9x11x1.2 mm)”
• Figure 4, “Mechanical Specifications: x16D (105 balls) Package (11x15x1.2 mm)”
on page 17
• Figure 5, “Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2
mm)”
• Figure 6, “Mechanical Specifications: x16C (107-ball) package (8x10x1.0 mm)” on
page 19
• Figure 7, “Mechanical Specifications: x16C (107-ball) package (8x10x1.2 mm)” on
page 20
• Figure 8, “Mechanical Specifications: x16C (107-ball) package (8x11x1.2 mm)” on
page 21
• Figure 9, “Mechanical Specifications: x16C (107-ball) package (11x11x1.2 mm)”
on page 22
April 2008
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Datasheet
13
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 1: Mechanical Specifications: x16D (105-ball) package (8x10x1.0 mm)
S1
Pin
1
Corner
1
2
3
4
5
6
7
8
9
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
SCS
Top Vi ew P- Bal l Si de
Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.0
Min
Nom
Max
0.0394
A
A1
A2
b
D
E
0.200
0.0079
0.660
0.375
10.00
8.00
0.800
105
0.0260
0.0148
0.3937
0.3150
0.0315
105
0.325
9.90
7.90
0.425
10.10
8.10
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
0.900
0.700
0.0039
0.0354
0.0276
0.700
0.500
0.800
0.600
0.0276
0.0197
0.0315
0.0236
Datasheet
14
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 2: Mechanical Specifications: x16D (105-ball) package (8x10x1.4 mm)
S1
Pin
1
Corner
1
2
3
4
5
6
7
8
9
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
SCS
Top Vi ew P- Bal l Si de
Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.4
Min
Nom
Max
0.0551
A
A1
A2
b
D
E
0.200
0.0079
1.070
0.375
10.00
8.00
0.800
105
0.0421
0.0148
0.3937
0.3150
0.0315
105
0.325
9.90
7.90
0.425
10.10
8.10
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
0.900
0.700
0.0039
0.0354
0.0276
0.700
0.500
0.800
0.600
0.0276
0.0197
0.0315
0.0236
April 2008
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Datasheet
15
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 3: Mechanical Specifications: x16D (105-ball) package (9x11x1.2 mm)
S1
Pin 1
Corner
1
2
3
4
5
6
7
8
9
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
Top View- Ball Side Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.2
Min
Nom
Max
0.0472
A
A1
A2
b
D
E
0.200
0.0079
0.860
0.375
11.00
9.00
0.800
105
0.0339
0.0148
0.4331
0.3543
0.0315
105
0.325
10.90
8.90
0.425
11.10
9.10
0.0128
0.4291
0.3504
0.0167
0.4370
0.3583
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
1.400
1.200
0.0039
0.0551
0.0472
1.200
1.000
1.300
1.100
0.0472
0.0394
0.0512
0.0433
Datasheet
16
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 4: Mechanical Specifications: x16D (105 balls) Package (11x15x1.2 mm)
April 2008
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Datasheet
17
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 5: Mechanical Specifications: x16 Split Bus (165-ball) package (10x11x1.2 mm)
S1
Ball one Corner
1
2
3
4
5
6
7
8
9
10 11
12
A
B
S2
C
D
E
F
G
H
J
D
K
L
M
e
b
N
P
R
E
Top View - Ball
Side Down
A2
A1
A
Y
Note: Drawing not to scale.
Millimeters
Min
Inches
Min
Dimensions
Package Height
Ball Height
Symbol
Nom
Max Notes
1.2
Nom
Max
0.0472
A
A1
A2
b
D
E
e
N
Y
S1
S2
0.200
0.0079
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
0.860
0.375
11.00
10.00
0.650
165
0.0339
0.0148
0.4331
0.3937
0.0256
165
0.325
10.90
9.90
0.425
11.10
10.10
0.0128
0.4291
0.3898
0.0167
0.4370
0.3976
0.100
1.525
1.700
0.0039
0.0600
0.0669
1.325
1.500
1.425
1.600
0.0522
0.0591
0.0561
0.0630
Datasheet
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April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 6: Mechanical Specifications: x16C (107-ball) package (8x10x1.0 mm)
S1
Pin
1
Corner
1
2
3
4
5
6
7
8
9
10
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
SCS
Top Vi ewP- Bal l Si de
Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.0
Min
Nom
Max
0.0394
A
A1
A2
b
D
E
0.200
0.0079
0.660
0.375
10.00
8.00
0.800
107
0.0260
0.0148
0.3937
0.3150
0.0315
107
0.325
9.90
7.90
0.425
10.10
8.10
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
0.900
0.700
0.0039
0.0354
0.0276
0.700
0.500
0.800
0.600
0.0276
0.0197
0.0315
0.0236
April 2008
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Datasheet
19
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 7: Mechanical Specifications: x16C (107-ball) package (8x10x1.2 mm)
S1
Pin
1
Corner
1
2
3
4
5
6
7
8
9
10
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
SCS
Top ViewP-Ball Side
Down
A2
A1
A
Y
Note: Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.2
Min
Nom
Max
0.0472
A
A1
A2
b
D
E
0.200
0.0079
0.860
0.375
10.00
8.00
0.800
107
0.0339
0.0148
0.3937
0.3150
0.0315
107
0.325
9.90
7.90
0.425
10.10
8.10
0.0128
0.3898
0.3110
0.0167
0.3976
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
0.900
0.700
0.0039
0.0354
0.0276
0.700
0.500
0.800
0.600
0.0276
0.0197
0.0315
0.0236
Datasheet
20
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 8: Mechanical Specifications: x16C (107-ball) package (8x11x1.2 mm)
Pin 1
Corner
S1
1
2
3
4
5
6
7
8
9
S2
A
B
C
D
E
F
D
G
H
J
K
L
e
M
b
E
Top View- Ball Side Down
A2
A1
A
Y
Note: Drawing not to scale.
Millimeters
Inches
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
Max Notes
1.2
Min
Nom
Max
0.0472
A
A1
A2
b
D
E
0.200
0.0079
0.860
0.375
11.00
8.00
0.800
107
0.0339
0.0148
0.4331
0.3150
0.0315
107
0.325
10.90
7.90
0.425
11.10
8.10
0.0128
0.4291
0.3110
0.0167
0.4370
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball Distance Along E
Corner to Ball Distance Along D
Y
S1
S2
0.100
0.900
1.200
0.0039
0.0354
0.0472
0.700
1.000
0.800
1.100
0.0276
0.0394
0.0315
0.0433
April 2008
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Datasheet
21
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 9: Mechanical Specifications: x16C (107-ball) package (11x11x1.2 mm)
Datasheet
22
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.0
Ballouts and Signal Descriptions
This section provides ballout and signal description information for x16D (105-ball),
x16C (107-ball), and x16 Split Bus (165-ball) packages, Non-Mux, AD-Mux, AA/D Mux
interfaces.
4.1
Ballouts, x16D
4.1.1
x16D (105-Ball) Ballout, Non-Mux
Figure 10: x16D (105-Ball) Electrical Ballout, Non-Mux
Pin 1
1
2
3
4
5
6
7
8
9
DU
A4
A6
A7
A19
A23
A24
A25
DU
A
B
C
D
E
F
A
B
C
D
E
F
A2
A1
A3
A5
A17
VSS
A18
F-DPD
VSS
A22
VSS
A26
VSS
N-ALE
A10
A9
A16
A15
A14
A13
A12
A11
VSS
VSS
D-VCC
ADV#
N-CLE
A0
S-VCC
WE#
D-VCC
D2-CS#
F1-VCC
F2-VCC
D-VCC
A21
Depop
(Index)
F4-CE# /
A27
F-WP1#
F-WP2#
RFU
Depop
(RFUs)
N-RE# /
S-CS1#
D1-CS#
F2-CE#
D-CAS# D-RAS#
A20
Depop
(RFUs)
G
H
J
F1-CE#
F3-CE#
VCCQ
VSS
D-BA0
D-BA1
F1-VCC
VSS
D-CKE
D-WE#
F2-VCC
VSS
F-RST#
OE#
A8
G
H
J
N-WE# /
S-CS2
D-DM1 / D-DM0 /
S-UB#
N-RY/BY#
F-VPP
DQ2
D-CLK#
D-CLK
F-CLK
DQ7
S-LB#
VCCQ
VSS
VCCQ
VSS
VCCQ
F-WAIT
K
L
VSS
DQ13
DQ14
K
L
DQ1
DQ3
DQ5
DQ6
DQ9
DQ11
DQ12
DU
DQ0
D-LDQS
DQ4
DQ8
DQ10
D-UDQS
DQ15
DU
M
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Active Balls
De-Populated Balls
Reserved for Future Use
Do Not Use
Legend:
April 2008
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Datasheet
23
Numonyx™ StrataFlash® Cellular Memory (M18)
4.1.2
x16D (105-Ball) Ballout, AD-Mux
Figure 11: x16D (105-Ball) Electrical Ballout, AD-Mux
Pin 1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DU
A4
A6
A7
A19
A23
A24
A25
DU
A
B
C
D
E
F
A2
A1
A3
VSS
A5
A17
VSS
A18
F-DPD
VSS
A22
VSS
A26
VSS
N-ALE
A10
A9
A16
A15
A14
A13
A12
A11
VSS
D-VCC
ADV#
N-CLE
A0
S-VCC
WE#
D-VCC
D2-CS#
F1-VCC
F2-VCC
D-VCC
A21
Depop
(Index)
F4-CE# /
A27
F-WP1#
F-WP2#
RFU
Depop
(RFUs)
N-RE# /
S-CS1#
D1-CS# D-CAS# D-RAS#
A20
Depop
(RFUs)
G
H
J
F2-CE#
F1-CE#
F3-CE#
VCCQ
VSS
D-BA0
D-BA1
F1-VCC
VSS
D-CKE
D-WE#
F2-VCC
VSS
F-RST#
OE#
A8
G
H
J
N-WE# /
S-CS2
D-DM1 / D-DM0 /
R-UB#
N-RY/BY#
F-VPP
AD2
D-CLK#
D-CLK
F-CLK
AD7
R-LB#
VCCQ
VSS
VCCQ
VSS
VCCQ
F-WAIT
K
L
VSS
AD13
AD14
K
L
AD1
AD3
AD5
AD6
AD9
AD11
AD12
M
DU
AD0
D-LDQS
AD4
AD8
AD10
D-UDQS
AD15
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Active Balls
De-Populated Balls
Reserved for Future Use
Do Not Use
Legend:
Datasheet
24
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.1.3
x16D Mux (105-Ball) Ballout, AA/D Mux
Figure 12: x16D (105-Ball) Electrical Ballout, AA/D Mux
Pin 1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DU
A4
A6
A7
RFU
RFU
RFU
RFU
DU
A
B
C
D
E
F
A2
A1
A3
A5
RFU
VSS
RFU
F-DPD
VSS
RFU
VSS
F-ADV2#
VSS
RFU
A15
A14
A13
A12
A11
VSS
VSS
D-VCC
F-ADV#
N-CLE
A0
S-VCC
WE#
D-VCC
D2-CS#
F-VCC
F-VCC
F4-CE#
D-VCC
RFU
N-ALE
A10
Depop
(Index)
F-WP1#
F-WP2#
RFU
Depop
(RFU)
S-CS1 /
N-RE#
D1-CS#
F2-CE#
D-CAS# D-RAS#
RFU
A9
Depop
(RFU)
G
H
J
F1-CE#
F3-CE#
VCCQ
VSS
D-BA0
D-BA1
F-VCC
VSS
D-CKE
D-WE#
F-VCC
VSS
F-RST#
OE#
A8
G
H
J
S-CS2 /
N-WE#
D-DM1 / D-DM0 /
S-UB#
N-RY/BY#
F-VPP
AD2
D-CLK#
D-CLK
F-CLK
AD7
S-LB#
VCCQ
VSS
VCCQ
VSS
VCCQ
F-WAIT
K
L
VSS
AD13
AD14
K
L
AD1
AD3
AD5
AD6
AD9
AD11
AD12
M
DU
1
AD0
2
D-LDQS
3
AD4
4
AD8
5
AD10
6
D-UDQS
7
AD15
8
DU
9
M
Top View - Ball Side Down
Active Balls
De-Populated Balls
Reserved for Future Use
Do Not Use
Legend:
April 2008
309823-10
Datasheet
25
Numonyx™ StrataFlash® Cellular Memory (M18)
4.2
Signal Descriptions, x16D
Table 7:
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 1 of 4)
Symbol
Type
Signal Descriptions
Notes
Address and Data Signals, Non-Mux
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
•
•
•
•
•
•
•
•
•
4-Gbit: AMAX = A27
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
A[MAX: 0]
Input
1
128-Mbit: AMAX = A22
A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.
A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.
A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.
Unused address inputs should be treated as RFU.
DATA INPUT/OUTPUTS: Global device signals.
DQ[15:0] are used to input commands and write-data during Write cycles, and to output read-
data during Read cycles. During NAND accesses, DQ[7:0] are used to input commands, address-
data, and write-data, and to output read-data.
Input/
Output
DQ[15:0]
F-ADV#
Data signals are High-Z when the device is deselected or its output is disabled.
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,
or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108
MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to
133 MHz.
Input
In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV# or
continuously flows through while F-ADV# is low.
Address and Data Signals, AD-Mux
ADDRESS: Global device signals.
Shared address inputs for all Flash and SRAM memory die during Read and Write operations.
•
•
•
•
•
•
4-Gbit: AMAX = A27
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
A[MAX:16]
Input
1
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash and SRAM lower address
and data signals; LPSDRAM data signals.
During AD-Mux flash and SRAM Write cycles, AD[15:0] are used to input the lower address
followed by commands or write-data.
During AD-Mux flash Read cycles, AD[15:0] are used to input the lower address followed by
read-data output.
Input /
Output
AD[15:0]
A[15:0]
During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write
cycles or to output read-data during Read cycles.
During NAND accesses, AD[7:0] are used to input commands, address, or write-data, and to
output read-data.
AD[15:0] are High-Z when the flash or SRAM is deselected or its output is disabled.
Input
RFU, except for DRAM.
Datasheet
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April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 2 of 4)
Symbol
Type
Signal Descriptions
Notes
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,
or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108
MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to
133 MHz.
F-ADV#
Input
In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
•
•
•
•
•
•
•
•
•
4-Gbit: AMAX = A27
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
A[MAX: 0]
Input
1
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.
A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.
A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AAD-Mux flash address and data;
LPSDRAM data.
During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower
address, and commands or write-data.
During AAD-Mux flash Read cycles, AD[15:0] are used to input the upper address and lower
address, and output read-data.
During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write
cycles or to output read-data during Read cycles.
Input /
Output
AD[15:0]
During NAND accesses, AD[7:0] are used to input commands, address-data, or write-data, and
to output read-data.
AD[15:0] are High-Z when the device is deselected or its output is disabled.
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
During a synchronous flash Read operation, the address is latched on the F-ADV# rising edge or
the first F-CLK edge after F-ADV# low in devices that support up to 104 MHz, and on the last
rising F-CLK edge after F-ADV# low in devices that support upto 133 MHz.
F-ADV#
During a synchronous flash Read operation, the address is latched on the rising edge of F-ADV#
or the first active F-CLK edge whichever occurs first.
In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.
Input
F-ADV2#
During AAD-Mux flash accesses, the upper address is latched on the valid edge of F-CLK while
F-ADV2# is low; the lower address is latched on the valid edge of F-CLK while F-ADV# is low.
The upper address is always latched first, followed by the lower address.
Control Signals
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT
outputs are placed in a High-Z state.
F[4:1]-
CE#
•
•
F1-CE# is dedicated to flash die #1.
F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,
any unused flash chip enable should be treated as RFU.
Input
1
•
For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2
while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3-
CE# selects NAND die #3 if present.
FLASH CLOCK: Flash-specific signal; rising active-edge input.
F-CLK synchronizes the flash with the system clock during synchronous operations.
F-CLK
Input
Input
Input
LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input.
D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock.
D-CLK
D-CLK#
2
2
DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input.
D-CLK# synchronizes the DDR LPSDRAM with the system clock.
April 2008
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Datasheet
27
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 3 of 4)
Symbol
Type
Signal Descriptions
Notes
OUTPUT ENABLE: Flash- and SRAM-specific signal; low-true input.
When low, OE# enables the output drivers of the selected flash or SRAM die. When high, OE#
disables the output drivers of the selected flash or SRAM die and places the output drivers in
High-Z.
OE#
Input
FLASH RESET: Flash-specific signal; low-true input.
F-RST#
Input
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
FLASH WAIT: Flash -specific signal; configurable-true output.
F-WAIT
WE#
Output
Input
Input
When asserted, F-WAIT indicates invalid output data. F-WAIT is driven whenever F-CE# and
OE# are low. F-WAIT is High-Z whenever F-CE# or OE# is high.
WRITE ENABLE: Flash- and SRAM-specific signal; low-true input.
When low, WE# enables Write operations for the enabled flash or SRAM die.
LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input.
D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define the
LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK.
D-WE#
2
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
F-
Input
WP[2:1]#
•
•
•
F-WP1# is dedicated to flash die #1.
F-WP2# is common to all other flash dies, if present. Otherwise it is RFU.
For NOR/NAND stacked device, F-WP1# selects all NOR dies; F-WP2# selects all NAND dies.
FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.
F-DPD
N-CLE
N-ALE
Input
Input
Input
When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode.
NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-CLE enables commands to be latched on the rising edge of N-WE#.
2
2
NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.
NAND READ ENABLE: NAND-specific signal; low-true input.
N-RE#
Input
2, 4
When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#
disables the output drivers of the selected NAND die and places the output drivers in High-Z.
NAND READY/BUSY: NAND-specific signal; low-true output.
N-RY/BY#
N-WE#
Output
Input
Input
Input
Input
2
2, 5
2
When low, N-RY/BY# indicates the NAND is busy performing a read, program, or erase
operation. When high, N-RY/BY# indicates the NAND device is ready.
NAND WRITE ENABLE: NAND-specific signal; low-true input.
When low, N-WE# enables Write operations for the enabled NAND die.
LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input.
D-CKE
When high, D-CKE indicates that the next D-CLK edge is valid. When low, D-CKE indicates that
the next D-CLK edge is invalid and the selected LPSDRAM die is suspended.
LPSDRAM BANK SELECT: LPSDRAM-specific input signals.
D-BA[1:0] selects one of four banks in the LPSDRAM die.
D-BA[1:0]
D-RAS#
2
LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
2
D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define the
LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK.
LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
D-CAS#
Input
Input
2
2
D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define the
LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK.
LPSDRAM CHIP SELECT: LPSDRAM-specific signal; low-true input.
When low, D-CS# selects the associated LPSDRAM memory die and starts the command input
cycle. When D-CS# is high, commands are ignored but operations continue.
D[2:1]-
CS#
•
D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#, define
the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-CLK.
•
D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present.
Otherwise, any unused LPSDRAM chip selects should be treated as RFU.
Datasheet
28
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 7:
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 4 of 4)
Symbol
Type
Signal Descriptions
Notes
LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input.
When high, D-DM[1:0] controls masking of input data during writes and output data during
reads.
D-DM[1:0]
Input
2, 3
•
•
D-DM1 corresponds to the data on DQ[15:8].
D-DM0 corresponds to the data on DQ[7:0].
LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals.
D-UDQS and D-LDQS provide as output the read-data strobes, and as input the write-data
strobes.
D-UDQS
D-LDQS
Input/
Output
2
•
•
D-UDQS corresponds to the data on DQ[15:8].
D-LDQS corresponds to the data on DQ[7:0].
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both are asserted, S-CS1# and S-CS2 select the SRAM die. When either is deasserted, the
SRAM die is deselected and its power is reduced to standby levels.
S-CS1#
S-CS2
Input
Input
2, 4, 5
2, 3
SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs.
S-UB#
S-LB#
When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM Read and Write
cycles. When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0].
Power Signals
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
F-VPP
Power
FLASH CORE POWER SUPPLY: Flash specific.
F1-VCC supplies the core power to the NOR flash die.
F1-VCC
Power
Power
FLASH CORE POWER SUPPLY: Flash specific.
F2-VCC supplies the core power to either 1) the NOR flash die in stack packages with multiple
NOR flash dies, or 2) NAND flash die in stack packages with NOR-NAND flash dies.
F2-VCC
6
I/O POWER SUPPLY: Global device I/O power.
VCCQ
D-VCC
S-VCC
VSS
Power
Power
Power
VCCQ supplies the device input/output driver voltage.
LPSDRAM CORE POWER SUPPLY: LPSDRAM specific.
D-VCC supplies the core power to the LPSDRAM die.
2
2
SRAM POWER SUPPLY: SRAM specific.
S-VCC supplies the core power to the SRAM die.
DEVICE GROUND: Global ground reference for all signals and power supplies.
Groun
d
Connect all VSS balls to system ground. Do not float any VSS connections.
DO NOT USE:
DU
—
—
Ball should not be connected to any power supplies, signals, or other balls. Ball can be left
floating.
RESERVED FOR FUTURE USE:
RFU
Reserved by Numonyx for future device functionality/enhancement. Ball must be left floating.
Notes:
1.
F4-CE# and A27 share the same package ball at location E6. Only one signal function is available, depending on the
stacked device combination.
2.
3.
Only available on stacked device combinations with NAND, SRAM, and/or LPSDRAM die; otherwise, treated as RFU.
D-DM[1:0] and S-UB#/S-LB# share the same package balls at locations H8 and H9, respectively. Only one signal function
for each ball location is available, depending on the stacked device combination.
S-CS1# and N-RE# share the same package ball at location F6. Only one signal function is available, depending on the
stacked device combination.
S-CS2 and N-WE# share the same package ball at location H2. Only one signal function is available, depending on the
stacked device combination.
4.
5.
6.
In stack packages with only one NOR flash die, this signal can be left floating.
4.3
Ballouts, x16C
4.3.1
x16C (107-Ball) Ballout, Non-Mux
April 2008
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Datasheet
29
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 13: x16C (107-Ball) Electrical Ballout, Non-Mux
Pin 1
1
2
DU
A4
3
4
A27
5
6
7
8
9
DU
A
B
C
D
E
F
N-CLE
A18
A26
P-VCC
F1-VCC
S-CS2
R-WE#
ADV#
F-WE#
DQ5
F-DPD
F2-VCC
CLK
VSS
A21
A
B
C
D
E
F
A19
VSS
A11
A12
A13
A15
A16
F2-CE#
DU
N-ALE
VSS
A5
R-LB#
A17
A23
VSS
A22
A3
A24
F-VPP
F-WP1#
F-RST#
DQ10
DQ3
P1-CS#
A20
A9
VSS
A2
A7
A25
A10
F-WP2#
VCCQ
VSS
A1
A6
R-UB#
DQ2
DQ1
DQ9
F3-CE#
VCCQ
A8
A14
A0
DQ8
DQ13
DQ14
DQ6
WAIT
DQ7
DQ15
VCCQ
VSS
G
H
J
G
H
J
F2-OE# /
N-RE#
R-OE#
DQ0
DQ12
DQ4
S-CS1# /
N-WE#
RFU
F1-OE#
P2-CS#
VSS
DQ11
S-VCC
F1-VCC
VCCQ
P-Mode# /
P-CRE
F4-CE#
RFU
F1-CE#
VSS
P-VCC
VSS
F2-VCC
VSS
K
L
K
L
VSS
M
DU
N-RY/BY#
RFU
RFU
RFU
RFU
RFU
RFU
DU
M
1
2
3
4
5
6
7
8
9
Top View - Ball Side Down
Active Balls
Reserved for Future Use
Do Not Use
Legend:
Datasheet
30
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.3.2
x16C (107-Ball) Ballout, AD-Mux
Figure 14: x16C (107-Ball) Electrical Ballout, AD-Mux
Pin 1
1
2
3
N-CLE
A18
4
A27
5
6
7
8
9
DU
A
B
C
D
E
F
DU
A26
P-VCC
F1-VCC
S-CS2
R-WE#
ADV#
F-WE#
AD5
F-DPD
F2-VCC
CLK
VSS
A21
A
B
C
D
E
F
DU
N-ALE
VSS
RFU
RFU
RFU
RFU
RFU
RFU
R-OE#
A19
VSS
RFU
RFU
RFU
RFU
A16
R-LB#
A17
A23
VSS
A22
A24
F-VPP
F-WP1#
F-RST#
AD10
AD3
P1-CS#
A20
RFU
RFU
RFU
WAIT
AD7
AD15
VCCQ
VSS
RFU
8
VSS
RFU
RFU
AD8
A25
F-WP2#
VCCQ
VSS
R-UB#
AD2
AD1
AD9
F3-CE#
VCCQ
RFU
4
RFU
G
H
J
AD13
AD14
AD6
F2-CE#
G
H
J
F2-OE# /
N-RE#
AD0
AD12
AD4
S-CS1# /
N-WE#
RFU
F1-OE#
P2-CS#
VSS
AD11
S-VCC
F1-VCC
RFU
VCCQ
P-Mode# /
P-CRE
K
L
F4-CE#
RFU
F1-CE#
VSS
P-VCC
VSS
F2-VCC
VSS
K
L
VSS
DU
9
M
DU
N-RY/BY#
2
RFU
3
RFU
RFU
M
1
5
6
7
Top View - Ball Side Down
Active Balls
Reserved for Future Use
Do Not Use
Legend:
April 2008
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Datasheet
31
Numonyx™ StrataFlash® Cellular Memory (M18)
4.3.3
x16C (107-Ball) Ballout, AA/D-Mux
Figure 15: x16C (107-Ball) Electrical Ballout, AA/D-Mux
Pin 1
1
2
3
4
RFU
RFU
RFU
RFU
RFU
R-UB#
AD2
5
6
7
8
9
DU
A
B
C
D
E
F
DU
N-CLE
RFU
RFU
P-VCC
F1-VCC
S-CS2
R-WE#
ADV#
F-WE#
AD5
F-DPD
F2-VCC
CLK
VSS
RFU
RFU
RFU
RFU
RFU
WAIT
AD7
AD15
VCCQ
VSS
RFU
8
A
B
C
D
E
F
DU
N-ALE
VSS
RFU
RFU
RFU
RFU
RFU
RFU
R-OE#
VSS
RFU
RFU
RFU
RFU
RFU
F2-CE#
R-LB#
RFU
VSS
F-VPP
F-WP1#
F-RST#
AD10
AD3
P1-CS#
RFU
VSS
RFU
F-WP2#
VCCQ
VSS
RFU
RFU
G
H
J
AD8
AD13
AD14
AD6
G
H
J
F2-OE# /
N-RE#
AD0
AD1
AD12
AD4
S-CS1# /
N-WE#
RFU
F1-OE#
P2-CS#
VSS
AD9
AD11
S-VCC
F1-VCC
RFU
VCCQ
P-Mode# /
P-CRE
K
L
F4-CE#
RFU
F1-CE#
VSS
F3-CE#
VCCQ
RFU
4
P-VCC
VSS
F2-VCC
VSS
K
L
VSS
DU
9
M
DU
N-RY/BY#
2
RFU
F-ADV2#
6
RFU
M
1
3
5
7
Top View - Ball Side Down
Active Balls
Reserved for Future Use
Do Not Use
Legend:
Datasheet
32
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.4
Signal Descriptions x16C
Table 8:
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 1
of 3)
Symbol
Type
Signal Descriptions
Notes
Address and Data Signals, Non-Mux
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
• 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22
• 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21
A[MAX:0]
Input
• 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20
• 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19
• 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18
Unused address inputs should be treated as RFU.
DATA INPUT/OUTPUTS: Global device signals.
Inputs data and commands during Write cycles, outputs data during Read cycles. Data signals
are High-Z when the device is deselected or its output is disabled.
Input /
Output
DQ[15:0]
ADV#
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,
or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108
MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to
133 MHz.
Input
In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or
continuously flows through while ADV# is low.
Address and Data Signals, AD-Mux
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
• 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22
• 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21
A[MAX:16]
Input
• 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20
• 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19
• 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals.
During AD-Mux Write cycles, AD[15:0] are used to input the lower address followed by
commands or data. During AD-Mux Read cycles, AD[15:0] are used to input the lower address
followed by read-data output.
Input /
Output
AD[15:0]
During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and
output read-data.
AD[15:0] are High-Z when the device is deselected or its output is disabled.
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,
or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108
MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to
133 MHz.
ADV#
Input
In an asynchronous flash Read operation, the address is latched on the rising edge of ADV#.
Address and Data Signals, AAD-Mux
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals.
During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower
address, and commands or data. During AAD-Mux flash Read cycles, AD[15:0] are used to
input the upper address and lower address, and output read-data.
During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and
output read-data.
Input /
Output
AD[15:0]
AD[15:0] are High-Z when the device is deselected or its output is disabled.
April 2008
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Datasheet
33
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 8:
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 2
of 3)
Symbol
Type
Signal Descriptions
Notes
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
F-ADV2#
ADV#
During AAD-Mux flash accesses, the upper address is latched on the valid edge of CLK while
F-ADV2# is low; the lower address is latched on the valid edge of CLK while ADV# is low.
Input
The upper address is always latched first, followed by the lower address.
Control Signals
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT
outputs are placed in a High-Z state.
•
•
F1-CE# is dedicated to flash die #1.
F[4:1]-CE#
Input
F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,
any unused flash chip enable should be treated as RFU.
•
For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2
while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3-
CE# selects NAND die #3 if present.
CLOCK: Flash- and Synchronous PSRAM-specific input signal.
CLK
Input
Input
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during
synchronous operations.
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE#
disables the output drivers of the selected flash die and places the output drivers in High-Z.
F[2:1]-OE#
2
1
•
•
For NOR only stacked device, F[2:1]-OE# are common to all NOR dies in the device.
For NOR/NAND stacked device, F1-OE# enables all NOR dies, F2-OE# selects all NAND dies
if present.
RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z.
R-OE#
Input
Input
FLASH RESET: Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
F-RST#
WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output.
When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid
output data.
WAIT
Output
•
WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output
enable is low.
•
WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output
enable is high.
FLASH WRITE ENABLE: Flash-specific signal; low-true input.
F-WE#
R-WE#
Input
Input
When low, F-WE# enables Write operations for the enabled flash die. Address and data are
latched on the rising edge of F-WE#.
RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-WE# enables Write operations for the selected memory die. Data is latched on the
rising edge of R-WE#.
1
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
F-WP[2:1]#
Input
•
•
•
F-WP1# is dedicated to flash die #1.
F-WP2# is common to all other flash dies, if present. Otherwise it is RFU.
For NOR/NAND stacked device, F-WP1# selects all NOR dies, while F-WP2# selects all
NAND dies.
FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.
When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode.
F-DPD
N-CLE
Input
Input
NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-CLE enables commands to be latched on the rising edge of N-WE#.
1
Datasheet
34
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 8:
Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 3
of 3)
Symbol
Type
Signal Descriptions
Notes
NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.
N-ALE
Input
Input
1
NAND READ ENABLE: NAND-specific signal; low-true input.
N-RE#
1, 2
When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#
disables the output drivers of the selected NAND die and places the output drivers in High-Z.
NAND READY/BUSY: NAND-specific signal; low-true output.
N-RY/BY#
N-WE#
P-CRE
Output
Input
Input
1
When low, N-RY/BY# indicates the NAND is busy performing a Read, Program, or Erase
operation. When high, N-RY/BY# indicates the NAND device is ready.
NAND WRITE ENABLE: NAND-specific signal; low-true input.
When low, N-WE# enables Write operations for the enabled NAND die.
1, 4
1, 3
PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations.
PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.
P-MODE#
Input
Input
1, 3
When low, P-MODE# enables access to the configuration register, and to enter or exit Low-
Power mode. When high, P-MODE# enables normal Read or Write operations.
PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
P[2:1]-CS#
1
•
•
P1-CS# is dedicated to PSRAM die #1.
P2-CS# IS dedicated to PSRAM die #2. Otherwise, any unused PSRAM chip select should be
treated as RFU.
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
S-CS1#
S-CS2
Input
Input
1, 4
1
RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read
and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0].
R-UB#
R-LB#
Power Signals
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP
Power
F-VPP supplies program or erase power to the flash die.
FLASH CORE POWER SUPPLY: Flash specific.
F[2:1]-VCC supplies the core power to the flash die.
For NOR/NAND stacked device, F1-VCC is dedicated for all NOR dies, F2-VCC is dedicated for all
NAND dies.
F[2:1]-VCC
Power
5
I/O POWER SUPPLY: Global device I/O power.
VCCQ supplies the device input/output driver voltage.
VCCQ
P-VCC
S-VCC
VSS
Power
Power
Power
PSRAM CORE POWER SUPPLY: PSRAM specific.
1
1
P-VCC supplies the core power to the PSRAM die.
SRAM POWER SUPPLY: SRAM specific.
S-VCC supplies the core power to the SRAM die.
DEVICE GROUND: Global ground reference for all signals and power supplies.
Connect all VSS balls to system ground. Do not float any VSS connections.
Groun
d
DO NOT USE:
DU
—
—
Ball should not be connected to any power supplies, signals, or other balls. Ball can be left
floating.
RESERVED for FUTURE USE:
Reserved by Numonyx for future device functionality and enhancement. Ball must be left
floating.
RFU
April 2008
309823-10
Datasheet
35
Numonyx™ StrataFlash® Cellular Memory (M18)
Notes:
1.
2.
Only available on stacked device combinations with NAND, SRAM, and/or LPSDRAM die. Otherwise treated as RFU.
F2-OE# and N-RE# share the same package ball at location H9. Only one signal function is available, depending on the
stacked device combination.
3.
4.
5.
P-CRE and P-MODE# share the same package ball at location K9. Only one signal function is available, depending on the
stacked device combination.
S-CS1# and N-WE# share the same package ball at location J2. Only one signal function is available, depending on the
stacked device combination.
The F2-VCC signal applies to a NAND flash die if one exists; if not, the F2-VCC signal applies to the NOR flash die.
Datasheet
36
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
4.5
Ballouts, x16 Split Bus
4.5.1
x16 Split Bus (165-Ball) Ballout, Non-Mux
Figure 16: x16 Split Bus (165 Active Ball) Electrical Ballout, Non-Mux
Pin 1
1
2
3
4
5
6
7
8
9
10
11
12
B: D-BA0
B: D-A11
B: D-A4
A
B
C
D
E
F
DU
B: D-A2
B: D-A0
B: D-A12 B: D-A8 B: D-A6
B: D-A13 B: D-A9 B: D-A7
B: D-CKE B: D-A14 A: VSS
DU
A
B
C
D
E
F
B: D-BA1
B: D-WE#
B: D-A5
RFU
A: F-A15
B: D-A3
B: D-A1
RFU
DU
DU
A: F3-
CE# /
N2-CE#
A: F4-
CE# /
N1-CE#
A: F-D7 / A: F-D14 /
N-ADQ7
A: F-A13 A: F-A14 A: F-A16 A: VSS
N-ADQ14
B: D1-
CE#
B: D2-
CE#
B: D-
CLK#
A: F-D15 /
N-ADQ15 N-ADQ6
A: F-D6 /
B: D-VCC
RFU
A: VSS
A: VCCQ
A: VCCQ
A: F-A22 A: F2-CE# B: D-A10
A: F-A21 A: N-R/B# A: F-DPD
B: D-CLK
A: F-A12
A: F-A11
B: D-
RAS#
B: D-
CAS#
A: F-
WAIT
A: F-D13 /
RFU
RFU
N-ADQ13
A: F2-
VCC /
N-VCC
Depop
(Index)
Depop
(RFU)
Depop
(RFU)
A: F-D5 /
A: VSS
A: F-A10 A: F-A20 A: F-WE# A: VSS
A: F-
A: VSS
RFU
N-ADQ5
Depop
(RFU)
A: F-
ADV#
Depop
(RFU)
A: F-D12 / A: F-D4 /
N-ADQ12
RFU
WP2# /
N-WP#
A: F-A26 A: F-WP1#
B: D-VCC
G
H
J
A: F-A9
G
H
J
N-ADQ4
Depop
(RFU)
Depop
(RFU)
A: F1-
VCC
A: F1-CE#
RFU
A: F-A8 A: F-A24 A: F-A25 A: VSS
A: VSS
RFU
RFU
A: F-CLK
A: F2-
VCC /
Depop
(RFU)
Depop
(RFU)
A: F-D10 /
N-ADQ10
A: F-D11 /
N-ADQ11
A: F-OE#
A: VCCQ
A: VCCQ
A: VSS
RFU
A: F-A19 A: F-A23 A: N-CLE
RFU
RFU
A: F-A18
N-VCC
Depop
(RFU)
Depop
(RFU)
A: F-D3 /
N-ADQ3
B: D-VCC
K
L
A: F-A7 A: F-A17
RFU
A: VSS
A: VSS
A: VSS
RFU
K
L
A: F-
RST#
A: F-D2 /
N-ADQ2
A: F1-VCC
B: D-DM0
B: D-VSS
B: D-D5
A: N-RE#
A: F-A6 A: N-ALE A: N-WE#
B: D-
RFU
A: F-VPP
A: F-A5
A: F-A3
A: F-A1
DU
B: D-
VDDQ
B: D-
VDDQ
B: D-
DM1
B: D-
VDDQ
A: F-D1 / A: F-D9 /
N-ADQ1
M
N
P
R
A: F-A4
RFU
M
N
P
R
VDDQ
N-ADQ9
B: D-
DQS0
B: D-
DQS1
A: F-D8 /
N-ADQ8 N-ADQ0
A: F-D0 /
A: VSS
B: D-D7
A: F-A2 B: D-VSS
B: D-VSS
B: D-VSS
B: D-D14
A: F-A0
B: D-D1
B: D-D3
B: D-D8 B: D-D10 B: D-D12
B: D-D9 B: D-D11 B: D-D13
RFU
DU
B: D-D4
5
B: D-D6
6
B: D-D15
10
DU
2
B: D-D0
3
B: D-D2
4
DU
11
1
7
8
9
12
Top View- Ball Side Down
B5173-01
April 2008
309823-10
Datasheet
37
Numonyx™ StrataFlash® Cellular Memory (M18)
4.6
Signal Descriptions, x16 Split Bus
Table 9:
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 1 of 4)
Symbol
Type
Signal Descriptions
Notes
Address and Data Signals, Non-Mux
FLASH ADDRESS: Flash device signals.
Dedicated address inputs for Flash memory die during read and write operations.
•
•
•
•
•
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
F-A[MAX:0]
Input
Input
Unused address inputs are RFU.
LPSDRAM ADDRESS: LSPDRAM device signals.
Dedicated address inputs for LPSDRAM memory die during read and write operations.
•
•
•
A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.
A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.
A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.
D-A[MAX:0]
Unused address inputs are RFU.
FLASH DATA INPUT/OUTPUTS: Flash device signals.
•
•
•
Inputs Flash data and commands during write cycles.
Outputs data during read cycles.
Data signals are High-Z when the device is deselected or its output is disabled.
Input/
Output
F-DQ[15:0]
D-DQ[15:0]
LPSDRAM DATA INPUT/OUTPUTS: LPSDRAM device signals.
•
•
•
Inputs LPSDRAM data and commands during write cycles.
Outputs data during read cycles.
Data signals are High-Z when the device is deselected or its output is disabled.
Input/
Output
Address and Data Signals, A/D Mux
ADDRESS: Flash device signals.
Shared address inputs for all Flash memory die during Read and Write operations.
•
•
•
•
•
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
F-A[MAX:16]
Input
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash lower address and data
signals; LPSDRAM data signals.
During AD-Mux flash Write cycles, ADQ[15:0] are used to input the lower address followed by
commands or write-data.
During AD-Mux flash Read cycles, ADQ[15:0] are used to input the lower address followed by
read-data output.
Input /
Output
F-ADQ[15:0]
During LPSDRAM accesses, ADQ[15:0] are used to input commands and write-data during
Write cycles or to output read-data during Read cycles.
During NAND accesses, ADQ[7:0] are used to input commands, address, or write-data, and to
output read-data.
ADQ[15:0] are High-Z when the flash is deselected or its output is disabled.
Control Signals
Datasheet
38
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 9:
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 2 of 4)
Symbol
Type
Signal Descriptions
Notes
FLASH ADDRESS VALID: Flash-specific signal; low-true input.
During synchronous flash Read operations, the address is latched on the rising edge of F-
ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up
to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support
up to 133 MHz.
F-ADV#
Input
In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die.
When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby
levels, and its data and F-WAIT outputs are placed in a High-Z state.
F[4:1]-CE#
Input
•
•
F1-CE# is dedicated to flash die #1.
F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,
treat any unused flash chip enable as RFU.
•
When NAND is used, F4-CE# is dedicated for NAND die 1 and NAND die 2. Otherwise, this
is RFU.
FLASH CLOCK: Flash-specific signal; configurable active-edge input.
F-CLK synchronizes the flash memory with the system clock during synchronous operations.
F-CLK
Input
Input
Input
LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input.
D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock.
D-CLK
D-CLK#
1
1
DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input.
D-CLK# synchronizes the DDR LPSDRAM with the system clock.
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
•
•
When low, OE# enables the output drivers of the selected flash die.
When high, OE# disables the output drivers of the selected flash die and places the
output drivers in High-Z.
F-OE#
Input
Input
FLASH RESET: Flash-specific signal; low-true input.
•
•
F-RST#
F-WAIT
When low, F-RST# resets internal operations and inhibits writes.
When high, F-RST# enables normal operation.
FLASH WAIT: Flash-specific signal; configurable-true output.
When asserted, F-WAIT indicates invalid output data.
•
•
Output
F-WAIT is driven whenever F-CE# and OE# is low.
F-WAIT is High-Z whenever F-CE# or OE# is high.
FLASH WRITE ENABLE: Flash-specific signal; low-true input.
F-WE#
N-WE#
Input
Input
When low, WE# enables write operations for the selected flash die.
NAND WRITE ENABLE: NAND-specific signal; low-true input.
When low, WE# enables write operations for the selected NAND die.
1
1
LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input.
D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define
the LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK.
D-WE#
Input
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism.
When high, F-WP# overrides the Lock-Down function, enabling locked-down blocks to be
unlocked with the Unlock command.
F-WP[2:1]#
Input
•
•
F-WP1# is dedicated to flash die #1.
F-WP2# is used for NAND die when available. Otherwise, this signal is for all other NOR
die.
FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.
When enabled in the ECR, F-DPD is used to enter or exit Deep Power-Down mode.
F-DPD
N-CLE
N-ALE
Input
Input
Input
NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-CLE enables commands to be latched on the rising edge of WE#.
1
1
NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-ALE enables addresses to be latched on the rising edge of WE#.
April 2008
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Datasheet
39
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 9:
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 3 of 4)
Symbol
Type
Signal Descriptions
Notes
NAND READY/BUSY: NAND-specific signal; low-true output.
•
When low, N-RY/BY# indicates the NAND device is busy performing a read, program, or
erase operations.
N-R/B#
N-RE#
D-CKE
Output
1
•
When high, N-RY/BY# indicates the NAND device is ready.
NAND READ ENABLE: NAND-specific signal; drives the data onto the flash bus after the falling
edge of N-RE#.
Output
Input
1
1
This signal increments the internal column address and reads out each data.
LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input.
•
•
When high, D-CKE indicates that the next D-CLK edge is valid.
When low, D-CKE indicates that the next D-CLK edge is invalid and the selected LPSDRAM
die is suspended.
LPSDRAM BANK SELECT: LPSDRAM-specific input signals.
D-BA[1:0] selects one of four banks in the LPSDRAM die.
D-BA[1:0]
D-RAS#
Input
Input
1
1
LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define
the LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK.
LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
D-CAS#
Input
1
D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define
the LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK.
LPSDRAM CHIP ENABLE: LPSDRAM-specific signal; low-true input.
When low, D-CS# selects the associated LPSDRAM memory die and starts the command input
cycle.
When D-CS# is high, commands are ignored but operations continue.
D[2:1]-CE#
Input
1
•
D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#,
define the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-
CLK.
•
D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present.
Otherwise, treat any unused LPSDRAM chip selects as RFU.
LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input.
When high, D-DM[1:0] controls masking of input data during writes and output data during
reads.
D-DM[1:0]
Input
1
1
•
•
D-DM1 corresponds to the data on DQ[15:8].
D-DM0 corresponds to the data on DQ[7:0].
LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals.
D-DQS1 and D-DQS0 provide as output the read data strobes, and as input the write data
strobes.
D-DQS1
D-DQS0
Input /
Output
•
•
D-DQS1 corresponds to the data on DQ[15:8].
D-DQS0 corresponds to the data on DQ[7:0].
SRAM CHIP SELECTS: SRAM-specific signals.
•
•
•
•
S-CS1# low-true input.
S-CS2# high-true input.
When both are asserted, S-CS1# and S-CS2 select the SRAM die.
S-CS1#
S-CS2#
Input
Input
Power
3
When either is deasserted, the SRAM die is deselected and its power is reduced to
standby levels.
SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs.
•
S-UB#
S-LB#
When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM read and
write cycles.
When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0].
2,3
•
Power Signals
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
F-VPP
Datasheet
40
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 9:
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 4 of 4)
Symbol
Type
Signal Descriptions
Notes
FLASH CORE POWER SUPPLY: Flash specific.
F-VCC supplies the core power to the flash die.
F[2:1]-VCC
Power
•
•
F1-VCC is dedicated for NOR die.
F2-VCC is used for NAND die when available. Otherwise, this signal is for NOR die. (When
NAND is available, the F2-VCC signal is named N-VCC.)
LPSDRAM CORE POWER SUPPLY: LPSDRAM specific.
D-VCC supplies the core power to the LPSDRAM die.
D-VCC
S-VCC
VCCQ
D-VDDQ
VSS
Power
Power
Power
Power
Ground
1
SRAM POWER SUPPLY: SRAM specific.
S-VCC supplies the core power to the SRAM die.
FLASH I/O POWER SUPPLY: Global device I/O power.
VCCQ supplies the device input/output driver voltage to the flash die.
LPSDRAM I/O POWER SUPPLY: Global device I/O power.
VDDQ supplies the device input/output driver voltage to the LPSDRAM die.
1
1
FLASH DEVICE GROUND: Global ground reference for all flash signals and power supplies.
Connect all A: VSS balls to system ground. Do not float any VSS connections.
LPSDRAM DEVICE GROUND: Global ground reference for all LPSDRAM signals and power
supplies.
D-VSS
DU
Ground
Connect all B: D-VSS balls to system ground. Do not float any VSS connections.
DO NOT USE:
—
—
Do not connect this ball to any power supplies, signals, or other balls. This ball can be left
floating.
RESERVED for FUTURE USE:
RFU
Reserved by Numonyx for future device functionality and enhancement. This ball must be left
floating.
Notes:
6.
Available only on stacked device combinations with NAND, and/or LPSDRAM die. Otherwise, treat the signal as RFU.
April 2008
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Datasheet
41
Numonyx™ StrataFlash® Cellular Memory (M18)
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent
damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without
notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.
Table 10: Absolute Maximum Ratings
Parameter
Min
Max
Unit
Conditions
Notes
Temperature under Bias Expanded
Storage Temperature
–30
–65
+85
°C
°C
V
—
—
—
—
1
1
+125
F-VCC Voltage
–2.0
–2.0
VCCQ + 2.0
VCCQ + 2.0
2,3
2,4
VCCQ and P-VCC Voltage
V
Voltage on any input/output signal (except
VCC, VCCQ,and VPP)
–2.0
VCCQ + 2.0
V
—
2,4
F-VPP Voltage
–2.0
—
+11.5
100
80
V
—
—
2,3
5
ISH Output Short Circuit Current
VPPH Time
mA
—
Hours
Cycles
6
Block Program/Erase Cycles: Main Blocks
100,000
—
F-VPP = VCC or F-VPP = VPPH
6
Notes:
1.
2.
3.
Temperature is Ambient, not Case.
Voltage is referenced to VSS
During signal transitions, minimum DC voltage may undershoot to –2.0 V for periods < 20 ns; maximum DC voltage
may overshoot to VCC (max) + 2.0 V for periods < 20 ns.
.
4.
During signal transitions, minimum DC voltage may undershoot to –1.0 V for periods < 20 ns; maximum DC voltage
may overshoot to VCCQ (max) + 1.0 V for periods < 20 ns.
5.
6.
Output shorted for no more than one second. No more than one output shorted at a time.
Operation beyond this limit may degrade performance.
5.2
Operating Conditions
Warning:
Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Table 11: Operating Conditions
Symbol
TC
Description
Min
Max
Unit
Conditions
Operating Temperature (Case Temperature)
VCC Supply Voltage
–30
+1.7
+1.7
+0.9
+8.5
+85
+2.0
+2.0
+2.0
+9.5
°C
V
—
—
—
—
—
VCC
VCCQ
VPPL
VPPH
I/O Supply Voltage
V
Programming Voltage (Logic Level)
Factory Programming Voltage (High Level)
V
V
Datasheet
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April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
6.0
Electrical Characteristics
6.1
Initialization
Proper device initialization and operation is dependent on the power-up/down
sequence, reset procedure, and adequate power-supply decoupling. The following
sections describe each of these areas.
6.1.1
Power-Up/Down Characteristics
To prevent conditions that could result in spurious program or erase operations, the
power-up/power-down sequence shown in Table 12 is recommended. Note that each
power supply must reach its minimum voltage range before applying/removing the
next supply voltage.
Table 12: Power-Up/Down Sequence
Power Supply
Power-Up Sequence
Voltage
Power-Down Sequence
VCC(min)
VCCQ(min)
VPP(min)
1st
2nd
3rd
1st
3rd
2nd
1st
2nd
1st*
2nd
2nd*
Sequencing not
required*
Sequencing not
required*
2nd*
1st*
1st
* Power supplies connected or sequenced together.
Device inputs must not be driven until all supply voltages reach their minimum range.
RST# should be low during power transitions.
Note:
If VCCQ is below VLKOQ, the device is reset.
6.1.2
Reset Characteristics
During power-up and power-down, RST#should be asserted to prevent spurious
program or erase operations. While RST#is low, device operations are disabled; all
inputs such as address and control are ignored; and all outputs such as data and WAIT
are placed in High-Z. Invalid bus conditions are effectively masked out.
Upon power-up, RST#can be deasserted after tVCCPH, allowing the device to exit from
reset. Upon exiting from reset, the device defaults to asynchronous Read Array mode,
and the Status Register defaults to 0080h. Array data is available after tPHQV, or a bus-
write cycle can begin after tPHWL.
If RST#is asserted during a program or erase operation, the operation will abort and
array contents at that location will be invalid.
For proper system initialization, connect RST#to the low-true reset signal that asserts
whenever the processor is reset. This will ensure the flash device is in the expected
read mode (i.e., Read Array) upon startup.
6.1.3
Power Supply Decoupling
High-speed flash memories require adequate power-supply decoupling to prevent
external transient noise from affecting device operations, and to prevent internally-
generated transient noise from affecting other devices in the system.
April 2008
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Datasheet
43
Numonyx™ StrataFlash® Cellular Memory (M18)
Ceramic chip capacitors of 0.01 to 0.1 µF capacitors should be used between all VCC,
VCCQ, VPPsupply connections and system ground. These high-frequency, inherently
low-inductance capacitors should be placed as close as possible to the device package,
or on the opposite side of the printed circuit board close to the center of the device-
package footprint.
Larger (4.7 µF to 33.0 µF) electrolytic or tantulum bulk capacitors should also be
distributed as needed throughout the system to compensate for voltage sags caused by
circuit trace inductance.
Transient current magnitudes depend on the capacitive and inductive loading on the
device’s outputs. For best signal integrity and device performance, high-speed design
rules should be used when designing the printed-circuit board. Circuit-trace
impedances should match output-driver impedance with adequate ground-return
paths. This will help minimize signal reflections (overshoot/undershoot) and noise
caused by high-speed signal edge rates.
6.2
DC Current Specifications
The M18 device includes specifications for different lithographies, densities, and
frequencies. For additional information on combinations, see Table 4, “M18 Product
Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional
Description.
Table 13: DC Current Specifications (Sheet 1 of 3)
1.7 V – 2.0 V
Litho
(nm)
Density
(Mbit)
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
V
CC = VCC Max
ILI
Input Load Current
—
±1
µA
µA
VCCQ = VCCQ Max
VIN = VCCQ or VSS
1
V
CC = VCC Max
ILO
Output Leakage Current
—
±1
95
VCCQ = VCCQ Max
VIN = VCCQ or VSS
256
35
90
65
90
65
512
128
50
45
120
115
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
ICCS
VCC Standby
µA
1,2
RST# = VCCQ or GND
256
512
50
60
130
160
(for ICCS
)
WP# = VIH
1,024
256
70
35
185
95
512
128
50
45
120
115
VCC = VCC Max
VCCQ = VCCQ Max
CE# = VSSQ
RST# = VCCQ
All inputs are at rail to
rail (VCCQ or VSSQ).
ICCAPS APS
µA
—
256
512
50
60
70
130
160
185
1,024
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 13: DC Current Specifications (Sheet 2 of 3)
1.7 V – 2.0 V
Litho
(nm)
Density
(Mbit)
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
V
CC = VCC Max
VCCQ = VCCQ Max
CE# = VCCQ
RST# = VCCQ
ECR[15] = VCCQ
DPD = VCCQ or VSSQ
IDPD
DPD
2
30
µA
8
All inputs are at rail to
rail (VCCQ or VSSQ).
V
CC = VCCMAX
Average VCC Read: Asynchronous Single Word Read
f = 5 MHz, (1 CLK)
CE# = VIL
OE# = VIH
Inputs: VIL or VIH
ICCR
ICCR
ICCR
ICCR
ICCR
25
11
30
15
mA
mA
1,3,4,5
1,3,4,5
1,3,4,5
1,3,4,5
1,3,4,5
VCC = VCCMAX
CE# = VIL
OE# = VIH
Average VCC Read:
Page Mode Read
Burst = 16 Word
f = 13 MHz, (17 CLK)
Inputs: VIL or VIH
Burst = 8 Word
22
19
25
26
23
30
26
24
33
32
26
34
36
30
42
35
33
46
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = VCCMAX
CE# = VIL
OE# = VIH
Average VCC Read:
Burst = 16 Word
Burst = Continuous
Burst = 8 Word
Synchronous Burst Read
f = 66 MHz, LC = 7
Inputs: VIL or VIH
VCC = VCCMAX
CE# = VIL
OE# = VIH
Average VCC Read:
Burst = 16 Word
Burst = Continuous
Burst = 8 Word
Synchronous Burst Read
f = 108 MHz, LC = 10
Inputs: VIL or VIH
VCC = VCCMAX
CE# = VIL
OE# = VIH
Average VCC Read:
Synchronous Burst Read
f = 133 MHz, LC = 13
Burst = 16 Word
Burst = Continuous
Inputs: VIL or VIH
ICCW,
ICCE
ICCBC
VCC Program
VCC Erase
VCC Blank Check
VPP = VPPL or VPP =
VPPH, program/erase in
progress
1,3,4,
5,7
35
35
50
95
mA
256
90
65
512
128
50
45
120
115
ICCWS, VCC Program Suspend
CE# = VCCQ; suspend in
progress
µA
1,3,6
ICCES
VCC Erase Suspend
256
512
50
60
70
130
160
185
1,024
IPPS,
IPPWS,
IPPES
VPP Standby
VPP Program Suspend
VPP Erase Suspend
VPP = VPPL; suspend in
progress
0.2
5
µA
3
IPPR
VPP Read
2
15
µA
VPP ≤ VCC
3
3
VPP = VPPL = VPPH,
program in progress
IPPW
VPP Program
0.05
0.1
mA
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Datasheet
45
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 13: DC Current Specifications (Sheet 3 of 3)
1.7 V – 2.0 V
Litho
(nm)
Density
(Mbit)
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
VPP = VPPL = VPPH, erase
in progress
IPPE
VPP Erase
VPP Blank Check
0.05
0.1
mA
mA
3
3
VPP = VPPL = VPPH, blank
check in progress
IPPBC
0.05
0.1
Notes:
1.
2.
3.
4.
5.
6.
7.
All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C.
ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
Sampled, not 100% tested.
VCC read + program current is the sum of VCC read and VCC program currents.
VCC read + erase current is the sum of VCC read and VCC erase currents.
ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR
ICCW, ICCE measured over typical or max times specified in Section 7.4, “Program and Erase
Characteristics” on page 68
8.
IDPD is the current measured 40 µs after entering DPD.
6.3
DC Voltage Specifications
Table 14: DC Voltage Specifications
VCCQ
1.7 V – 2.0 V
Symbol
Parameter
Unit
Test Condition
Notes
Min
Max
VIL
Input Low Voltage
0
0.4
—
1
VIH
Input High Voltage
VCCQ –0.4
VCCQ
—
—
VCC = VCCMIN
VCCQ = VCCQMIN
IOL = 100 µA
VOL
Output Low Voltage
—
0.1
—
—
—
V
VCC = VCCMIN
VCCQ = VCCQMIN
IOH = –100 µA
VOH
Output High Voltage
VCCQ –0.1
VPPLK
VLKO
VPP Lock-Out Voltage
VCC Lock Voltage
—
0.4
—
—
—
—
2
1.0
0.9
—
—
VLKOQ
VCCQ Lock Voltage
—
Notes:
1.
During signal transitions, voltage can undershoot to –1.0 V and overshoot to maximum VCCQ+1.0 V for durations of < 2
ns.
2.
VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Datasheet
46
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
6.4
Capacitance
Table 15: Capacitance
Symbol
CIN
Parameter
Min
Typ
Max
Unit
Condition
Notes
Input Capacitance (Address, CLK, CE#,
OE#, ADV#, WE#, WP#, DPD and RST#)
2
2
4
5
6
6
VIN = 0 - 2.0 V
pF
1,2
COUT
Output Capacitance (Data and WAIT)
VOUT = 0 - 2.0 V
Notes:
1.
2.
3.
TC = +25°C, f = 1 MHz.
Sampled, not 100% tested.
Silicon die capacitance only. Add 1 pF for discrete packages; for SCSP total capacitance equals 2 pF + sum of silicon die
capacitance.
April 2008
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Datasheet
47
Numonyx™ StrataFlash® Cellular Memory (M18)
7.0
NOR Flash AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following conventions:
Figure 17: Timing Symbol Notation Convention
E L Q V
t
Source Signal
Source State
Target State
Target Signal
Table 16: Codes for Timing Signals and Timing States
Signal
Code
State
Code
Address
Data - Read
A
Q
D
E
High
Low
High-Z
Low-Z
Valid
Invalid
—
H
L
Data - Write
Z
Chip Enable (CE#)
Output Enable (OE#)
Write Enable (WE#)
Address Valid (ADV#)
Reset (RST#)
X
G
W
V
P
V
I
—
—
—
—
—
Clock (CLK)
C
T
—
WAIT
—
Note:
Exceptions to this conventions include tACC and tAPA. tACC is a generic timing symbol
that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and
tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash
device datasheet, and is the address-to-data delay for subsequent page-mode reads.
7.1
AC Test Conditions
Figure 18: AC Input/Output Reference Waveform
VCCQ
VIH
Input
V
CCQ/2
Test Points
VCCQ/2
Output
VIL
tRISE/FALL
0V
Note: AC test inputs are driven at VCCQ for Logic ‘1’ and 0.0 V for Logic ‘0’. Input/output timing begins and ends at VCCQ/2.
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 17: AC Input Requirements
Symbol
Parameter
Frequency
Min
0.3
Max
Unit
Condition
@133MHz, 108MHz
@66MHz
1.2
3
Inputs rise/fall time (Address, CLK, CE#,
OE#, ADV#, WE#, WP#)
tRISE/FALL
tASKW
VIL to VIH or VIH to VIL
At VCCQ/2
0
0
ns
Address-Address skew
3
Figure 19: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
2.
3.
See the following table for component values.
Test configuration component value for worst case speed conditions.
CL includes jig capacitance.
Table 18: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration
CL (pF)
1.7 V Standard Test
2.0 V Standard Test
30
30
Figure 20: Clock Input AC Waveform
R201
R202
VIH
VCCQ/2
VIL
CLK [C]
R203
CLKINPUT.vsd
7.2
Read Specifications
Read specifications for 108 MHz and 133 MHz M18 devices are included here. For
additional information on lithography, density, and frequency combinations, see
Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the
Section 2.0, “Functional Description.
Devices which support frequencies up to 133 MHz must meet additional timing
specifications for synchronous reads (for address latching with CLK) as listed in
Table 20, “AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V” on page 51.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 19: AC Read, 108 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 1 of 2)
96 ns
Nbr.
Symbol
Parameter1
Unit
Notes
Min
Max
Asynchronous Specifications
R1
R2
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read cycle time
96
—
—
—
—
0
—
96
96
20
150
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
2
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
R3
R4
R5
—
3
R6
R7
OE# low to output in low-Z
0
2,3
R8
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
—
—
0
R9
9
3
R10
R11
R12
R13
R14
R15
R16
R17
—
—
11
9
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
tGLTX
tGHTZ
7
—
—
3
CE# low to WAIT valid
—
—
—
—
0
CE# high to WAIT high Z
OE# high to WAIT valid (AD-Mux only)
OE# low to WAIT valid
7
—
—
3
7
OE# low to WAIT in low-Z
—
9
OE# low to WAIT in high-Z (non-mux only)
0
3
Latching Specifications
R101
R102
R103
R104
R105
R106
R107
R108
R111
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tVHGL
tAPA
Address setup to ADV# high
CE# low to ADV# high
5
9
—
—
96
—
—
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
4
ADV# low to output valid
—
7
ADV# pulse width low
ADV# pulse width high
7
Address hold from ADV# high
ADV# high to OE# low (AD-Mux only)
Page address access (non-mux only)
RST# high to ADV# high
5
7
—
—
—
—
30
tPHVH
Clock Specifications
R200
R201
fCLK
tCLK
CLK frequency
CLK period
—
108
—
MHz
ns
—
—
9.26
CLK
R202
R203
tCH/CL
CLK high/low time
0.45
0.3
0.55
1.2
—
—
period
tFCLK/RCLK CLK fall/rise time
ns
Synchronous Specifications
R301
R302
tAVCH
tVLCH
Address setup to CLK high
ADV# low setup to CLK high
5
5
—
—
ns
ns
—
—
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 19: AC Read, 108 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
96 ns
Nbr.
Symbol
Parameter1
Unit
Notes
Min
Max
R303
R304
R305
R306
R307
R311
R312
tELCH
tCHQV
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
CE# low setup to CLK high
CLK to output valid
5
—
2
—
7
ns
ns
ns
ns
ns
ns
ns
—
—
—
4
Output hold from CLK high
—
—
7
Address hold from CLK high
CLK high to WAIT valid
CLK high to ADV# Setup
WAIT hold from CLK
5
—
2
—
—
—
—
—
2
Notes:
1.
See Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
maximum allowable input slew rate.
2.
3.
4.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
Sampled, not 100% tested.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 1 of 2)
96 ns
Nbr.
Symbol
Parameter1
Units
Notes
Min
Max
Asynchronous Specifications
R1
R2
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read cycle time
96
—
—
—
—
0
—
96
96
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
2
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
R3
R4
R5
150
—
—
7
—
3
R6
CE# low to output in low-Z
R7
OE# low to output in low-Z
0
2,3
R8
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
—
—
0
R9
7
3
R10
R11
R12
R13
R14
R15
R16
R17
—
—
8
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
tGLTX
tGHTZ
7
—
—
3
CE# low to WAIT valid
—
—
—
—
0
CE# high to WAIT high Z
7
OE# high to WAIT valid (AD-Mux only)
OE# low to WAIT valid
5.5
5.5
—
7
—
—
3
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z (non-mux only)
0
3
Latching Specifications
R101
R102
R103
tAVVH
tELVH
tVLQV
Address setup to ADV# high
CE# low to ADV# high
5
7
—
—
ns
ns
ns
—
—
—
ADV# low to output valid
96
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
96 ns
Nbr.
Symbol
Parameter1
Units
Notes
Min
Max
R104
R105
R106
R107
R108
R111
tVLVH
tVHVL
tVHAX
tVHGL
tAPA
ADV# pulse width low
ADV# pulse width high
7
7
—
—
—
—
15
—
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
Address hold from ADV# high
ADV# high to OE# low (AD-Mux only)
Page address access (non-mux only)
RST# high to ADV# high
5
2
—
30
tPHVH
Clock Specifications
R200
R201
fCLK
tCLK
CLK frequency
CLK period
—
133
—
MHz
ns
—
—
7.5
CLK
Period
R202
R203
tCH/CL
CLK high/low time
0.45
0.3
0.55
1.2
4
tFCLK/RCLK CLK fall/rise time
ns
—
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
R313
R314
R315
R316
R317
tAVCH
tVLCH
tELCH
tCHQV
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
tCHVH
tCHGL
tACC
Address setup to CLK high
ADV# low setup to CLK high
CE# low setup to CLK high
CLK to output valid
2
2
—
—
—
5.5
—
—
5.5
—
—
—
—
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clks
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.5
—
2
Output hold from CLK high
Address hold from CLK high
CLK high to WAIT valid
2
—
2
CLK high to ADV# Setup
WAIT hold from CLK high
2
ADV# hold from CLK high
CLK to OE# low (AD-Mux only)
Read access time from address latching clock
ADV# pulse width low for sync reads
ADV# high to CLK high
2
2
96
1
tVLVH
tVHCH
2
—
Notes:
1.
See Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
maximum allowable input slew rate.
2.
3.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
Sampled, not 100% tested.
7.2.1
Read Timing Waveforms
The following sections show the timing waveforms for Asynchronous and Synchronous
read specifications for Non-Mux and AD-Mux M18 devices.
The Synchronous read timing waveforms apply to both the 108 and 133 MHz devices.
However please note that M18 devices which only support up to 108 MHz need not
meet the R313 to R317 timing specifications.
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Please note that the WAIT signal polarity in all the timing waveforms is low-true
(RCR10 = 0). WAIT is shown as de-asserted with valid data (RCR8 = 0). WAIT is de-
asserted during asynchronous reads.
Table 21: List of Read Timing waveforms
M18 Device
Description
Async Page-Mode Read
Synchronous 8- or 16-word Burst Read
Non-Mux
Synchronous Continuous Mis-aligned Burst Read
Synchronous Burst with Burst-Interrupt
Async Single-Word Read
Synchronous 8- or 16-word Burst Read
Synchronous Continuous Mis-aligned Burst Read
Synchronous Burst with Burst-Interrupt
ADMux
7.2.2
Timings: Non-Mux Device, Async Read
Figure 21: Async Page-Mode Read (Non-Mux)
R1
R2
R106
A[MAX:4]
A[3:0]
R101
R111
R105
R104
R103
ADV#
R102
R11
R13
R3
CE#
R4
R17
OE#
R12
R15
R16
WAIT
R9
R8
R7
R6
R108
R10
R108
R10
R108
R10
R10
DQ[15:0]
R5
RST#
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.2.3
Timings: Non-Mux Device, Sync Read
Figure 22: Sync Single-Word Array/Non-Array Read, 108 MHz
Latency Count
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
CE# [E]
OE# [G]
WAIT [T]
R7
R16
R307
R304
R13
R4
R8
R9
R305
Data [D/Q]
Figure 23: Synchronous 8- or 16-word Burst Read (Non-Mux)
R1
Latency Count
R201
R202
R202
CLK
R306
R302
A[MAX:0]
R301
R101
R106
R317
R104
R316
R105
R311
R313
ADV#
R11
R13
R102
R303
CE#
OE#
R16
R15
R12
R307
R307
R312
R17
WAIT
R315
R7
R304
R4
R103
R3
R8
R305
R304
R305
R304
R2
R9
DQ[15:0]
RST#
R111
R5
Notes:
1.
8-word and 16-word burst are always wrap-only.
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2.
3.
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation.
.
Figure 24: Synchronous Continuous Mis-aligned Burst (Non-Mux)
R1
Latency Count
R201
R202
R202
CLK
R306
R302
A[MAX:0]
R301
R101
R105
R106
R317
R104
R316
R311
R313
ADV#
R102
R303
R11
R13
CE#
OE#
R12
R15
R307
R307
R312
R307
R312
R16
R7
R17
R10
WAIT
R315
R4
R103
R10
R6
R304
R9
R2
R3
R305
R304
R305
R304
R8
DQ[15:0]
RST#
Q
Q
Q
End of WL
Q
Q
R111
R5
Notes:
1.
2.
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation.
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Numonyx™ StrataFlash® Cellular Memory (M18)
.
Figure 25: Sync Burst with Burst-Interrupt (Non-Mux)
R202
R1
Latency Count
R201
R202
CLK
R302
R306
R302
R306
A[MAX:0]
R301
R101
R301
R101
R106
R317
R10
R313
R313
R104
R316
R311
R11
R104
R316
R311
R105
ADV#
R303
R102
R102
R303
CE#
OE#
R12
R307
R307
R312
R16
R15
WAIT
R315
R7
R4
R103
R6
R304
R2
R3
R304
R305
R305
DQ[15:0]
RST#
Q
Q
Q
Q
R111
R5
Notes:
1.
2.
3.
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only
For legacy-latching (ADV# OR CLK latching), ADV# can be held low throughout the synchronous read operation.
A burst can be interrupted by toggling CE# or ADV#. If ADV# interrupts burst, then R105 applies.
Datasheet
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7.2.4
Timings: AD-Mux Device, Async Read
Figure 26: Async Single-Word Read (AD-Mux)
R1
R1
R2
R2
A[MAX:16]
A/DQ[15:0]
A
A
R7
R7
A
Q
A
Q
R101
R106
R101
R106
R111
R103
R104
R102
R104
R102
R105
R103
R3
ADV#
CE#
R10
R8
R11
R10
R8
R3
R4
R4
R107
R9
R107
R9
OE#
WAIT
RST#
R12
R13
R12
R13
R5
Note: Diagram shows back-to-back read operations.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.2.5
Timings: AD-Mux Device, Sync Read
.
Figure 27: Synchronous 8- or 16-word burst read (AD-Mux)
R1
Latency Count
R201
R202
R202
CLK
A[MAX:16]
A
A
A
A
R315
R304
R305
R302
R306
R304
R2
R302
R306
A/DQ[15:0]
Q
Q
Q
R313
R313
R301
R101
R301
R101
R106
R317
R10
R104
R316
R104
R316
R103
R311
R11
R311
R105
ADV#
CE#
R303
R102
R303
R102
R3
R7
R107
R314
R10
R9
R4
OE#
R307
R15
R16
R12
WAIT
RST#
R111
R5
Notes:
1.
2.
8-word and 16-word burst are always wrap-only.
R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
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Figure 28: Synchronous Continuous Mis-Aligned Burst (AD-Mux)
R1
Latency Count
R201
R202
R202
CLK
A[MAX:16]
A
A
R306
R315
R2
R304
R305
R304
R305
R302
R304
A/DQ[15:0]
Q
Q
Q
End of WL
Q
Q
Q
R104
R301
R101
R105
R106
R317
R316
R103
R311
R313
ADV#
R102
R11
R8
R3
R303
R10
CE#
OE #
R107
R314
R7
R10
R9
R4
R307
R307
R312
R307
R312
R13
R15
R16
R12
R14
WAIT
RST#
R111
R5
Note: R2, R3 and R103 apply to legacy-latching only; R315 and R316 apply to clock-only latching only.
Figure 29: Synchronous Burst with Burst-Interrupt (AD-Mux)
R1
Latency Count
R201
R202
R202
CLK
A[MAX:16]
A
A
A
A
R315
R304
R305
R302
R306
R304
R2
R302
R306
A/DQ[15:0]
Q
Q
Q
R313
R313
R301
R101
R301
R101
R106
R317
R10
R104
R316
R104
R316
R103
R311
R11
R311
R105
ADV#
CE#
R303
R102
R303
R102
R3
R7
R107
R314
R10
R9
R4
OE#
R307
R15
R16
R12
WAIT
RST#
R111
R5
Notes:
1.
2.
R2, R3 and R103 apply to legacy-latching only (ADV# OR CLK latching); R315 and R316 apply to clock-only latching only
A burst can be interrupted by toggling CE# or ADV#.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.3
Write Specifications
The M18 device includes specifications for different lithographies, densities, and
frequencies. For additional information on combinations, see Table 4, “M18 Product
Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional
Description.
Table 22: AC Write Specifications
Number
W1
Symbol
tPHWL
Parameter (1, 2)
Min
Max
Units
Notes
RST# high recovery to WE# low
CE# setup to WE# low
150
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2
W2
tELWL
0
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
tQVBL
tBHWH
tWHGL
tVLWH
tWHQV
WE# write pulse width low
Data setup to WE# high
40
1,2,4
W4
40
W5
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high (non-mux only)
WE# pulse width high
40
W6
0
1,2
W7
0
W8
0
W9
20
1,2,5
W10
W11
W12
W13
W14
W15
W16
VPP setup to WE# high
200
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
0
1,2,3,7
0
200
WE# high to OE# low
0
1,2,8
1,2
ADV# low to WE# high (AD-Mux only)
WE# high to read valid
55
tAVQV+30
1,2,3,9
Write to Synchronous Read Specifications
W19
W27
W28
tWHCH
tWHEL
tWHVL
WE# high to Clock high
WE# high to CE# low
WE# high to ADV# low
15
9
—
—
—
ns
ns
ns
1,2,3,6,9
1,2,3,6,9
1,2,3,6,9
7
Bus Write with Active Clock Specifications
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
—
—
27
27
ns
ns
1,2,10,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5.
6.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
tWHCH must be met when transitioning from a write cycle to a synchronous burst read. In addition there must be a CE#
toggle after WE# goes high.
7.
8.
9.
VPP and WP# should be at a valid level until erase or program success is determined.
When doing a Read Status operation following any command that alters the Status Register data, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
10.
11.
This specification is applicable only if the part is configured in synchronous mode and an active clock is running. Either
tVHWL or tCHWL must be met depending on the whether the address is latched on ADV# or CLK.
These specifications are not applicable to 133 MHz devices.
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.3.1
Write Timing Waveforms
The following sections show the timing waveforms for write specifications and write-to-
read and read-to-write transitions for Non-Mux and AD-Mux M18 devices.
The Synchronous read timings apply to both the 108 and 133 MHz devices. However
please note that M18 devices which only support up to 108 MHz need not meet the
R313 to R317 timing specifications.
Please note that the WAIT signal polarity in all the timing waveforms is low-true
(RCR10 = 0). WAIT is de-asserted during asynchronous reads.
Table 23: List of Write Timing waveforms
M18 Device
Description
Write to Write
Async Read to Write
Write to Async Read
Sync Read to Write
Write to Sync Read
Write to Write
Non-Mux
Async Read to Write
Write to Async Read
Sync Read to Write
Write to Sync Read
ADMux
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.3.2
Timings: Non Mux Device
Figure 30: Write to Write (Non-Mux)
W5
W8
W5
W8
Address [A]
ADV#
W2
W6
W2
W6
CE# [E}
W3
W9
W3
WE# [W]
OE# [G]
W7
W7
W4
W4
Data [D/Q]
W1
RST# [P]
W13
WP#
Figure 31: Async Read to Write (Non-Mux)
Address [A]
ADV# [V]
A
A
R105
R11
CE# [E]
OE# [G]
W6
W7
W2
W3
W15
WE# [W]
R4
R10
R8
R9
R2
R3
W4
D/Q[15:0]
WAIT [T]
Q
D
R15
R17
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 32: Write to Async Read (Non-Mux)
Address [A]
ADV# [V]
Write Adr
Read Adr
W2
R11
CE# [E]
W5
W6
W3
W8
WE# [W]
OE# [G]
WAIT [T]
W14
R15
R4
R17
High-Z
R3
R2
R10
R8
W7
W4
W16
R9
D
Q
Data [D/Q]
.
Figure 33: Sync Read to Write (Non-Mux)
R311
R313
R306
W22
CLK [C]
Address [A]
CE# [E]
R301
W5
R303
R11
R302
R316
R105
ADV# [V]
W3
WE# [W]
OE# [G]
R305
R304
R304
R307
R305
W4
W7
Data [D/Q]
WAIT [T]
Q0
Q1
D
High-Z
High-Z
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 34: Write to Sync Read (Non-Mux)
W19
R302
R303
CLK
R301
Wrt Addr
Rd Addr
Address [A]
R311
R105
R313
ADV# [V]
CE# [E]
W9
R11
W27
W3
W22
W28
WE# [W]
OE# [G]
W14
W7
R304
R305
R304
R305
W4
R304
R307
R305
Q2
D
Q0
Q1
Data [D/Q]
WAIT [T]
R15
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7.3.3
Timings: AD-Mux Device
Figure 35: Write to Write (AD-Mux)
A[max-16] [A]
W5
W4
R101
W7
W6
A/DQ[15-0] [A/D]
ADV# [v]
A
D
A
D
R106
W15
W2
W2
W6
CE# [E]
W3
W9
W3
WE# [W]
OE# [G]
W1
RST# [P]
WP#
W13
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 36: Async Read to Write (AD-Mux)
A[Max:16]
A/DQ[15:0]
ADV# [V]
A
A
R2
R10
A
Q
A
D
R101
R105
R8
R11
R3
CE# [E]
OE# [G]
R4
R107
R9
W7
W3
W4
W15
WE# [W]
WAIT [T]
R12
R13
R12
R13
Figure 37: Write to Async Read (AD-Mux)
W5
A[Max:16]
A/DQ[15:0]
CE# [E]
A
A
A
W4
W7
W6
R2
R3
D
A
Q
R11
R8
R105
W15
ADV# [V]
WE# [W]
W2
W3
R4
R107
W14
R9
OE# [G]
R12
R13
R12
R13
WAIT [T]
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 38: Sync Read to Write (AD-Mux)
R311
R313
R306
W22
CLK [C]
R301
W5
A[Max:16]
A
A
A
R305
R304
R304
R305
A/DQ[15:0]
CE# [E]
A
Q0
Q1
D
R303
R11
R302
R316
W15
ADV# [V]
W7
W4
WE# [W]
OE# [G]
R307
High-Z
High-Z
WAIT [T]
Notes:
1.
2.
CLK may be stopped during write cycle.
W22 is the time between the Address-latching-CLK and WE#. In case of ADV#-latching, W21 must be met instead.
Figure 39: Write to Sync Read (AD-Mux)
W19
CLK
W5
A[Max:16]
A/DQ[15:0]
WAIT [T]
A
A
A
A
W4
R305
R304
R305
R304
W7
R304
R307
R305
Q2
D
Q0
Q1
R15
R105
W15
W28
ADV# [V]
CE# [E]
R11
W3
W22
W27
WE# [W]
OE# [G]
W14
Note: CLK may be stopped during write cycle.
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.4
Program and Erase Characteristics
The M18 device includes specifications for different lithographies, densities, and
frequencies. For additional information on combinations, see Table 4, “M18 Product
Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional
Description.
Table 24: Program-Erase Characteristics
V
PPL/VPPH
Nbr.
Symbol
Parameter
Unit Notes
Density
(Mbit)
Litho (nm)
Min
Typ
Max
Conventional Word Programming
Single word (first
—
—
—
—
—
—
115
50
230
230
word)
Program
Time
W200
tPROG/W
µs
1,2
Single word
(subsequent word)
Buffered Programming
W200
tPROG/W
Single word
—
—
—
—
250
500
4.3
µs
256, 512
Program
Time
90
2.15
1
One Buffer (512
words)
W250
tPROG/PB
ms
128, 256, 512,
1024
65
1.02
2.05
Buffered Enhanced Factory Programming
90
256, 512
4.2
W451
W452
tBEFP/W
Single word
—
5
—
—
1,3,4
1
Program
Time
65
—
128, 256, 512
—
2.0
—
µs
tBEFP/
Setup
Buffered EFP Setup
Erasing and Suspending
Erase
Time
128-Kword Main
Array Block
W501
tERS/MAB
—
—
—
0.9
4
s
1
W600
W601
tSUSP/P
tSUSP/E
Suspen
d
Latency
Program suspend
Erase suspend
—
—
—
—
—
—
20
20
30
30
1
1
µs
Blank Check
Blank
Check
W702
tBC/MB
Main array block
—
—
—
3.2
—
ms
1
Notes:
1.
Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions.
Sampled, but not 100% tested.
2.
3.
4.
First and subsequent words refer to first word and subsequent words in Control Mode programming region.
Averaged over entire device.
BEFP not validated at VPPL
.
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
7.5
Reset Specifications
Table 25: Reset Specifications
Nbr.
Symbol
tPLPH
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
100
—
ns
1,2,3,4,7
1,3,4,7
1,3,4,7
1,4,5,6
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
25
25
—
P2
tPLRH
—
µs
P3
tVCCPH
300
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
Not applicable if RST# is tied to Vccq.
Sampled, but not 100% tested.
If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC
VCC(min).
≥
7.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Figure 40: Reset Operation Timing
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
7.6
Deep Power Down Specifications
Table 26: Deep Power Down Specifications (Sheet 1 of 2)
Nbr.
Symbol
Parameter
DPD asserted pulse width
Min
100
Max
Unit
Notes
S1
t
SLSH (tSHSL)
—
ns
1,2,3
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Table 26: Deep Power Down Specifications (Sheet 2 of 2)
Nbr.
Symbol
Parameter
CE# high to DPD asserted
Min
Max
Unit
Notes
S2
S3
tEHSH (tEHSL)
0
—
—
1,2
1,2
t
SHEL (tSLEL)
DPD deasserted to CE# low
75
µs
RST# high during DPD state to CE# low (DPD
deasserted to CE# low)
S4
tPHEL
75
—
1,2
Notes:
1.
2.
3.
These specifications are valid for all device versions (packages and speeds).
Sampled, but not 100% tested.
DPD must remain asserted for the duration of Deep Power Down mode. DPD current levels are achieved 40 µs after
entering the DPD mode.
Figure 41: Deep Power Down Operation Timing
S2
S1
DPD [S]
S3
CE# [E]
RST# [P]
Note: DPD pin is low-true (ECR14 = 0)
Figure 42: Reset During Deep Power Down Operation Timing
RST# [P]
S2
DPD [S]
S4
CE# [E]
Note: DPD pin is low-true (ECR14 = 0)
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8.0
NOR Flash Bus Interface
The flash device uses low-true control signal inputs, and is selected by asserting the
chip enable (CE#) input. The output enable (OE#) input is asserted for read
operations, while the write enable (WE#) input is asserted for write operations. OE#
and WE# should never be asserted at the same time; otherwise, indeterminate device
operation will result. All bus cycles to or from the flash memory conform to standard
microcontroller bus cycles.
Commands are written to the device to control all operations.
Table 27 shows the logic levels that must be applied to the control-signal inputs of the
device for the various bus operations.
Table 27: Flash Memory Control Signals
Operation
RST#
DPD2
CE#1
OE#1
WE#1
Address1
Data I/O
Reset
Read
Low
High
High
High
High
High
X
X
X
X
Valid
X
High-Z
Output
High-Z
Low
Low
Low
High
High
High
Output Disable
High
High
High
High
Low
High
High
Valid
Valid
Input
Input
Write
Low
Standby
High
High
High
Low
High
High
X
X
X
X
X
X
High-Z
High-Z
Deep Power-Down
Notes:
1.
2.
X = Don’t care (High or Low)
DPD polarity determined by ECR14. Shown low-true here.
8.1
Bus Reads
To perform a read operation, both CE# and OE# must be asserted; #RST# and WE#
must be deasserted. OE# is the data-output control and when asserted, the output
data is driven on to the data I/O bus. All read operations are independent of the
voltage level on VPP.
The Automatic Power Savings (APS) feature provides low power operation following
reads during active mode. After data is read from the memory array and the address
lines are quiescent, APS automatically places the device into standby. In APS, device
current is reduced to ICCAPS
.
The device supports two read configurations:
• Asynchronous reads. RCR15 = 1. This is the default configuration after power-up/
reset.
— Non-multiplexed devices support asynchronous page-mode reads. AD-
Multiplexed devices support only asychronous single-word reads.
• Synchronous Burst reads. RCR15 = 0.
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8.1.1
8.1.2
Asynchronous single-word reads
In asynchronous single-word read mode, a single word of data corresponding to the
address is driven onto the data bus after the initial access delay. The address is latched
when ADV# is deasserted. For AD-multiplexed devices, ADV# must be deasserted
before OE# is asserted.
If only asynchronous reads are to be performed, CLK must be tied to a valid VIH or VIL
level, and the WAIT signal can be floated. In addition, for non-multiplexed devices,
ADV# must be tied to ground.
Asynchronous Page Mode (Non-multiplexed devices only)
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address is driven onto the data bus after the initial access
delay. Subsequent words in the page are output after the page access delay. A[3:0]
bits determine which page word is output during a read operation. A[MAX:4] and ADV#
must be stable throughout the page access.
WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch
the address, or held low throughout the read cycle. CLK is not used for asynchronous
page-mode reads, and is ignored.
8.1.3
Synchronous Burst Mode
Synchronous burst mode is a clock-synchronous read operation that improves the read
performance of flash memory over that of asynchronous reads.
Synchronous burst mode is enabled by programming the Read Configuration Register
(RCR) of the flash memory device. The RCR is also used to configure the burst
parameters of the flash device, including Latency Count, burst length of 8, 16 and
continuous, and WAIT polarity.
Three additional signals are used for burst mode: CLK, ADV#, and WAIT.
The address for synchronous read operations is latched on the ADV# rising edge or the
first rising CLK edge after ADV# low, whichever occurs first for devices that support up
to 108 MHz. For devices that support up to 133 MHz, the address is latched on the last
CLK edge when ADV# is low.
During synchronous read modes, the first word is output from the data buffer on the
rising CLK edge after the initial access latency delay. Subsequent data is output on
rising CLK edges following a tCHQV delay. However, for a synchronous non-array read,
the same word of data will be output on successive rising clock edges until the burst
length requirements are satisfied.
8.1.3.1
WAIT Operation
Upon power up or exit from reset, WAIT polarity defaults to low-true operation (RCR10
= 0). During synchronous reads (RCR15 = 0), WAIT asserts when read data is invalid,
and deasserts when read data is valid. During asynchronous reads (RCR15 = 1), WAIT
is deasserted. During writes, WAIT is High-Z on non-mux devices, and deasserted on
AD-mux devices. Table 28 summarizes WAIT behavior.
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Table 28: WAIT Behavior Summary
Device Operation
CE#
High
OE#
WE#
WAIT
High-Z
Notes
Device not selected
Non-Mux Device
Standby
X
X
1
2
Output Disable
Sync Read
Async Read
Write
High
Low
Low
High
High
Low
Low
High
High
High
High
Low
High-Z
Active
Deasserted
High-Z
Low
Output Disable
Sync Read
Async Read
Write
High
High
High
Low
Deasserted
Active
2
AD-Mux Device
Deasserted
Deasserted
Notes:
1.
2.
X = don’t care (high or low).
Active: WAIT asserted = invalid data; WAIT deasserted = valid data.
8.2
8.3
8.4
Bus Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. All device write operations are asynchronous, with CLK being ignored, but
CLK can be kept active/toggling. During a write operation in non-muxed devices,
address and data are latched on the rising edge of WE# or CE#, whichever occurs first.
During a write operation in muxed devices, address is latched during the rising edge of
ADV# OR CE# whichever occurs first and Data is latched during the rising edge of WE#
OR CE# whichever occurs first.
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal
circuitry is turned off and outputs are placed in a high-impedance state. The device
shuts down any operation in progress, a process which takes a minimum amount of
time to complete.
To return from reset mode, RST# must be deasserted. Normal operation is restored
after a wake-up interval.
Deep Power-Down
The device enters DPD mode when the following two conditions are met: ECR15 is
set(1) and DPD is asserted. The two conditions can be satisfied in any order. ECR14 bit
determines the DPD asserted logic level. While in this mode, RST# and CE# must be
deasserted.
The device exits DPD mode when DPD is deasserted. There is an exit latency before the
device returns to standby mode and any operations are allowed. See the datasheet for
the timing specifications.
The device should not be placed in DPD mode when a program/erase operation is
ongoing or suspended. If the device enters DPD mode in the middle of a program,
erase or suspend, the operation is terminated and the memory contents at the aborted
location (for a program) or block (for an erase) are no longer valid.
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While in DPD mode, the read-mode of each partition, configuration registers (RCR and
ECR), and block lock bits, are preserved. Status register is reset to 0080h; i.e., if the
Status register contains error bits, they will be cleared.
8.5
Standby
When CE# is deasserted, the device is deselected and placed in standby, substantially
reducing power consumption. In standby, data outputs are placed in high-Z,
independent of the level placed on OE#. If deselected during a Program or Erase
operation, the device continues to consume active power until the operation is
complete. There is no additional latency for subsequent read operations.
8.6
8.7
Output Disable
When OE# is deasserted with CE# asserted, the device outputs are disabled. Output
pins are placed in a high-impedance state. WAIT is deasserted in AD-muxed devices
and driven to High-Z in non-multiplexed devices.
Bus Cycle Interleaving
When issuing commands to the device, a read operation can occur between the two
write cycles of a 2-cycle command. (See Figure 43 and Figure 44) However, a write
operation cannot occur between the two write cycles of a 2-cycle command and will
cause a command sequence error (See Figure 45).
Figure 43: Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition A
Partition B
OE# [G]
Data [D/Q]
0x20
0xD0
0xFF
Figure 44: Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
OE# [G]
Data [D/Q]
0x20
Valid Array Data
0xD0
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Figure 45: Operating Mode with Illegal Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
Partition A
OE# [G]
Data [D/Q]
0x20
0xFF
0xD0
SR[7:0]
8.7.1
Read Operation During Program Buffer fill
Due to the large buffer size of devices, the system interrupt latency may be impacted
during the buffer fill phase of a buffered programming operation. Please refer to the
relevant Application Note listed in Section 1.4, “Additional Information” on page 7 to
implement a software solution for your system.
8.8
Read-to-Write and Write-to-Read Bus Transitions
Consecutive read and write bus cycles must be properly separated from each other to
avoid bus contention. These cycle separation specs are described in the sections below.
8.8.1
8.8.2
Write to Asynchronous read transition
To transition from a bus write to an asynchronous read operation, either CE# or ADV#
must be toggled after WE# goes high.
Write to synchronous read transition
To transition from a bus write to a synchronous read operation, either CE# or ADV#
must be toggled after WE# goes high. In addition, W19 (tWHCH -WE# high to CLK high)
must be met.
8.8.3
8.8.4
Asynchronous/Synchronous read to write transition
To transition from a asynchronous/synchronous read to a write operation, either CE# or
ADV# must be toggled after OE# goes high.
Bus write with active clock
To perform a bus write when the device is in synchronous mode and the clock is active,
W21 (tVHWL- ADV# High to WE# Low) or W22 (tCHWL -Clock high to WE# low) must be
met.
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9.0
NOR Flash Operations
This section describes the operational features of NOR flash memory. Operations are
command-based—command codes are first issued to the device, and then the device
performs the desired operation. All command codes are issued to the device using bus-
write cycles as explained in Section 3.0, “NOR Flash Bus Interface” on page 10. A
complete list of available command codes can be found in Section 5.0, “Device
Command Codes” on page 40.
9.1
Status Register
The Status Register (SR) is a 16-bit, read-only register that indicates device and
partition status, and operational errors. To read the Status Register, issue the Read
Status Register command. Subsequent reads output Status Register information on
AD/DQ[15:10].
SR status bits are set and cleared by the device. SR error bits are set by the device,
and must be cleared using the Clear Status Register command. Upon power-up or exit
from reset, the Status Register defaults to 0080h.
Table 29: Status Register Bit Definitions (Sheet 1 of 2)
Status Register (SR) Bits
Default Value = 0080h
Program
/Erase
Voltage
Error
Region
Reserved Program
Status
Erase
Suspend
Status
Program
Suspend
Status
Block-
Partition
Locked
Status
Error
Ready
Status
Erase
Error
Program
Error
15-10
9-8
7
6
5
4
3
2
1
0
Bit
Name
Description
15-10
Reserved
Reserved for future use; these bits will always be set to zero.
SR9 SR8
0
1
0
0
=
=
Region program successful.
Region program error - Attempted write with object data to Control
Mode region.
9-8
Region Program Status
0
1
1
1
=
=
Region program error - Attempted rewrite to Object Mode region.
Region program error - Attempted write using illegal command.
SR4 will also be set along with SR[8,9] for the above error
conditions.
0
1
=
=
Device is busy; SR[9:8], SR[6:1] are invalid;
Device is ready; SR[9:8], SR[6:1] are valid.
7
6
Ready Status
0
1
=
=
Erase suspend not in effect.
Erase suspend in effect.
Erase Suspend Status
Erase
Error /
Blank
Check
Error
SR5 SR4
5
0
0
1
1
0
1
0
1
=
=
=
=
Program or erase operation successful.
Program error - operation aborted.
Erase error: operation aborted / Blank check error: operation failed.
Command sequence error - command aborted.
Command
Sequence Error
Program
Error
4
3
0
1
=
=
VPP within acceptable limits during program or erase operation.
VPP not within acceptable limits during program or erase operation.
VPP Error
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Table 29: Status Register Bit Definitions (Sheet 2 of 2)
Status Register (SR) Bits
Default Value = 0080h
Program
/Erase
Voltage
Error
Region
Reserved Program
Status
Erase
Suspend
Status
Program
Suspend
Status
Block-
Partition
Locked
Status
Error
Ready
Status
Erase
Error
Program
Error
15-10
9-8
7
6
5
4
3
2
1
0
Bit
2
Name
Description
0
1
=
=
Program suspend not in effect.
Program suspend in effect.
Program Suspend Status
Block-Locked Error
0
1
=
=
Block NOT locked during program or erase - operation successful.
Block locked during program or erase - operation aborted.
1
SR7 SR0
0
0
1
1
0
1
0
1
=
=
=
=
Active program or erase operation in addressed partition.
BEFP: Program or Verify complete, or Ready for data.
Active program or erase operation in other partition.
BEFP: Program or Verify in progress.
No active program or erase operation in any partition.
BEFP: Operation complete
0
Partition Status
Reserved.
9.1.1
Clearing the Status Register
The Status Register (SR) contain status and error bits which are set by the device. SR
status bits are cleared by the device; however, SR error bits are cleared by issuing the
Clear Status Register command. Resetting the device also clears the Status Register.
Table 30: Clear Status Register Command Bus Cycles
Setup Write Cycle
Command
Confirm Write Cycle
Address Bus Data Bus
Address Bus
Data Bus
Clear Status Register
Device Address
0050h
---
---
Depending on the current state of the partition, issuing the Clear Status Command will
place the addressed partition in Read Status mode. Please see 'Next State' Table for
further details. Other partitions are not affected.
Note:
Care should be taken to avoid Status Register ambiguity. If a command sequence error
occurs while in an Erase Suspend condition, the Status Register will indicate a
Command Sequence error by setting SR4 and SR5. When the erase operation is
resumed (and finishes), any errors that may have occurred during the erase operation
will be masked by the Command Sequence error. To avoid this situation, clear the
Status Register prior to resuming a suspended erase operation.
The Clear Status Register command functions independent of the voltage level on VPP.
9.2
Read Configuration Register
The Read Configuration Register (RCR) is a 16-bit read/write register used to select
bus-read modes, and to configure synchronous-burst read characteristics of the flash
device. All Read Configuration Register bits are set and cleared using the Program Read
Configuration Register command.
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Upon power-up or exit from reset, the Read Configuration Register defaults to
asynchronous mode (RCR15 = 1; RCR[14:11] and RCR[9:0] are ignored).
To read the RCR value, issue the Read Device Information command to the desired
partition. Subsequent reads from the <partition base address> + 05h will output
RCR[15:0] on the data bus.
When using a Latency Count of Code 2 and a Data Hold of two cycles (CR9 = 1), WAIT
must be configured to deassert with valid data (CR8 = 0).
Table 31: Read Configuration Register Bit Definitions
Read Configuration Register (RCR)
Default: CR15 = 1
Burst Length
Read
WAIT
Polarity
WAIT
Delay
Latency Count
Mode
R
Reserved
15
14
13
12
11
10
9
8
7:3
2
1
0
Bit
Name
Description
0 = Synchronous burst-mode reads
15
Read Mode
1 = Asynchronous page-mode reads (default)
Bits: 14 13 12 11
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
=
=
=
=
=
=
=
=
=
=
3
4
5
6
7
8
9
14:11
Latency Count
10
11
12
(Other bit settings are reserved)
0
1
=
=
WAIT signal is active low (default)
WAIT signal is active high
10
WAIT Polarity
9
Reserved
WAIT Delay
Reserved
Write 0 to reserved bits
0
1
=
=
WAIT de-asserted with valid data
WAIT de-asserted one cycle before valid data (default)
8
7:3
Write 0 to reserved bits
0
0
1
1
1
1
0
1
1
=
=
=
8-word burst (wrap only)
16-word burst (wrap only)
Continuous-word burst (no-wrap; default) (Other bit settings
are reserved)
2:0
Burst Length
9.2.1
Latency Count
The Latency Count value programmed into RCR[14:11] is the number of valid CLK
edges from address-latch to the start of the data-output delay. When the Latency
Count has been satisfied, output data is driven after tCHQV.
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Figure 46: Latency Count Period
Latency Count
CLK Latch (1)
CLK
ADV# (1)
ADV#-Latch (2)
ADV# (2)
A[Max:0]
CE#
OE#
tCHQV
DQ[15:0]
Notes:
1.
2.
Address latched on valid clock edge with ADV# low and LC count begins.
Address latched on ADV# rising edge. LC count begins on subsequent valid CLK edge.
Table 32: CLK Frequencies for LC Settings
VCCQ = 1.7 V to 2.0 V
Latency Count Setting
Frequency Supported (MHz)
3
≤ 32.6 MHz
≤ 43.5 MHz
≤ 54.3 MHz
≤ 65.2 MHz
≤ 76.1 MHz
≤ 87 MHz
4
5
6
7
8
9
≤ 97.8 MHz
≤ 108.7 MHz
≤ 119.6 MHz
≤ 130.4 MHz
≤ 133.3 MHz
10
11
12
13
9.3
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile 16-bit, read/write register used
to select Deep Power Down (DPD) operation and to modify the output-driver strength
of the flash device. All Enhanced Configuration Register bits are set and cleared using
the Program Enhanced Configuration Register command. Upon power-up or exit from
reset, the Enhanced Configuration Register defaults to 0004h.
To read the value of the ECR, issue the Read Device Information command to the
desired partition. Subsequent reads from the <partition base address> + 06h returns
ECR[15:0].
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Table 33: Enhanced Configuration Register Bit Definitions
Enhanced Configuration Register
Default = 0004h
Output Driver Control
Deep Power Down
DPD Polarity
14
Reserved
(DPD) Mode
15
13:3
2
1
0
Bit
Name
Description
0
1
= DPD Disabled (default)
15
Deep Power Down (DPD) Mode
=
DPD Enabled
0
1
=
=
Active Low (default)
Active High
14
DPD Pin Polarity
Reserved
13:3
Write 0 to reserved bits
Bits:
2
0
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
=
=
=
=
=
=
1
2
3
2:0
Output Driver Control
4 (default)
5
6
(Other bit settings are reserved)
9.3.1
Output Driver Control
Output Driver Control enables the user to adjust the device’s output-driver strength of
the data I/O bus and WAIT signal. Upon power-up or reset, ECR[2:0] defaults to an
output impedance setting of 30 Ohms. To change the output-driver strength, ECR[2:0]
must be programmed to the desired setting as shown in Table 34, “Output Driver
Control Characteristics”.
Table 34: Output Driver Control Characteristics
Control Bits ECR[2:0]
Impedance @ VCCQ/2 (Ohm)
90
Driver Multiplier
Load Driven at Same Speed (pF)
10
001
(1)
1/3
1/2
2/3
1
010
011
100
101
110
(2)
60
45
30
20
15
15
20
30
35
40
(3)
(4) default
(5)
3/2
2
(6)
9.3.2
Programming the ECR
The ECR is programmed by issuing the Program Enhanced Configuration Register
command. This is a two-cycle command sequence requiring a Setup command to be
issued first, followed by a Confirm command. Bus-write cycles to the flash device
between the setup and confirm commands are not allowed—a command sequence
error will result. However, flash bus-read cycles between the Setup and Confirm
commands are allowed.
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Table 35: Program Enhanced Configuration Register Command Bus Cycles
Setup Write Cycle
Confirm Write Cycle
Command
Address Bus
Register Data
Data Bus
Address Bus
Data Bus
Program Enhanced Configuration Register
0060h
Register Data
0004h
To program the Enhanced Configuration Register, the desired settings for ECR[15:0]
are placed on the address bus. The setup command (0060h) is driven on the data bus.
Upon issuing the setup command, the device/addressed partition is automatically
changed to Read Status Register mode.
Next, the Confirm command (0004h) is driven on the data bus. After issuing the
Confirm command, the addressed partition is automatically switched to Read Array
mode.
This command functions independently of the applied VPP voltage.
Note:
Since the desired register value is placed on the address lines, any hardware-
connection offsets between the host’s address outputs and the flash device’s address
inputs must be considered, similar to programming the RCR.
9.4
Read Operations
The following types of data can be read from the device: array data, device
information, CFI data, and device status Upon power-up or return from reset, the
device defaults to Read Array mode. To change the device’s read mode, the appropriate
command must be issued to the device. Table 36, “Read Mode Command Bus Cycles”
shows the command codes used to configure the device for the desired read mode. The
following sections describe each read mode.
Table 36: Read Mode Command Bus Cycles
Setup Write Cycle
Address Bus
Partition Address
Confirm Write Cycle
Address Bus Data Bus
Command
Data Bus
00FFh
Read Array
---
---
---
---
---
---
---
---
Read Status Register
Read Device Information
CFI Query
Partition Address
Partition Address
Partition Address
0070h
0090h
0098h
9.4.1
Read Array
Upon power-up or exit from reset, the device defaults to Read Array mode. Issuing the
Read Array command places the addressed partition in Read Array mode. Subsequent
reads output array data. The addressed partition remains in Read Array mode until a
different read command is issued, or a program or erase operation is performed in that
partition, in which case, the read mode is automatically changed to Read Status.
To changea partition to Read Array mode while it is programming or erasing, first issue
the Suspend command. After the operation has been suspended, issue the Read Array
command to the partition. When the program or erase operation is subsequently
resumed, the read state of the partition will not change. To change the read state of
the partition to Status read mode, issue a Read Status command to the partition.
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Note:
Issuing the Read Array command to a partition that is actively programming or erasing
causes subsequent reads from that partition to output invalid data. Valid array data is
output only after the program or erase operation has finished.
The Read Array command functions independent of the voltage level on VPP.
9.4.2
Read Status Register
Issuing the Read Status Register command places the addressed partition in Read
Status Register mode. Subsequent reads from that partition output Status Register
information. The addressed partition remains in Read Status Register mode until a
different read-mode command is issued to that partition. Performing a program, erase,
or block-lock operation also changes the partition’s read mode to Read Status Register
mode.
The Status Register is updated on the falling edge of CE#, or OE# when CE# is low.
Status Register contents are valid only when SR7 = 1.
The Read Status Register command functions independent of the voltage level on VPP.
9.4.3
Read Device Information
Issuing the Read Device Information command places the addressed partition in Read
Device Information mode. Subsequent reads output device information on the data
bus. The address offsets for reading the available device information are shown here.
Table 37: Device Information Summary
Device Information
Address Bus
Data Bus
Device Manufacturer Code (Numonyx)
Device ID Code
Partition Base Address + 00h
Partition Base Address + 01h
0089h
Device IDs
D0 = Lock Status
D1 = Lock-Down Status
Main Block Lock Status
Block Base Address + 02h
Read Configuration Register
Partition Base Address + 05h
Partition Base Address + 06h
Configuration Register Data
Enhanced Configuration
Register Data
Enhanced Configuration Register
OTP Lock Register 0
Partition Base Address + 80h
Lock Register 0 Data
Factory-Programmed Data
User Data
OTP Register - Factory Segment
OTP Register - User-Programmable Segment
OTP Lock Register 1
Partition Base Address + 81h to 84h
Partition Base Address + 85h to 88h
Partition Base Address + 89h
Lock Register 1 Data
User Data
OTP Registers 1 through 16
Partition Base Address + 8Ah to 109h
The addressed partition remains in Read Device Information mode until a different read
command is issued. Also, performing a program, erase, or block-lock operation changes
the addressed partition to Read Status Register mode.
Note:
Issuing the Read Device Information command to a partition that is actively
programming or erasing changes that partition’s read mode to Read Device Information
mode. Subsequent reads from that partition will return invalid data until the program or
erase operation has completed.
The Read Device Information command functions independent of the voltage level on
VPP.
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9.4.4
CFI Query
Issuing the CFI Query command places the addressed partition in CFI Query mode.
Subsequent reads from that partition output CFI information.
The addressed partition remains in CFI Query mode until a different read command is
issued, or a program or erase operation is performed, which changes the read mode to
Read Status Register mode.
Note:
Issuing the CFI Query command to a partition that is actively programming or erasing
changes that partition’s read mode to CFI Query mode. Subsequent reads from that
partition will return invalid data until the program or erase operation has completed.
The CFI Query command functions independent of the voltage level on VPP.
9.5
Programming Modes
To understand programming modes, it is also important to understand the fundamental
memory array configuration. The flash device main array is divided as follows:
• The main array of the 128-Mbit device is divided into eight 16-Mbit partitions. Each
parition is divided into eight 256-KByte blocks: 8 x 8 = 64 blocks in the main array
of a 128-Mbit device.
• The main array of the 256-Mbit device is divided into eight 32-Mbit partitions. Each
partition is divided into sixteen 256-KByte blocks: 8 x 16 = 128 blocks in the main
array of a 256-Mbit device.
• The main array of the 512-Mbit device is divided into eight 64-Mbit partitions. Each
partition is divided into thirty-two 256-KByte blocks: 8 x 32 = 256 blocks in the
main array of a 256-Mbit device.
• The main array of the 1-Gbit device is divided into eight 128-Mbit partitions. Each
partition is divided into sixty-four 256-KByte blocks: 8 x 64 = 512 blocks in the
main array of a 1-Gbit device.
Each block is divided into as many as two-hundred-fifty-six 1-KByte programming
regions. Each region is divided into as many as thirty-two 32-Byte segments.
Each programming region in a flash block can be configured for one of two
programming modes: Control Mode or Object Mode. The programming mode is
automatically set based on the data pattern when a region is first programmed. The
selection of either Control Mode or Object Mode is done according to the specific needs
of the system with consideration given to two types of information:
• Control Mode: Flash File System (FFS) or Header information, including frequently
changing code or data
• Object Mode: Large, infrequently changing code or data, such as objects or
payloads
By implementing the appropriate programming mode, software can efficiently organize
how information is stored in the flash memory array.
Control Mode programming regions and Object Mode programming regions can be
intermingled within the same erase block. However, the programming mode of any
region within a block can be changed only after erasing the entire block.
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9.5.1
Control Mode
Control Mode programming is invoked when only the A-half (A3 = 0) of the
programming region is programmed to 0s, as shown in Figure 47, “Configurable
Programming Regions: Control Mode and Object Mode” on page 85. The B-half (A3 =
1) remains erased. Control mode allows up to 512 bytes of data to be programmed in
the region. The information can be programmed in bits, bytes, or words.
Control Mode supports the following programming methods:
— Single-word Programming (0041h)
— Buffered Programming (00E9h/00D0h), and
— Buffered Enhanced Factory Programming (0080h/00D0h)
When buffered programming is used in Control Mode, all addresses must be in the A-
half of the buffer (A3 = 0). During buffer fill, the B-half (A3 = 1) addresses do not need
to be filled with 0xFFFF.
Control Mode programming is useful for storing dynamic information, such as FFS
Headers, File Info, and so on. Typically, Control Mode programming does not require
the entire 512 bytes of data to be programmed at once. It may also contain data that is
changed after initial programming using a technique known as “bit twiddling”. Header
information can be augmented later with additional new information within a Control
Mode-programmed region. This allows implementation of legacy file systems, as well as
transaction-based power-loss recovery.
In a control mode region, programming operations can be performed multiple times.
However, care must be taken to avoid programming any zero’s in the B-half (A3 = 1) of
the region. Violation of this usage will cause SR4 and SR9 to be set, and the program
operation will be aborted. See Table 38, “Programming Region Next State Table” on
page 88 for details.
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Figure 47: Configurable Programming Regions: Control Mode and Object Mode
Main Array
256-Kbyte Block
256 KBytes
256 KBytes
.
.
1 KByte
256 KBytes
Programming region in Object Mode
256 KBytes
Address Bit A3 = 0: Allows up to 1
KByte of data to be programmed .
.
.
256 KBytes
512 Bytes
512 Bytes
Programming region in Control Mode
.
.
.
A half
B half
(Control
(Erased)
Mode )
Address Bit A3 = 1: Allows up to 512
Bytes of data to be programmed to
the A half by bit, byte, or word.
.
.
.
.
.
.
.
.
.
.
.
.
Programming region in Object Mode
1 KByte
.
.
.
Programming region in Object Mode
256 KBytes
1 KByte
256 KBytes
.
.
256 KBytes
9.5.2
Object Mode
Object mode programming is invoked when one or more bits are programmed to zero
in the B-half of the programming region (A3 = 1). Object mode allows up to 1KB to be
stored in a programming region. Multiple regions are used to store more than 1Kbyte of
information. If the object is less than 1Kbyte, the unused content will remain as 0xFFFF
(erased).
Object Mode supports two programming methods:
— Buffered Programming (00E9h/00D0h), and
— Buffered Enhanced Factory Programming (0080h/00D0h)
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Single-word programming (0041h) is not supported in Object mode. To perform
multiple programming operations within a programming region, Control mode must be
used.
Object mode is useful for storing static information, such as objects or payloads, that
rarely change.
Once the programming region is configured in Object mode, it cannot be augmented or
over-written without first erasing the entire block containing the region. Subsequent
programming operations to a programming region configured in Object mode will cause
SR4 and SR8 to be set and the program operation to be aborted. See Table 38,
“Programming Region Next State Table” on page 88 for details.
Note:
Issuing the 41h command to the B-half of an erased region will set error bits SR8 and
SR9, and the programming operation will not proceed. See Table 38, “Programming
Region Next State Table” on page 88 for more details.
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Figure 48: Configurable Programming Regions: Control Mode and Object Mode Segments
32 Bytes
Segments
31
Object
30
Object
Object
Object
Object
.
.
3
2
1
0
Object
Object
Object
Object
Object
Programming region in
Object Mode
Program up to
1 KByte of data
1 KByte
.
.
.
256-Kbyte Block
1 KByte
512 Bytes
512 Bytes
A half
B half
(Control
(Erased)
Mode)
Program up to 512
Bytes of data
Programming
region in
Control Mode
Segments
31
Sequence Table Entry
Header
Header
Header
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
30
.
.
3
2
1
0
Header
File Information
Header
Directory Information
Header
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Sequence Table Entry
Header
16 Bytes
16 Bytes
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Table 38: Programming Region Next State Table
Command Issued
Current State of
Programming
Region
0041h to B-half
(A3 = 1)
0041h to A-half
(A3 = 0)
00E9h to B-half
(A3 = 1)
00E9h to A-half
(A3 = 0)
Program Successful
SR[4,8,9] = 0
Region configured to
Control Mode
Program Successful
SR[4,8,9] = 0
Region configured to
Object Mode
Program Successful
SR[4,8,9] = 0
Region configured to
Control Mode
Erased
Program Fail;
Object data to Control
mode region
Program Fail; Illegal
Command
SR[4,8,9] = 1
Program Successful
SR[4,8,9] = 0
Program Successful
SR[4,8,9] = 0
Control Mode
Object Mode
SR[4,9] = 1
SR8 = 0
Program Fail; Rewrite to Object mode region
SR[4,8] = 1
SR9 = 0
9.6
Programming Operations
Programming the flash array changes ‘ones’ to ‘zeros’. To change zeros to ones, an
Erase operation must be performed. Only one programming operation can occur at a
time. Programming is permitted during Erase Suspend.
Information is programmed into the flash array by issuing the appropriate command.
Table 39, “Programming Commands Bus Cycles” shows the two-cycle command
sequences used for programming.
Table 39: Programming Commands Bus Cycles
Setup Write Cycle
Address Bus Data Bus
Confirm Write Cycle
Command
Address Bus
Data Bus
Single-Word Program
Device Address
Device Address
Device Address
0041h
00E9h
0080h
Device Address
Device Address
Device Address
Array Data
00D0h
Buffered Program
Buffered Enhanced Factory Program
00D0h
Caution:
All programming operations require the addressed block to be unlocked, and a
valid VPP voltage applied throughout the programming operation. Otherwise,
the programming operation will abort, setting the appropriate Status Register
error bit(s).
The following sections describe each programming method.
9.6.1
Single-Word Programming
Main array programming is performed by first issuing the Single-Word Program
command. This is followed by writing the desired data at the desired array address. The
read mode of the addressed partition is automatically changed to Read Status Register
mode, which remains in effect until another read-mode command is issued.
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Note:
Issuing the Read Status Register command to another partition switches that partition’s
read mode to Read Status Register mode, thereby allowing programming progress to
be monitored from that partition’s address.
Single-Word Programming is supported in Control mode only. The array address
specified must be in the A-half of the programming region.
During programming, the Status Register indicates a busy status (SR7 = 0). Upon
completion, the Status Register indicates a ready status (SR7 = 1). The Status Register
should be checked for any errors, then cleared.
The only valid commands during programming are Read Array, Read Device
Information, CFI Query, Read Status and Program Suspend. After programming has
finished, any valid command can be issued.
Note:
Issuing the Read Array, Read Device Information, or CFI Query command to a partition
that is actively programming causes subsequent reads from that partition to output
invalid data. Valid data is output only after the program operation has finished.
Standby power levels are not realized until the programming operation has finished.
Asserting RST# immediately aborts the programming operation, and array contents at
the addressed location are indeterminate. The addressed block should be erased, and
the data re-programmed.
9.6.2
Note:
Buffered Programming
Buffered Programming programs multiple words simultaneously into the flash memory
array. Data is first written to a write buffer and then programmed into the flash
memory array in buffer-size increments. This can significantly reduce the effective
word-write time. Section 6.0, “Flow Charts” on page 41 contains a flow chart of the
buffered-programming operation.
Optimal performance and power consumption is realized only by aligning the start
address on 32-word boundaries, e.g., A[4:0] = 00000b. Crossing a 32-word boundary
during a Buffered Programming operation can cause the programming time to double.
Buffered Programming is supported in both Control mode and Object mode. In Object
mode, the region must be programmed only once between erases. However in Control
mode, the region may be programmed multiple times.
Caution:
When using the Buffered Program command in Object mode, the start address
must be aligned to the 512-word buffer boundary. In Control mode, the
programming array address specified must be in the A-half of the
programming region.
First issue the Read Status command to the desired partition. The read mode of the
addressed partition is changed to Read Status Register mode.
Poll SR7 to determine write-buffer availability (0 = not available, 1 = available). If the
write buffer is not available, re-issue the Read Status command and check SR7; repeat
until SR7 = 1.
If desired issue a Read Array command to the desired partition to change the read
mode of the partition to Array reads.
To perform a buffered programming operation, issue the Buffered Program setup
command at the desired starting address. Next, issue a word count at the desired
starting address. The word count is the total number of words to be written into the
write buffer, minus one. This value can range from 0000h (one word) up to a maximum
of 01FFh (512 words). Exceeding the allowable range causes the operation to abort.
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Following the word count, subsequent bus-write cycles fill the write buffer with user-
data up to the word count.
Note:
User-data is programmed into the flash array at the address issued when filling the
write buffer.
The Confirm command (00D0h) is issued after all user-data is written into the write
buffer. The read mode of the device/addressed partition is automatically changed to
Read Status Register mode. If other than the Confirm command is issued to the device,
a command sequence error occurs and the operation aborts.
After the Confirm command has been issued, the write-buffer contents are
programmed into the flash memory array. The Status Register indicates a busy status
(SR7 = 0) during array programming.
During array programming, the only valid commands are Read Array, Read Device
Information, CFI Query, Read Status, and Program Suspend. After array programming
has completed (SR7 = 1), any valid command can be issued. Reading from another
partition is allowed while data is being programmed into the flash memory array from
the write buffer.
Note:
Issuing the Read Array, Read Device Information, or CFI Query command to a partition
that is actively programming or erasing causes subsequent reads from that partition to
output invalid data. Valid data is output only after the program or erase operation has
finished.
Upon completion of array programming, the Status Register indicates ready (SR7 =
1b). A full Status Register check should be performed to check for any programming
errors. Then the Status Register should be cleared using the Clear Status Register
command.
A subsequent buffered programming operation can be initiated by repeating the
buffered programming sequence. Any errors in the Status Register caused by the
previous operation must be cleared to prevent them from masking any errors that may
occur during the subsequent operation.
9.6.3
Buffered Enhanced Factory Programming (BEFP)
Buffered Enhanced Factory Programming (BEFP) improves programming performance
through the use of the write buffer, elevated programming voltage (VPPH), and
enhanced programming algorithm. User-data is written into the write buffer, then the
buffer contents are automatically written into the flash array in buffer-size increments.
BEFP is allowed in both Control Mode and Object Mode. The programming mode
selection for the entire flash array block is driven by the specific type of information,
such as header or object data. Header/object data is aligned on a 1 KB programming
region boundary in the main array block.
Internal verification during programming (inherent to MLC technology) and Status
Register error checking are used to determine proper completion of the programming
operation. This eliminates delays incurred when switching between single-word
program and verify operations.
BEFP consists of three distinct phases:
1. Setup Phase: VPPH and block-lock checks
2. Program/Verify Phase: buffered programming and verification
3. Exit Phase: block-error check
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Section 6.0, “Flow Charts” on page 41 contains a flow chart of the BEFP operation.
Table 40, “BEFP Requirements and Considerations” on page 91 lists specific BEFP
requirements and considerations.
Note:
For BEFP voltage and temperature operating restrictions, see the datasheet. The block
erase cycles in Table 40, “BEFP Requirements and Considerations” are recommended
for optimal performance. If exceeded some degradation in performance may occur;
however, the internal algorithm will still function correctly.
Table 40: BEFP Requirements and Considerations
Temperature (TCASE) must be 25 °C, ± 5 °C
Voltage on VCC must be within the allowable operating range
Voltage on VPP must be within the allowable operating range
Block being programmed must be erased and unlocked
Block cycling below 100 erase cycles
BEFP Requirements
Reading from another partition during EFP (RWW) is not allowed
BEFP programs within one block at a time
BEFP Considerations
BEFP cannot be suspended
9.6.3.1
Caution:
9.6.3.2
Setup Phase
Issuing the BEFP Setup and Confirm command sequence starts the BEFP algorithm. The
read mode of the addressed partition is automatically changed to Read Status Register
mode.
The address used when issuing the setup/confirm commands must be buffer-size
aligned within the block being programmed -- buffer contents cannot cross block
boundaries.
The Read Status Register command must not be issued -- it will be interpreted
as data to be written to the write buffer.
A setup delay (tBEFP/Setup) occurs while the internal algorithm checks VPP and block-lock
status. If errors are detected, the appropriate Status Register error bits are set and the
operation aborts.
The Status Register should be polled for successful BEFP setup, indicated by SR[7,0] =
0 (Device Busy, Buffer Ready for Data).
Program/Verify Phase
Data is first written into the write buffer, then programmed into the flash array. During
the buffer-fill sequence, the address used must be buffer-size aligned. Use of any other
address will cause the operation to abort with a program fail error, and any data
previously loaded in the buffer will not be programmed into the array.
The buffer-fill data is stored in sequential buffer locations starting at address 00h. A
word count equal to the maximum buffer size is used, therefore, the buffer must be
completely filled. If the amount of data is less than the maximum buffer size, the
remaining buffer locations must be “padded” with FFFFh to completely fill the buffer.
Flash array programming starts as soon as the write buffer is full. Data words from the
write buffer are programmed into sequential array locations. SR0 = 1 indicates the
write buffer is not available while the BEFP algorithm programs the array.
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The Status Register should be polled for SR0 = 0 (Buffer Ready for Data) to determine
when the array programming has completed, and the write buffer is again available for
loading. The internal address is automatically incremented to enable subsequent array
programming to continue from where the previous buffer-fill/array-program sequence
ended within the block. This cycle can be repeated to program the entire block.
To exit the Program/Verify Phase, write FFFFh to an address outside of the block.
9.6.3.3
Exit Phase
The Status Register should be polled for SR7 = 1 (Device Ready) indicating the BEFP
algorithm has finished running, and the device has returned to normal operation. A full
error check should be performed to ensure the block was programmed successfully.
9.7
Block Erase Operations
Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation
must be performed (see Section 9.6, “Programming Operations). Erasing is performed
on a block basis— an entire block is erased each time an erase command sequence is
issued. Once a block is fully erased, all addressable locations within that block read as
logical ‘ones’ (FFFFh).
Only one block-erase operation can occur at a time. A block-erase operation is not
permitted during Program Suspend.
To perform a block-erase operation, issue the Block Erase command sequence at the
desired block address. Table 41 shows the two-cycle Block Erase command sequence.
Table 41: Block-Erase Command Bus Cycles
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
Block Address 00D0h
Command
Address Bus
Data Bus
Block Erase
Device Address
0020h
Caution:
All block-erase operations require the addressed block to be unlocked, and a
valid voltage applied to VPP throughout the block-erase operation. Otherwise,
the operation aborts, setting the appropriate Status Register error bit(s).
The Erase Confirm command latches the address of the block to be erased. The
addressed block is preconditioned (programmed to all zeros), erased, and then verified.
The read mode of the addressed partition is automatically changed to Read Status
Register mode, and remains in effect until another read-mode command is issued.
Note:
Issuing the Read Status Register command to another partition switches that partition’s
read mode to the Read Status Register, thereby allowing block-erase progress to be
monitored from that partition’s address. SR0 indicates whether the addressed partition
or other partition is erasing.
During a block-erase operation, the Status Register indicates a busy status (SR7 = 0).
Upon completion, the Status Register indicates a ready status (SR7 = 1). The Status
Register should be checked for any errors, and then cleared.
The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, Read Status and Erase Suspend. After the block-erase
operation has completed, any valid command can be issued.
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Note:
Issuing the Read Array command to a partition that is actively erasing a main block
causes subsequent reads from that partition to output invalid data. Valid array data is
output only after the block-erase operation has finished.
Standby power levels are not realized until the block-erase operation has finished.
Asserting RST# immediately aborts the block-erase operation, and array contents at
the addressed location are indeterminate. The addressed block should be erased, and
the data re-programmed.
9.8
Blank Check Operation
Blank Check is used to see if a main-array block is completely erased. A Blank Check
operation is performed one block at a time, and cannot be used during Program
Suspend or Erase Suspend.
To use Blank Check, first issue the Blank Check setup command followed by the confirm
command. The read mode of the addressed partition is automatically changed to Read
Status Register mode, which remains in effect until another read-mode command is
issued.
Table 42: Blank Check Command Bus Cycles
Setup Write Cycle
Address Bus Data Bus
Block Address 00BCh
Confirm Write Cycle
Command
Address Bus
Data Bus
00D0h
Blank Check
Block Address
During a blank check operation, the Status Register indicates a busy status (SR7 = 0).
Upon completion, the Status Register indicates a ready status (SR7 = 1).
Note:
Issuing the Read Status Register command to another partition switches that partition’s
read mode to Read Status Register mode, thereby allowing the blank check operation
to be monitored from that partition’s address.
The Status Register should be checked for any errors, and then cleared. If the Blank
Check operation fails, i.e., the block is not completely erased, then the Status Register
will indicate a Blank Check error (SR[7,5] = 1).
The only valid command during a Blank Check operation is Read Status. Blank Check
cannot be suspended. After the blank check operation has completed, any valid
command can be issued.
9.9
Suspend and Resume
Program and erase operations of the main array can be suspended to perform other
device operations, and then subsequently resumed. However, OTP Register
programming or blank check operations cannot be suspended.
To suspend an on-going erase or program operation, issue the Suspend command to
any device address; the corresponding partition is not affected. Table 43 shows the
Suspend and Resume command bus-cycles.
Note:
Issuing the Suspend command does not change the read mode of the partition. The
partition will be in Read Status Register mode from when the erase or program
command was first issued, unless the read mode was changed prior to issuing the
Suspend command.
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Table 43: Suspend and Resume Command Bus Cycles
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
Command
Address Bus
Data Bus
Suspend
Resume
Device Address
Device Address
00B0h
00D0h
---
---
---
---
The program or erase operation suspends at pre-determined points during the
operation after a delay of tSUSP. Suspend is achieved when SR[7,6] = 1 (erase-
suspend) or SR[7,2] = 1 (program-suspend).
Note:
Throughout the Block Erase Suspend or Program Suspend period, the addressed block
must remain unlocked and a valid voltage applied to VPP. Otherwise, the erase or
program operation will abort, setting the appropriate Status Register error bit(s). Also,
WP# must remain unchanged.
Asserting RST# aborts suspended block-erase and programming operations -- array
contents at the addressed locations are indeterminate. The addressed block should be
erased, and the data re-programmed.
Not all commands are allowed when the device is suspended. Table 44 shows which
device commands are allowed during Program Suspend or Erase Suspend.
Table 44: Valid Commands During Suspend
Device Command
Program Suspend
Allowed
Erase Suspend
Read Array
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Read Status Register
Clear Status Register
Read Device Information
CFI Query
Allowed
Allowed
Allowed
Allowed
Word Program
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Buffered Program
Buffered Enhanced Factory Program
Block Erase
Not Allowed
Not Allowed
Not Allowed
Allowed
Program/Erase Suspend
Program/Erase Resume
During Suspend, reading from a block that is being erased or programmed is not
allowed. Also, programming to a block that is in erase-suspend state is not allowed,
and if attempted, will result in Status Register program error to be set (SR4 = 1).
A block-erase under program-suspend is not allowed. However, word-program under
erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-
suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.
To resume a suspended program or erase operation, issue the Resume command to
any device address. The read mode of the resumed partition is unchanged; issue the
Read Status Register command to return the partition to Read Status mode. The
operation continues where it left off, and the respective Status Register suspend bits
are cleared.
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When the Resume command is issued during a simultaneous erase-suspend/ program-
suspend condition, the programming operation is resumed first. Upon completion of the
programming operation, the Status Register should be checked for any errors, and
cleared. The resume command must be issued again to complete the erase operation.
Upon completion of the erase operation, the Status Register should be checked for any
errors, and cleared.
9.10
Simultaneous Operations
The multi-partition architecture of the flash device allows programming or erasing to
occur in one partition while reads are performed from another partition. Only status
reads are allowed in partitions that are busy programming or erasing.
Note:
When OTP Registercommands are issued to a parameter any partition address, the OTP
Registeris mapped onto that partition.
Table 45, “Read-While-Program and Read-While-Erase Rules” shows the rules for
reading from a partition while simultaneously programming or erasing within another
partition.
Table 45: Read-While-Program and Read-While-Erase Rules
Read modes allowed when program/erase busy in partition A
Non-Array Reads1
Active Operation
Read Status
Array Reads
Main-Array Program
Main-Array Erase
All partitions
All partitions
All partitions
All partitions except busy partition A
All partitions except busy partition A
All partitions except busy partition A
All partitions except busy partition A
All partitions except busy partition A
Not allowed
OTP Register Program
Note: OTP Register, Device Information, CFI Query.
9.11
Security
The flash device incorporates features for protecting main-array contents and for
implementing system-level security schemes. The following sections describe the
available features.
9.11.1
Block Locking
Two methods of block-lock control are available: software and hardware. Software
control uses the Block Lock and Block Unlock commands; hardware control uses WP#
along with the Block Lock-Down command.
Upon power up or exit from reset, all main array blocks are locked, but not locked
down. Locked blocks cannot be erased or programmed.
Block lock and unlock operations are independent of the voltage level on VPP.
Table 46 summarizes the command bus-cycles.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 46: Block Locking Command Bus Cycles
Setup Write Cycle
Confirm Write Cycle
Address Bus Data Bus
Command
Address Bus
Data Bus
Lock Block
Block Address
Block Address
Block Address
0060h
0060h
0060h
Block Address
Block Address
Block Address
0001h
00D0h
002Fh
Unlock Block
Lock-Down Block
To lock, unlock, or lock-down a block, first issue the setup command to any address
within the desired block. The read mode of the addressed partition is automatically
changed to Read Status Register mode. Next, issue the desired confirm command to
the block’s address. Note that the confirm command determines the operation
performed. The Status Register should be checked for any errors, and then cleared.
The lock status of a block can be determined by issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked), and DQ1 indicates the lock-
down status of the addressed block (0 = lock-down not issued; 1 = locked-down
issued). Section 9.4.3, “Read Device Information” on page 82 summarizes the details
of this operation.
Blocks cannot be locked or unlocked while being actively programmed or erased. Blocks
can be locked or unlocked during erase-suspend, but not during program-suspend.
Note:
If a block-erase operation is suspended, and then the block is locked or locked down,
the lock status of the block will be changed immediately. When resumed, the erase
operation will still complete.
Block lock-down protection is dependent on WP#. When WP# = VIL, blocks locked
down are locked, and cannot be unlocked using the Block Unlock command. When
WP# = VIH, block lock-down protection is disabled—locked-down blocks can be
individually unlocked using the Block Unlock command. Subsequently, when WP# =
VIL, previously locked-down blocks are once again locked and locked-down, including
locked-down blocks that may have been unlocked while WP# was de-asserted.
A locked-down block can only be unlocked by issuing the Unlock Block command with
WP# deasserted. To return an unlocked block to the locked-down state, a Lock-Down
command must be issued prior to asserting WP#.
Issuing the Block Lock-Down command to an unlocked block does not lock the block.
However, asserting WP# after issuing the Block Lock-Down command locks (and locks
down) the block. Lock-down for all blocks is cleared upon power-up or exit from reset.
Figure 49 summarizes block-locking operations.
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Figure 49: Block Locking Operations
Locked
Down
[0,1,1]
Hardware
Locked2
[0,1,1]
Locked
[X,0,1]
2
WP# = VIL
WP# = VIH
Power Up
-or-
Exit from Reset
Software
Locked
[1,1,1]
Unlocked
[X,0,0]
Unlocked
[1,1,0]
Software Control(Lock, Unlock, Lock-Down Command)
Hardware Control(WP#)
Notes:
1.
2.
[n,n,n] denotes logical state of WP#, DQ1,and DQ0, respectively; X = Don’t Care.
[0,1,1] states should be tracked by system software to differentiate between the Hardware-Locked state and the Lock-
Down state.
9.11.2
One-Time Programmable (OTP) Registers
The device contains seventeen 128-bit One-Time Programmable (OTP) Registers, and
twoa 16-bit OTP Lock Registers, as shown in Figure 50, “2-Kbit OTP Registers” on
page 98. The OTP Lock Register 0 is used for locking the OTP Register 0, and OTP Lock
Register 1 is used for locking OTP Registers 1 through 16.
The OTP Register 0 consists of two 64-bit segments: a lower segment that is pre-
programmed with a unique 64-bit value and locked at the factory; and an upper
segment that contains all “ones” and is user-programmable. OTP Registers 1 through
16 contain all “ones” and are user-programmable.
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Figure 50: 2-Kbit OTP Registers
0x109
128-bit OTP Register 16
(User-Programmable)
0x102
0x91
128-bit OTP Register 1
(User-Programmable)
0x8A
0x89
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OTP Lock Register 1
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit OTP Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OTP Lock Register 0
Each register contains OTP bits that can only be programmed from “one” to “zero” -
register bits cannot be erased from “zero” back to “one”. This feature makes the OTP
registers particularly useful for implementing system-level security schemes, for
permanently storing data, or for storing fixed system parameters.
OTP Lock Register bits “lock out” subsequent programming of the corresponding OTP
register. Each OTP Register can be locked by programming its corresponding lock bit to
zero. As long as an OTP register remains unlocked (that is, its lock bit = 1), any of its
remaining “one” bits can be programmed to “zero”.
Caution:
Once an OTP Register is locked, it cannot be unlocked. Attempts to program a
locked OTP Register will fail with error bits set.
To program any OTP bits, first issue the Program OTP Register setup command at any
device address. Next, write the desired OTP Register data at the desired OTP Register
address. OTP Register and OTP Lock Register programming is performed 16 bits at a
time; only “zeros” within the data word affect any change to the OTP register bits.
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Table 47: Program OTP Register Command Bus Cycles
Setup Write Cycle
Command
Confirm Write Cycle
Address Bus Data Bus
OTP Register Address Register Data
Address Bus
Data Bus
Program OTP Register
Device Address
00C0h
Attempting to program an OTP register outside of the OTP register space causes a
program error (SR4 = 1). Attempting to program a locked OTP Register causes a
program error and a lock error (SR4 = 1, SR1 = 1).
To read from any of the OTP registers, first issue the Read Device Information
command. Then read from the desired OTP Register address offset. For additional
details, refer to Section 9.4.3, “Read Device Information” on page 82.
9.11.3
Global Main-Array Protection
Global main-array protection can be implemented by controlling VPP. When
programming or erasing main-array blocks, VPP must be equal to, or greater than VPPL
(min). When VPP is below VPPLK, program or erase operations are inhibited, thus
providing absolute protection of the main array.
Various methods exist for controlling VPP, ranging from simple logic control to off-board
voltage control. Figure 51 shows example VPP supply connections that can be used to
support program/erase operations and main-array protection.
Figure 51: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VCC
VPP
VPPH
VPPL
PROT#
≤ 10ΚΩ
•
•
Factory Programming: VPP = VPPH
Program/Erase Protection: VPP ≤ VPPLK
•
•
Program/Erase Enable: PROT# = VIH
Program/Erase Protection: PROT# = VIL
VCC
VCC
VPP
VCC
VCC
VPP
VPPL
VPPL
VPPH
•
•
Low-Voltage Programming: VPP = VPPL
- or-
Factory Programming: VPP = VPPH
•
•
Low-Voltage Programming: VPP = VCC
Program/Erase Protection: None
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Numonyx™ StrataFlash® Cellular Memory (M18)
10.0
Device Command Codes
Table 48: Command Bus Operations
Code
(Setup/Confirm)
Command
Description
Program Read
Issuing this command sequence programs the Read Configuration
Register. The RCR value is placed on the address bus.
0060h/0003h
0060h/0004h
Configuration Register
Issuing this command sequence programs the Enhanced
Configuration Register. The ECR value is placed on the address
bus.
Program Enhanced
Configuration Register
Issuing this command programs the Protection Registers or the
Lock Registers associated with them.
Program OTP Register
Read Array
00C0h
00FFh
Issuing this command places the addressed partition in Read Array
mode. Subsequent reads outputs array data.
Issuing this command places the addressed partition in Read
Status mode. Subsequent reads outputs Status Register data.
Read Status Register
Clear Status Register
0070h
0050h
Issuing this command clears all error bits in the Status Register.
Issuing this command places the addressed partition in Read
Device Information mode. Subsequent reads from specified
address offsets outputs unique device information.
Read Device Information
CFI Query
0090h
0098h
Issuing this command places the addressed partition in CFI Query
mode. Subsequent reads from specified address offsets outputs
CFI data.
This command prepares the device for programming a single word
into the flash array. On the next bus write cycle, the address and
data are latched and written to the flash array. The addressed
partition automatically switches to Read Status Register mode.
Word Program
0041h
This command sequence initiates and executes a buffered
programming operation. Additional bus write/read cycles are
required between the setup and confirm commands to properly
perform this operation. The addressed partition automatically
switches to Read Status Register mode.
Buffered Program
00E9h/00D0h
0080h/00D0h
This command sequence initiates and executes a BEFP operation.
Additional bus write/read cycles are required after the confirm
command to properly perform the operation. The addressed
partition automatically switches to Read Status Register mode.
Buffered Enhanced Factory
Program
Issuing this command sequence erases the addressed block. The
addressed partition automatically switches to Read Status mode.
Block Erase
0020h/00D0h
00B0h
Issuing this command to any device address initiates a suspend of
a program or block-erase operation already in progress. SR6 = 1
indicates erase suspend, and SR2 = 1 indicates program suspend.
Program/Erase Suspend
Issuing this command to any device address resumes a suspended
program or block-erase operation. A program suspend nested
within an erase suspend is resumed first.
Program/Erase Resume
00D0h
This command sequence initiates the blank check operation on a
block.
Blank Check
Lock Block
00BCh/00D0h
0060h/0001h
Issuing this command sequence sets the lock bit of the addressed
block.
Issuing this command sequence clears the lock bit of the
addressed block.
Unlock Block
0060h/00D0h
0060h/002Fh
Lock Down Block
Issuing this command sequence locks down the addressed block.
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11.0
Flow Charts
Figure 52: Word Program for Main Array Flowchart
WORD PROGRAM PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0x41
Write
Write
Read
Setup
Addr = Location to program
Write 0x41,
Word Address
(Setup )
Data = Data to program
Addr = Location to program
Data
Write Data,
Word Address
(Confirm)
None
None
Main or Parameter status register data
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle
No
Suspend?
Yes
0
SR[7] =
1
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[4]:
1 = Data Program Error
Idle
Idle
None
None
0
1
1
Program
Success
SR[4] =
1
Check SR[1]:
1 = Block locked; operation aborted
Device Protect
Error
SR[1]
=
Check SR[3]:
Idle
None
1 =
VPP Error
0
Check SR[8] AND SR[9]:
00=Region program successfu.l
Vpp Range
Error
SR[3] =
0
10= Attempted write with object
data to Control Mode regio.n
Idle
None
01= Attempted rewrite to Object
Mode region.
SR[8] or
SR[9] =
1
See Table on the
right for explantion
11=Attempted write using illegal
command.
0
SR[3] MUST be cleared before the Write State Machine will
allow further program attempts.
Program Fail
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 53: Program Suspend/Resume Flowchart
P R O G R A M S U S P E N D / R E S U M E P R O C E D U R E
S ta rt
B u s
O p e ra tio n
P ro g ra m S u sp e n d
W rite B 0 h
C o m m an d
C o m m e n ts
A n y A dd re ss
P rog ra m D a ta = B 0 h
S u sp en d A dd r = B loc k to su sp en d (B A )
W rite
R e a d
S ta tu s
(1)
W rite S R
(1 )
R ea d
D a ta = S R
S a m e P a rtition
W rite
R e ad
S ta tus
A dd r = S am e pa rtition
R ea d S ta tu s
R eg iste r
S ta tus re gis ter d ata
A dd r = S usp en de d blo ck (B A )
C h eck S R .7
S tan db y
S tan db y
1 = W S M re ad y
0 = W S M bu sy
0
0
S R .7 =
1
C h eck S R .2
1 = P ro gram su sp en de d
0 = P ro gram co m ple ted
P ro gram
C om p lete d
S R .2 =
1
D a ta = F F h
A dd r = A ny ad dress w ith in the
su sp en de d p artitio n
R ea d
A rra y
W rite
R e ad
W rite
R e a d
A rra y
W rite F F h
S us p P a rtition
R e ad arra y d ata from b loc k o the r tha n
th e on e b ein g pro gram m ed
R ea d A rra y
D ata
P rog ra m D a ta = D 0 h
R es um e A dd r = S usp en de d blo ck (B A )
If th e s u s p en d e d p a rtitio n w as p lac ed in R e ad A rra y m o d e:
D o ne
N o
R ea din g
R e turn p artitio n to S tatu s m o de:
D a ta = S R
A dd r = S am e pa rtition
R ea d
S ta tus
(1 )
W rite
Y e s
P ro g ra m
R e su m e
R e a d
A rra y
W rite D 0 h
W rite F F h
A n y A dd re ss
P g m 'd P artitio n
P rog ram
R e su m e d
R ea d A rray
D ata
R e a d
S ta tu s
W rite 70 h
S a m e P a rtition
P G M _ S U S .W M F
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Figure 54: Buffered Program Flowchart
Buffer Programming Procedure
Bus
Operation
Command
Comments
SR[7] = Valid
Read
(Note 1)
None
Addr = Block Address
Issue Read Status
Register Command
at Partition Address
Check SR[7]:
1 = Write Buffer available
0 = No Write Buffer available
Idle
None
No
Write
(Note 2)
Data = 0xFF
Addr = Block Address
Read Array
0 = No
Flash Ready?
SR[7] =
Timeout?
Write
(Note 3)
Buffer Prog. Data = 0xE9
Setup
Addr = Block Address
1 = Yes
Data = N = Word Count - 1
(N = 0 corresponds to count = 1)
Addr = Buffer Address
Yes
Timeout error
Write
(Notes4,5)
None
Issue Read Array
Command at Partition
Write
(Notes 6, 7)
Data = Write Buffer Data
Addr = Word Address
Address
None
None
Write
(Notes 6, 7)
Data = Write Buffer Data
Addr = Word Address
Set Timeout or
Loop Counter
Write
Buffer Prog. Data = 0xD0
(Note 8)
Conf.
Addr = Block Address
Issue Buffer Prog. Cmd.
0xE9,
Read
(Note 9)
Status register Data
Addr = Block Address
None
Block Address
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Write Word Count-1,
Buffer Address
Standby
None
NOTES:
Buffer Program Data,
Word Address
X = X + 1
1. The device outputs the Status Register when read.
2. The device outputs the array data when read.
3. Buffer Programming is available in the main array only. This
algorithm may be used for MLC or PSBC programming. Upon
issuing 0xE9 the partition state does not changed.
4. Word count value on D[8:0] is loaded into the word count
register. Count ranges for this device are N = 0x000 to 0x1FF.
5. Buffer address on A[MAX:9] specifies a single 512-word
buffer-size array region. This is latched and held constant
during the entire operation.
Write Buffer Data,
Word Address
X = 0
No
No
Abort Buffer
Program?
X = N?
6. The word address within the buffer, specified by A [8:0], is
provided. Upper address bits are ignored.
7. The device aborts the Buffer Program command if the current
Yes
Write to another
Block Address
address is outside the original block address .
Yes
8. Upon issuing 0xD0 the partition is placed in Status Read
mode. If block address changes, Buffer Program will abort.
9. The Status Register indicates an improper command
sequence if the Buffer Program command is aborted; use the
Clear Status Register command to clear error bits.
Write Confirm 0xD0
and Block Address
Buffer Program Aborted
Full status check can be done after all erase and write
sequences complete. For a detailed flowchart, please refer to
‘Full Status Check Procedure’ flowchart under ‘Word Program
for Main Array’ flowchart.
Write 0xFF after the last operation to place the partition in the
Read Array state.
Suspend
Program
Loop
Read Status Register
No
0
Suspend
Program?
Yes
SR[7] =?
1
Full Status
Check if Desired
Program Complete
.
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 55: Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING(Buffered-EFP) PROCEDURE
Setup Phase
Program & Verify Phase
Exit Phase
Start
Data Stream Ready
Read Status Reg .
VPP applied ,
Block unlocked
Initialize Count :
X = 0
No (SR [7]=0)
BEFP
Exited?
Yes (SR[7]=1)
Write 0x80 @
Write Data @ 1ST
Word Address
1ST Word Address
Full Status Check
Procedure
Write 0xD0 @
Increment Count :
X = X+1
1ST Word Address
Program
Complete
BEFP setup delay
Read Status Reg .
N
X = 512?
Y
Read Status Reg .
No (SR[0]=1)
Yes (SR[7]=0)
BEFP Setup
Done ?
Program
Done ?
No (SR[7]=1)
Yes (SR[0]=0)
Check VPP , Lock
Errors (SR[3,1])
N
Last
Data?
Y
Exit
Write 0xFFFF,
Address Not within
Current Block
BEFP Setup
Bus
State
BEFP Program & Verify
BEFP Exit
Bus
State
Operation
Comments
Bus State Operation
Comments
Operation
Comments
Unlock
Block
Status
Read
Data = Status Register Data
Address = 1ST Word Addr .
Status
Register
Data = Status Reg. Data
Address = 1ST Word Addr
Write
VPPH applied to VPP
Read
Register
Write
(Note 2)
BEFP
Setup
Data = 0x80 @ 1ST Word
Address
Check SR [0]:
0 = Ready for Data
1 = Not Ready for Data
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
Data Stream
Standby
Check Exit
Status
Standby
Ready ?
BEFP
Confirm
Data = 0xD0 @ 1ST
Word Address
Write
Read
Initialize
Standby
Repeat for subsequent blocks
After BEFP exit , a full Status Register check can
determine if any program error occurred
;
X = 0
Count
Status
Register
Data = Status Reg . Data
Address = 1ST Word Addr
Write
Load
Data = Data to Program
;
(Note 3)
Buffer
Address = 1ST Word Addr .
BEFP
Setup
Done ?
Check SR [7]:
0 = BEFP Ready
1 = BEFP Not Ready
See full Status Register check procedure in the
Word Program flowchart .
Standby
Increment
Count
Standby
Standby
Read
X = X+1
Write0xFF to enter Read Array state
.
X = 512?
Yes = Read SR [0]
No = Load Next Data Word
Error
If SR[7] is set, check:
Buffer
Full?
Standby Condition SR[3] set = VPP Error
Check SR[1] set = Locked Block
Status
Register
Data = Status Reg . data
Address = 1ST Word Addr .
Check SR [0]:
0 = Program Done
1 = Program in Progress
Program
Done?
Standby
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Write
Exit Prog
Verify Phase current block
&
Data = 0xFFFF @ address not in
NOTES:
1. BEFP is available in the main array only
2. First-word address to be programmed within the target block must be aligned on a write
3. Write-buffer contents are programmed sequentially to the flash array starting at the first word address
.
-buffer boundary
.
; WSM internally increments addressing
.
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Figure 56: Block Erase for Main Array Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write
Read
Write 0x20
Block Address
(Block Erase)
Erase
Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write 0xD0,
Block Address
(Erase Confirm )
None
None
Status Register data
Suspend
Erase
Loop
Read Status
Register (2)
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
No
0
Suspend
Erase
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[4,5]:
Idle
Idle
None
None
Both 1 = Command Sequence Error
1,1
0
Command
Sequence Error
SR[4,5] =
0
Check SR[5]:
1 = Block Erase Error
Block Erase
Success
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
SR[5] =
1
Idle
Idle
None
None
Check SR[3]:
1
1
Block Locked
Error
SR[1] =
0
1 =
VPP Range Error
SR[1,3] must be cleared before the Write State Machine will
allow further erase attempts.
VPP Range
Error
SR[3] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Erase Fail
.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 57: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x70,
Same Partition
Read
Status
Data = 0x70
Addr = Any partition address
(Read Status)
Write
Write
Read
Data = 0xB0
Addr = Same partition address as
above
Erase
Suspend
Write 0xB0,
Any Address
(Erase Suspend)
Status Register data.
Addr = Same partition
None
None
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
Idle
None
0 = Erase completed
0
Erase
Completed
SR[6] =
1
Data = 0xFF or 0x40
Addr = Any address within the
suspended partition
Read Array
or Program
Write
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
None
Read Array
Data
Program
Loop
Program Data = 0xD0
Resume Addr = Any address
No
Write
Done
If the suspended partition was placed in
Read Array mode or a Program Loop:
Read
Status
Return partition to Status mode:
Data = 0x70
Write 0xD0,
Any Address
Write
(Erase Resume)
Register Addr = Same partition
Erase
Resumed
Write 0xFF,
Erased Partition
(Read Array)
Write 0x70,
Same Partition
Read Array
Data
(Read Status)
Datasheet
106
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Figure 58: Main Array Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Command
Operation
Comments
Write 0x60,
Block Address
Lock
Data = 0x60
(Lock Setup)
Write
Setup Addr = Block to lock/unlock/lock-down
Lock, Data = 0x01 (Block Lock)
Write either
0x01/0xD0/0x2F,
Block Address
Unlock, or
0xD0 (Block Unlock)
(Lock Confirm)
(Read Device ID)
Write
Write
Lock-Down
0x2F (Lock-Down Block)
Confirm Addr = Block to lock/unlock/lock-down
Read Data = 0x90
(Optional) Device ID Addr = Block address + offset 2
Write 0x90
Read Block Lock Block Lock status data
(Optional) Status Addr = Block address + offset 2
Read Block
Lock Status
Idle
None Confirm locking change on D[1,0].
Locking
No
Change?
Yes
Read Data = 0xFF
Array Addr = Block address
Write
Write 0xFF
Partition Address
(Read Main
Array)
Lock Change
Complete
d
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 59: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup )
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
None
None
Status Register Data.
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array stat.e
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[4]:
1 =Programming Error
Idle
Idle
Idle
None
Protection Register
Program Pass
0
1
1
SR[4] =
1
Check SR[1]:
1 = Block locked; operation aborted
None
None
Check SR[3]:
1 =VPP Range Error
Register Locked;
Program Aborted
SR[1] =
0
SR[3] must be cleared before the Write State Machine will
allow further program attempts.
SR[3] =
0
VPP Range Error
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
Protection Register
Program Fail
.
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 60: Blank Check Operation Flowchart
BLANK CHECK PROCEDURE
Start
Bus
Operation
Command
Comments
Write 0xBC,
Block Address
Blank
Check
Setup
Data = 0xBC
Addr = Block to be read (BA)
Write
Write
Read
Blank
Check
Confirm
Write 0xD0,
Block Address
Data = 0xD0
Addr = Block to be read (BA)
None
None
Status Register data.
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
No
0
SR[7] =
Repeat for subsequent block Blank Check.
1
Full Status register check should be read after Blank Check
has been performed on each block.
Full Blank
Check Status
Read
Blank Check
FULL BLANK CHECK STATUS CHECK PROCEDURE
Read Status
Register
Bus
Operation
Command
Comments
Check SR[4,5]:
Both 1 = Command Sequence Error
Idle
None
Command
Sequence Error
1,1
SR[4,5] =
0
Check SR[5]:
1 = Blank Check Error
Idle
None
Blank Check
Error
1
SR[1,3] must be cleared before the Write State Machine will
allow Blank Check to be performed.
SR[5] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
Blank Check
Successful
If an error is detected, clear the Status register before
attempting a Blank Check retry or other error recovery.
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
12.0
Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. It describes the database structure
containing the data returned by a read operation after issuing the CFI Query command.
System software can parse this database structure to obtain information about the
flash device, such as block size, density, bus width, and electrical specifications. The
system software will then know which command set(s) to use to properly perform flash
writes, block erases, reads and otherwise control the flash device.
12.1
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (A/DQ7-0) only. The
numerical offset value is the address relative to the maximum bus width supported by
the device. On this family of devices, the Query table device starting address is a 10h,
which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte
(A/DQ7-0) and 00h in the high byte (A/DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 49: Summary of Query Structure Output as a Function of Device and Mode
Hex
Offset
Hex
Code
Device
ASCII
00010:
00011:
51
52
“Q”
“R”
Device Addresses
Table 50: Example of Query Structure Output of x16 Devices (Sheet 1 of 2)
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
Value
Offset
Value
AX - A0
A15 - A0
AX - A0
A7 - A0
00010h
0051
“Q”
“R”
“Y”
00010h
0051
“Q”
“R”
“Y”
00011h
00012h
00013h
00014h
0052
00011h
00012h
00013h
00014h
0052
0059
0059
P_IDLO
P_IDHI
PrVendor
ID#
P_IDLO
P_IDLO
PrVendor
ID#
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Table 50: Example of Query Structure Output of x16 Devices (Sheet 2 of 2)
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
X - A0
Value
Offset
Value
A
A15 - A0
PrVendor
AX - A0
A7 - A0
ID#
00015h
00016h
00017h
00018h
PLO
00015h
P_IDHI
PHI
TblAdr
AltVendor
ID#
00016h
00017h
00018h
A_IDLO
A_IDHI
12.2
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations.
Block Erase Status (BSR[1]) allows system software to determine the success of the
last block erase operation. BSR[1] can be used just after power-up to verify that the
VCC supply was not accidentally removed during an erase operation. Only issuing
another operation to the block resets this bit. The Block Status Register is accessed
from word address 02h within each block.
Table 51: Block Status Register
Offset
Length
Description
Block Lock Status Register
Address
Value
(BA + 2)h
1
BA + 2
-00 or -01
BSR.0 Block Lock Status:
0 = Unlocked
(BA + 2)h
1
BA + 2
(bit 0): 0 or 1
1 = Locked
BSR.1 Block Lock Down Status:
0 = Not Locked Down
1 = Locked Down
(BA + 2)h
(BA + 2)h
1
1
BA + 2
BA + 2
(bit 0): 0 or 1
(bit 0): 0 or 1
BSR.2-3, 6-7: Reserved for future use
Note: BA = The beginning of a Block Address; that is, 020000h is the beginning location in word mode of the 256-KB block 1.
12.3
CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Table 52: CFI Identification (Sheet 1 of 2)
Offset
Length
Description
Address
Hex Code
Value
10
11
12
--51
--52
--59
“Q”
“R”
“Y”
10h
3
Query unique ASCII string “QRY”
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 52: CFI Identification (Sheet 2 of 2)
Offset
Length
Description
Address
Hex Code
Value
13
14
15
16
17
18
19
1A
--00
--02
--0A
--01
--00
--00
--00
--00
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms.
13h
2
15h
17h
19h
2
2
2
Extended Query Table primary algorithm address.
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists.
Secondary algorithm Extended Query Table address. 0000h
means none exists.
Table 53: System Interface Information (Sheet 1 of 2)
Offset
Length
Description
Address
Hex Code
Value
V
CC logic supply minimum
program/erase voltage.
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1Bh
1
1B
--17
1.7 V
2.0 V
8.5 V
VCC logic supply maximum
program/erase voltage.
1Ch
1Dh
1
1
1C
1D
--20
--85
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
VPP [programming] supply
minimum program/erase voltage.
bits 0-3 BCD 100 mV
bits 4-7 hex volts
VPP [programming] supply
maximum program/erase
voltage.
bits 0-3 BCD 100 mV
bits 4-7 hex volts
1Eh
1Fh
20h
1
1
1
1E
1F
20
--95
--06
9.5 V
64 µs
“n” such that typical single word
program timeout = 2n µs.
2048 µs (256, 512 Mbit -
90 nm; 1024 Mbit - 65
nm)
1024 µs (128. 256, 512
Mbit - 65 nm)
--0B (256, 512 Mbit - 90 nm;
1024 Mbit - 65 nm)
“n” such that typical full buffer
write timeout = 2n µs.
--0A (128. 256, 512 Mbit -
65 nm)
“n” such that typical block erase
timeout = 2n ms.
21h
22h
1
1
21
22
--0A
--00
1 s
NA
“n” such that typical full chip
erase timeout = 2n ms.
“n” such that maximum word
program timeout = 2n times
typical.
23h
1
23
--02
256 µs
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Table 53: System Interface Information (Sheet 2 of 2)
Offset
Length
Description
Address
Hex Code
Value
8192 µs (256, 512 Mbit -
90 nm; 128, 256, 512
Mbit - 65 nm)
4096 µs (1024 Mbit - 65
nm)
--02 (256, 512 Mbit - 90 nm;
128, 256, 512 Mbit - 65 nm)
--01 (1024 Mbit - 65 nm)
“n” such that maximum buffer
write timeout = 2n times typical.
24h
1
24
“n” such that maximum block
25h
26h
1
1
25
26
--02
--00
4 s
NA
erase timeout = 2n times typical.
“n” such that maximum chip
erase timeout = 2n times typical.
12.4
Device Geometry Definition
Table 54: Device Geometry Definition
Offset
Length
Description
n such that device size in bytes = 2n.
Address
27:
Hex Code
Value
27h
1
Flash device interface code assignment: n such that n + 1 specifies
the bit field that represents the flash device width capabilities as
described here:
Table 55, “Device
Geometry Definition: Addr,
Hex Code, Value” on
page 114
7
6
5
4
3
x64
11
—
2
x32
10
—
1
x16
9
0
x8
8
28h
2
—
15
—
—
14
—
—
13
—
—
12
—
28:
--01
x16
—
—
29:
--00
2A:
2B:
--0A
--00
2Ah
2Ch
2
1
n such that maximum number of bytes in write buffer = 2n.
1024
Number of erase block regions (x) within the device:
1) x = 0 means no erase blocking; the device erases in bulk.
2) x specifies the number of device regions with one or more
contiguous, same-size erase blocks.
2C:
3) Symmetrically blocked partitions have one blocking region.
2D:
2E:
2F:
30:
Erase block region 1 information:
bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.
bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.
2Dh
31h
35h
4
4
4
Table 55, “Device
Geometry
Definition: Addr,
Hex Code, Value”
on page 114
31:
32:
33:
34:
Reserved for future erase block region information.
Reserved for future erase block region information.
35:
36:
37:
38:
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 55: Device Geometry Definition: Addr, Hex Code, Value
128 Mbit
256 Mbit
512 Mbit
1 Gbit
Address
B
T
B
T
B
T
B
T
27
28
29
2A
2B
2C
2D
2E
2F
30
18
01
00
0A
00
01
3F
00
00
04
—
—
—
—
—
—
—
—
—
—
19
01
00
0A
00
01
7F
00
00
04
—
—
—
—
—
—
—
—
—
—
1A
01
00
0A
00
01
FF
—
—
—
—
—
—
—
—
—
—
1B
01
00
0A
00
01
FF
—
—
—
—
—
—
—
—
—
—
00
00
04
01
00
04
12.5
Numonyx-Specific Extended Query Table
Table 56: Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset
P = 10Ah
Description (Optional flash features and
commands
Length
Address
Hex Code
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
10A:
10B:
10C:
10D:
10E:
--50
--52
--49
--31
--34
P
R
I
Primary extended query table.
Unique ASCII string PRI
3
1
1
Major version number, ASCII
Minor version number, ASCII
1
4
Datasheet
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Table 56: Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset
P = 10Ah
Description (Optional flash features and
commands
Length
Address
Hex Code
Value
--E6 (Non-Mux)
--66 (A/D Mux)
10F:
Optional feature and command support:
(1 = yes; 0 = no)
Bits 10 - 31 are reserved; undefined bits are 0.
110:
111:
112:
--07
--00
--00
If the value in bit 31 is 1, an additional 31 bit field of
optional features follows the bit 30 field.
Bit 0: Chip erase supported.
Bit 0 = 0
No
Yes
Yes
No
Bit 1: Suspend erase supported.
Bit 2: Suspend program supported.
Bit 3: Legacy lock/unlock supported.
Bit 4: Queued erase supported.
Bit 5: Instant individual block locking supported.
Bit 6: OTP bits supported.
Bit 1 = 1
Bit 2 = 1
Bit 3 = 0
Bit 4 = 0
Bit 5 = 1
Bit 6 = 1
(P+5)h
(P+6)h
(P+7)h
(P+8)h
4
No
Yes
Yes
No: A/D Mux
Yes: Non-Mux
Bit 7: Page mode read supported.
Bit 7 = 0
Bit 8: Synchronous read supported.
Bit 9: Simultaneous operations supported.
Bit 30: CFI links to follow.
Bit 8 = 1
Bit 9 = 1
Yes
Yes
No
Bit 30 = 0
Bit 31 = 0
Bit 31: Another Optional Features field to follow.
No
Supported functions after Suspend: Read Array, Status,
Query. Other supported options include:
Bits 1 - 7: Reserved; undefined bits are 0.
113:
--01
(P+9)h
1
2
Bit 0: Program supported after Erase Suspend.
Bit 0 = 1
--33
--00
Bit 0 = 1
Bit 1 = 1
Yes
114:
115:
Block Lock Status Register mask: Bits 2 - 3 and 6 - 15
are reserved; undefined bits are 0.
(P+A)h
(P+B)h
2
2
Bit 0: Block Lock Bit Status register active.
Bit 1: Block Lock Down bit Status active.
Yes
Yes
Vcc logic supply highest performance program/erase
voltage:
Bits 0 - 3: BCD value in 100 mV
Bits 4 - 7: BCD value in volts
(P+C)h
(P+D)h
1
1
116:
117:
--18
1.8 V
9.0 V
VPP optimum program/erase supply voltage:
Bits 0 - 3: BCD value in 100 mV
Bits 4 - 7: Hex value in volts
--90
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 57: One Time Programmable (OTP) Register Information
Offset
P = 10Ah
Length
Description
Address
Hex Code
Value
Number of OTP register fields in JEDEC ID space. 00h indicates
that 256 OTP fields are available.
(P+E)h
1
118:
--02
2
OTP Field 1: OTP Description: This field describes user available
OTP register bytes. Some are preprogrammed with device-unique
serial numbers. Others are user programmable.
Bits 0 - 15 point to the OTP register Lock byte, the register’s first
byte.
(P+F)h
The following bytes are factory preprogrammed and user-
programmable:
(P+10)h
(P+11)h
(P+12)h
4
Bits 0 - 7 = Lock/bytes JEDEC plane physical low address.
Bits 8 - 15 = Lock/bytes JEDEC plane physical high address.
Bits 16 - 23 = n where 2n equals factory preprogrammed bytes.
Bits 24 - 31 = n where 2n equals user programmable bytes.
OTP Field 2: OTP Description
119:
11A:
11B:
11C:
--80
--00
--03
--03
80h
00h
8 byte
8 byte
11D:
11E:
11F:
120:
--89
--00
--00
--00
89h
00h
00h
00h
Bits 0 - 31 point to the OTP register physical Lock word address in
the JEDEC plane.
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
The following bytes are factory or user programmable:
Bits 32 - 39 = n where n equals factory programmed groups (low
byte).
Bits 40 - 47 = n where n equals factory programmed groups
(high byte).
Bits 48 - 55 = n where 2n equals factory programmed bytes/
groups.
121:
122:
123:
--00
--00
--00
0
0
0
10
Bits 56 - 63 = n where n equals user programmed groups (low
byte).
Bits 64 - 71 = n where n equals user programmed groups (high
byte).
Bits 72 - 79 = n where n equals user programmable bytes/
groups.
124:
125:
126:
--10
--00
--04
16
0
16
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Table 58: Burst Read Information
Offset
P = 10Ah
Description (Optional flash features and
commands)
Length
Address
Hex Code
Value
Page Mode Read capability:
Bits 0 - 7 = n where 2n hex value represents the
number of read-page bytes. See offset 28h for
device word width to determine page-mode data
output width. 00h indicates no read page buffer.
--05 (Non Mux) 32-byte (Non Mux)
(P+1D)h
(P+1E)h
1
1
127:
128:
--00 (A/D Mux
0 (AD Mux)
Number of synchronous mode read configuration
fields that follow. 00h indicates no burst capability.
--03
3
Synchronous mode read capability configuration 1:
Bits 3 - 7 = Reserved.
Bits 0 - 2 = n where 2n+1 hex value represents the
maximum number of continuous synchronous reads
when the device is configured for its maximum word
width.
A value of 07h indicates that the device is capable of
continuous linear bursts that will output data until
the internal burst counter reaches the end of the
device’s burstable address space.
(P+1F)h
1
129:
--02
8
This fields’s 3-bit value can be written directly to the
Read Configuration Register bits 0 - 2 if the device is
configured for its maximum word width. See offset
28h for word width to determine the burst data
output width.
(P+20)h
(P+21)h
1
1
Synchronous mode read capability configuration 2.
Synchronous mode read capability configuration 3.
12A:
12B:
--03
--07
16
Cont
Table 59: Partition and Erase Block Information—Region 1 (Sheet 1 of 2)
Offset
P = 10Ah
Address
Description (Optional flash features and commands)
Length
Bottom
Top
Bottom
Top
Number of device hardware partition regions with the device:
x = 0: a single hardware partition device (no fields follow). x specifies the
number of device partition regions containing one or more contiguous
erase block regions.
(P+22)h
(P+22)h
1
12C:
12C:
Partition Region 1 Information
(P+23)h
(P+24)h
(P+25)h
(P+26)h
(P+23)h
(P+24)h
(P+25)h
(P+26)h
12D:
12E:
12F:
130:
12D:
12E:
12F:
130:
Data size of this Partition Region information field: (number of
addressable locations, including this field.
2
1
Number of identical partitions within the partition region.
Number of Program or Erase operations allowed in a partition:
(P+27)h
(P+28)h
(P+27)h Bits 0 - 3 = Number of simultaneous Program operations.
Bits 4 - 7 = Number of simultaneous Erase operations.
1
1
131:
132:
131:
132:
Number of Program or Erase operations allowed in other partitions while a
partition in this region is in Program mode:
(P+28)h
Bits 0 - 3 = Number of simultaneous Program operations.
Bits 4 - 7 = Number of simultaneous Erase operations.
Number of Program or Erase operations allowed in other partitions while a
partition in this region is in Erase mode:
(P+29)h
(P+29)h
1
133:
133:
Bits 0 - 3 = Number of simultaneous Program operations.
Bits 4 - 7 = Number of simultaneous Erase operations.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 59: Partition and Erase Block Information—Region 1 (Sheet 2 of 2)
Offset
P = 10Ah
Address
Description (Optional flash features and commands)
Length
Bottom
Top
Bottom
Top
Types of erase block regions in this partition region:
x = 0: No erase blocking; the partition region erases in bulk.
x = Number of erase block regions with contiguous, same-size erase
(P+2A)h blocks.
Symmetrically blocked partitions have one blocking region.
(P+2A)h
1
134:
134:
Partition size = (Type 1 blocks) x (Type 1 block sizes) + (Type 2 blocks) x
(Type 2 block sizes) +...+ (Type n blocks) x (Type n block sizes).
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
(P+2F)h
(P+30)h
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
(P+2F)h
(P+30)h
135:
136:
137:
138:
139:
13A:
135:
136:
137:
138:
139:
13A:
Partition region 1 erase block type 1 information:
Bits 0 - 15 = y, y + 1: Number of identical-sized erase blocks in a
partition.
4
Bits 16 - 30 = z, where region erase block(s) size is z x 256 bytes.
Partition 1 (Erase Block Type 1):
Block erase cycles x 1000
2
1
Partition 1 (Erase Block Type 1) bits per cell; internal EDAC:
Bits 0 - 3 = bits per cell in erase region
Bit 4 = internal EDAC used (1=yes, 0=no)
Bit 5 - 7 = reserved for future use
(P+31)h
(P+31)h
13B:
13B:
Partition 1 (Erase Block Type 1) page mode and synchronous mode
capabilities:
Bits 0 = page mode host reads permitted (1=yes, 0=no)
Bit 1 = synchronous host reads permitted (1=yes, 0=no)
Bit 2 = synchronous host writes permitted (1=yes, 0=no)
Bit 3 - 7 = reserved for future use
(P+32)h
(P+32)h
1
13C:
13C:
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+33)h Partition 1 (Erase Block Type 1) programming region information:
13D:
13E:
13F:
140:
141:
13D:
13E:
13F:
140:
141:
Bits 0 - 7 = x, 2x: programming region aligned size (bytes)
(P+34)h
Bit 8 - 14 = reserved for future use
(P+35)h
(P+36)h
(P+37)h
Bit 15 = legacy flash operation; ignore 0:7
Bit 16 - 23 = y: control mode valid size (bytes)
Bit 24 - 31 = reserved for future use
6
Bit 32 - 39 = z: control mode invalid size (bytes)
Bit 40 - 46 = reserved for future use
Bit 47 = legacy flash operation (ignore 23:16 and 39:32)
(P+38)h
(P+38)h
142:
142:
Table 60: Partition and Erase Block Region Information (Sheet 1 of 2)
128 Mbit
256 Mbit
512 Mbit
1 Gbit
Address
B
T
B
T
B
T
B
T
12C:
12D:
12E:
12F:
130:
131:
132:
133:
--01
--16
--00
--08
--00
--11
--00
--00
—
—
—
—
—
—
—
—
--01
--16
--00
--08
--00
--11
--00
--00
—
—
—
—
—
—
—
—
--01
--16
--00
--08
--00
--11
--00
--00
—
—
—
—
—
—
—
—
--01
--16
--00
--08
--00
--11
--00
--00
—
—
—
—
—
—
—
—
Datasheet
118
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 60: Partition and Erase Block Region Information (Sheet 2 of 2)
128 Mbit
256 Mbit
512 Mbit
1 Gbit
Address
B
T
B
T
B
T
B
T
134:
135:
136:
137:
138:
139:
13A:
13B:
--01
--07
--00
--00
--04
--64
--00
--12
—
—
—
—
—
—
—
—
--01
--0F
--00
--00
--04
--64
--00
--12
—
—
—
—
—
—
—
—
--01
--1F
--00
--00
--04
--64
--00
--12
—
—
—
—
—
—
—
—
--01
--3F
--00
--00
--04
--64
--00
--12
—
—
—
—
—
—
—
—
--02 Mux
--03 Non Mux
--02 Mux
--03 Non Mux
--02 Mux
--03 Non Mux
--02 Mux
--03 Non Mux
13C:
—
—
—
—
13D:
13E:
13F:
140:
141:
142:
--0A
--00
--10
--00
--10
--00
—
—
—
—
—
—
--0A
--00
--10
--00
--10
--00
—
—
—
—
—
—
--0A
--00
--10
--00
--10
--00
—
—
—
—
—
—
--0A
--00
--10
--00
--10
--00
—
—
—
—
—
—
April 2008
309823-10
Datasheet
119
Numonyx™ StrataFlash® Cellular Memory (M18)
13.0
Next State
The Next State Table shows command inputs and the resulting next state of the chip.
The Output Next State Table shows command inputs and the resulting output
multiplexed next state of the chip.
Table 61: Next State Table (Sheet 1 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(0
(2 3h
(F
(4
(E
(2
(8
(D
0h
)
(7
(5 0h (6
(B (C
(0
(x
xh
)
(B
0)
Fh 1h 9h 0h 0h
0h 0h
,
98
h)
0h Ch 0h 1h Fh
,
04
h)
other
)
)
)
)
)
)
)
)
)
)
)
)
Lo
ck
/
RC
R
/
EC
R
Se
tu
p
Pr
og
rm
Er
as
e
BE
FP
Se
tu
p
OT
P
Se
tu
p
BC
BP
Se
tu
p
Re
ad
y
N/
A
N/
A
Se
tu
p
Ready
Ready
Ready
Ready
Se
tu
p
Se
tu
p
Re
ad
y
(L
oc
k
Er
ror
[B
ot
ch
])
Re
Re ad
Re
ad
y
(U
nlo
ck
ad
y
(L
oc
k
y
(L
oc
k
Re
ad
y
(S
et
Ready
(Lock Error
[Botch])
Ready (Lock
Error [Botch])
Lock/RCR/ECR
Setup
N/
A
N/
A
Ready (Lock Error [Botch])
do
Bl wn CR
Blo
ck)
oc
k)
Bl
oc
k)
)
N/
A
N/
A
Setup
OTP Busy
OTP Busy
OTP Busy
OTP Busy
IS
OT
P
Bu
in OT
IS in
OT
P
P
Bu
Illegal State
in OTP Busy
N/
A
OTP
Busy
OTP
OTP Busy
OTP Busy
Re
ad
y
Busy
sy Bu sy
sy
IS in OTP
Busy
OTP Busy
OTP Busy
Datasheet
120
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 2 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(0
(F
(4
(E
(2
(8
(D
(7
0h 0h
)
(5
0h (6
(B
(C
(0
(2
3h (x
(B
0)
Fh 1h 9h 0h 0h 0h
)
,
98
h)
0h Ch 0h 1h Fh
)
,
04
h)
xh
)
other
)
)
)
)
)
)
)
)
)
)
N/
A
N/
A
Setup
Word Program Busy
Pgm Busy
IS
in
Pg
m
Pg
m
Pg
m
Pg
m
Pg
IS in
Pgm
Busy
m
Word Pgm
Busy
IS in Word
Pgm Busy
Word Pgm
Busy
N/
A
Busy
Pgm Busy
Re
ad
y
Bu
Bu
Bu Su
sy Bu sy
sy
sy
sp
IS in Pgm
Busy
Word Pgm Busy
Word
Progra
m
Pg
m
Su
sp
(E
r
bit
s
cle
ar)
W
or
d
Pg
m
Su
sp
IS Pg
Pg
m
in
m
Pg
m
Bu
sy
IS in
Pgm
Susp
Illegal State
in Pgm
Suspend
Word
Program
Suspend
Pg Su
sp
Pgm
Susp
N/
A
Word Pgm
Susp
Suspend
Su
m
N/
A
sp Su en
sp
d
IS in Pgm
Suspend
Word Program Suspend
April 2008
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Datasheet
121
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 3 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(5 0h (6
(0
(F
(4
(E
(2
(8
(D
0h
)
(7
0h 0h
)
(B (C
(0
(2 3h
(x
xh
)
(B
0)
Fh 1h 9h 0h 0h
)
,
0h Ch 0h 1h Fh
)
,
04
h)
other
)
)
)
)
)
98
h)
)
)
)
)
Setup
BP Load 1
BP Load 2 if word count >0, else BP confirm
BP Load 1
(10)
Re
ad
y
(E
rro
r
[B
ot
ch
])
BP Confirm
if data load
in program
buffer is
complete,
else BP
load 2
BP Load 2
(10)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
N/
A
Re
ad
y
(E
rro
r
[B
ot
ch
])
Re
ad
y
(E
BP
rro
Bu
r
BP
Confirm
sy
[B
ot
ch
])
Ill
eg
al
Buffer
Progra
m
IS
in
IS
in
BP
Bu
sy
St
at
e
(BP)
BP
BP
BP BP BP
Bu Su Bu
BP
Bu
sy
BP
Bu
sy
BP Busy
Bu BP Bu
sy Bu sy
sy
Re
ad
y
sy
sp
sy
in
BP
Bu
sy
BP
Bu
sy
IS in BP
Busy
Ill
eg
al
St
at
e
BP
Su
IS BP
BP
sp
(E BP
r
IS
in
Su BP
BP
Su
sp
en
d
BP
in
Su
BP Su
Bu
sy
BP
Suspend
N/
A
Su BP sp
sp Su en
sp
en
d
BP Susp
bit sp Su
in
sp
d
s
cle
ar)
sp
N/
A
BP
Bu
sy
BP
Su
sp
en
d
IS in BP
Suspend
Datasheet
122
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 4 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(0
(F
(4
(E
(2
(8
(D
(7
0h 0h
)
(5
0h (6
(B
(C
(0
(2
3h (x
(B
0)
Fh 1h 9h 0h 0h 0h
)
,
98
h)
0h Ch 0h 1h Fh
)
,
04
h)
xh
)
other
)
)
)
)
)
)
)
)
)
)
Era
se
Bu
sy
N/
A
Ready (Err
Botch0])
N/
A
Setup
Busy
Ready (Error [Botch])
IS
Ready (Error [Botch])
Er
as
e
in
Er
as
e
Er
as
e
Er
as
e
Su
sp
Era
se
Bu
sy
IS in
Erase
Busy
IS in Erase
N/
A
Erase Busy
Erase Busy
Erase Busy
Re
ad
y
Busy
Bu
Bu
sy Bu sy
sy
IS in Erase
Busy
Erase Busy
Lo
ck
/
RC
R/
EC
R
Se
tu
p
W
or
d
Erase
Er
BP
as
Pg Se
e
IS
in
Er
as
e
m
Se
tu
p
in
Er
tu
p
in
Er
as
e
Er
as
e
Su
sp
Su Er
Er
as
e
IS in
Erase
Suspen
d
Era
se
Bu
sy
Erase
Suspen
d
sp
(E
r
bit sp
s
cle
ar)
as
e
Su
Erase
Suspend
N/
A
Suspend
Erase Susp
N/
A
Su
sp Su
sp
in
as Su
e
Su
sp
Er
as
e
sp
Su
sp
IS in Erase
Susp
Erase Suspend
Word Pgm
Busy in Ers
Suspend
N/
A
N/
A
Setup
Word Pgm busy in Erase Suspend
W
or
d
W
or
d
W
IS
in
Wo
or
rd
d
Word
Progra
m in
Erase
Suspe
Pg Pg Pg
m
bu bu bu
sy
in
Er
as
e
Pg
Pg
m
IS in
Word
Pgm
busy in
Ers
m
m
Er
as
e
Su
sp
m
bu
sy
in
Era
se
Su
sp
Word Pgm
busy in Erase
Susp
IS in Word
Pgm busy in
Ers Susp
Su
sp
in
Busy
sy
in
Er
s
sy
in
Er
as
e
Word Pgm busy in Erase Susp
nd
Susp
Er
s
Su
sp
Su
Su sp Su
sp
sp
April 2008
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Datasheet
123
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 5 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(5 0h (6
(0
(F
(4
(E
(2
(8
(D
0h
)
(7
0h 0h
)
(B (C
(0
(2 3h
(x
xh
)
(B
0)
Fh 1h 9h 0h 0h
)
,
0h Ch 0h 1h Fh
)
,
04
h)
other
)
)
)
)
)
98
h)
)
)
)
)
IS
in
Er
as
e
Su
sp
Illegal
State (IS)
in Pgm
busy in
Erase
Word Pgm
busy in
Erase
Word Pgm busy in Erase Suspend
Suspend
Suspend
W
or
d
Pg
W
or
d
Pg
m
su
sp
in
Er
as
e
Su
sp
W
or
d
Pg
m
su
sp
in
Er
as
e
Su
sp
W
W
or
d
W
or
d
Pg
m
Su
sp
in
Er
as
e
Su
sp
iS
in
pg
m
su
sp
in
Er
as
e
Su
sp
m
Su
sp
in
Wo or
rd
Pg
m
bu
sy
in
d
Pg Pg
m
su Su
sp sp
in
Word
IS in
m
Progra
Er
as
e
Su
sp
:
Er
ror
bit
s
pgm
susp in
Erase
Susp
IS in Word
Pgm Susp in
Erase Susp
Word Pgm
Susp in
Erase Susp
Word Pgm
Susp in
Erase Susp
m in
N/
A
Suspend
Erase
Suspe
nd
in
Er
as
e
Era Er
se
Su
sp
as
e
Su Su
sp sp
N/
A
cle
ar
Illegal
State in
Word
Program
Suspend
in Erase
Suspend
Word
PgmSuspen
d in Erase
Suspend
Word Pgm Suspend in Erase Suspend
Datasheet
124
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 6 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(0
(F
(4
(E
(2
(8
(D
(7
0h 0h
)
(5
0h (6
(B
(C
(0
(2
3h (x
(B
0)
Fh 1h 9h 0h 0h 0h
)
,
98
h)
0h Ch 0h 1h Fh
)
,
04
h)
xh
)
other
)
)
)
)
)
)
)
)
)
)
Setup
BP Load 1
BP Load 2 if word count >0, else BP confirm
BP Load 1
(10)
Er
as
e
Su
sp
:
Er
ror
[B
ot
ch
]
BP Confirm
in Erase
Suspend
when
count=0,
ELSE BP
load 2
BP Load 2
(10)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
N/
A
BP
Bu
sy
in
Ers
Su
sp
BP
Confirm
Erase Suspend (Error
[BotchBP])
Erase Susp: Error [Botch BP]
IS
BP
in
BP
BP
Su
sp
in
Er
as
e
Bu BP Bu
sy Bu sy
Er
as
e
Su
sp
in
Er
as
e
sy
in
Er
as
e
in
Er
as
e
Illegal State
in BP Busy in
Erase Susp
IS in BP Busy
BP Busy in
in Erase
BP Busy in
Erase Susp
N/
A
BP Busy in
Erase Susp
BP in
BP Busy
Erase Susp
Suspend
Erase
Suspe
nd
Su
Su
Su
sp
sp Su sp
sp
IS
in
Er
as
e
IS in BP
Busy
BP Busy in Erase Suspend
Su
sp
BP
Su
sp
in
BP
Er
Su
as
sp
e
Su
sp
:
Er
ror
bit
s
IS
BP
in
BP
BP
Su BP Su
sp Su sp
Bu
Illegal
sy
in
Er
as
e
sp
in
Er
as
e
in
State in
BPSusp
in Erase
Susp
in IS in BP Busy
in
Era
se
Su
sp
BP Susp in
Erase Susp
N/
A
BP Susp in
Erase Susp
BP Susp
Er BPBusy
as in Erase
e
Su
Er
as
e
in Erase
Suspend
N/
A
Susp
Su
Su
sp
sp Su sp
sp
April 2008
309823-10
Datasheet
125
cle
ar
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 61: Next State Table (Sheet 7 of 7)
Command Input and Resulting Chip Next State
Current Chip State
(9
(5 0h (6
(0
(F
(4
(E
(2
(8
(D
0h
)
(7
0h 0h
)
(B (C
(0
(2 3h
(x
xh
)
(B
0)
Fh 1h 9h 0h 0h
)
,
0h Ch 0h 1h Fh
)
,
04
h)
other
)
)
)
)
)
98
h)
)
)
)
)
Er
as
e
Su
sp
:
Er
ror
[B
ot
ch
]
Er
as
e
Era
se
Su
sp:
Un
-
loc
k
Blo
ck
Er
as
e
Er
as
e
Su
Lock/RCR/ECR
Setup in Erase
Suspend
Su sp
Erase
Susp: Error
[Botch]
Erase Suspend: Lock
Error [Botch]
Erase Susp: Lock Error
[Botch]
Su N/
N/
A
sp
Bl
k
Bl
k
Lk
-
sp
CR
Se
t
A
Lo
ck Do
wn
BC
Bu
sy
Ready:
Error
[Botch]
N/
A
Setup
Ready (Error [Botch])
IS
Ready: Error [Botch]
Blank
Check
(BC)
Blank
Check
Busy
BC
in BC
Bu BC Bu
sy Bu sy
sy
IS in BC
Busy
IS in BC
Busy
N/
A
BC Busy
BC Busy
BC Busy
BC Busy
Re
ad
y
IS in Blank
Check
BC Busy
Busy
BE
FP
Lo
ad
Da
ta
N/
A
Setup
Ready: Error [Botch]
Ready: Error [Botch]
BEFP
Re
ad
y
Re
ad
y
BEFP Program and Verify Busy (if Block Address given matches address given on
BEFP Setup command). Commands treated as data. (7)
BEFP Busy
BEFP Busy
Datasheet
126
April 2008
309823-10
Numonyx™ StrataFlash® Cellular Memory (M18)
Table 62: Output Next State Table
Command Input to Chip and Resulting Output MUX Next State
Current Chip State
(9
(0
(F
(4
(E
(E
(2
(8 (D
(7 (5 0h (6 (B (C (0 (2 3h
ot
he
r
(B
0)
Fh 1h 9h Bh 0h 0h 0h
)
0h 0h
,
98
h)
0h Ch 0h 1h Fh
,
04
h)
)
)
)
)
)
)
)
)
)
)
)
)
)
BEFPSetup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Confirm
WordPgmSetup,
Word Pgm Setup in Erase
Susp,
Status Read
BP Confirm in Erase
Suspend,
Blank Check Setup,
Blank Check Busy
Ar
ra
y
Re
ad
Lock/RCR/ECR Setup,
Status
Read
Status Read
Lock/RCR/ECR Setup in
Erase Susp
BP Setup, Load 1, Load 2
Output MUX will not change
BP Setup, Load1, Load 2 -
in Erase Susp.
BP Busy
BP Busy in Erase Suspend
Word Program Busy,
Word Prgm Busy in Erase
Suspend,
Status
Read
Erase Busy
Ready,
Word Prgm Suspend,
BP Suspend,
Phase-1 BP Suspend,
Erase Suspend,
Output MUX
does not
change
Status
Read
Output
MUX
Status Read
does
not
Change
BP Suspend in Erase
Suspend
SR
Re
ad
Status
Read
OTP Busy
Notes:
1.
The Partition Data When Read field shows what users read from the flash chip after issuing the appropriate command,
given the Partition Address is not changed from the address given during the command. Read-while-write functionality
gives more flexibility in data output from the device. The data read from the chip depends on the Partition Address applied
to the device. Depending on the command issued to the chip, each partition is placed into one of the following three
output states during commands: Read Array, Read Status or Read ID/CFI. This partition's output state is retained until a
April 2008
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Datasheet
127
Numonyx™ StrataFlash® Cellular Memory (M18)
new command is issued to the chip at that Partition Address. This allows the user to set partition #1's output state to Read
Array, and partition #4's output state to Read Status. Each time the partition address is changed to partition #4 (without
issuing a new command), the Status will be read from the chip.
Illegal commands include commands outside of the allowed command set (allowed commands: 41H [pgm], 20H [erase],
etc.)
All partitions default to Read Array on powerup.
If a Read Array is attempted from a busy partition, the result is unreliable data. When the user returns to this partition
address later, the output mux will be in the “Read Array” state from its last visit. the Read ID and Read Query commands
perform the same function in the device. The ID and Query data are located at different locations in the address map.
1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will
occur.
The Clear Status command clears only the error bits in the status register if the device is not in the following modes: 1)
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2) Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
2.
3.
4.
5.
6.
7.
8.
BEFP writes are allowed only when the status register bit #0 = 0 or else the data is ignored.
The current state is that of the chip and not of the partition. Each partition remembers which output (Array, ID/CFI or
Status) it was last pointed to on the last instruction to the chip, but the next state of the chip does not depend on where
the partition's output mux is presently pointing to.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
9.
10.
Buffered programming will botch when a different block address (as compared to address given with E9 command) is
written during the BP Load1 and BP Load2 states.
11.
12.
WA0 refers to the block address latched during the first write cycle of the current operation.
All two cycle commands are considered as a contiguous whole during device suspend states. Individual commands are not
parsed separately; that is, the 2nd cycle of an erase command issued in program suspend will NOT resume the program
operation.
13.
The Buffered Program setup command (0xE9) will not change the partition state. The Buffered Program Confirm command
(0xD0) will place the partition in read status mode.
Appendix A AADM Mode
A.1
AADM Feature Overview
The following is a list of general requirements for AADM mode. Additional details can be
found in subsequent sections.
• Feature Availability: AADM mode is available in devices that are configured as A/
D MUX. With this configuration, AADM mode is enabled by setting a specific volatile
bit in the RCR.
• High Address Caputure (A[MAX:16]): When AADM mode is enabled,
A[MAX:16] and A[15:0] are captured from the A/DQ[15:0] balls. The selection of
A[MAX:16] or A[15:0] is determined by the state of the OE# input, as A[MAX:16]
is captured when OE# is at VIL.
• Read & Write Cycle Support: In AADM mode, both asynchronous and
synchronous Cycles are supported.
• Customer Requirements: For AADM operation, the customer is required to
ground A16-Amax.
• Other Characteristics: For AADM, all other device characteristics (pgm time,
erase time, ICCS, etc.) are the same as A/D MUX unless otherwise stated.
A.2
AADM Mode Enable (RCR[4]=1)
Setting RCR.4 to its non-default state (‘1b) enables AADM mode:
• The default device configuration upon Reset or Powerup is A/D MUX Mode
• Upon setting RCR[4]=1, the upper Addresses A[max:16] are latched as all 0’s by
default.
Datasheet
128
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Numonyx™ StrataFlash® Cellular Memory (M18)
A.3
Bus Cycles and Address Capture
AADM bus operations have one or two address cycles. For two address cycles, the
upper address (A[MAX:16]) must be issued first, followed by the lower address
(A[15:0]). For bus operations with only one address cycle, only the lower address is
issued. The upper address that applies is the one that was most recently latched on a
previous bus cycle. For all read cycles, sensing begins when the lower address is
latched, regardless of whether there are one or two address cycles.
In bus cycles, the external signal that distinguishes the upper address from the lower
address is OE#. When OE# is at VIH, a lower address is captured; when OE# is at VIL,
an upper address is captured.
When the bus cycle has only one address cycle, the timing waveform is similar to A/D
MUX mode. The lower address is latched when OE# is at VIH, and data is subsequently
outputted after the falling edge of OE#.
Note:
When the device initially enters AADM mode, the upper address is internally latched as
all 0’s.
A.3.1
WAIT Behavior
The WAIT behavior in AADM mode functions the same as the legacy M18 non-MUX
WAIT behavior (ADMux WAIT behavior is unique). In other words, WAIT will always be
driven whenever DQ[15:0] is driven, and WAIT will tri-state whenever DQ[15:0] tri-
state. In asynchronous mode (RCR[15] = ‘1b), WAIT always indicates “valid data”
when driven. In synchronous mode (RCR[15] = ‘0b), WAIT indicates “valid data” only
after the latency count has lapsed and the data output data is truly valid.
A.3.2
Asynchronous Read and Write Cycles
For asynchronous read and write cycles, ADV# must be toggled high-low-high a
minimum of one time and a maximum of two times during a bus cycle. If ADV# is
toggled low twice during a bus cycle, OE# must be held low for the first ADV# rising
edge and OE# must be held high for the second ADV# rising edge. The first ADV#
rising edge (with OE# low) captures A[MAX:16]. The second ADV# rising edge (with
OE# high) captures A[15:0]. Each bus cycle must toggle ADV# high-low-high at least
one time in order to capture A[15:0]. For asynchronous reads, sensing begins when the
lower address is latched.
During asynchronous cycles, it is optional to capture A[MAX:16]. If these addresses are
not captured, then the previously captured A[MAX:16] contents will be used.
A.3.2.1
Asynchronous Read Cycles
For asynchronous read and latching specifications, refer to Table 63, “AADM
Aynchronous and Latching Timings” on page 130. For asynchronous read timing
diagrams, refer to Figure 61, “AADM Asynchronous Read Cycle (Latching A[MAX:0])”
on page 130 and Figure 62, “AADM Asynchronous Read Cycle (Latching A[15:0] only)”
on page 131. For AADM, note that asynchronous read access is from the rising edge of
ADV# rather than the falling edge. (i.e. TVHQV rather than TVLQV)
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 63: AADM Aynchronous and Latching Timings
Num
Sym
Min (nS)
Max (nS)
Num
Sym
Min (nS)
Max (nS)
R4
R5
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
20
R17
tGHTZ
tAVVH
tELVH
tVLVH
tVHVL
tVHAX
tVHGL
9
150
R101
R102
R104
R105
R106
R107
R109
R111
R127
R128
R129
5
9
7
7
5
3
R6
0
0
R7
R8
9
9
R9
R10
R11
R12
R13
R15
R16
0
7
(1)
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tVHQV
96
11
9
tPHVH
tGHVH
tGLVH
tVHGH
30
3
7
3
0
3
Notes:
1.
2.
TVHQV applies to asynchronous read access time.
A read cycle may be restarted prior to completing a pending read operation, but this may occur only once before the sense
operation is allowed to complete.
Figure 61: AADM Asynchronous Read Cycle (Latching A[MAX:0])
A/DQ[15:0]
A[MAX:16]
A[15:0]
DQ[15:0]
R101
R106
R106
R105
R101
R104
R104
R109
ADV#
CE#
OE#
R8
R11
R102
R128
R7
R9
R129
R127
R107
R4
R127+R107
R15
R16
R17
R13
WAIT
Notes:
1.
Diagram shows WAIT as active low (RCR.10=0)
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
1
Figure 62: AADM Asynchronous Read Cycle (Latching A[15:0] only)
A/DQ[15:0]
A[15:0]
DQ[15:0]
R101
R106
R104
R109
ADV#
CE#
OE#
R8
R11
R102
R7
R9
R107
R4
R127+R107
R15
R17
R13
R16
WAIT
Notes:
1.
2.
Diagram shows WAIT as active low (RCR.10=0).
Without latching A[MAX:16] in the Asynchronous Read Cycle, the previously latched A[MAX:16] applies.
A.3.2.2
Asynchronous Write Cycles
For asynchronous write specifications, refer to Table 64, “AADM Write Timings” on
page 132. For asynchronous write timing diagrams, refer to Figure 63, “AADM
Asynchronous Write Cycle (Latching A[MAX:0])” on page 132 and Figure 64, “AADM
Asynchronous Write Cycle (Latching A[15:0] only)” on page 132.
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 64: AADM Write Timings
Num
Symbol
Min(nS)
Num
Symbol
Min(nS)
W1
W2
W3
W4
W6
W7
tPHWL
tELWL
150
0
W9
tWHWL
tVPWH
tWVVL
tBHWH
tWHGL
tGHWL
20
200
0
W10
W11
W13
W14
W23
tWLWH
tDVWH
tWHEH
tWHDX
40
40
0
200
0
0
0
Figure 63: AADM Asynchronous Write Cycle (Latching A[MAX:0])
W7
A/DQ[15:0]
ADV#
A[MAX:16]
A[15:0]
DQ[15:0]
W6
CE#
OE#
W14
W2
W23
W4
W2
W3
W9
WE#
WP#
W13
W1
RST#
Figure 64: AADM Asynchronous Write Cycle (Latching A[15:0] only)
W7
A/DQ[15:0]
ADV#
A[15:0]
DQ[15:0]
W6
CE#
OE#
W14
W4
W2
W2
W3
W9
WE#
WP#
W13
W1
RST#
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A.3.3
Synchronous Read and Write Cycles
Just as asynchronous bus cycles, synchronous bus cycles (RCR[15] = ‘0b) can have
one or two address cycles. If the are two address cycles, the upper address must be
latched first with OE# at VIL followed by the lower address with OE# at VIH. If there is
only one address cycle, only the lower address will be latched and the previously
latched upper address applies. For reads, sensing begins when the lower address is
latched, but for synchronous reads, addresses are latched on a rising clock CLK instead
of a rising ADV# edge.
For synchronous bus cycles with two address cycles, it is not necessary to de-assert
ADV# between the two address cycles. This allows both the upper and lower address to
be latched in only two clock periods.
A.3.3.1
Synchronous Read Cycles
For synchronous read specifications, refer to Table 65, “AADM Synchronous Timings” on
page 133. For synchronous read timing diagrams, refer to the following:
• Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address
Cycles)” on page 134
• Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address
Cycles)” on page 134
• Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135
Table 65: AADM Synchronous Timings
Target (104 MHz)
Target (104 MHz)
(108MHz)
Notes
(3)
Notes
(3)
(108MHz)
Num
Sym
Num
Sym
Min (nS)
Max (nS)
Min (nS)
Max (nS)
R201
R203
R301
R302
R303
R304
R305
R306
R307
tCLK
tRISE/FALL
tAVCH
9
See note
1.5
1
5
R311
R312
R313
R314
R316
R317
R318
R319
R320
tCHVL
tCHTX
tCHVH
tCHGL
tVLVH
tVHCH
tCHGH
tGHCH
tGLCH
2.5
2
3
3
2
2
4
tVLCH
2
2.5
tCLK
3
tELCH
3.5
2*tCLK
tCHQV
tCHQX
tCHAX
7
7
2
5
2
4
3
tCHTV
3
Notes:
1.
2.
The device must operate down to 9.6MHz in synchronous burst mode.
During the address capture phase of a read burst bus cycle, OE# timings relative to CLK shall be identical to those of
ADV# relative to CLK.
3.
4.
In synchronous burst read cycles, the asynchronous OE# to ADV# setup and hold times must also be met (Tghvh & Tvhgl)
to signify that the address capture phase of the bus cycle is complete.
To prevent A/D bus contention between the host and the memory device, OE# may only be asserted low after the host has
satisfied the ADDR hold spec, Tchax.
5.
6.
Rise and fall time specified between Vil & Vih
A read cycle may only be terminated (prior to the completion of sensing data) one time before a full bus cycle must be
allowed to complete.
April 2008
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133
Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 65: AADM Sync Burst Read Cycle (ADV# De-asserted between Address Cycles)
A/DQ[15:0]
CLK
A[MAX:16]
R306
A[15:0]
DQ[15:0]
DQ[15:0]
A
R306
R315
R305
R301
R301
R304
R302
R317
R313
R302
R317
R313
R311
R311
R316
R316
ADV#
CE#
R303
R318
R314
R320
R319
OE#
WE#
R307
R312
WAIT
Notes:
1.
2.
Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0).
For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram).
Figure 66: AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address Cycles)
A/DQ[15:0]
CLK
A[MAX:16]
R306
A[15:0]
R306
DQ[15:0]
DQ[15:0]
A
R305
R315
R301
R301
R304
R302
R317
R313
R311
ADV#
CE#
R303
R318
R314
R320
R319
OE#
WE#
R307
R312
WAIT
Notes:
1.
Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0)
Datasheet
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Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 67: AADM Sync Burst Read Cycle (Latching A[15:0] only)
A/DQ[15:0]
CLK
A[15:0]
R306
DQ[15:0]
DQ[15:0]
A
R305
R315
R301
R302
R304
R317
R313
R311
ADV#
CE#
R303
R314
OE#
WE#
R307
R312
WAIT
Notes:
1.
2.
3.
Diagram shows WAIT as active low (RCR.10=0) and asserted with Data (RCR.8=0).
For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in timing diagram)
Without latching A[MAX:16] in the Sync Read Cycle, the previously latched A[MAX:16] applies.
A.3.4
Synchronous Write Cycles
For synchronous writes, only the address latching cycle(s) are synchronous.
Synchronous address latching is depicted in the timing diagrams for synchronous read
cycles:
• Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address
Cycles)” on page 134
• Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address
Cycles)” on page 134
• Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135
The actual write operation (rising WE# edge) is asynchronous and is independent of
CLK. Asynchronous writes are depicted in the timing diagrams for asynchronous write
cycles:
• Figure 63, “AADM Asynchronous Write Cycle (Latching A[MAX:0])” on page 132
• Figure 64, “AADM Asynchronous Write Cycle (Latching A[15:0] only)” on page 132
A.3.5
System Boot
Systems that use the AADM mode will boot from the bottom 128k Bytes of device
memory because A[MAX:16] are expected to be grounded in-system. The 128k Byte
boot region is sufficient to perform required boot activities before setting RCR[4] to
enable AADM mode.
April 2008
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Numonyx™ StrataFlash® Cellular Memory (M18)
Appendix B Additional Information
Order Number
Document/Tool
Numonyx™ StrataFlash® Cellular Memory (M18) Developer’s Manual
315567
Numonyx™ StrataFlash® Cellular Memory (M18 SCSP); 2048-Mbit M18 (Non-Mux and AD-Mux I/O)
Family with Synchronous PSRAM Datasheet
307654
310048
309311
®
®
Designing with Numonyx™ StrataFlash Wireless Memory and Pre-enabling Numonyx™ StrataFlash
Cellular Memory, Application Note 822
®
®
Numonyx™ StrataFlash Cellular Memory (M18 SCSP) to ARM PrimeCellTM Design Guide, Application
Note 841
®
Migration Guide for Numonyx™ StrataFlash Cellular Memory (M18) 90 nm to 65 nm, Application Note
860
315651
310058
Effect of Program Buffer Size on System Interrupt Latency, Application Note 816
Notes:
4.
Visit Numonyx’s World Wide Web home page at http://www.numonyx.com for technical documentation and tools or for
the most current information on Numonyx flash products.
Appendix C Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please
contact your local Numonyx representative.
Table 66: 38F Type Stacked Components
PF
38F
5070
M0
Y
0
B
0
Product Die/
Density
Configuration
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Package
Designator
Product Line
Designator
NOR Flash Prodcut
Family
Ballout
Identifier
Device
Details
Char 1 = Flash
die #1
V =
1.8 V Core
0 =
Char 2 = Flash
die #2
First character
applies to Flash
die #1
No parameter
blocks; Non-
Mux I/O
B =
x16D
Ballout
and I/O;
Separate Chip
Enable per die
Char 3 =
interface
0 =
PF =
SCSP, RoHS
RAM die #1
Second character
applies to Flash
die #2
(See
(See
Original
released
version of
this
(See
Table 70,
“Voltage /
NOR Flash
CE#
Table 72
Table 71,
“Parameter
/ Mux
Char 4 =
RAM die #2
StackedNOR
Flash + RAM
,
RD =
“Ballout
Decoder
” on
(See Table 69,
“NOR Flash
Family
SCSP, Leaded
product
Configurati
on
Configurati
on
(See
page 13
9 for
Table 68,
“38F / 48F
Density
Decoder”
on
Decoder”
on
Decoder” on
page 138 for
details)
Decoder”
on
details)
page 138
for details)
page 138
for details)
page 137 for
details)
Datasheet
136
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Table 67: 48F Type Stacked Components
PC
48F
4400
P0
V
B
0
0
Product Die/
Density
Configuration
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Package
Designator
Product Line
Designator
NOR Flash Prodcut
Family
Ballout
Identifier
Device
Details
PC =
Char 1 = Flash
die #1
Easy BGA,
RoHS
V =
B =
Bottom
parameter;
Non-Mux I/O
interface
1.8 V Core
and 3 V I/O;
Virtual Chip
Enable
First character
applies to Flash
dies #1 and #2
Char 2 = Flash
die #2
0 =
Discrete
Ballout
RC =
Easy BGA,
Leaded
0 =
Char 3 = Flash
die #3
Second character
applies to Flash
dies #3 and #4
Original
released
version of
this
(See
(See
JS =
(See
Table 70,
“Voltage /
NOR Flash
CE#
Table 72
Stacked
NOR Flash
only
TSOP, RoHS
Table 71,
“Parameter
/ Mux
,
Char 4 = Flash
die #4
“Ballout
Decoder
” on
(See Table 69,
“NOR Flash
Family
product
TE =
Configurati
on
Configurati
on
TSOP, Leaded
(See
page 13
9 for
Decoder”
on
Table 68,
“38F / 48F
Density
Decoder” on
page 138 for
details)
Decoder”
on
PF =
SCSP, RoHS
details)
page 138
for details)
page 138
for details)
Decoder”on
page 137 for
details)
RD =
SCSP, Leaded
Table 68: 38F / 48F Density Decoder
Code
Flash Density
RAM Density
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
No Die
No Die
32-Mbit
64-Mbit
128-Mbit
256-Mbit
512-Mbit
1-Gbit
4-Mbit
8-Mbit
16-Mbit
32-Mbit
64-Mbit
128-Mbit
256-Mbit
512-Mbit
1-Gbit
2-Gbit
4-Gbit
8-Gbit
16-Gbit
32-Gbit
64-Gbit
128-Gbit
256-Gbit
512-Gbit
2-Gbit
4-Gbit
8-Gbit
16-Gbit
32-Gbit
64-Gbit
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Numonyx™ StrataFlash® Cellular Memory (M18)
Table 69: NOR Flash Family Decoder
Code
Family
Marketing Name
C
C3
Numonyx™ Advanced+ Boot Block Flash Memory
J3v.D
Numonyx™ Embedded Flash Memory
Numonyx™ StrataFlash® Wireless Memory
Numonyx™ StrataFlash® Cellular Memory
Numonyx™ StrataFalsh® Embedded Memory
Numonyx™ Wireless Flash Memory
No Die
J
L
L18 / L30
M18
M
P
P30 / P33
W18 / W30
-
W
0(zero)
Table 70: Voltage / NOR Flash CE# Configuration Decoder
I/O Voltage
Code
Core Voltage (Volt)
CE# Configuration
Seperate Chip Enable per die
(Volt)
Z
3.0
1.8
3.0
3.0
1.8
3.0
3.0
1.8
3.0
1.8
1.8
3.0
1.8
1.8
1.8
1.8
1.8
3.0
Seperate Chip Enable per die
Seperate Chip Enable per die
Virtual Chip Enable
Virtual Chip Enable
Virtual Chip Enable
Virtual Address
Y
X
V
U
T
R
Q
P
Virtual Address
Virtual Address
Table 71: Parameter / Mux Configuration Decoder (Sheet 1 of 2)
Code, Mux
Identification
Number of Flash Die
Bus Width
Flash Die 1
Flash Die 2
Flash Die 3
Flash Die 4
0 = Non Mux
1 = AD Mux
Any
NA
Notation used for stacks that contain no parameter blocks
3 = "Full" AD
Mux
1
2
3
4
2
4
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
-
-
-
Top
-
-
B = Non Mux
C = AD Mux
X16
X32
Bottom
Top
Top
Bottom
-
-
F = "Full" Ad
Mux
Top
-
Bottom
Bottom
Top
Top
Datasheet
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Table 71: Parameter / Mux Configuration Decoder (Sheet 2 of 2)
Code, Mux
Identification
Number of Flash Die
Bus Width
Flash Die 1
Flash Die 2
Flash Die 3
Flash Die 4
1
2
3
4
2
4
Top
-
-
-
-
-
-
Top
Top
Top
Top
Top
Bottom
Top
T = Non Mux
U = AD Mux
X16
Bottom
Top
W = "Full" Ad
Mux
Bottom
Top
Bottom
-
-
X32
Top
Bottom
Bottom
Table 72: Ballout Decoder
Code
Ballout Definition
0 (Zero)
SDiscrete ballout (Easay BGA and TSOP)
B
x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus)
x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus)
QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus)
x32SH ballout, 106 ball (x32 NOR only Share Bus)
C
Q
U
V
x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus
x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus
W
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